flashrom

flashrom@flashrom.org

5 participants
9161 discussions

Re: [flashrom] [PATCH] Add infrastructure to support libusb-1.0.
by Carl-Daniel Hailfinger 18 Jan '16

18 Jan '16

On 07.01.2016 19:50, Stefan Tauner wrote: > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Thanks! Comments below. > diff --git a/Makefile b/Makefile > index 6ddca58..500f71f 100644 > --- a/Makefile > +++ b/Makefile > @@ -966,6 +986,24 @@ ifeq ($(CHECK_LIBUSB0), yes) > rm -f .test.c .test.o .test$(EXEC_SUFFIX); exit 1; }; } 2>>$(BUILD_DETAILS_FILE); echo $? >&3 ; } | tee -a $(BUILD_DETAILS_FILE) >&4; } 3>&1;} | { read rc ; exit ${rc}; } } 4>&1 > @rm -f .test.c .test.o .test$(EXEC_SUFFIX) > endif > +ifeq ($(CHECK_LIBUSB1), yes) > + @printf "Checking for libusb-1.0 headers... " > + @echo "$$LIBUSB1_TEST" > .test.c > + @printf "\nexec: %s\n" "$(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o" >>$(BUILD_DETAILS_FILE) > + @$(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o >/dev/null && \ > + echo "found." || ( echo "not found."; echo; \ > + echo "Please install libusb-1.0 headers."; \ > + echo "See README for more information."; echo; \ > + rm -f .test.c .test.o; exit 1) > + @printf "Checking if libusb-1.0 is usable... " > + @printf "\nexec: %s\n" "$(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(USB1LIBS)" >>$(BUILD_DETAILS_FILE) > + @$(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(USB1LIBS) >/dev/null && \ > + echo "yes." || ( echo "no."; \ > + echo "Please install libusb-1.0."; \ > + echo "See README for more information."; echo; \ > + rm -f .test.c .test.o .test$(EXEC_SUFFIX); exit 1) > + @rm -f .test.c .test.o .test$(EXEC_SUFFIX) > +endif The libusb1 test doesn't use the same fd redirect and tee operations which are present in the libusb0 test. Is that intentional? Regards, Carl-Daniel

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Re: [flashrom] Can't identify SPI chip with buspirate_spi programmer
by David Hendricks 17 Jan '16

17 Jan '16

Hi Donald, Were you able to get it working? With the battery disconnected as you describe flashing with the Bus Pirate should work fine. I suspect there must be a bad connection elsewhere. You might be able to get further assistance on #flashrom on irc.freenode.net . On Thu, Jan 14, 2016 at 11:52 PM, Donald Dade <donald.dade(a)gmail.com> wrote: > Hi again, > > Something else which just occurred to me: > > I used flashrom on the Chromebook itself to program this very same > chip in the first place, without the -p option, which I assume > defaults to the internal programmer. It worked perfectly. Now that I > bricked it somehow, I tried to restore the BIOS image using flashrom > and the bus pirate as the programmer. This is the failure whose log I > sent you previously. > > Any idea why the internal programmer works, but the bus pirate > programmer can't recognize the chip? > > Thanks, > > Donald > > > On Thu, Jan 14, 2016 at 10:47 PM, Donald Dade <donald.dade(a)gmail.com> > wrote: > > Hi, > > > > I bricked my Chromebook and am trying to recover it. > > > > I'm using: > > > > Ubuntu 15.10 > > Bus Pirate v3.6 with firmware v6.2 > > flashrom 0.9.8 r1914 > > > > to try to read a: > > > > Windbond 25Q64FV on a Toshiba Chromebook 2 2015 (battery disconnected) > > > > by doing: > > > > sudo ./flashrom-0.9.8-r1914 -p buspirate_spi:dev=/dev/ttyUSB0 -r > > spi.bin -VVV -o log.txt > > > > but no operations are supported because the chip is not recognized. > > Can you provide any advice on how to move forward? > > > > Thank you, > > > > Donald > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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[PATCH] Add atapromise programmer
by Joseph Lehner 17 Jan '16

17 Jan '16

This patch adds a new programmer that supports (admittedly ancient) Promise ATA controllers. I've successfully tested this on an Ultra100 controller I had lying around. Mine uses a 128 kB MX29F001T flash chip, but I was not able to write anything past the first page (32 kB), which is not that much of a problem, since the option ROM files for these controllers are only 16 kB). It uses a (dirty?) hack to limit the chip size to 16 kB (so you can flash unmodified images) and provides an "allow32k=y" option, allowing you to flash larger images. Signed-off-by: Joseph C. Lehner <joseph.c.lehner(a)gmail.com>

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[commit] r1916 - trunk
by repository service 17 Jan '16

17 Jan '16

Author: hailfinger Date: Sun Jan 17 00:45:25 2016 New Revision: 1916 URL: http://flashrom.org/trac/flashrom/changeset/1916 Log: Add atapromise programmer Supported controllers are Promise PDC20262 (FastTrak66/Ultra66), PDC20265 (FastTrak100 Lite/Ultra100), PDC20267 (FastTrak100/Ultra100). At least the Ultra100 only has address lines A0-A14 wired up, limiting addressable chip size to 32 kB. The flash chips mounted on those controllers usually is 128 kB, i.e. parts of the flash chip are inaccessible. As a workaround, the driver implicitly truncates the size of all flash chips to 32 kB. Works well for the factory installed flash. Do NOT use as a generic programmer for chips >32 kB. Signed-off-by: Joseph C. Lehner <joseph.c.lehner(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Urja Rannikko <urjaman(a)gmail.com> Added: trunk/atapromise.c Modified: trunk/Makefile trunk/flashrom.8.tmpl trunk/flashrom.c trunk/programmer.h Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sat Jan 16 19:50:27 2016 (r1915) +++ trunk/Makefile Sun Jan 17 00:45:25 2016 (r1916) @@ -227,6 +227,11 @@ else override CONFIG_ATAVIA = no endif +ifeq ($(CONFIG_ATAPROMISE), yes) +UNSUPPORTED_FEATURES += CONFIG_ATAPROMISE=yes +else +override CONFIG_ATAPROMISE = no +endif ifeq ($(CONFIG_IT8212), yes) UNSUPPORTED_FEATURES += CONFIG_IT8212=yes else @@ -449,6 +454,9 @@ # VIA VT6421A LPC memory support CONFIG_ATAVIA ?= yes +# Promise ATA controller support. +CONFIG_ATAPROMISE ?= no + # Always enable FT2232 SPI dongles for now. CONFIG_FT2232_SPI ?= yes @@ -626,6 +634,12 @@ NEED_PCI := yes endif +ifeq ($(CONFIG_ATAPROMISE), yes) +FEATURE_CFLAGS += -D'CONFIG_ATAPROMISE=1' +PROGRAMMER_OBJS += atapromise.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_IT8212), yes) FEATURE_CFLAGS += -D'CONFIG_IT8212=1' PROGRAMMER_OBJS += it8212.o Added: trunk/atapromise.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/atapromise.c Sun Jan 17 00:45:25 2016 (r1916) @@ -0,0 +1,177 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2015 Joseph C. Lehner <joseph.c.lehner(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) + +#include <string.h> +#include <stdlib.h> +#include "flash.h" +#include "programmer.h" +#include "hwaccess.h" + +#define MAX_ROM_DECODE (32 * 1024) +#define ADDR_MASK (MAX_ROM_DECODE - 1) + +/* + * In the absence of any public docs on the PDC2026x family, this programmer was created through a mix of + * reverse-engineering and trial and error. + * + * The only device tested is an Ultra100 controller, but the logic for programming the other 2026x controllers + * is the same, so it should, in theory, work for those as well. + * + * While the tested Ultra100 controller used a 128 kB MX29F001T chip, A16 and A15 showed continuity to ground, + * thus limiting the the programmer on this card to 32 kB. Without other controllers to test this programmer on, + * this is currently a hard limit. Note that ROM files for these controllers are 16 kB only. + * + * Since flashrom does not support accessing flash chips larger than the size limit of the programmer (the + * tested Ultra100 uses a 128 kB MX29F001T chip), the chip size is hackishly adjusted in atapromise_limit_chip. + */ + +static uint32_t io_base_addr = 0; +static uint32_t rom_base_addr = 0; + +static uint8_t *atapromise_bar = NULL; +static size_t rom_size = 0; + +const struct dev_entry ata_promise[] = { + {0x105a, 0x4d38, NT, "Promise", "PDC20262 (FastTrak66/Ultra66)"}, + {0x105a, 0x0d30, NT, "Promise", "PDC20265 (FastTrak100 Lite/Ultra100)"}, + {0x105a, 0x4d30, OK, "Promise", "PDC20267 (FastTrak100/Ultra100)"}, + {0}, +}; + +static void atapromise_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); +static uint8_t atapromise_chip_readb(const struct flashctx *flash, const chipaddr addr); + +static const struct par_master par_master_atapromise = { + .chip_readb = atapromise_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = atapromise_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + +void *atapromise_map(const char *descr, uintptr_t phys_addr, size_t len) +{ + /* In case fallback_map ever returns something other than NULL. */ + return NULL; +} + +static void atapromise_limit_chip(struct flashchip *chip) +{ + static uint32_t last_model_id = 0; + unsigned int i, size; + + if (chip->model_id == last_model_id) + return; + + size = chip->total_size * 1024; + if (size > rom_size) { + /* Undefine all block_erasers that don't operate on the whole chip, + * and adjust the eraseblock size of the one that does. + */ + for (i = 0; i < NUM_ERASEFUNCTIONS; ++i) { + if (chip->block_erasers[i].eraseblocks[0].size != size) { + chip->block_erasers[i].eraseblocks[0].count = 0; + chip->block_erasers[i].block_erase = NULL; + } else { + chip->block_erasers[i].eraseblocks[0].size = rom_size; + break; + } + } + + if (i != NUM_ERASEFUNCTIONS) { + chip->total_size = rom_size / 1024; + if (chip->page_size > rom_size) + chip->page_size = rom_size; + } else { + msg_pdbg("Failed to adjust size of chip \"%s\" (%d kB).\n", chip->name, + chip->total_size); + } + } + + last_model_id = chip->model_id; +} + +int atapromise_init(void) +{ + struct pci_dev *dev = NULL; + + if (rget_io_perms()) + return 1; + + dev = pcidev_init(ata_promise, PCI_BASE_ADDRESS_4); + if (!dev) + return 1; + + io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_4) & 0xfffe; + if (!io_base_addr) { + return 1; + } + + /* Not exactly sure what this does, because flashing seems to work + * well without it. However, PTIFLASH does it, so we do it too. + */ + OUTB(1, io_base_addr + 0x10); + + rom_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_5); + if (!rom_base_addr) { + msg_pdbg("Failed to read BAR5\n"); + return 1; + } + + rom_size = dev->rom_size > MAX_ROM_DECODE ? MAX_ROM_DECODE : dev->rom_size; + atapromise_bar = (uint8_t*)rphysmap("Promise", rom_base_addr, rom_size); + if (atapromise_bar == ERROR_PTR) { + return 1; + } + + max_rom_decode.parallel = rom_size; + register_par_master(&par_master_atapromise, BUS_PARALLEL); + + msg_pwarn("Do not use this device as a generic programmer. It will leave anything outside\n" + "the first %zu kB of the flash chip in an undefined state. It works fine for the\n" + "purpose of updating the firmware of this device (padding may neccessary).\n", + rom_size / 1024); + + return 0; +} + +static void atapromise_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) +{ + uint32_t data; + + atapromise_limit_chip(flash->chip); + data = (rom_base_addr + (addr & ADDR_MASK)) << 8 | val; + OUTL(data, io_base_addr + 0x14); +} + +static uint8_t atapromise_chip_readb(const struct flashctx *flash, const chipaddr addr) +{ + atapromise_limit_chip(flash->chip); + return pci_mmio_readb(atapromise_bar + (addr & ADDR_MASK)); +} + +#else +#error PCI port I/O access is not supported on this architecture yet. +#endif Modified: trunk/flashrom.8.tmpl ============================================================================== --- trunk/flashrom.8.tmpl Sat Jan 16 19:50:27 2016 (r1915) +++ trunk/flashrom.8.tmpl Sun Jan 17 00:45:25 2016 (r1916) @@ -233,6 +233,8 @@ .sp .BR "* atavia" " (for flash ROMs on VIA VT6421A SATA controllers)" .sp +.BR "* atapromise" " (for flash ROMs on Promise PDC2026x ATA/RAID controllers)" +.sp .BR "* it8212" " (for flash ROMs on ITE IT8212F ATA/RAID controller)" .sp .BR "* ft2232_spi" " (for SPI flash ROMs attached to an FT2232/FT4232H/FT232H family \ @@ -636,7 +638,7 @@ .SS .BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\ , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\ -, " satamv" , " atahpt", " atavia " and " it8212 " programmers +, " satamv" , " atahpt", " atavia ", " atapromise " and " it8212 " programmers .IP These programmers have an option to specify the PCI address of the card your want to use, which must be specified if more than one card supported @@ -669,6 +671,13 @@ For more information please see .URLB https://flashrom.org/VT6421A "its wiki page" . .SS +.BR "atapromise " programmer +.IP +This programmer is currently limited to 32 kB, regardless of the actual size of the flash chip. This stems +from the fact that, on the tested device (a Promise Ultra100), not all of the chip's address lines were +actually connected. You may use this programmer to flash firmware updates, since these are only 16 kB in +size (padding to 32 kB is required). +.SS .BR "nicintel_eeprom " programmer .IP This is the first programmer module in flashrom that does not provide access to NOR flash chips but EEPROMs @@ -1059,8 +1068,8 @@ .BR satasii ", " nicintel ", " nicintel_eeprom " and " nicintel_spi need PCI configuration space read access and raw memory access. .sp -.B satamv -needs PCI configuration space read access, raw I/O port access and raw memory +.BR satamv " and " atapromise +need PCI configuration space read access, raw I/O port access and raw memory access. .sp .B serprog @@ -1076,7 +1085,7 @@ needs no access permissions at all. .sp .BR internal ", " nic3com ", " nicrealtek ", " nicnatsemi ", " -.BR gfxnvidia ", " drkaiser ", " satasii ", " satamv ", " atahpt" and " atavia +.BR gfxnvidia ", " drkaiser ", " satasii ", " satamv ", " atahpt ", " atavia " and " atapromise have to be run as superuser/root, and need additional raw access permission. .sp .BR serprog ", " buspirate_spi ", " dediprog ", " usbblaster_spi ", " ft2232_spi " and " pickit2_spi Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sat Jan 16 19:50:27 2016 (r1915) +++ trunk/flashrom.c Sun Jan 17 00:45:25 2016 (r1916) @@ -182,6 +182,18 @@ }, #endif +#if CONFIG_ATAPROMISE == 1 + { + .name = "atapromise", + .type = PCI, + .devs.dev = ata_promise, + .init = atapromise_init, + .map_flash_region = atapromise_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + #if CONFIG_IT8212 == 1 { .name = "it8212", Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sat Jan 16 19:50:27 2016 (r1915) +++ trunk/programmer.h Sun Jan 17 00:45:25 2016 (r1916) @@ -57,6 +57,9 @@ #if CONFIG_ATAVIA == 1 PROGRAMMER_ATAVIA, #endif +#if CONFIG_ATAPROMISE == 1 + PROGRAMMER_ATAPROMISE, +#endif #if CONFIG_IT8212 == 1 PROGRAMMER_IT8212, #endif @@ -460,6 +463,13 @@ extern const struct dev_entry ata_via[]; #endif +/* atapromise.c */ +#if CONFIG_ATAPROMISE == 1 +int atapromise_init(void); +void *atapromise_map(const char *descr, uintptr_t phys_addr, size_t len); +extern const struct dev_entry ata_promise[]; +#endif + /* it8212.c */ #if CONFIG_IT8212 == 1 int it8212_init(void);

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[commit] r1915 - trunk
by repository service 16 Jan '16

16 Jan '16

Author: stefanct Date: Sat Jan 16 19:50:27 2016 New Revision: 1915 URL: http://flashrom.org/trac/flashrom/changeset/1915 Log: Fix file descriptor leak in serial.c. Found by Coverity as "CID 1348465: Resource leaks". Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/serial.c Modified: trunk/serial.c ============================================================================== --- trunk/serial.c Fri Jan 15 00:05:55 2016 (r1914) +++ trunk/serial.c Sat Jan 16 19:50:27 2016 (r1915) @@ -282,18 +282,20 @@ const int flags = fcntl(fd, F_GETFL); if (flags == -1) { msg_perr_strerror("Could not get serial port mode: "); - return SER_INV_FD; + goto err; } if (fcntl(fd, F_SETFL, flags & ~O_NONBLOCK) != 0) { msg_perr_strerror("Could not set serial port mode to blocking: "); - return SER_INV_FD; + goto err; } if (serialport_config(fd, baud) != 0) { - close(fd); - return SER_INV_FD; + goto err; } return fd; +err: + close(fd); + return SER_INV_FD; #endif }

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Re: [flashrom] Issue with internal access to the W39V040FB
by Carl-Daniel Hailfinger 15 Jan '16

15 Jan '16

Hi Andrey, On 15.01.2016 15:33, Andrey Korolyov wrote: > On Sun, Jan 3, 2016 at 9:44 PM, Andrey Korolyov <andrey(a)xdel.ru> wrote: >>> >> Hi Andrey, >>> >> >>> >> please post complete logs of a working and non-working probe as well as >>> >> the exact flashrom version you are using. The output of lspci -nnv >>> >> might become handy as well. >>> >> >> > >> > >> > Thanks Stefan, >> > >> > even giving out a fact that I am very lucky to hit very twisted issues >> > at all, this time it looks like chip eventually stopped to respond via >> > an appropriate interface (slight voltage change? bit-flip during a >> > board initialization? lack of a probe delay? ), so I think that the >> > initial report could be incorrect, as the flash is not responding >> > anymore even where is was supposed to. Nevertheless, the appropriate >> > log and lspci output are attached, please take a look on them if they >> > could be helpful. > Got an another sample of the same board, because original was died > from overheating during EEPROM resoldering procedure. Internal WRITE > effectively bricked a board over cold reboot but I finally obtained > logs with some possible usefulness. Should I check same random > behavior as I reported previously after reflashing the chip > externally? Unfortunate to me, the board layout strictly requires chip > desoldering before I would be able to program it with anything, > in-place attempts are failing even with external power source, but > when de-soldered, chip flashes just perfectly via Minipro. > > flashrom v0.9.7-r1711 on NetBSD 7.0 (i386) > flashrom is free software, get the source code at http://www.flashrom.org > > flashrom was built with libpci 3.3.0, GCC 4.8.4, little endian > Command line (7 args): flashrom -p internal:laptop=this_is_not_a_laptop -c W39V040FB -r bios.bin -V > Calibrating delay loop... OS timer resolution is 5 usecs, 166M loops per second, 10 myus = 14 us, 100 myus = 105 us, 1000 myus = 1004 us, 10000 myus = 10042 us, 20 myus = 24 us, OK. > Initializing internal programmer > [...] > Found chipset "AMD CS5536" with PCI ID 1022:2080. Enabling flash write... No MSR support for your OS yet. > FAILED! > Warning: unexpected second chipset match: "AMD CS5536" > ignoring, please report lspci and board URL to flashrom(a)flashrom.org > with 'CHIPSET: your board name' in the subject line. I suspect this may be part of the issue. Another suspicion is that older NetBSD may automatically enable the MSRs we need, and later NetBSD versions don't. Regards, Carl-Daniel

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Re: [flashrom] Issue with internal access to the W39V040FB
by Andrey Korolyov 15 Jan '16

15 Jan '16

On Sun, Jan 3, 2016 at 9:44 PM, Andrey Korolyov <andrey(a)xdel.ru> wrote: >> Hi Andrey, >> >> please post complete logs of a working and non-working probe as well as >> the exact flashrom version you are using. The output of lspci -nnv >> might become handy as well. >> > > > Thanks Stefan, > > even giving out a fact that I am very lucky to hit very twisted issues > at all, this time it looks like chip eventually stopped to respond via > an appropriate interface (slight voltage change? bit-flip during a > board initialization? lack of a probe delay? ), so I think that the > initial report could be incorrect, as the flash is not responding > anymore even where is was supposed to. Nevertheless, the appropriate > log and lspci output are attached, please take a look on them if they > could be helpful. Got an another sample of the same board, because original was died from overheating during EEPROM resoldering procedure. Internal WRITE effectively bricked a board over cold reboot but I finally obtained logs with some possible usefulness. Should I check same random behavior as I reported previously after reflashing the chip externally? Unfortunate to me, the board layout strictly requires chip desoldering before I would be able to program it with anything, in-place attempts are failing even with external power source, but when de-soldered, chip flashes just perfectly via Minipro.

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Re: [flashrom] Can't identify SPI chip with buspirate_spi programmer
by Donald Dade 15 Jan '16

15 Jan '16

Hi again, Something else which just occurred to me: I used flashrom on the Chromebook itself to program this very same chip in the first place, without the -p option, which I assume defaults to the internal programmer. It worked perfectly. Now that I bricked it somehow, I tried to restore the BIOS image using flashrom and the bus pirate as the programmer. This is the failure whose log I sent you previously. Any idea why the internal programmer works, but the bus pirate programmer can't recognize the chip? Thanks, Donald On Thu, Jan 14, 2016 at 10:47 PM, Donald Dade <donald.dade(a)gmail.com> wrote: > Hi, > > I bricked my Chromebook and am trying to recover it. > > I'm using: > > Ubuntu 15.10 > Bus Pirate v3.6 with firmware v6.2 > flashrom 0.9.8 r1914 > > to try to read a: > > Windbond 25Q64FV on a Toshiba Chromebook 2 2015 (battery disconnected) > > by doing: > > sudo ./flashrom-0.9.8-r1914 -p buspirate_spi:dev=/dev/ttyUSB0 -r > spi.bin -VVV -o log.txt > > but no operations are supported because the chip is not recognized. > Can you provide any advice on how to move forward? > > Thank you, > > Donald

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Can't identify SPI chip with buspirate_spi programmer
by Donald Dade 15 Jan '16

15 Jan '16

Hi, I bricked my Chromebook and am trying to recover it. I'm using: Ubuntu 15.10 Bus Pirate v3.6 with firmware v6.2 flashrom 0.9.8 r1914 to try to read a: Windbond 25Q64FV on a Toshiba Chromebook 2 2015 (battery disconnected) by doing: sudo ./flashrom-0.9.8-r1914 -p buspirate_spi:dev=/dev/ttyUSB0 -r spi.bin -VVV -o log.txt but no operations are supported because the chip is not recognized. Can you provide any advice on how to move forward? Thank you, Donald A non-text attachment has been stripped: winbond_25Q64FV.bmp

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Re: [flashrom] [PATCH 2/2] Set LC_ALL globally in Makefile.
by Stefan Tauner 15 Jan '16

15 Jan '16

On Thu, 7 Jan 2016 19:22:41 +0100 Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > While we're at it, comment and simplify the debug_shell function as well. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > --- > Makefile | 11 ++++++++--- > 1 file changed, 8 insertions(+), 3 deletions(-) > > diff --git a/Makefile b/Makefile > index 757f3a8..6ddca58 100644 > --- a/Makefile > +++ b/Makefile > @@ -77,8 +77,13 @@ PKG_CONFIG += --static > LDFLAGS += -static > endif > > +LC_ALL=C > +export LC_ALL > + Apparently this does only make LC_ALL visible in recipe commands but not globally/in shell functions, cf. http://stackoverflow.com/a/26518222/1905491 However, maybe we should set it here anyway? I certainly would not hurt. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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