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[PATCH] Give warning for CH341A programmer in alternate mode
by Keno Fischer 09 Jan '17

09 Jan '17

My programmer with this chip has a jumper to select between USB <-> UART translation and USB <-> SPI translation. Only the latter is applicable for use as an SPI programmer of course, but it's an easy and non-obvious mistake to make. The UART mode (and a printer mode not exposed on my programmer, but available on the chip according to the datasheet), are indicated through different USB IDs, which we can easily detect. Do so, and print an informative warning when such a device is detected. Signed-off-by: Keno Fischer <keno(a)juliacomputing.com> --- ch341a_spi.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 54 insertions(+), 5 deletions(-) diff --git a/ch341a_spi.c b/ch341a_spi.c index 6eb2804..7eba6b1 100644 --- a/ch341a_spi.c +++ b/ch341a_spi.c @@ -93,6 +93,16 @@ const struct dev_entry devs_ch341a_spi[] = { {0}, }; +/* The CH341A has alternate modes, indicated as different USB device IDs and + * generally selectible on programmers via jumpers. Those alternate modes are + * unsuitable for use as a programmer, but we want to be able to detect them, + * to give a nice error message to the user. */ +const struct dev_entry devs_ch341a_spi_alternate[] = { + {0x1A86, 0x5523, OK, "Winchiphead (WCH)", "CH341A Serial"}, + {0x1A86, 0x5584, OK, "Winchiphead (WCH)", "CH341A Printer"}, + {0}, +}; + enum trans_state {TRANS_ACTIVE = -2, TRANS_ERR = -1, TRANS_IDLE = 0}; static void print_hex(const void *buf, size_t len) @@ -431,6 +441,47 @@ static int ch341a_spi_shutdown(void *data) return 0; } +static bool device_matches(const struct libusb_device_descriptor *desc, const struct dev_entry *entry) +{ + return desc->idVendor == entry->vendor_id && desc->idProduct == entry->device_id; +} + +static struct libusb_device_handle *ch341a_find_device() +{ + struct libusb_device *dev, **devs; + struct libusb_device_handle *dev_handle = NULL; + size_t i = 0; + + if (libusb_get_device_list(NULL, &devs) < 0) + return dev_handle; + + while ((dev = devs[i++]) != NULL) { + struct libusb_device_descriptor desc; + const struct dev_entry *entry; + if (libusb_get_device_descriptor(dev, &desc) < 0) + goto out; + for (entry = devs_ch341a_spi_alternate; entry->vendor_id != 0; ++entry) { + if (device_matches(&desc, entry)) { + msg_pwarn("CH341A device in alternate mode detected.\n" + "There may be a jumper on your programmer to switch modes.\n"); + } + } + for (entry = devs_ch341a_spi; entry->vendor_id != 0; ++entry) { + if (device_matches(&desc, entry)) { + if (dev_handle) { + msg_pwarn("Multiple CH341A devices detected. Selecting the first.\n"); + goto out; + } + libusb_open(dev, &dev_handle); + } + } + } + +out: + libusb_free_device_list(devs, 1); + return dev_handle; +} + int ch341a_spi_init(void) { if (handle != NULL) { @@ -444,13 +495,11 @@ int ch341a_spi_init(void) return -1; } - libusb_set_debug(NULL, 3); // Enable information, warning and error messages (only). + libusb_set_debug(NULL, 4); // Enable information, warning and error messages (only). - uint16_t vid = devs_ch341a_spi[0].vendor_id; - uint16_t pid = devs_ch341a_spi[0].device_id; - handle = libusb_open_device_with_vid_pid(NULL, vid, pid); + handle = ch341a_find_device(); if (handle == NULL) { - msg_perr("Couldn't open device %04x:%04x.\n", vid, pid); + msg_perr("No usable CH341A USB device found.\n"); return -1; } -- 1.7.10.4

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Working W25Q256
by note importa 04 Jan '17

04 Jan '17

Hello, i just write to say that i got working a winbond W25Q256 memory whit flashrom applying the patches for this chip. Its works great i can erase write and read whit no problems. Im using a raspberry pi model b Cya and thanks for this awsome job.

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Re: [flashrom] [PATCH 3/10] 4BA: Winbond W25Q256.V chip (32MB) declaration, 4-bytes addr mode
by Marcos Ledesma 03 Jan '17

03 Jan '17

Hello, i want to know how I modify flashrom files to add w25q256 support. Thanks. Descripción: Marcos-Ledesma

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Verifying flash... FAILED
by Joe Lee 25 Dec '16

25 Dec '16

I flashed a ThinkPad T500 and got this message. > Verifying flash... FAILED at 0x0004c001! Expected=0x3e, Found=0xc7, failed byte count from 0x00000000-0x007fffff: 0x6 > Your flash chip is in an unknown state. Cheers!

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Re: [flashrom] FAILED: GA-B75M-D3V
by Nico Huber 24 Dec '16

24 Dec '16

On 23.12.2016 08:19, David Hendricks wrote: > Looks like it failed to overwrite the descriptor region (Intel ME-related > headache): https://www.flashrom.org/ME According to the log, the descriptor is writeable. Also the error occurs right behind it. When I looked through it first, I thought there might be a board speci- fic write-protection. But now that David pointed me to the 0x1000 here: >> 0x000000-0x00ffff:EFAILED at 0x00001000! Expected=0xff, Found=0x20, I think you just selected the wrong chip. MX25L6405 uses a 64KiB erase- block size by default, but only 4KiB (i.e. everything before 0x1000) got erased. So it's likely one of the other chips flashrom proposed (it can't know by itself, since the chip vendors reuse their IDs...). MX25L6405D seems to be a good choice if you don't know for sure which chip you have. It uses a subset of the functions the other chips use. Hope that helps, Nico > > You can target regions more carefully using a layout file. It appears the > other regions (ME, BIOS, GbE) are unlocked, so you can try creating a > layout that includes only those regions. > > On Mon, Dec 19, 2016 at 7:54 PM, Shawn <citypw(a)gmail.com> wrote: > >> Hi flashrom maintainers, >> >> I failed to write a modified ROM to the flash via internal. Maybe this >> chipset can only be writable via external programmer? >> >> root@sysresccd /root % flashrom -p internal >> flashrom v0.9.8-r1888 on Linux 4.4.28-std490-amd64 (x86_64) >> flashrom is free software, get the source code at http://www.flashrom.org >> >> Calibrating delay loop... OK. >> Found chipset "Intel B75". >> Enabling flash write... Warning: SPI Configuration Lockdown activated. >> OK. >> Found Macronix flash chip "MX25L6405" (8192 kB, SPI) mapped at >> physical address 0xff800000. >> Found Macronix flash chip "MX25L6405D" (8192 kB, SPI) mapped at >> physical address 0xff800000. >> Found Macronix flash chip "MX25L6406E/MX25L6408E" (8192 kB, SPI) >> mapped at physical address 0xff800000. >> Found Macronix flash chip >> "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E" (8192 kB, SPI) mapped at >> physical address 0xff800000. >> Multiple flash chip definitions match the detected chip(s): >> "MX25L6405", "MX25L6405D", "MX25L6406E/MX25L6408E", >> "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E" >> Please specify which chip definition to use with the -c <chipname> option. >> >> >> root@sysresccd /root % flashrom -VV -p internal -c MX25L6405 -w >> factory_giga1.bin.new.new >> flashrom v0.9.8-r1888 on Linux 4.4.28-std490-amd64 (x86_64) >> flashrom is free software, get the source code at http://www.flashrom.org >> >> flashrom was built with libpci 3.4.1, GCC 4.8.5, little endian >> Command line (7 args): flashrom -VV -p internal -c MX25L6405 -w >> factory_giga1.bin.new.new >> Calibrating delay loop... OS timer resolution is 1 usecs, 1944M loops >> per second, 10 myus = 10 us, 100 myus = 117 us, 1000 myus = 1021 us, >> 10000 myus = 10021 us, 4 myus = 4 us, OK. >> Initializing internal programmer >> No coreboot table found. >> Using Internal DMI decoder. >> DMI string chassis-type: "Desktop" >> DMI string system-manufacturer: "Gigabyte Technology Co., Ltd." >> DMI string system-product-name: "To be filled by O.E.M." >> DMI string system-version: "To be filled by O.E.M." >> DMI string baseboard-manufacturer: "Gigabyte Technology Co., Ltd." >> DMI string baseboard-product-name: "B75M-D3V" >> DMI string baseboard-version: "To be filled by O.E.M." >> Found ITE Super I/O, ID 0x8728 on port 0x2e >> Found chipset "Intel B75" with PCI ID 8086:1e49. >> Enabling flash write... Root Complex Register Block address = 0xfed1c000 >> GCS = 0xc64: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 >> (SPI) >> Top Swap: enabled (A16(+) inverted) >> 0xfff80000/0xffb80000 FWH IDSEL: 0x0 >> 0xfff00000/0xffb00000 FWH IDSEL: 0x0 >> 0xffe80000/0xffa80000 FWH IDSEL: 0x1 >> 0xffe00000/0xffa00000 FWH IDSEL: 0x1 >> 0xffd80000/0xff980000 FWH IDSEL: 0x2 >> 0xffd00000/0xff900000 FWH IDSEL: 0x2 >> 0xffc80000/0xff880000 FWH IDSEL: 0x3 >> 0xffc00000/0xff800000 FWH IDSEL: 0x3 >> 0xff700000/0xff300000 FWH IDSEL: 0x4 >> 0xff600000/0xff200000 FWH IDSEL: 0x5 >> 0xff500000/0xff100000 FWH IDSEL: 0x6 >> 0xff400000/0xff000000 FWH IDSEL: 0x7 >> 0xfff80000/0xffb80000 FWH decode enabled >> 0xfff00000/0xffb00000 FWH decode enabled >> 0xffe80000/0xffa80000 FWH decode enabled >> 0xffe00000/0xffa00000 FWH decode enabled >> 0xffd80000/0xff980000 FWH decode enabled >> 0xffd00000/0xff900000 FWH decode enabled >> 0xffc80000/0xff880000 FWH decode enabled >> 0xffc00000/0xff800000 FWH decode enabled >> 0xff700000/0xff300000 FWH decode enabled >> 0xff600000/0xff200000 FWH decode enabled >> 0xff500000/0xff100000 FWH decode enabled >> 0xff400000/0xff000000 FWH decode enabled >> Maximum FWH chip size: 0x100000 bytes >> SPI Read Configuration: prefetching enabled, caching enabled, >> BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled >> SPIBAR = 0xf7795000 + 0x3800 >> 0x04: 0xe008 (HSFS) >> HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 >> Warning: SPI Configuration Lockdown activated. >> Reading OPCODES... done >> OP Type Pre-OP >> op[0]: 0x02, write w/ addr, none >> op[1]: 0x03, read w/ addr, none >> op[2]: 0x20, write w/ addr, none >> op[3]: 0x05, read w/o addr, none >> op[4]: 0x9f, read w/o addr, none >> op[5]: 0x01, write w/o addr, none >> op[6]: 0x00, read w/o addr, none >> op[7]: 0x00, read w/o addr, none >> Pre-OP 0: 0x06, Pre-OP 1: 0x00 >> 0x06: 0x0000 (HSFC) >> HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 >> 0x08: 0x00000000 (FADDR) >> 0x50: 0x0000ffff (FRAP) >> BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff >> 0x54: 0x00000000 FREG0: Flash Descriptor region >> (0x00000000-0x00000fff) is read-write. >> 0x58: 0x07ff0000 FREG1: BIOS region (0x00000000-0x007fffff) is read-write. >> 0x5C: 0x04ff0001 FREG2: Management Engine region >> (0x00001000-0x004fffff) is read-write. >> 0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused. >> 0x64: 0x00001fff FREG4: Platform Data region is unused. >> 0x74: 0x00000000 (PR0 is unused) >> 0x78: 0x00000000 (PR1 is unused) >> 0x7C: 0x00000000 (PR2 is unused) >> 0x80: 0x00000000 (PR3 is unused) >> 0x84: 0x00000000 (PR4 is unused) >> 0x90: 0x84 (SSFS) >> SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 >> 0x91: 0xf94240 (SSFC) >> SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=2, SME=0, SCF=1 >> 0x94: 0x0006 (PREOP) >> 0x96: 0x043b (OPTYPE) >> 0x98: 0x05200302 (OPMENU) >> 0x9C: 0x0000019f (OPMENU+4) >> 0xA0: 0x00000000 (BBAR) >> 0xC4: 0x00802005 (LVSCC) >> LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 >> 0xC8: 0x00002005 (UVSCC) >> UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 >> 0xD0: 0x00000000 (FPB) >> Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. >> === Content Section === >> FLVALSIG 0x0ff0a55a >> FLMAP0 0x02040003 >> FLMAP1 0x12100206 >> FLMAP2 0x00210120 >> >> --- Details --- >> NR (Number of Regions): 3 >> FRBA (Flash Region Base Address): 0x040 >> NC (Number of Components): 1 >> FCBA (Flash Component Base Address): 0x030 >> ISL (ICH/PCH Strap Length): 18 >> FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 >> NM (Number of Masters): 3 >> FMBA (Flash Master Base Address): 0x060 >> MSL/PSL (MCH/PROC Strap Length): 1 >> FMSBA (Flash MCH/PROC Strap Base Address): 0x200 >> >> === Component Section === >> FLCOMP 0x09300024 >> FLILL 0x00000000 >> >> --- Details --- >> Component 1 density: 8 MB >> Component 2 is not used. >> Read Clock Frequency: 20 MHz >> Read ID and Status Clock Freq.: 33 MHz >> Write and Erase Clock Freq.: 33 MHz >> Fast Read is supported. >> Fast Read Clock Frequency: 33 MHz >> Dual Output Fast Read Support: enabled >> No forbidden opcodes. >> >> === Region Section === >> FLREG0 0x00000000 >> FLREG1 0x07ff0000 >> FLREG2 0x04ff0001 >> FLREG3 0x00001fff >> FLREG4 0x00001fff >> >> --- Details --- >> Region 0 (Descr.) 0x00000000 - 0x00000fff >> Region 1 (BIOS ) 0x00000000 - 0x007fffff >> Region 2 (ME ) 0x00001000 - 0x004fffff >> Region 3 (GbE ) is unused. >> Region 4 (Platf.) is unused. >> >> === Master Section === >> FLMSTR1 0xffff0000 >> FLMSTR2 0xffff0000 >> FLMSTR3 0xffff0118 >> >> --- Details --- >> Descr. BIOS ME GbE Platf. >> BIOS rw rw rw rw rw >> ME rw rw rw rw rw >> GbE rw rw rw rw rw >> >> OK. >> No IT87* serial flash segment enabled. >> The following protocols are supported: FWH, SPI. >> Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 >> 0xc2, id2 0x2017 >> Found Macronix flash chip "MX25L6405" (8192 kB, SPI) mapped at >> physical address 0xff800000. >> Chip status register is 0x00. >> Chip status register: Status Register Write Disable (SRWD, SRP, ...) is >> not set >> Chip status register: Bit 6 is not set >> Chip status register: Block Protect 3 (BP3) is not set >> Chip status register: Block Protect 2 (BP2) is not set >> Chip status register: Block Protect 1 (BP1) is not set >> Chip status register: Block Protect 0 (BP0) is not set >> Chip status register: Write Enable Latch (WEL) is not set >> Chip status register: Write In Progress (WIP/BUSY) is not set >> Block protection is disabled. >> Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. >> Reading old flash chip contents... done. >> Erasing and writing flash chip... Trying erase function 0... >> 0x000000-0x00ffff:EFAILED at 0x00001000! Expected=0xff, Found=0x20, >> failed byte count from 0x00000000-0x0000ffff: 0xb55d >> ERASE FAILED! >> Reading current flash chip contents... done. Looking for another erase >> function. >> Trying erase function 1... 0x000000-0x00ffff:EInvalid OPCODE 0x06, >> will not execute. >> spi_block_erase_d8 failed during command execution at address 0x0 >> Reading current flash chip contents... done. Looking for another erase >> function. >> Trying erase function 2... 0x000000-0x7fffff:EInvalid OPCODE 0x06, >> will not execute. >> spi_chip_erase_60 failed during command execution >> Reading current flash chip contents... done. Looking for another erase >> function. >> Trying erase function 3... 0x000000-0x7fffff:EInvalid OPCODE 0x06, >> will not execute. >> spi_chip_erase_c7 failed during command execution >> Looking for another erase function. >> No usable erase functions left. >> FAILED! >> Uh oh. Erase/write failed. Checking if anything has changed. >> Reading current flash chip contents... done. >> Apparently at least some data has changed. >> Your flash chip is in an unknown state. >> Get help on IRC at chat.freenode.net (channel #flashrom) or >> mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! >> ------------------------------------------------------------ >> ------------------- >> DO NOT REBOOT OR POWEROFF! >> Restoring MMIO space at 0xf77988a0 >> Restoring PCI config space for 00:1f:0 reg 0xdc >> >> >> -- >> GNU powered it... >> GPL protect it... >> God blessing it... >> >> regards >> Shawn >> >> _______________________________________________ >> flashrom mailing list >> flashrom(a)flashrom.org >> https://www.flashrom.org/mailman/listinfo/flashrom >> > > > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > https://www.flashrom.org/mailman/listinfo/flashrom >

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Re: [flashrom] FAILED: GA-B75M-D3V
by David Hendricks 23 Dec '16

23 Dec '16

Looks like it failed to overwrite the descriptor region (Intel ME-related headache): https://www.flashrom.org/ME You can target regions more carefully using a layout file. It appears the other regions (ME, BIOS, GbE) are unlocked, so you can try creating a layout that includes only those regions. On Mon, Dec 19, 2016 at 7:54 PM, Shawn <citypw(a)gmail.com> wrote: > Hi flashrom maintainers, > > I failed to write a modified ROM to the flash via internal. Maybe this > chipset can only be writable via external programmer? > > root@sysresccd /root % flashrom -p internal > flashrom v0.9.8-r1888 on Linux 4.4.28-std490-amd64 (x86_64) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > Found chipset "Intel B75". > Enabling flash write... Warning: SPI Configuration Lockdown activated. > OK. > Found Macronix flash chip "MX25L6405" (8192 kB, SPI) mapped at > physical address 0xff800000. > Found Macronix flash chip "MX25L6405D" (8192 kB, SPI) mapped at > physical address 0xff800000. > Found Macronix flash chip "MX25L6406E/MX25L6408E" (8192 kB, SPI) > mapped at physical address 0xff800000. > Found Macronix flash chip > "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E" (8192 kB, SPI) mapped at > physical address 0xff800000. > Multiple flash chip definitions match the detected chip(s): > "MX25L6405", "MX25L6405D", "MX25L6406E/MX25L6408E", > "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E" > Please specify which chip definition to use with the -c <chipname> option. > > > root@sysresccd /root % flashrom -VV -p internal -c MX25L6405 -w > factory_giga1.bin.new.new > flashrom v0.9.8-r1888 on Linux 4.4.28-std490-amd64 (x86_64) > flashrom is free software, get the source code at http://www.flashrom.org > > flashrom was built with libpci 3.4.1, GCC 4.8.5, little endian > Command line (7 args): flashrom -VV -p internal -c MX25L6405 -w > factory_giga1.bin.new.new > Calibrating delay loop... OS timer resolution is 1 usecs, 1944M loops > per second, 10 myus = 10 us, 100 myus = 117 us, 1000 myus = 1021 us, > 10000 myus = 10021 us, 4 myus = 4 us, OK. > Initializing internal programmer > No coreboot table found. > Using Internal DMI decoder. > DMI string chassis-type: "Desktop" > DMI string system-manufacturer: "Gigabyte Technology Co., Ltd." > DMI string system-product-name: "To be filled by O.E.M." > DMI string system-version: "To be filled by O.E.M." > DMI string baseboard-manufacturer: "Gigabyte Technology Co., Ltd." > DMI string baseboard-product-name: "B75M-D3V" > DMI string baseboard-version: "To be filled by O.E.M." > Found ITE Super I/O, ID 0x8728 on port 0x2e > Found chipset "Intel B75" with PCI ID 8086:1e49. > Enabling flash write... Root Complex Register Block address = 0xfed1c000 > GCS = 0xc64: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 > (SPI) > Top Swap: enabled (A16(+) inverted) > 0xfff80000/0xffb80000 FWH IDSEL: 0x0 > 0xfff00000/0xffb00000 FWH IDSEL: 0x0 > 0xffe80000/0xffa80000 FWH IDSEL: 0x1 > 0xffe00000/0xffa00000 FWH IDSEL: 0x1 > 0xffd80000/0xff980000 FWH IDSEL: 0x2 > 0xffd00000/0xff900000 FWH IDSEL: 0x2 > 0xffc80000/0xff880000 FWH IDSEL: 0x3 > 0xffc00000/0xff800000 FWH IDSEL: 0x3 > 0xff700000/0xff300000 FWH IDSEL: 0x4 > 0xff600000/0xff200000 FWH IDSEL: 0x5 > 0xff500000/0xff100000 FWH IDSEL: 0x6 > 0xff400000/0xff000000 FWH IDSEL: 0x7 > 0xfff80000/0xffb80000 FWH decode enabled > 0xfff00000/0xffb00000 FWH decode enabled > 0xffe80000/0xffa80000 FWH decode enabled > 0xffe00000/0xffa00000 FWH decode enabled > 0xffd80000/0xff980000 FWH decode enabled > 0xffd00000/0xff900000 FWH decode enabled > 0xffc80000/0xff880000 FWH decode enabled > 0xffc00000/0xff800000 FWH decode enabled > 0xff700000/0xff300000 FWH decode enabled > 0xff600000/0xff200000 FWH decode enabled > 0xff500000/0xff100000 FWH decode enabled > 0xff400000/0xff000000 FWH decode enabled > Maximum FWH chip size: 0x100000 bytes > SPI Read Configuration: prefetching enabled, caching enabled, > BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled > SPIBAR = 0xf7795000 + 0x3800 > 0x04: 0xe008 (HSFS) > HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 > Warning: SPI Configuration Lockdown activated. > Reading OPCODES... done > OP Type Pre-OP > op[0]: 0x02, write w/ addr, none > op[1]: 0x03, read w/ addr, none > op[2]: 0x20, write w/ addr, none > op[3]: 0x05, read w/o addr, none > op[4]: 0x9f, read w/o addr, none > op[5]: 0x01, write w/o addr, none > op[6]: 0x00, read w/o addr, none > op[7]: 0x00, read w/o addr, none > Pre-OP 0: 0x06, Pre-OP 1: 0x00 > 0x06: 0x0000 (HSFC) > HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 > 0x08: 0x00000000 (FADDR) > 0x50: 0x0000ffff (FRAP) > BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff > 0x54: 0x00000000 FREG0: Flash Descriptor region > (0x00000000-0x00000fff) is read-write. > 0x58: 0x07ff0000 FREG1: BIOS region (0x00000000-0x007fffff) is read-write. > 0x5C: 0x04ff0001 FREG2: Management Engine region > (0x00001000-0x004fffff) is read-write. > 0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused. > 0x64: 0x00001fff FREG4: Platform Data region is unused. > 0x74: 0x00000000 (PR0 is unused) > 0x78: 0x00000000 (PR1 is unused) > 0x7C: 0x00000000 (PR2 is unused) > 0x80: 0x00000000 (PR3 is unused) > 0x84: 0x00000000 (PR4 is unused) > 0x90: 0x84 (SSFS) > SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 > 0x91: 0xf94240 (SSFC) > SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=2, SME=0, SCF=1 > 0x94: 0x0006 (PREOP) > 0x96: 0x043b (OPTYPE) > 0x98: 0x05200302 (OPMENU) > 0x9C: 0x0000019f (OPMENU+4) > 0xA0: 0x00000000 (BBAR) > 0xC4: 0x00802005 (LVSCC) > LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 > 0xC8: 0x00002005 (UVSCC) > UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 > 0xD0: 0x00000000 (FPB) > Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. > === Content Section === > FLVALSIG 0x0ff0a55a > FLMAP0 0x02040003 > FLMAP1 0x12100206 > FLMAP2 0x00210120 > > --- Details --- > NR (Number of Regions): 3 > FRBA (Flash Region Base Address): 0x040 > NC (Number of Components): 1 > FCBA (Flash Component Base Address): 0x030 > ISL (ICH/PCH Strap Length): 18 > FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 > NM (Number of Masters): 3 > FMBA (Flash Master Base Address): 0x060 > MSL/PSL (MCH/PROC Strap Length): 1 > FMSBA (Flash MCH/PROC Strap Base Address): 0x200 > > === Component Section === > FLCOMP 0x09300024 > FLILL 0x00000000 > > --- Details --- > Component 1 density: 8 MB > Component 2 is not used. > Read Clock Frequency: 20 MHz > Read ID and Status Clock Freq.: 33 MHz > Write and Erase Clock Freq.: 33 MHz > Fast Read is supported. > Fast Read Clock Frequency: 33 MHz > Dual Output Fast Read Support: enabled > No forbidden opcodes. > > === Region Section === > FLREG0 0x00000000 > FLREG1 0x07ff0000 > FLREG2 0x04ff0001 > FLREG3 0x00001fff > FLREG4 0x00001fff > > --- Details --- > Region 0 (Descr.) 0x00000000 - 0x00000fff > Region 1 (BIOS ) 0x00000000 - 0x007fffff > Region 2 (ME ) 0x00001000 - 0x004fffff > Region 3 (GbE ) is unused. > Region 4 (Platf.) is unused. > > === Master Section === > FLMSTR1 0xffff0000 > FLMSTR2 0xffff0000 > FLMSTR3 0xffff0118 > > --- Details --- > Descr. BIOS ME GbE Platf. > BIOS rw rw rw rw rw > ME rw rw rw rw rw > GbE rw rw rw rw rw > > OK. > No IT87* serial flash segment enabled. > The following protocols are supported: FWH, SPI. > Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2017 > Found Macronix flash chip "MX25L6405" (8192 kB, SPI) mapped at > physical address 0xff800000. > Chip status register is 0x00. > Chip status register: Status Register Write Disable (SRWD, SRP, ...) is > not set > Chip status register: Bit 6 is not set > Chip status register: Block Protect 3 (BP3) is not set > Chip status register: Block Protect 2 (BP2) is not set > Chip status register: Block Protect 1 (BP1) is not set > Chip status register: Block Protect 0 (BP0) is not set > Chip status register: Write Enable Latch (WEL) is not set > Chip status register: Write In Progress (WIP/BUSY) is not set > Block protection is disabled. > Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. > Reading old flash chip contents... done. > Erasing and writing flash chip... Trying erase function 0... > 0x000000-0x00ffff:EFAILED at 0x00001000! Expected=0xff, Found=0x20, > failed byte count from 0x00000000-0x0000ffff: 0xb55d > ERASE FAILED! > Reading current flash chip contents... done. Looking for another erase > function. > Trying erase function 1... 0x000000-0x00ffff:EInvalid OPCODE 0x06, > will not execute. > spi_block_erase_d8 failed during command execution at address 0x0 > Reading current flash chip contents... done. Looking for another erase > function. > Trying erase function 2... 0x000000-0x7fffff:EInvalid OPCODE 0x06, > will not execute. > spi_chip_erase_60 failed during command execution > Reading current flash chip contents... done. Looking for another erase > function. > Trying erase function 3... 0x000000-0x7fffff:EInvalid OPCODE 0x06, > will not execute. > spi_chip_erase_c7 failed during command execution > Looking for another erase function. > No usable erase functions left. > FAILED! > Uh oh. Erase/write failed. Checking if anything has changed. > Reading current flash chip contents... done. > Apparently at least some data has changed. > Your flash chip is in an unknown state. > Get help on IRC at chat.freenode.net (channel #flashrom) or > mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! > ------------------------------------------------------------ > ------------------- > DO NOT REBOOT OR POWEROFF! > Restoring MMIO space at 0xf77988a0 > Restoring PCI config space for 00:1f:0 reg 0xdc > > > -- > GNU powered it... > GPL protect it... > God blessing it... > > regards > Shawn > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > https://www.flashrom.org/mailman/listinfo/flashrom >

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FAILED: GA-B75M-D3V
by Shawn 20 Dec '16

20 Dec '16

Hi flashrom maintainers, I failed to write a modified ROM to the flash via internal. Maybe this chipset can only be writable via external programmer? root@sysresccd /root % flashrom -p internal flashrom v0.9.8-r1888 on Linux 4.4.28-std490-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel B75". Enabling flash write... Warning: SPI Configuration Lockdown activated. OK. Found Macronix flash chip "MX25L6405" (8192 kB, SPI) mapped at physical address 0xff800000. Found Macronix flash chip "MX25L6405D" (8192 kB, SPI) mapped at physical address 0xff800000. Found Macronix flash chip "MX25L6406E/MX25L6408E" (8192 kB, SPI) mapped at physical address 0xff800000. Found Macronix flash chip "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E" (8192 kB, SPI) mapped at physical address 0xff800000. Multiple flash chip definitions match the detected chip(s): "MX25L6405", "MX25L6405D", "MX25L6406E/MX25L6408E", "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E" Please specify which chip definition to use with the -c <chipname> option. root@sysresccd /root % flashrom -VV -p internal -c MX25L6405 -w factory_giga1.bin.new.new flashrom v0.9.8-r1888 on Linux 4.4.28-std490-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.4.1, GCC 4.8.5, little endian Command line (7 args): flashrom -VV -p internal -c MX25L6405 -w factory_giga1.bin.new.new Calibrating delay loop... OS timer resolution is 1 usecs, 1944M loops per second, 10 myus = 10 us, 100 myus = 117 us, 1000 myus = 1021 us, 10000 myus = 10021 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Desktop" DMI string system-manufacturer: "Gigabyte Technology Co., Ltd." DMI string system-product-name: "To be filled by O.E.M." DMI string system-version: "To be filled by O.E.M." DMI string baseboard-manufacturer: "Gigabyte Technology Co., Ltd." DMI string baseboard-product-name: "B75M-D3V" DMI string baseboard-version: "To be filled by O.E.M." Found ITE Super I/O, ID 0x8728 on port 0x2e Found chipset "Intel B75" with PCI ID 8086:1e49. Enabling flash write... Root Complex Register Block address = 0xfed1c000 GCS = 0xc64: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 (SPI) Top Swap: enabled (A16(+) inverted) 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x100000 bytes SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled SPIBAR = 0xf7795000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 Warning: SPI Configuration Lockdown activated. Reading OPCODES... done OP Type Pre-OP op[0]: 0x02, write w/ addr, none op[1]: 0x03, read w/ addr, none op[2]: 0x20, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x9f, read w/o addr, none op[5]: 0x01, write w/o addr, none op[6]: 0x00, read w/o addr, none op[7]: 0x00, read w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x00 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write. 0x58: 0x07ff0000 FREG1: BIOS region (0x00000000-0x007fffff) is read-write. 0x5C: 0x04ff0001 FREG2: Management Engine region (0x00001000-0x004fffff) is read-write. 0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00001fff FREG4: Platform Data region is unused. 0x74: 0x00000000 (PR0 is unused) 0x78: 0x00000000 (PR1 is unused) 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) 0x90: 0x84 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf94240 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=2, SME=0, SCF=1 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x0000019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00802005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 0xD0: 0x00000000 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x02040003 FLMAP1 0x12100206 FLMAP2 0x00210120 --- Details --- NR (Number of Regions): 3 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 18 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x09300024 FLILL 0x00000000 --- Details --- Component 1 density: 8 MB Component 2 is not used. Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 33 MHz Write and Erase Clock Freq.: 33 MHz Fast Read is supported. Fast Read Clock Frequency: 33 MHz Dual Output Fast Read Support: enabled No forbidden opcodes. === Region Section === FLREG0 0x00000000 FLREG1 0x07ff0000 FLREG2 0x04ff0001 FLREG3 0x00001fff FLREG4 0x00001fff --- Details --- Region 0 (Descr.) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x00000000 - 0x007fffff Region 2 (ME ) 0x00001000 - 0x004fffff Region 3 (GbE ) is unused. Region 4 (Platf.) is unused. === Master Section === FLMSTR1 0xffff0000 FLMSTR2 0xffff0000 FLMSTR3 0xffff0118 --- Details --- Descr. BIOS ME GbE Platf. BIOS rw rw rw rw rw ME rw rw rw rw rw GbE rw rw rw rw rw OK. No IT87* serial flash segment enabled. The following protocols are supported: FWH, SPI. Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Found Macronix flash chip "MX25L6405" (8192 kB, SPI) mapped at physical address 0xff800000. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set Chip status register: Bit 6 is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Block protection is disabled. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x00ffff:EFAILED at 0x00001000! Expected=0xff, Found=0x20, failed byte count from 0x00000000-0x0000ffff: 0xb55d ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. Trying erase function 1... 0x000000-0x00ffff:EInvalid OPCODE 0x06, will not execute. spi_block_erase_d8 failed during command execution at address 0x0 Reading current flash chip contents... done. Looking for another erase function. Trying erase function 2... 0x000000-0x7fffff:EInvalid OPCODE 0x06, will not execute. spi_chip_erase_60 failed during command execution Reading current flash chip contents... done. Looking for another erase function. Trying erase function 3... 0x000000-0x7fffff:EInvalid OPCODE 0x06, will not execute. spi_chip_erase_c7 failed during command execution Looking for another erase function. No usable erase functions left. FAILED! Uh oh. Erase/write failed. Checking if anything has changed. Reading current flash chip contents... done. Apparently at least some data has changed. Your flash chip is in an unknown state. Get help on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! Restoring MMIO space at 0xf77988a0 Restoring PCI config space for 00:1f:0 reg 0xdc -- GNU powered it... GPL protect it... God blessing it... regards Shawn

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W836xx:Notebook Acer E5-553G-17ZN: flashrom -V
by Martin Vyšohlíd 18 Dec '16

18 Dec '16

flashrom -V[VV] reports attached...

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W836xx: DG965SS: flashrom -V
by Frank Reischl 17 Dec '16

17 Dec '16

*Flash chip is Atmel 26DF081A, I'm finding that I can't read it in-circuit either, with a TL866A programmer and clip. flashrom v0.9.7-r1782 on Linux 3.16.0-4-586 (i686) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.1, GCC 4.8.2, little endian Command line (3 args): flashrom -p internal -V Calibrating delay loop... OS timer resolution is 1 usecs, 2386M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 999 us, 10000 myus = 14067 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Desktop" DMI string system-manufacturer: " " DMI string system-product-name: " " DMI string system-version: " " DMI string baseboard-manufacturer: "Intel Corporation" DMI string baseboard-product-name: "DG965SS" DMI string baseboard-version: "AAD41678-308" W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: f1. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found chipset "Intel ICH8/ICH8R" with PCI ID 8086:2810. Enabling flash write... Root Complex Register Block address = 0xfed1c000 GCS = 0x400464: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x1 (SPI) Top Swap : not enabled 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytesSPI Read Configuration: prefetching disabled, caching enabled, BIOS_CNTL = 0x02: BIOS Lock Enable: enabled, BIOS Write Enable: disabled Warning: Setting Bios Control at 0xdc from 0x02 to 0x01 failed. New value is 0x02. SPIBAR = 0xb77be000 + 0x3020 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 Warning: SPI Configuration Lockdown activated. Reading OPCODES... done 0x06: 0x3f00 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x00ff0035 FREG1: BIOS region (0x00035000-0x000fffff) is read-write. 0x5C: 0x00340003 FREG2: Warning: Management Engine region (0x00003000-0x00034fff) is locked. 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write. Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see http://flashrom.org/ME for details. Writes have been disabled for safety reasons. You can enforce write support with the ich_spi_force programmer option, but you will most likely harm your hardware! If you force flashrom you will get no support if something breaks. On a few mainboards it is possible to enable write access by setting a jumper (see its documentation or the board itself). 0x90: 0x00 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0x91: 0x004024 (SSFC) SSFC: SCGO=0, ACS=1, SPOP=0, COP=2, DBC=0, SME=0, SCF=0 0x94: 0x0000 (PREOP) 0x96: 0x0008 (OPTYPE) 0x98: 0x0000ab9f (OPMENU) 0x9C: 0x00000000 (OPMENU+4) 0xC1: 0xffffffff (VSCC) VSCC: BES=0x3, WG=1, WSR=1, WEWS=1, EO=0xff, VCL=1 Enabling hardware sequencing because some important opcode is locked. PROBLEMS, continuing anyway The following protocols are supported: FWH, Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Found 1 attached SPI flash chip with a density of 1024 kB. There is only one partition containing the whole address space (0x000000 - 0x0fffff). There are 256 erase blocks with 4096 B each. Found Programmer flash chip "Opaque flash chip" (1024 kB, Programmer-specific) at physical address 0x0. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x77, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x77, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x77, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x60, id2 0x7c, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x77, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x77, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Programmer flash chip "Opaque flash chip" (1024 kB, Programmer-specific). No operations were specified. Restoring PCI config space for 00:1f:0 reg 0xdc

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New SPI NAND Flash product Support
by Victor Lim 14 Dec '16

14 Dec '16

Hi, Hatim, How are you doing? I would like to ask for your help to include the following Gigadevice SPI NAND into the FlashRom support. These are the part #s, GD25F1GQ4UCYIG GD25F2GQ4UCYIG GD25F4GQ4UCYIG GD25F1GQ4RCYIG GD25F2GQ4RCYIG GD25F4GQ4RCYIG GD25F1GQ4UBYIG GD25F2GQ4UBYIG GD25F4GQ4UBYIG GD25F1GQ4RBYIG GD25F2GQ4RBYIG GD25F4GQ4RBYIG This is the link to the datasheet. http://www.gigadevice.com/product-series/7.html?locale=en_US Thanks, Victor Lim (Gigadevice/MK IV/FAE Manager) Gigadevice Semiconductor Inc. Tel: 408-855-8336 Mobile: 408-883-3856 Website: http://us.gigadevice.com This email was sent to you by GigaDevice, A Global Innovative Memory Architect The information contained in this e-mail message (and any attachment transmitted herewith) is privileged and confidential and is intended for the exclusive use of the addressee(s). If you are not an intended addressee, any disclosure, reproduction, distribution or other dissemination or use of this communication is strictly prohibited. If you have received this communication in error, please delete this communication and contact us by replying to this e-mail immediately. -----Original Message----- From: Hatim Kanchwala [mailto:hatim@hatimak.me] Sent: Friday, March 25, 2016 1:27 PM To: Victor Lim <vlim(a)gigadevice.com> Cc: flashrom(a)flashrom.org; ksong(a)gigadevice.com Subject: Re: [flashrom] New SPI NOR Flash product Support Hello Victor, I am doing fine, thanks :) The following chips have been tested successfully - GD25D05B/10B, GD25LQ10B/20B/40B/80B, GD25Q21B/41B and GD25VQ41B (reported by David Hendrix). Test logs for the first 8 of these chips can be found here - https://www.flashrom.org/pipermail/flashrom/2016-March/014537.html. The patches for all these chips and additionally GD25Q80C/16C have been sent and are waiting for further review. I have ordered some IC clips, so I will test the remaining chips as soon as those arrive. Unfortunately, one of the chips you explicitly requested support for, GD25Q128C was not included in the samples so was not tested. But support for it has already been added ;) Apologies for the late reply. :) On Tuesday 22 March 2016 01:20 AM, Victor Lim wrote: > Hi, Hatim, > > How are you doing? Hope all the sample test results are good. > Can you please update the status so that I can ask customer to try out. > > Regards, > > Victor > > > > -----Original Message----- > From: Hatim Kanchwala [mailto:hatim@hatimak.me] > Sent: Wednesday, February 24, 2016 9:02 AM > To: Victor Lim <vlim(a)gigadevice.com> > Cc: flashrom(a)flashrom.org; ksong(a)gigadevice.com > Subject: Re: [flashrom] New SPI NOR Flash product Support > > Hello Victor, > > Support for two chips you requested was added some time ago in r1937 > (look here https://tracker.coreboot.org/trac/flashrom/changeset/1937). > I am waiting for samples to perform tests. FedEx was in touch > regarding documents for customs clearance, so delivery should be in a > day or two. In the meanwhile I am working on support for other > GigaDevice chips (http://www.gigadevice.com/product-series/12.html). > > On Wednesday 24 February 2016 04:47 AM, Victor Lim wrote: >> Hi, Hatim, >> >> How is the new program to include these two part #? >> I have sent the samples to you, but they are held up at the Fedex >> facility at New Delhi. >> Can you please give Fedex the instruction for delivery? >> The tracking # is 806824856677 >> >> Regards, >> >> Victor >> >> >> >> >> -----Original Message----- >> From: Victor Lim [mailto:vlim@gigadevice.com] >> Sent: Tuesday, February 9, 2016 3:02 PM >> To: 'Hatim Kanchwala' <hatim(a)hatimak.me> >> Cc: 'flashrom(a)flashrom.org' <flashrom(a)flashrom.org> >> Subject: RE: [flashrom] New SPI NOR Flash product Support >> >> Thanks, Hatim, >> >> Please help me on these two part #s, datasheets are attached. >> 1) GD25VQ41B >> 2) GD25Q128C >> >> Can you provide the ship to address, I will send you same samples. >> What package type do you prefer? >> >> Regards, >> >> Victor >> >> >> >> -----Original Message----- >> From: Hatim Kanchwala [mailto:hatim@hatimak.me] >> Sent: Tuesday, February 9, 2016 12:27 PM >> To: Victor Lim <vlim(a)gigadevice.com> >> Cc: flashrom(a)flashrom.org >> Subject: Re: [flashrom] New SPI NOR Flash product Support >> >> Hello Victor, >> >> I have recently started looking at flashrom and have contributed by >> adding a few SPI flashchip definitions. I would be glad to add >> support for the SPI chips. Usually datasheets are sufficient for >> adding flashchip support (as long as datasheets convey full >> information on functionality). However, the chips remain untested. I >> would be glad to test them as well if you are willing to provide >> samples (I am at a University, so I have access to a lab with equipment for testing). >> >> On Wednesday 10 February 2016 12:18 AM, Victor Lim wrote: >>> Hi, Flashrom team, >>> >>> >>> >>> I am the FAE manager for Gigadevice and would like to know how I can >>> work >> with you to add our part # to your support list. >>> >>> A customer of mine is looking to program our GD25VQ41B with your >>> tool and >> found that it is not supported by your tools. >>> >>> It would like grateful if you can support our entire SPI NOR portfolio. >>> >>> >>> >>> Regards, >>> >>> >>> >>> Victor Lim(Gigadevice/MK IV/FAE Manager) >>> >>> >>> >>> Gigadevice Semiconductor Inc. >>> >>> Tel: 408-855-8336 >>> Mobile: 408-883-3856 >>> >>> Website: www.gigadevice.com <http://www.gigadevice.com/> >>> >>> 2975 Bowers Ave,Suite 323 >>> >>> Santa Clara, CA 95051, USA >>> >>> >>> >>> This email was sent to you by GigaDevice, A Global Innovative Memory >> Architect >>> >>> >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> -- >>> >>> The information contained in this e-mail message (and any attachment >> transmitted herewith) is privileged and confidential and is intended >> for the exclusive use of the addressee(s). If you are not an intended >> addressee, any disclosure, reproduction, distribution or other >> dissemination or use of this communication is strictly prohibited. If >> you have received this communication in error, please delete this >> communication and contact us by replying to this e-mail immediately. >>> >>> >>> >>> >>> >>> _______________________________________________ >>> flashrom mailing list >>> flashrom(a)flashrom.org >>> http://www.flashrom.org/mailman/listinfo/flashrom >>> >> > > -- > Kind Regards, > Hatim Kanchwala > http://hatimak.me > B. Tech. Electrical Engineering > Indian Institute of Technology Patna > > -- Kind Regards, Hatim Kanchwala http://hatimak.me B. Tech. Electrical Engineering Indian Institute of Technology Patna

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