flashrom

flashrom@flashrom.org

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9161 discussions

Bug report and questions - GA-G41M-ES2L under Debian Jessie Amd64
by Alapi Zsolt 28 Mar '17

28 Mar '17

Dear Flashrom Hackers, I wanted to put Libreboot for my GA-G41M-ES2L motherboard, I downloaded the newest Libreboot rom and burned into the flashchip from Debian Jessie, unfortunately my system don't boot anymore. I have a backup from vendor BIOS from the 2 BIOS chips, I had made it before flashing. I know, I shouldn't reboot after this message(below the email) but I do that, it was a mistake. What was the problem: 1. Flashrom bug ? 2. Bad Libreboot rom file ? ---- I bought another GA-G41M-ES2L motherboard. I plan to put a Coreboot to that with the latest flasrom. I compile everything based on coreboot wiki. https://www.coreboot.org/Board:gigabyte/ga-g41m-es2l 3. What do you suggest I do or I don't ? 4. Flashrom will kill the second one motherboard too ? 5. For the old one can I buy flashrom chips anywhere on the net ? (I can't use external programmer, but I know guy who can change the bad chip to a new one.) ----------- I plan a 2. coreboot machine this board is: GA-945GCM-S2L motherboard. 6. Can I put a coreboot for that based this action on Coreboot wiki ? https://www.coreboot.org/Board:gigabyte/ga-945gcm-s2l Thanks for your help! Zsolt ---------------------------------------------------------------------------------------------------------------------------------------------------------------- root@debian:/home/zsolt/BACKUP# flashrom -p internal:dualbiosindex=0 -w ga-g41m-es2l_usqwerty_txtmode.rom flashrom v0.9.7-r1782 on Linux 3.16.0-4-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel ICH7/ICH7R". Enabling flash write... OK. DualBIOS: Selected chip: 0 Found Macronix flash chip "MX25L8005/MX25V8005" (1024 kB, SPI) at physical address 0xfff00000. Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. root@debian:/home/zsolt/BACKUP# flashrom -p internal:dualbiosindex=1 -w ga-g41m-es2l_usqwerty_txtmode.rom flashrom v0.9.7-r1782 on Linux 3.16.0-4-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel ICH7/ICH7R". Enabling flash write... OK. DualBIOS: Selected chip: 1 Found Macronix flash chip "MX25L8005/MX25V8005" (1024 kB, SPI) at physical address 0xfff00000. Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED.

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REPORT: Dell Inspiron 7548 (Read) (Failure)
by Umang Raghuvanshi 28 Mar '17

28 Mar '17

flashrom v0.9.9-r1955 on Linux 4.10.3-1-zen (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.4.1, GCC 5.3.0, little endian Command line (5 args): flashrom -r test --programmer internal -VV Calibrating delay loop... OS timer resolution is 1 usecs, 2662M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 990 us, 10000 myus = 9914 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. Using Internal DMI decoder. No DMI table found. W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 85. Found ITE EC, ID 0x8528, Rev 0x0a on port 0x4e. Found chipset "Intel Broadwell U Premium" with PCI ID 8086:9cc3. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... Root Complex Register Block address = 0xfed1c000 GCS = 0x61: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (LPC) Top Swap: enabled (A16(+) inverted) 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x100000 bytes SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled SPIBAR = 0x00007fc4b0c76000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 Reading OPCODES... done OP Type Pre-OP op[0]: 0x02, write w/ addr, none op[1]: 0x3b, read w/ addr, none op[2]: 0x20, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x9f, read w/o addr, none op[5]: 0x01, write w/o addr, none op[6]: 0x00, read w/o addr, none op[7]: 0x00, read w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x00 0x06: 0x3f00 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0 0x08: 0x00001000 (FADDR) 0x50: 0x00004a4b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x4a, BRRA 0x4b 0x54: 0x00000000 0x58: 0x07ff01a0 FREG1: BIOS region (0x001a0000-0x007fffff) is read-write. 0x5C: 0x019f0001 0x60: 0x00007fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00007fff FREG4: Platform Data region is unused. 0x74: 0x00000000 (PR0 is unused) 0x78: 0x00000000 (PR1 is unused) 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) Writes have been disabled for safety reasons. You can enforce write support with the ich_spi_force programmer option, but you will most likely harm your hardware! If you force flashrom you will get no support if something breaks. On a few mainboards it is possible to enable write access by setting a jumper (see its documentation or the board itself). 0x90: 0xc0 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0x91: 0xf84010 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=0, SME=0, SCF=0 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05203b02 (OPMENU) 0x9C: 0x0000019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x80802025 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xC8: 0x00002025 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 0xD0: 0x50444653 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x02040003 FLMAP1 0x15100206 FLMAP2 0x00210120 --- Details --- NR (Number of Regions): 3 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 21 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x40300044 FLILL 0xad604221 --- Details --- Component 1 density: 8 MB Component 2 is not used. Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 20 MHz Write and Erase Clock Freq.: 20 MHz Fast Read is supported. Fast Read Clock Frequency: 33 MHz Dual Output Fast Read Support: disabled Invalid instruction 0: 0x21 Invalid instruction 1: 0x42 Invalid instruction 2: 0x60 Invalid instruction 3: 0xad === Region Section === FLREG0 0x00000000 FLREG1 0x07ff01a0 FLREG2 0x019f0001 FLREG3 0x00007fff FLREG4 0x00007fff --- Details --- Region 0 (Descr.) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x001a0000 - 0x007fffff Region 2 (ME ) 0x00001000 - 0x0019ffff Region 3 (GbE ) is unused. Region 4 (Platf.) is unused. === Master Section === FLMSTR1 0x0a0b0000 FLMSTR2 0x0c0d0000 FLMSTR3 0x08080118 --- Details --- Descr. BIOS ME GbE Platf. BIOS r rw rw ME r rw rw GbE rw Enabling hardware sequencing because some important opcode is locked. OK. Super I/O ID 0x8528 is not on the list of flash-capable controllers. The following protocols are supported: FWH, Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Hardware sequencing reports 1 attached SPI flash chip with a density of 8192 kB. The flash address space (0x000000 - 0x7fffff) is divided at address 0x653000 in two partitions. The first partition ranges from 0x000000 to 0x652fff. In that range are 1619 erase blocks with 4096 B each. The second partition ranges from 0x653000 to 0x7fffff. In that range are 429 erase blocks with 4096 B each. Found Programmer flash chip "Opaque flash chip" (8192 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH00B4, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH004, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xf3, id2 0xab, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xf3, id2 0xab, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xf3, id2 0xab, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xf3, id2 0xab, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xf3, id2 0xab, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xf3, id2 0xab, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xf3, id2 0xab, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xf3, id2 0xab, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Programmer flash chip "Opaque flash chip" (8192 kB, Programmer-specific). Reading flash... Reading 8388608 bytes starting at 0x000000. HSFS: FDONE=1, FCERR=1, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0 FAILED. Restoring MMIO space at 0x7fc4b0c798a0 -- Cheers, Umang Raghuvanshi.

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Re: [flashrom] Fwd: Re: Problem with flashrom and FT2232 Port B
by Nico Huber 28 Mar '17

28 Mar '17

Hi Zak, please always keep the mailing list in CC, you will get less attention otherwise. On 23.03.2017 12:16, Nico Huber wrote: > > -------- Forwarded Message -------- > Subject: Re: [flashrom] Problem with flashrom and FT2232 Port B > Date: Wed, 22 Mar 2017 18:01:18 +0100 > From: Zak <zackwarrior(a)gmail.com> > To: Nico Huber <nico.huber(a)secunet.com> > > Yeah of course if another program is trying to access the device it can > explain the error but i would not be able to get the port a either, > since the device is used with another app, and i tryed it on few > different computers and still get the same error I was just guessing. The FT2232H has two separate USB interfaces, but maybe it's impossible to block one interface without the other, idk. > > It's only on the port B, I already submitted this error a year aggo or > more but wasn't patched It's working fine on ArchLinux here (see attached log). I don't have access to a Windows installation and no intend to fix anything there. It's possible that you ask for something that only you are interested in. I guess you have to fix it by yourself then. Nico

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Flash Access on Shuttle XH170V failed
by Michael Fuckner 27 Mar '17

27 Mar '17

Hi, I added PCI ID for my chipset, but I can't access/ read FLash chip. Any idea how to proceed? Regards, Michael! [root@revo flashrom]# diff chipset_enable.c.bak chipset_enable.c 1783a1784 > {0x8086, 0xa144, NT, "Intel", "Sunrise Point-H", enable_flash_pch9}, ------------------------------------------------------- [root@revo flashrom]# ./flashrom -V -p internal flashrom v0.9.9-r1954 on Linux 4.9.13-201.fc25.x86_64 (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.5.4, GCC 6.3.1 20161221 (Red Hat 6.3.1-1), little endian Command line (3 args): ./flashrom -V -p internal Calibrating delay loop... OS timer resolution is 1 usecs, 2789M loops per second, 10 myus = 10 us, 100 myus = 104 us, 1000 myus = 1014 us, 10000 myus = 10007 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Desktop" DMI string system-manufacturer: "Shuttle Inc." DMI string system-product-name: "XH170" DMI string system-version: "V1.0" DMI string baseboard-manufacturer: "Shuttle Inc." DMI string baseboard-product-name: "FH170" DMI string baseboard-version: "1.0" Found ITE Super I/O, ID 0x8772 on port 0x2e Found chipset "Intel Sunrise Point-H" with PCI ID 8086:a144. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... Root Complex Register Block address = 0x0 Error accessing ICH RCRB, 0x4000 bytes at 0x0000000000000000 /dev/mem mmap failed: Resource temporarily unavailable FAILED! FATAL ERROR! Error: Programmer initialization failed.

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[PATCH v2] nicintel_eeprom: Support for I210 emulated EEprom
by Ricardo Ribalda Delgado 23 Mar '17

23 Mar '17

On the I210 family there is no MAC EEprom, instead there is a big flash (typically around 16Mb) with contents of the old MAC plus other stuff. There is an interface to program the whole flash, but once it is programmed it enters a "Secure Mode" that disables the interface. Luckily, the section with the MAC can still be updated via the EEprom interface. This patch adds support for this interface. root@qt5022-fglrx:~# ./flashrom -p nicintel_eeprom:pci=01:0.0 -w kk.raw -V flashrom v0.9.9-unknown on Linux 4.10.0-qtec-standard (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.4.1, GCC 5.3.0, little endian Command line (5 args): ./flashrom -p nicintel_eeprom:pci=01:0.0 -w kk.raw -V Calibrating delay loop... OS timer resolution is 1 usecs, 1856M loops per second, 10 myus = 10 us, 100 myus = 102 us, 1000 myus = 1017 us, 10000 myus = 10044 us, 4 myus = 4 us, OK. Initializing nicintel_eeprom programmer Found "Intel I210 Gigabit Network Connection" (8086:1533, BDF 01:00.0). Requested BAR is of type MEM, 32bit, not prefetchable Requested BAR is of type MEM, 32bit, not prefetchable The following protocols are supported: Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Found Programmer flash chip "Opaque flash chip" (4 kB, Programmer-specific) on nicintel_eeprom. Found Programmer flash chip "Opaque flash chip" (4 kB, Programmer-specific). Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:W Erase/write done. Verifying flash... VERIFIED. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- v2: Please completely ignore v1. nicintel_eeprom.c | 174 ++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 168 insertions(+), 6 deletions(-) diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index b5d4202b01e0..a63e937f1ce4 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -25,6 +25,12 @@ * 4.7: Access to shared resources (FIXME: we should probably use this semaphore interface) * 7.4: Register Descriptions */ +/* + * Datasheet: Intel Ethernet Controller I210: Datasheet + * 8.4.3: EEPROM-Mode Read Register + * 8.4.6: EEPROM-Mode Write Register + * Write process inspired on kernel e1000_i210.c + */ #include <stdlib.h> #include <unistd.h> @@ -34,10 +40,11 @@ #include "hwaccess.h" #define PCI_VENDOR_ID_INTEL 0x8086 -#define MEMMAP_SIZE (0x14 + 3) /* Only EEC and EERD are needed. */ +#define MEMMAP_SIZE 0x1c /* Only EEC, EERD and EEWR are needed. */ #define EEC 0x10 /* EEPROM/Flash Control Register */ #define EERD 0x14 /* EEPROM Read Register */ +#define EEWR 0x18 /* EEPROM Write Register */ /* EPROM/Flash Control Register bits */ #define EE_SCK 0 @@ -49,6 +56,8 @@ #define EE_PRES 8 #define EE_SIZE 11 #define EE_SIZE_MASK 0xf +#define EE_FLUPD 23 +#define EE_FLUDONE 26 /* EEPROM Read Register bits */ #define EERD_START 0 @@ -56,11 +65,18 @@ #define EERD_ADDR 2 #define EERD_DATA 16 +/* EEPROM Write Register bits */ +#define EEWR_CMDV 0 +#define EEWR_DONE 1 +#define EEWR_ADDR 2 +#define EEWR_DATA 16 + #define BIT(x) (1<<x) #define EE_PAGE_MASK 0x3f static uint8_t *nicintel_eebar; static struct pci_dev *nicintel_pci; +static bool done_i20_write = false; #define UNPROG_DEVICE 0x1509 @@ -71,10 +87,35 @@ const struct dev_entry nics_intel_ee[] = { {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Ext. PHY)"}, {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Dual Gigabit Ethernet Controller (Copper)"}, {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"}, + {PCI_VENDOR_ID_INTEL, 0x1531, NT, "Intel", "I210 Gigabit Network Connection Unprogrammed"}, + {PCI_VENDOR_ID_INTEL, 0x1532, NT, "Intel", "I211 Gigabit Network Connection Unprogrammed"}, + {PCI_VENDOR_ID_INTEL, 0x1533, OK, "Intel", "I210 Gigabit Network Connection"}, + {PCI_VENDOR_ID_INTEL, 0x1536, NT, "Intel", "I210 Gigabit Network Connection SERDES Fiber"}, + {PCI_VENDOR_ID_INTEL, 0x1537, NT, "Intel", "I210 Gigabit Network Connection SERDES Backplane"}, + {PCI_VENDOR_ID_INTEL, 0x1538, NT, "Intel", "I210 Gigabit Network Connection SGMII"}, + {PCI_VENDOR_ID_INTEL, 0x1539, NT, "Intel", "I211 Gigabit Network Connection"}, {0}, }; -static int nicintel_ee_probe(struct flashctx *flash) +static inline bool is_i210(uint16_t device_id) +{ + return (device_id & 0xff00) == 0x1500; +} + +static int nicintel_ee_probe_i210(struct flashctx *flash) +{ + /* Emulated eeprom has a fixed size of 4 KB */ + flash->chip->total_size = 4; + flash->chip->page_size = flash->chip->total_size * 1024; + flash->chip->tested = TEST_OK_PREW; + flash->chip->gran = write_gran_1byte_implicit_erase; + flash->chip->block_erasers->eraseblocks[0].size = flash->chip->page_size; + flash->chip->block_erasers->eraseblocks[0].count = 1; + + return 1; +} + +static int nicintel_ee_probe_82580(struct flashctx *flash) { if (nicintel_pci->device_id == UNPROG_DEVICE) flash->chip->total_size = 16; /* Fall back to minimum supported size. */ @@ -103,6 +144,15 @@ static int nicintel_ee_probe(struct flashctx *flash) return 1; } +static int nicintel_ee_probe(struct flashctx *flash) +{ + if (is_i210(nicintel_pci->device_id)) + return nicintel_ee_probe_i210(flash); + + return nicintel_ee_probe_82580(flash); +} + +#define MAX_ATEMPTS 10000000 static int nicintel_ee_read_word(unsigned int addr, uint16_t *data) { uint32_t tmp = BIT(EERD_START) | (addr << EERD_ADDR); @@ -110,7 +160,7 @@ static int nicintel_ee_read_word(unsigned int addr, uint16_t *data) /* Poll done flag. 10.000.000 cycles seem to be enough. */ uint32_t i; - for (i = 0; i < 10000000; i++) { + for (i = 0; i < MAX_ATEMPTS; i++) { tmp = pci_mmio_readl(nicintel_eebar + EERD); if (tmp & BIT(EERD_DONE)) { *data = (tmp >> EERD_DATA) & 0xffff; @@ -151,6 +201,83 @@ static int nicintel_ee_read(struct flashctx *flash, uint8_t *buf, unsigned int a return 0; } +static int nicintel_ee_write_word_i210(unsigned int addr, uint16_t data) +{ + uint32_t eewr; + + eewr = addr << EEWR_ADDR; + eewr |= data << EEWR_DATA; + eewr |= BIT(EEWR_CMDV); + pci_mmio_writel(eewr, nicintel_eebar + EEWR); + + programmer_delay(5); + for (int i = 0; i < MAX_ATEMPTS; i++) + if (pci_mmio_readl(nicintel_eebar + EEWR) & BIT(EEWR_DONE)) + return 0; + return -1; +} + +static int nicintel_ee_write_i210(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) +{ + done_i20_write = true; + + if (addr & 1) { + uint16_t data; + + if (nicintel_ee_read_word(addr / 2, &data)) { + msg_perr("Timeout reading heading byte\n"); + return -1; + } + + data &= 0xff; + data |= (buf ? (buf[0]) : 0xff) << 8; + + if (nicintel_ee_write_word_i210(addr / 2, data)) { + msg_perr("Timeout writing heading word\n"); + return -1; + } + + if (buf) + buf ++; + addr ++; + len --; + } + + while (len > 0) { + uint16_t data; + + if (len == 1) { + if (nicintel_ee_read_word(addr / 2, &data)) { + msg_perr("Timeout reading tail byte\n"); + return -1; + } + + data &= 0xff00; + data |= buf ? (buf[0]) : 0xff; + } else { + if (buf) + data = buf[0] | (buf[1] << 8); + else + data = 0xffff; + } + + if (nicintel_ee_write_word_i210(addr / 2, data)) { + msg_perr("Timeout writing Shadow RAM\n"); + return -1; + } + + if (buf) + buf += 2; + if (len > 2) + len -= 2; + else + len = 0; + addr += 2; + } + + return 0; +} + static int nicintel_ee_bitset(int reg, int bit, bool val) { uint32_t tmp; @@ -224,7 +351,7 @@ static int nicintel_ee_req(void) return 0; } -static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) +static int nicintel_ee_write_82580(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) { if (nicintel_ee_req()) return -1; @@ -262,6 +389,13 @@ out: nicintel_ee_bitset(EEC, EE_REQ, 0); /* Give up direct access. */ return ret; } +static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) +{ + if (is_i210(nicintel_pci->device_id)) + return nicintel_ee_write_i210(flash, buf, addr, len); + + return nicintel_ee_write_82580(flash, buf, addr, len); +} static int nicintel_ee_erase(struct flashctx *flash, unsigned int addr, unsigned int len) { @@ -275,6 +409,25 @@ static const struct opaque_master opaque_master_nicintel_ee = { .erase = nicintel_ee_erase, }; +static int nicintel_ee_shutdown_i210(void *arg) +{ + if (!done_i20_write) + return 0; + + uint32_t flup = pci_mmio_readl(nicintel_eebar + EEC); + + flup |= BIT(EE_FLUPD); + pci_mmio_writel(flup, nicintel_eebar + EEC); + + for (int i = 0; i < MAX_ATEMPTS; i++) + if (pci_mmio_readl(nicintel_eebar + EEC) & BIT(EE_FLUDONE)) + return 0; + + msg_perr("Flash update failed\n"); + + return -1; +} + static int nicintel_ee_shutdown(void *eecp) { uint32_t old_eec = *(uint32_t *)eecp; @@ -306,9 +459,14 @@ int nicintel_ee_init(void) if (!io_base_addr) return 1; - nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", io_base_addr, MEMMAP_SIZE); + nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", + io_base_addr + (is_i210(dev->device_id) ? 0x12000 : 0), MEMMAP_SIZE); + if (!nicintel_eebar) + return 1; + nicintel_pci = dev; - if (dev->device_id != UNPROG_DEVICE) { + if ((dev->device_id != UNPROG_DEVICE) && ! is_i210(dev->device_id)) + { uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting the EE_PRES definition), @@ -327,5 +485,9 @@ int nicintel_ee_init(void) return 1; } + if (is_i210(dev->device_id)) + if (register_shutdown(nicintel_ee_shutdown_i210, NULL)) + return 1; + return register_opaque_master(&opaque_master_nicintel_ee); } -- 2.11.0

1 0

[PATCH] nicintel_eeprom: Support for I210 emulated EEprom
by Ricardo Ribalda Delgado 23 Mar '17

23 Mar '17

On the I210 family there is no MAC EEprom, instead there is a big flash (typically around 16Mb) with contents of the old MAC plus other stuff. There is an interface to program the whole flash, but once it is programmed it enters a "Secure Mode" that disables the interface. Luckily, the section with the MAC can still be updated via the EEprom interface. This patch adds support for this interface. root@qt5022-fglrx:~# ./flashrom -p nicintel_eeprom:pci=01:0.0 -w kk.raw -V flashrom v0.9.9-unknown on Linux 4.10.0-qtec-standard (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.4.1, GCC 5.3.0, little endian Command line (5 args): ./flashrom -p nicintel_eeprom:pci=01:0.0 -w kk.raw -V Calibrating delay loop... OS timer resolution is 1 usecs, 1856M loops per second, 10 myus = 10 us, 100 myus = 102 us, 1000 myus = 1017 us, 10000 myus = 10044 us, 4 myus = 4 us, OK. Initializing nicintel_eeprom programmer Found "Intel I210 Gigabit Network Connection" (8086:1533, BDF 01:00.0). Requested BAR is of type MEM, 32bit, not prefetchable Requested BAR is of type MEM, 32bit, not prefetchable The following protocols are supported: Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Found Programmer flash chip "Opaque flash chip" (4 kB, Programmer-specific) on nicintel_eeprom. Found Programmer flash chip "Opaque flash chip" (4 kB, Programmer-specific). Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:W Erase/write done. Verifying flash... VERIFIED. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- nicintel_eeprom.c | 172 ++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 166 insertions(+), 6 deletions(-) diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index b5d4202b01e0..77754f0f2534 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -25,6 +25,12 @@ * 4.7: Access to shared resources (FIXME: we should probably use this semaphore interface) * 7.4: Register Descriptions */ +/* + * Datasheet: Intel Ethernet Controller I210: Datasheet + * 8.4.3: EEPROM-Mode Read Register + * 8.4.6: EEPROM-Mode Write Register + * Write process inspired on kernel e1000_i210.c + */ #include <stdlib.h> #include <unistd.h> @@ -34,10 +40,11 @@ #include "hwaccess.h" #define PCI_VENDOR_ID_INTEL 0x8086 -#define MEMMAP_SIZE (0x14 + 3) /* Only EEC and EERD are needed. */ +#define MEMMAP_SIZE 0x1c /* Only EEC, EERD and EEWR are needed. */ #define EEC 0x10 /* EEPROM/Flash Control Register */ #define EERD 0x14 /* EEPROM Read Register */ +#define EEWR 0x18 /* EEPROM Write Register */ /* EPROM/Flash Control Register bits */ #define EE_SCK 0 @@ -49,6 +56,8 @@ #define EE_PRES 8 #define EE_SIZE 11 #define EE_SIZE_MASK 0xf +#define EE_FLUPD 23 +#define EE_FLUDONE 26 /* EEPROM Read Register bits */ #define EERD_START 0 @@ -56,11 +65,18 @@ #define EERD_ADDR 2 #define EERD_DATA 16 +/* EEPROM Write Register bits */ +#define EEWR_CMDV 0 +#define EEWR_DONE 1 +#define EEWR_ADDR 2 +#define EEWR_DATA 16 + #define BIT(x) (1<<x) #define EE_PAGE_MASK 0x3f static uint8_t *nicintel_eebar; static struct pci_dev *nicintel_pci; +static bool done_i20_write = false; #define UNPROG_DEVICE 0x1509 @@ -71,10 +87,35 @@ const struct dev_entry nics_intel_ee[] = { {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Ext. PHY)"}, {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Dual Gigabit Ethernet Controller (Copper)"}, {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"}, + {PCI_VENDOR_ID_INTEL, 0x1531, NT, "Intel", "I210 Gigabit Network Connection Unprogrammed"}, + {PCI_VENDOR_ID_INTEL, 0x1532, NT, "Intel", "I211 Gigabit Network Connection Unprogrammed"}, + {PCI_VENDOR_ID_INTEL, 0x1533, OK, "Intel", "I210 Gigabit Network Connection"}, + {PCI_VENDOR_ID_INTEL, 0x1536, NT, "Intel", "I210 Gigabit Network Connection SERDES Fiber"}, + {PCI_VENDOR_ID_INTEL, 0x1537, NT, "Intel", "I210 Gigabit Network Connection SERDES Backplane"}, + {PCI_VENDOR_ID_INTEL, 0x1538, NT, "Intel", "I210 Gigabit Network Connection SGMII"}, + {PCI_VENDOR_ID_INTEL, 0x1539, NT, "Intel", "I211 Gigabit Network Connection"}, {0}, }; -static int nicintel_ee_probe(struct flashctx *flash) +static inline bool is_i210(uint16_t device_id) +{ + return (device_id & 0xff00) == 0x1500; +} + +static int nicintel_ee_probe_i210(struct flashctx *flash) +{ + /* Emulated eeprom has a fixed size of 4 KB */ + flash->chip->total_size = 4; + flash->chip->page_size = flash->chip->total_size * 1024; + flash->chip->tested = TEST_OK_PREW; + flash->chip->gran = write_gran_1byte_implicit_erase; + flash->chip->block_erasers->eraseblocks[0].size = flash->chip->page_size; + flash->chip->block_erasers->eraseblocks[0].count = 1; + + return 1; +} + +static int nicintel_ee_probe_82580(struct flashctx *flash) { if (nicintel_pci->device_id == UNPROG_DEVICE) flash->chip->total_size = 16; /* Fall back to minimum supported size. */ @@ -103,6 +144,15 @@ static int nicintel_ee_probe(struct flashctx *flash) return 1; } +static int nicintel_ee_probe(struct flashctx *flash) +{ + if (is_i210(nicintel_pci->device_id)) + return nicintel_ee_probe_i210(flash); + + retirm nicintel_ee_probe_82580(flash); +} + +#define MAX_ATEMPTS 10000000 static int nicintel_ee_read_word(unsigned int addr, uint16_t *data) { uint32_t tmp = BIT(EERD_START) | (addr << EERD_ADDR); @@ -110,7 +160,7 @@ static int nicintel_ee_read_word(unsigned int addr, uint16_t *data) /* Poll done flag. 10.000.000 cycles seem to be enough. */ uint32_t i; - for (i = 0; i < 10000000; i++) { + for (i = 0; i < MAX_ATEMPTS; i++) { tmp = pci_mmio_readl(nicintel_eebar + EERD); if (tmp & BIT(EERD_DONE)) { *data = (tmp >> EERD_DATA) & 0xffff; @@ -151,6 +201,80 @@ static int nicintel_ee_read(struct flashctx *flash, uint8_t *buf, unsigned int a return 0; } +static int nicintel_ee_write_word_i210(struct flashctx *flash, unsigned int addr, uint16_t data) +{ + uint32_t eewr; + + eewr = (addr/2) << EEWR_ADDR; + eewr |= data << EEWR_DATA; + eewr |= BIT(EEWR_CMDV); + pci_mmio_writel(eewr, nicintel_eebar + EEWR); + + programmer_delay(5); + for (int i = 0; i < MAX_ATEMPTS; i++) + if (pci_mmio_readl(nicintel_eebar + EEWR) & BIT(EEWR_DONE)) + return 0; + return -1; +} + +static int nicintel_ee_write_i210(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) +{ + done_i20_write = true; + + if (addr & 1) { + uint16_t data; + + if (nicintel_ee_read_word(addr-1, &data)) { + msg_perr("Timeout reading heading byte\n"); + return -1; + } + + data &= 0xff; + data |= (buf ? (buf[0]) : 0xff) << 8; + + if (nicintel_ee_write_word_i210(flash, addr-1, data)) { + msg_perr("Timeout writing heading word\n"); + return -1; + } + + if (buf) + buf ++; + addr ++; + len ++; + } + + while (len > 0) { + uint16_t data; + + if (len == 1) { + if (nicintel_ee_read_word(addr-1, &data)) { + msg_perr("Timeout reading tail byte\n"); + return -1; + } + + data &= 0xff00; + data |= buf ? (buf[0]) : 0xff; + } else { + if (buf) + data = buf[0] | (buf[1] << 8); + else + data = 0xffff; + } + + if (nicintel_ee_write_word_i210(flash, addr, data)) { + msg_perr("Timeout writing Shadow RAM\n"); + return -1; + } + + if (buf) + buf += 2;; + len -= 2; + addr += 2; + } + + return 0; +} + static int nicintel_ee_bitset(int reg, int bit, bool val) { uint32_t tmp; @@ -224,7 +348,7 @@ static int nicintel_ee_req(void) return 0; } -static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) +static int nicintel_ee_write_82580(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) { if (nicintel_ee_req()) return -1; @@ -262,6 +386,13 @@ out: nicintel_ee_bitset(EEC, EE_REQ, 0); /* Give up direct access. */ return ret; } +static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) +{ + if (is_i210(nicintel_pci->device_id)) + return nicintel_ee_write_i210(flash, buf, addr, len); + + return nicintel_ee_write_82580(flash, buf, addr, len); +} static int nicintel_ee_erase(struct flashctx *flash, unsigned int addr, unsigned int len) { @@ -275,6 +406,25 @@ static const struct opaque_master opaque_master_nicintel_ee = { .erase = nicintel_ee_erase, }; +static int nicintel_ee_shutdown_i210(void *arg) +{ + if (!done_i20_write) + return 0; + + uint32_t flup = pci_mmio_readl(nicintel_eebar + EEC); + + flup |= BIT(EE_FLUPD); + pci_mmio_writel(flup, nicintel_eebar + EEC); + + for (int i = 0; i < MAX_ATEMPTS; i++) + if (pci_mmio_readl(nicintel_eebar + EEC) & BIT(EE_FLUDONE)) + return 0; + + msg_perr("Flash update failed\n"); + + return -1; +} + static int nicintel_ee_shutdown(void *eecp) { uint32_t old_eec = *(uint32_t *)eecp; @@ -298,6 +448,7 @@ int nicintel_ee_init(void) if (rget_io_perms()) return 1; + struct pci_dev *dev = pcidev_init(nics_intel_ee, PCI_BASE_ADDRESS_0); if (!dev) return 1; @@ -306,9 +457,14 @@ int nicintel_ee_init(void) if (!io_base_addr) return 1; - nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", io_base_addr, MEMMAP_SIZE); + nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", + io_base_addr + (is_i210(dev->device_id) ? 0x12000 : 0), MEMMAP_SIZE); + if (!nicintel_eebar) + return 1; + nicintel_pci = dev; - if (dev->device_id != UNPROG_DEVICE) { + if ((dev->device_id != UNPROG_DEVICE) && ! is_i210(dev->device_id)) + { uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting the EE_PRES definition), @@ -327,5 +483,9 @@ int nicintel_ee_init(void) return 1; } + if (is_i210(dev->device_id)) + if (register_shutdown(nicintel_ee_shutdown_i210, NULL)) + return 1; + return register_opaque_master(&opaque_master_nicintel_ee); } -- 2.11.0

1 0

Chip AT26DF321-SU is recognized as AT25DF321
by The_Raven Raven 23 Mar '17

23 Mar '17

Hello I discovered that the chip "AT26DF321-SU" is recognized as "AT25DF321". This is the output from a "AT26DF321-SU": Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4700 Found Atmel flash chip "AT25DF321" (4096 kB, SPI) on serprog. Chip status register is 0x1c. Chip status register: Sector Protection Register Lock (SRPL) is not set Chip status register: Bit 6 is not set Chip status register: Erase/Program Error (EPE) is not set Chip status register: WP# pin (WPP) is not asserted Chip status register: Software Protection Status (SWP): all sectors are protected Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set It seems that both chips have the same ID's. I have readed and written the "AT26DF321-SU" and it worked. If you need more informations or if i should test something -> Let me know. Greetings Greetings

1 0

Re: [flashrom] Problem with flashrom and FT2232 Port B
by Nico Huber 22 Mar '17

22 Mar '17

On 22.03.2017 14:08, Zak wrote: > Heya > > Thanks for the reply, I'm using the latest version 1.2 for windows and I > use this programmer with other softwares with that same dll and it works > fine on both ports > > But in case I tried with the old libftdi 0.18 and it's the same error Sorry, I'm just poking in the dark. Another idea: Some other driver or program might have claimed access to port B and is blocking it. flash- rom doesn't know how to handle that, maybe your "other softwares" do. Nico > > Regards > > Le 22 mars 2017 12:14, "Nico Huber" <nico.huber(a)secunet.com> a écrit : > >> Hi Zak, >> >> On 21.03.2017 17:28, Zak wrote: >>> Hello, >>> >>> I got flashrom compiled for windows and it works like a charm (has to >>> tweet the code a little, add data for the chips i want to work with, add >>> 4BA and fast rading for FT2232), it works perfectly fine but only for >>> the port A (flashrom -p ft2232_spi:type=2232H,port=A) >>> >>> Using default programmer "ft2232_spi" with arguments "type=2232H,port=A". >>> Calibrating delay loop... OK. >>> Found Macronix flash chip "flashrom -p >>> ft2232_spi:type=2232H,port=AMX25L25665E" (32768 kB, SPI) >>> on ft2232_spi. >>> Reading flash... (0% to done.) >>> >>> If i use the port B (flashrom -p ft2232_spi:type=2232H,port=B), i get >>> this error >>> >>> Calibrating delay loop... OK. >>> Unable to reset FTDI device (USB device unavailable). >>> Unable to set latency timer (USB device unavailable). >>> Unable to set bitmode to SPI (USB device unavailable). >>> ftdi_write_data: -666, USB device unavailable >>> Error: Programmer initialization failed. >>> >>> I get this error also if i try to compile with make >>> CONFIG_DEFAULT_PROGRAMMER=PROGRAMMER_FT2232_SPI >>> CONFIG_DEFAULT_PROGRAMMER_ARGS="type=2232H,port=B" to force port B >>> >>> I looked around i didn't find any solution to fix this, anyone could >>> give me a hand? >> >> the problem probably lies within your (windows) version of libftdi. I'd >> try another OS / libftdi to rule that out. >> >> Nico >> >> >

1 0

[PATCH] nicintel_spi: Support for I210/I211 cards
by Ricardo Ribalda Delgado 22 Mar '17

22 Mar '17

Implements I210 "raw" flash access as detailed in: http://www.intel.com/content/www/us/en/embedded/products/networking/i210-et… Unfortunately, most of the time the card is in Secure Mode, which means that the raw access is not available. But his should be pretty useful for bringing up boards. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- nicintel_spi.c | 94 ++++++++++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 71 insertions(+), 23 deletions(-) diff --git a/nicintel_spi.c b/nicintel_spi.c index 9195c79e56c9..89f162f96e00 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -70,6 +70,9 @@ #define FL_SO 3 #define FL_REQ 4 #define FL_GNT 5 +#define FL_LOCKED 6 +#define FL_ABORT 7 +#define FL_CLR_ERR 8 /* Currently unused */ // #define FL_BUSY 30 // #define FL_ER 31 @@ -95,6 +98,14 @@ const struct dev_entry nics_intel_spi[] = { {PCI_VENDOR_ID_INTEL, 0x152a, NT, "Intel", "82599 10 Gigabit Dual Port Backplane Controller with FCoE"}, {PCI_VENDOR_ID_INTEL, 0x1557, NT, "Intel", "82599 10 Gigabit SFI Network Controller"}, + {PCI_VENDOR_ID_INTEL, 0x1531, OK, "Intel", "I210 Gigabit Network Connection Unprogrammed"}, + {PCI_VENDOR_ID_INTEL, 0x1532, NT, "Intel", "I211 Gigabit Network Connection Unprogrammed"}, + {PCI_VENDOR_ID_INTEL, 0x1533, NT, "Intel", "I210 Gigabit Network Connection"}, + {PCI_VENDOR_ID_INTEL, 0x1536, NT, "Intel", "I210 Gigabit Network Connection SERDES Fiber"}, + {PCI_VENDOR_ID_INTEL, 0x1537, NT, "Intel", "I210 Gigabit Network Connection SERDES Backplane"}, + {PCI_VENDOR_ID_INTEL, 0x1538, NT, "Intel", "I210 Gigabit Network Connection SGMII"}, + {PCI_VENDOR_ID_INTEL, 0x1539, NT, "Intel", "I211 Gigabit Network Connection"}, + {0}, }; @@ -182,32 +193,10 @@ static int nicintel_spi_shutdown(void *data) return 0; } -int nicintel_spi_init(void) +static int nicintel_spi_82599_enable_flash() { - struct pci_dev *dev = NULL; uint32_t tmp; - if (rget_io_perms()) - return 1; - - dev = pcidev_init(nics_intel_spi, PCI_BASE_ADDRESS_0); - if (!dev) - return 1; - - uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); - if (!io_base_addr) - return 1; - - if (dev->device_id < 0x10d8) { - nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, - MEMMAP_SIZE); - } else { - nicintel_spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000, - MEMMAP_SIZE); - } - if (nicintel_spibar == ERROR_PTR) - return 1; - /* Automatic restore of EECD on shutdown is not possible because EECD * does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED, * but other bits with side effects as well. Those other bits must be @@ -228,6 +217,65 @@ int nicintel_spi_init(void) if (register_shutdown(nicintel_spi_shutdown, NULL)) return 1; + return 0; +} + +static int nicintel_spi_i210_enable_flash() +{ + uint32_t tmp; + + tmp = pci_mmio_readl(nicintel_spibar + FLA); + if (tmp & (1 << FL_LOCKED)) { + msg_perr("Flash is in Secure Mode. Abort.\n"); + return 1; + } + + if (!(tmp & (1 << FL_ABORT))) + return 0; + + tmp |= (1 << FL_CLR_ERR); + pci_mmio_writel(tmp, nicintel_spibar + FLA); + tmp = pci_mmio_readl(nicintel_spibar + FLA); + if (!tmp & (1 << FL_ABORT)) { + msg_perr("Unable to clear Flash Access Error. Abort\n"); + return 1; + } + + return 0; +} + +int nicintel_spi_init(void) +{ + struct pci_dev *dev = NULL; + + if (rget_io_perms()) + return 1; + + dev = pcidev_init(nics_intel_spi, PCI_BASE_ADDRESS_0); + if (!dev) + return 1; + + uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; + + if ((dev->device_id & 0xfff0) == 0x1530) { + nicintel_spibar = rphysmap("Intel I210 Gigabit w/ SPI flash", io_base_addr + 0x12000, + MEMMAP_SIZE); + if (!nicintel_spibar || nicintel_spi_i210_enable_flash()) + return 1; + } else if (dev->device_id < 0x10d8) { + nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, + MEMMAP_SIZE); + if (!nicintel_spibar || nicintel_spi_82599_enable_flash()) + return 1; + } else { + nicintel_spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000, + MEMMAP_SIZE); + if (!nicintel_spibar || nicintel_spi_82599_enable_flash()) + return 1; + } + if (register_spi_bitbang_master(&bitbang_spi_master_nicintel)) return 1; -- 2.11.0

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[PATCH] sb600spi: Add support for Merlin Falcon Chipset
by Ricardo Ribalda Delgado 22 Mar '17

22 Mar '17

This patch has been tested on a board similar to AMD Bettong. 00:14.0 SMBus [0c05]: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller [1022:790b] (rev 4a) 00:14.3 ISA bridge [0601]: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge [1022:790e] (rev 11) root@qt5022-fglrx:~# ./flashrom -p internal -w kk.rom flashrom v0.9.9-unknown on Linux 4.10.0-qtec-standard (x86_64) flashrom is free software, get the source code at https://flashrom.org Calibrating delay loop... OK. coreboot table found at 0x9ffd6000. Found chipset "AMD FP4". Enabling flash write... OK. Found Micron/Numonyx/ST flash chip "N25Q128..1E" (16384 kB, SPI) mapped at physical address 0x00000000ff000000. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- chipset_enable.c | 1 + sb600spi.c | 28 +++++++++++++++++++++++----- 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index b181b9349b02..82bac112a29c 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1492,6 +1492,7 @@ const struct penable chipset_enables[] = { {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd_768_8111}, {0x1022, 0x7468, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111}, {0x1022, 0x780e, OK, "AMD", "FCH", enable_flash_sb600}, + {0x1022, 0x790e, OK, "AMD", "FP4", enable_flash_sb600}, {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501}, {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496}, {0x1039, 0x0530, OK, "SiS", "530", enable_flash_sis530}, diff --git a/sb600spi.c b/sb600spi.c index 6bd56798e839..68f8d8ac532b 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -149,6 +149,23 @@ static void determine_generation(struct pci_dev *dev) "Please report this to flashrom(a)flashrom.org and include this log and\n" "the output of lspci -nnvx, thanks!.\n", rev); } + } else if (dev->device_id == 0x790e) { + struct pci_dev *smbus_dev = pci_dev_find(0x1022, 0x790B); + if (smbus_dev == NULL) { + msg_pdbg("No SMBus device with ID 1022:790B found.\n"); + return; + } + uint8_t rev = pci_read_byte(smbus_dev, PCI_REVISION_ID); + if (rev == 0x4a) { + amd_gen = CHIPSET_YANGTZE; + msg_pdbg("Yangtze detected.\n"); + } else { + msg_pwarn("FCH device found but SMBus revision 0x%02x does not match known values.\n" + "Please report this to flashrom(a)flashrom.org and include this log and\n" + "the output of lspci -nnvx, thanks!.\n", rev); + } + + #endif } else msg_pwarn("%s: Unknown LPC device %" PRIx16 ":%" PRIx16 ".\n" @@ -646,12 +663,13 @@ int sb600_probe_spi(struct pci_dev *dev) /* Look for the SMBus device. */ smbus_dev = pci_dev_find(0x1002, 0x4385); - if (!smbus_dev) { + if (!smbus_dev) smbus_dev = pci_dev_find(0x1022, 0x780b); /* AMD FCH */ - if (!smbus_dev) { - msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); - return ERROR_NONFATAL; - } + if (!smbus_dev) + smbus_dev = pci_dev_find(0x1022, 0x790b); /* AMD FP4 */ + if (!smbus_dev) { + msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); + return ERROR_NONFATAL; } /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ -- 2.11.0

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