- flashrom - mail.coreboot.org

[PATCH 1/4] sbxxx: Add detection for the remaining AMD chipset families.
by Stefan Tauner 09 Aug '13

09 Aug '13

Also, correct prettyprinting of the registers of the various families, and abort if SpiAccessMacRomEn or SpiHostAccessRomEn prohibit full access. Tested reading/writing on ASRock IMB-A180, and chipset detection on one of each affected generation by Chris Goodrich from Sage. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- sb600spi.c | 125 +++++++++++++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 97 insertions(+), 28 deletions(-) diff --git a/sb600spi.c b/sb600spi.c index cb7c4ac..754148b 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -57,7 +57,28 @@ static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; static void determine_generation(struct pci_dev *dev) { amd_gen = CHIPSET_AMD_UNKNOWN; - if (dev->device_id == 0x780e) { + msg_pdbg2("Trying to determine the generation of the SPI interface... "); + if (dev->device_id == 0x438d) { + amd_gen = CHIPSET_SB6XX; + msg_pdbg("SB6xx detected.\n"); + } else if (dev->device_id == 0x439d) { + struct pci_dev *smbus_dev = pci_dev_find(0x1002, 0x4385); + if (smbus_dev == NULL) + return; + uint8_t rev = pci_read_byte(smbus_dev, PCI_REVISION_ID); + if (rev >= 0x39 && rev <= 0x3D) { + amd_gen = CHIPSET_SB7XX; + msg_pdbg("SB7xx/SP5100 detected.\n"); + } else if (rev >= 0x40 && rev <= 0x42) { + amd_gen = CHIPSET_SB89XX; + msg_pdbg("SB8xx/SB9xx/Hudson-1 detected.\n"); + } else { + msg_pwarn("SB device found but SMBus revision 0x%02x does not match known values.\n" + "Assuming SB8xx/SB9xx/Hudson-1. Please send a log to flashrom(a)flashrom.org\n", + rev); + amd_gen = CHIPSET_SB89XX; + } + } else if (dev->device_id == 0x780e) { /* The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and Yangtze (Kabini/Temash) * although they use different SPI interfaces. */ #ifdef USE_YANGTZE_HEURISTICS @@ -94,7 +115,11 @@ static void determine_generation(struct pci_dev *dev) "the output of lspci -nnvx, thanks!.\n", rev); } #endif - } + } else + msg_pwarn("%s: Unknown LPC device %" PRIx16 ":%" PRIx16 ".\n" + "Please report this to flashrom(a)flashrom.org and include this log and\n" + "the output of lspci -nnvx, thanks!\n", + __func__, dev->vendor_id, dev->device_id); } static void reset_internal_fifo_pointer(void) @@ -334,6 +359,12 @@ int sb600_probe_spi(struct pci_dev *dev) sb600_spibar += tmp & 0xfff; determine_generation(dev); + if (amd_gen == CHIPSET_AMD_UNKNOWN) { + /* FIXME: Eventually this should be a fatal error, but until we are certain to have covered all + * IDs actually found in the wild, try to mimmick the previous behavior. */ + msg_pwarn("Could not determine chipset generation. Assuming SB6xx."); + amd_gen = CHIPSET_SB6XX; + } if (amd_gen == CHIPSET_YANGTZE) { msg_perr("SPI on Kabini/Temash and newer chipsets are not yet supported.\n" @@ -341,32 +372,70 @@ int sb600_probe_spi(struct pci_dev *dev) return ERROR_NONFATAL; } - tmp = pci_read_long(dev, 0xa0); - msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " - "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, - (tmp & 0x4) >> 2); - tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; - msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); - - tmp = pci_read_byte(dev, 0xbb); - /* FIXME: Set bit 3,6,7 if not already set. - * Set bit 5, otherwise SPI accesses are pointless in LPC mode. - * See doc 42413 AMD SB700/710/750 RPR. - */ - msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", - tmp & 0x1, (tmp & 0x20) >> 5); - tmp = mmio_readl(sb600_spibar); - /* FIXME: If SpiAccessMacRomEn or SpiHostAccessRomEn are zero on - * SB700 or later, reads and writes will be corrupted. Abort in this - * case. Make sure to avoid this check on SB600. - */ - msg_pdbg("(0x%08" PRIx32 ") fastReadEnable=%u, SpiArbEnable=%i, SpiAccessMacRomEn=%i, " - "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " - "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", - tmp, (tmp >> 18) & 0x1, - (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, - (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, - (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); +/* Chipset support matrix for SPI Base_Addr (LPC PCI reg 0xa0) + * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson234 yangtze + * 3 rsvd <- <- ? <- ? RouteTpm2Spi + * 2 rsvd AbortEnable rsvd ? <- ? <- + * 1 rsvd SpiRomEnable <- ? <- ? <- + * 0 rsvd AltSpiCSEnable rsvd ? <- ? <- + */ + if (amd_gen >= CHIPSET_SB7XX) { + tmp = pci_read_long(dev, 0xa0); + msg_pdbg("SpiRomEnable=%i", (tmp >> 1) & 0x1); + if (amd_gen == CHIPSET_SB7XX) + msg_pdbg(", AltSpiCSEnable=%i, AbortEnable=%i", tmp & 0x1, (tmp >> 2) & 0x1); + + tmp = pci_read_byte(dev, 0xba); + msg_pdbg(", PrefetchEnSPIFromIMC=%i", (tmp & 0x4) >> 2); + + tmp = pci_read_byte(dev, 0xbb); + /* FIXME: Set bit 3,6,7 if not already set. + * Set bit 5, otherwise SPI accesses are pointless in LPC mode. + * See doc 42413 AMD SB700/710/750 RPR. + */ + if (amd_gen == CHIPSET_SB7XX) + msg_pdbg(", SpiOpEnInLpcMode=%i", (tmp >> 5) & 0x1); + msg_pdbg(", PrefetchEnSPIFromHost=%i\n", tmp & 0x1); + } + +/* Chipset support matrix for SPI_Cntrl0 (spibar + 0x0) + * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson234 yangtze + * 17 rsvd <- <- ? <- ? <- + * 18 rsvd <- fastReadEnable<1> ? <- ? SpiReadMode[0]<1> + * 19 SpiArbEnable <- <- ? <- ? <- + * 20 (FifoPtrClr) <- <- ? <- ? <- + * 21 (FifoPtrInc) <- <- ? <- ? IllegalAccess + * 22 SpiAccessMacRomEn <- <- ? <- ? <- + * 23 SpiHostAccessRomEn <- <- ? <- ? <- + * 24:26 ArbWaitCount <- <- ? <- ? <- + * 27 SpiBridgeDisable <- <- ? <- ? rsvd + * 28 rsvd DropOneClkOnRd = SPIClkGate ? <- ? <- + * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1]<1> + * 31 rsvd <- SpiBusy ? <- ? <- + * + * <1> see handle_speed + */ + tmp = mmio_readl(sb600_spibar + 0x00); + msg_pdbg("(0x%08" PRIx32 ") SpiArbEnable=%i", tmp, (tmp >> 19) & 0x1); + + msg_pdbg(", SpiAccessMacRomEn=%i, SpiHostAccessRomEn=%i, ArbWaitCount=%i", + (tmp >> 22) & 0x1, (tmp >> 23) & 0x1, (tmp >> 24) & 0x7); + + switch (amd_gen) { + case CHIPSET_SB7XX: + msg_pdbg(", DropOneClkOnRd/SpiClkGate=%i", (tmp >> 28) & 0x1); + case CHIPSET_SB89XX: + case CHIPSET_HUDSON234: + msg_pdbg(", SpiBusy=%i", (tmp >> 31) & 0x1); + default: break; + } + msg_pdbg("\n"); + + if (((tmp >> 22) & 0x1) == 0 || ((tmp >> 23) & 0x1) == 0) { + msg_perr("ERROR: State of SpiAccessMacRomEn or SpiHostAccessRomEn prohibits full access.\n"); + return ERROR_NONFATAL; + } + tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; msg_pdbg("NormSpeed is %s MHz\n", speed_names[tmp]); -- Kind regards, Stefan Tauner

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Re: [flashrom] [PATCH] Detect AMD Yangtze (found in Kabini and Tamesh).
by Stefan Tauner 09 Aug '13

09 Aug '13

On Sun, 4 Aug 2013 16:03:27 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and > Yangtze (Kabini/Temash) but the SPI interface does. Bail out in case we > detect Yangtze and add infrastructure to distinguish other families too for > further refactorings. > > Also, add ASRock IMB-A180 to the laptop whitelist. > > Tested on ASRock IMB-A180 with and w/o USE_YANGTZE_HEURISTICS. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Thanks a lot to Sage for testing! Self-acked and committed in r1706. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Broken OPMENUs (was: #flashrom talk (atomix vs. stefanct))
by Stefan Tauner 08 Aug '13

08 Aug '13

We could get this to work eventually today: http://paste.flashrom.org/view.php?id=1747 But coincidentally this was the second occurrence of a very broken OPMENU in a just a few days and I like to evaluate our options here. There are two problems with board above. The first one is the configuration of the OPMENU register which specifies the RDID probe command to be opcode + address bytes although RDID does not require an address (and flashrom naturally does not send dummy bytes by default): OP Type Pre-OP op[0]: 0x9f, read w/ addr, none I could fix this with an ugly hack that is not mergeable as is and is not easy to refine to something beautiful either I think: I have enlarged the write buffer of the RDID command to 4 Bytes and use its content as dummy bytes for the address the chipset wanted. Together with my check_trans patch we may be able to design something generic that is somewhat sane and mergeable. Alternatively we could handle some of the problems inside ichspi.c by rewriting the read and write arrays: if we want to write 1, 2 or 3 bytes we just need to create a new buffer and copy the contents over. We "just" need to make sure the flash chip happily ignores the (well chosen) dummy bytes and the read back values get repeated in the right rhythm... the more I think about it the less probable a mergeable solution seems possible, it rather worked for RDID just by accident and not many other opcodes would work. :/ The second problem with the board is related to the above. AAI on ichspi does not work as can be seen here: http://paste.flashrom.org/view.php?id=1746 After fixing the probing we ran into the problem that AAI transactions are not compatible with the current state of flashrom. I need to look into this (and AAI) in more detail, but my guess is that a similar approach as outlined above could solve this too... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1706 - trunk
by repository service 08 Aug '13

08 Aug '13

Author: stefanct Date: Thu Aug 8 14:00:19 2013 New Revision: 1706 URL: http://flashrom.org/trac/flashrom/changeset/1706 Log: Detect AMD Yangtze (found in Kabini and Tamesh). The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and Yangtze (Kabini/Temash) but the SPI interface does. Bail out in case we detect Yangtze and add infrastructure to distinguish other families too for further refactorings. Also, add ASRock IMB-A180 to the laptop whitelist and refine the IMC warning a bit. Tested on ASRock IMB-A180 with and w/o USE_YANGTZE_HEURISTICS, and by Chris Goodrich from Sage on - SB600 - SB700 - SB800 - Hudson 3 (A70M) - Kabini Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/chipset_enable.c trunk/sb600spi.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Tue Jul 30 11:34:44 2013 (r1705) +++ trunk/board_enable.c Thu Aug 8 14:00:19 2013 (r1706) @@ -2234,6 +2234,7 @@ /* * Suited for all boards with ambiguous DMI chassis information, which should be * whitelisted because they are known to work: + * - ASRock IMB-A180(-H) * - MSC Q7 Tunnel Creek Module (Q7-TCTC) */ static int p2_not_a_laptop(void) @@ -2321,6 +2322,7 @@ {0x8086, 0x27b9, 0xa0a0, 0x0632, 0x8086, 0x27da, 0xa0a0, 0x0632, NULL, NULL, NULL, P3, "AOpen", "i945GMx-VFX", 0, OK, intel_ich_gpio38_raise}, {0x8086, 0x277c, 0xa0a0, 0x060b, 0x8086, 0x27da, 0xa0a0, 0x060b, NULL, NULL, NULL, P3, "AOpen", "i975Xa-YDG", 0, OK, board_aopen_i975xa_ydg}, {0x8086, 0x27b8, 0x1849, 0x27b8, 0x8086, 0x27da, 0x1849, 0x27da, "^ConRoeXFire-eSATA2", NULL, NULL, P3, "ASRock", "ConRoeXFire-eSATA2", 0, OK, intel_ich_gpio16_raise}, + {0x1022, 0x1536, 0x1849, 0x1536, 0x1022, 0x780e, 0x1849, 0x780e, "^Kabini CRB$", NULL, NULL, P2, "ASRock", "IMB-A180(-H)", 0, OK, p2_not_a_laptop}, {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e}, {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41GX$", NULL, NULL, P3, "ASRock", "K7S41GX", 0, OK, w836xx_memw_enable_2e}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Tue Jul 30 11:34:44 2013 (r1705) +++ trunk/chipset_enable.c Thu Aug 8 14:00:19 2013 (r1706) @@ -1304,7 +1304,7 @@ {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, - {0x1022, 0x780e, OK, "AMD", "Hudson", enable_flash_sb600}, + {0x1022, 0x780e, OK, "AMD", "FCH", enable_flash_sb600}, {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501}, {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496}, {0x1039, 0x0530, OK, "SiS", "530", enable_flash_sis530}, Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Tue Jul 30 11:34:44 2013 (r1705) +++ trunk/sb600spi.c Thu Aug 8 14:00:19 2013 (r1706) @@ -44,6 +44,58 @@ */ static uint8_t *sb600_spibar = NULL; +enum amd_chipset { + CHIPSET_AMD_UNKNOWN, + CHIPSET_SB6XX, + CHIPSET_SB7XX, /* SP5100 too */ + CHIPSET_SB89XX, /* Hudson-1 too */ + CHIPSET_HUDSON234, + CHIPSET_YANGTZE, +}; +static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; + +static void determine_generation(struct pci_dev *dev) +{ + amd_gen = CHIPSET_AMD_UNKNOWN; + if (dev->device_id == 0x780e) { + /* The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and Yangtze (Kabini/Temash) + * although they use different SPI interfaces. */ +#ifdef USE_YANGTZE_HEURISTICS + /* This heuristic accesses the SPI interface MMIO BAR at locations beyond those supported by + * Hudson in the hope of getting 0xff readback on older chipsets and non-0xff readback on + * Yangtze (and newer, compatible chipsets). */ + int i; + msg_pdbg("Checking for AMD Yangtze (Kabini/Temash) or later... "); + for (i = 0x20; i <= 0x4f; i++) { + if (mmio_readb(sb600_spibar + i) != 0xff) { + amd_gen = CHIPSET_YANGTZE; + msg_pdbg("found.\n"); + return; + } + } + msg_pdbg("not found. Assuming Hudson.\n"); + amd_gen = CHIPSET_HUDSON234; +#else + struct pci_dev *smbus_dev = pci_dev_find(0x1022, 0x780B); + if (smbus_dev == NULL) { + msg_pdbg("No SMBus device with ID 1022:780B found.\n"); + return; + } + uint8_t rev = pci_read_byte(smbus_dev, PCI_REVISION_ID); + if (rev >= 0x11 && rev <= 0x15) { + amd_gen = CHIPSET_HUDSON234; + msg_pdbg("Hudson-2/3/4 detected.\n"); + } else if (rev >= 0x39 && rev <= 0x3A) { + amd_gen = CHIPSET_YANGTZE; + msg_pdbg("Yangtze detected.\n"); + } else { + msg_pwarn("FCH device found but SMBus revision 0x%02x does not match known values.\n" + "Please report this to flashrom(a)flashrom.org and include this log and\n" + "the output of lspci -nnvx, thanks!.\n", rev); + } +#endif + } +} static void reset_internal_fifo_pointer(void) { @@ -212,9 +264,9 @@ if (!amd_imc_force) programmer_may_write = 0; - msg_pinfo("Writes have been disabled for safety reasons because the IMC is active\n" - "and it could interfere with accessing flash memory. Flashrom will try\n" - "to disable it temporarily but even then this might not be safe:\n" + msg_pinfo("Writes have been disabled for safety reasons because the presence of the IMC\n" + "was detected and it could interfere with accessing flash memory. Flashrom will\n" + "try to disable it temporarily but even then this might not be safe:\n" "when it is reenabled and after a reboot it expects to find working code\n" "in the flash and it is unpredictable what happens if there is none.\n" "\n" @@ -281,6 +333,14 @@ */ sb600_spibar += tmp & 0xfff; + determine_generation(dev); + + if (amd_gen == CHIPSET_YANGTZE) { + msg_perr("SPI on Kabini/Temash and newer chipsets are not yet supported.\n" + "Please try a newer version of flashrom.\n"); + return ERROR_NONFATAL; + } + tmp = pci_read_long(dev, 0xa0); msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, @@ -312,9 +372,8 @@ /* Look for the SMBus device. */ smbus_dev = pci_dev_find(0x1002, 0x4385); - if (!smbus_dev) { - smbus_dev = pci_dev_find(0x1022, 0x780b); /* AMD Hudson */ + smbus_dev = pci_dev_find(0x1022, 0x780b); /* AMD FCH */ if (!smbus_dev) { msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); return ERROR_NONFATAL;

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Re: [flashrom] Invalid OPCODE 0x9f
by Carl-Daniel Hailfinger 08 Aug '13

08 Aug '13

Hello Vasiliy, can you try something? In ichspi.c line 1083, change result = run_opcode(flash, *opcode, addr, count, data); to result = run_opcode(flash, *opcode, addr | 0x800000, count, data); It might help, it might fail completely, but it's at least something you can try. Good luck! Regards, Carl-Daniel Am 07.08.2013 19:51 schrieb Vasiliy Vylegzhanin: > Oh, I see now, FLOCKDN is set. The only write command that effects > protected regions is chip erase. Damn. > I wonder, how vendor tool flash this. > > > On Wed, Aug 7, 2013 at 6:48 PM, Stefan Tauner < > stefan.tauner(a)student.tuwien.ac.at> wrote: > >> On Wed, 7 Aug 2013 14:42:40 +0400 >> Vasiliy Vylegzhanin <6vasia(a)gmail.com> wrote: >> >>> And I failed. There are some (modified?) phoenix flash tools, but they >>> refuse to flash the same BIOS version. >>> I've added W25x64 REMS ID and tried to flash it. Somehow flashrom managed >>> to erase whole chip and yes, it failed to write @0x00580000. >>> Is there any way to write write-protected regions on W25X64? I really >>> don't want to desolder it, and I can't reboot cause BB is erased. >>> Write log attached. >> Hello Vasiliy, >> >> there are no write-protected regions that are specific to the flash >> chip, it all depends on the Intel chipset configuration only (i.e. the >> same would have happened with another flash chip). >> >> TBH I dont totally grasp your log. Your overall analysis seems to be >> correct though: the erase opcode might have got through. I wonder what >> your changes are exactly. Can you please post your patch? I also wonder >> how your images look like. If you can please upload them to >> http://paste.flashrom.org (they will be password protected there >> because we are not allowed to redistribute vendor images of course...) >> >> -- http://www.hailfinger.org/

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Re: [flashrom] Invalid OPCODE 0x9f
by Stefan Tauner 07 Aug '13

07 Aug '13

On Wed, 7 Aug 2013 14:42:40 +0400 Vasiliy Vylegzhanin <6vasia(a)gmail.com> wrote: > And I failed. There are some (modified?) phoenix flash tools, but they > refuse to flash the same BIOS version. > I've added W25x64 REMS ID and tried to flash it. Somehow flashrom managed > to erase whole chip and yes, it failed to write @0x00580000. > Is there any way to write write-protected regions on W25X64? I really don't > want to desolder it, and I can't reboot cause BB is erased. > Write log attached. Hello Vasiliy, there are no write-protected regions that are specific to the flash chip, it all depends on the Intel chipset configuration only (i.e. the same would have happened with another flash chip). TBH I dont totally grasp your log. Your overall analysis seems to be correct though: the erase opcode might have got through. I wonder what your changes are exactly. Can you please post your patch? I also wonder how your images look like. If you can please upload them to http://paste.flashrom.org (they will be password protected there because we are not allowed to redistribute vendor images of course...) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[PATCH] Refine messages related to erase/write recovery.
by Stefan Tauner 07 Aug '13

07 Aug '13

We are more verbose inside erase_and_write_flash() although it does not matter as much as here - at the end of the process. New output for the non-fatal (i.e. read-protected + successful read) case: Reading old flash chip contents... done. Erasing and writing flash chip... spi_block_erase_d8 failed during command execution at address 0x8000 Reading current flash chip contents... done. spi_chip_erase_c7 failed during command execution FAILED! Uh oh. Erase/write failed. Checking if anything has changed. Reading current flash chip contents... done. Good. Writing to the flash chip apparently didn't do anything. Please check the connections (especially those to write protection pins) between the programmer and the flash chip. If you think the error is caused by flashrom please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks! Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashrom.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/flashrom.c b/flashrom.c index db5b1c7..694d01e 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1979,16 +1979,19 @@ int doit(struct flashctx *flash, int force, const char *filename, int read_it, if (write_it) { if (erase_and_write_flash(flash, oldcontents, newcontents)) { - msg_cerr("Uh oh. Erase/write failed. Checking if " - "anything changed.\n"); + msg_cerr("Uh oh. Erase/write failed. Checking if anything has changed.\n"); + msg_cinfo("Reading current flash chip contents... "); if (!flash->chip->read(flash, newcontents, 0, size)) { + msg_cinfo("done.\n"); if (!memcmp(oldcontents, newcontents, size)) { - msg_cinfo("Good. It seems nothing was changed.\n"); + msg_cinfo("Good. "); nonfatal_help_message(); ret = 1; goto out; } - } + msg_cinfo("Apparently at least some data has changed.\n"); + } else + msg_cerr("Can't even read anymore!\n"); emergency_help_message(); ret = 1; goto out; -- Kind regards, Stefan Tauner

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#flashrom talk (atomix vs. stefanct)
by verperlung＠gmx.net 07 Aug '13

07 Aug '13

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Re: [flashrom] Invalid OPCODE 0x9f
by Stefan Tauner 07 Aug '13

07 Aug '13

The restricted opcode is not so unusual. We have encountered the same with some thinkpads. Vendors don't need proper RDID because they usually know which chip is installed so they don't have to support 300+ chips like flashrom does. On Mon, 29 Apr 2013 14:47:35 +0400 Vasiliy Vylegzhanin <6vasia(a)gmail.com> wrote: > 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write. > 0x58: 0x07ff0580 FREG1: BIOS region (0x00580000-0x007fffff) is read-write. > 0x5C: 0x057f0003 FREG2: Management Engine region (0x00003000-0x0057ffff) is read-write. > 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write. > 0x64: 0x00000fff FREG4: Platform Data region is unused. > 0x74: 0x00000000 (PR0 is unused) > 0x78: 0x00000000 (PR1 is unused) > 0x7C: 0x00000000 (PR2 is unused) > 0x80: 0x87ff0770 PR3: WARNING: 0x00770000-0x007fffff is read-only. > 0x84: 0x875f0580 PR4: WARNING: 0x00580000-0x0075ffff is read-only. The protected regions are a bigger problem. This configuration protects almost the complete BIOS region and this can not be disabled at runtime. Does the vendor offer updates for the BIOS? Did you look into the BIOS configuration menu if there is a switch to allow BIOS modifications? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 2/2] Improve getrevision.sh.
by David Hendricks 07 Aug '13

07 Aug '13

Overall this is great! I definitely think it's easier to read, test, and maintain than the Makefile approach. But I suppose we'll find out how others feel... On Tue, Aug 6, 2013 at 6:51 PM, Stefan Tauner < stefan.tauner(a)student.tuwien.ac.at> wrote: > - remove bashism > - simplify some git-related code > - there is only one sane time format. > - vastly improve git_url() to print the correct remote url and > "nearest" branch > - add "-dirty" to local revisions if there are uncommitted changes > - indicate in local revisions how many git-only commits were done > since branching from upstream svn > - fix svn_revision() fallback to svn info and remove git-svn > - print leading r in script instead of hardcode it in the makefile; > no more "0.9.7-runknown" > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > Makefile | 2 +- > util/getrevision.sh | 156 > +++++++++++++++++++++++++++++----------------------- > 2 files changed, 89 insertions(+), 69 deletions(-) > > diff --git a/Makefile b/Makefile > index da0d0da..e1a4474 100644 > --- a/Makefile > +++ b/Makefile > @@ -329,7 +329,7 @@ CLI_OBJS = cli_classic.o cli_output.o print.o > SVNVERSION := $(shell ./util/getrevision.sh -u) > > RELEASE := 0.9.6.1 > -VERSION := $(RELEASE)-r$(SVNVERSION) > +VERSION := $(RELEASE)-$(SVNVERSION) > RELEASENAME ?= $(VERSION) > > SVNDEF := -D'FLASHROM_VERSION="$(VERSION)"' > diff --git a/util/getrevision.sh b/util/getrevision.sh > index 678d66b..95a57fe 100755 > --- a/util/getrevision.sh > +++ b/util/getrevision.sh > @@ -5,6 +5,7 @@ > # Copyright (C) 2005 coresystems GmbH <stepan(a)coresystems.de> > # Copyright (C) 2009,2010 Carl-Daniel Hailfinger > # Copyright (C) 2010 Chromium OS Authors > +# Copyright (C) 2013 Stefan Tauner > # > # This program is free software; you can redistribute it and/or modify > # it under the terms of the GNU General Public License as published by > @@ -23,18 +24,17 @@ > > EXIT_SUCCESS=0 > EXIT_FAILURE=1 > +date_format="+%Y-%m-%dT%H:%M:%S%z" # There is only one valid timeformat > FFS! ISO 8601 > > svn_revision() { > LC_ALL=C svnversion -cn . 2>/dev/null | \ > - sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | \ > - grep "[0-9]" || > + sed -e "s/.*://" -e "s/$[0-9]*$.*/r\1/" | \ > + grep "r[0-9]" || > LC_ALL=C svn info . 2>/dev/null | \ > - awk '/^Revision:/ {print $$2 }' | \ > - grep "[0-9]" || > - LC_ALL=C git svn info . 2>/dev/null | \ > - awk '/^Revision:/ {print $$2 }' | \ > - grep "[0-9]" || > - echo '' > + grep "Last Changed Rev:" | \ > + sed -e "s/^Last Changed Rev: *//" -e "s/$[0-9]*$.*/r\1/" > | \ > + grep "r[0-9]" || > + echo "unknown" > } > > svn_url() { > @@ -45,74 +45,81 @@ svn_url() { > ) > } > > +svn_has_local_changes() { > + svn status | egrep '^ *[ADMR] *' > /dev/null > +} > + > svn_timestamp() { > - local date_format="+%Y-%m-%d %H:%M:%S" > local timestamp > > - # are there local changes in the client? > - if svn status | egrep '^ *[ADMR] *' > /dev/null ; then > - timestamp=$(date "${date_format} +") > + if svn_has_local_changes ; then > + timestamp=$(date "${date_format}") > else > # No local changes, get date of the last log record. > local last_commit_date=$(svn info | grep '^Last Changed > Date:' | \ > awk '{print $4" "$5" "$6}') > - timestamp=$(date --utc --date "${last_commit_date}" \ > - "${date_format} UTC") > + timestamp=$(date -d "${last_commit_date}" "${date_format}") > fi > > echo "${timestamp}" > } > > -git_revision() { > - echo $(git log --oneline | head -1 | awk '{print $1}') > -} > - > -# Retrieve svn revision using git log data (for git mirrors) > +# Retrieve svn revision using git log data (for git-svn mirrors) > gitsvn_revision() { > local r > > - git log| > - grep git-svn-id| > - sed > 's/.*git-svn-id:[[:blank:]]*$[^@]\+$@[0-9]\+[[:blank:]]\+$[^[:blank:]]\+$/\1 > \2/'| > - sort| > - uniq| > - read url uuid > - > - r=$(git log --grep="git-svn-id.*$uuid"| grep git-svn-id | \ > - sed 's/.*@//;s/[[:blank:]].*//'| \ > - sort -n | \ > - tail -1) > + # If this is a "native" git-svn clone we could use git svn log > like so > + # if [ -e .git/svn/.metadata ]; then > + # r=$(git svn log --oneline -1 | sed > 's/^r//;s/[[:blank:]].*//') > + # else > + r=$(git log --grep git-svn-id -1 | \ > + grep git-svn-id | \ > + sed 's/.*@/r/;s/[[:blank:]].*//') > + # fi > > echo "${r}" > } > > +git_has_local_changes() { > + git update-index -q --refresh > + ! git diff-index --quiet HEAD -- > +} > + > git_timestamp() { > - local date_format="+%b %d %Y %H:%M:%S" > local timestamp > > - # are there local changes in the client? > - if git status | \ > - egrep '^# Change(s to be committed|d but not updated):$' > > /dev/null > - then > - timestamp=$(date "${date_format} +") > + # are there local changes? > + if git_has_local_changes ; then > + timestamp=$(date "${date_format}") > else > - # No local changes, get date of the last log record. > - local last_commit_date=$(git log | head -3 | grep '^Date:' > | \ > - awk '{print $3" "$4" "$6" "$5" > "$7}') > - timestamp=$(date --utc --date "${last_commit_date}" \ > - "${date_format} UTC") > + # No local changes, get date of the last commit > + timestamp=$(date -d "$(git log --pretty=format:"%cD" -1)" > "${date_format}") > fi > > echo "${timestamp}" > } > > git_url() { > - # Only the first line of `git remote' is considered. > - echo $(LC_ALL=C git remote show origin 2>/dev/null | > - grep 'Fetch URL:' | > - sed 's/.*URL:[[:blank:]]*//' | > - grep ^. > - ) > + # get all remote branches containing the last commit > + branches=$(git branch -r --contains HEAD | cut -c 3-) > + if [ -z "$branches" ] ; then > + echo "No remote branch contains current HEAD">&2 > + return > + fi > + > + # find "nearest" branch > + local diff=9000 > + local target= > + for branch in $branches ; do > + curdiff=$(git rev-list --count HEAD..$branch) > + if [ $curdiff -ge $diff ] ; then > + continue > + fi > + diff=$curdiff > + target=$branch > + done > + > + echo "$(git ls-remote --exit-code --get-url ${target%/*}) > ${target#*/}" > } > I am seeing a lot of errors when trying this. The version in the previous patch worked, though it kept the http:// prefix which is kind of superfluous. Try cloning http://git.chromium.org/chromiumos/third_party/flashrom.git . $ sh getrevision.sh -U fatal: ambiguous argument 'HEAD..->': unknown revision or path not in the working tree. Use '--' to separate paths from revisions, like this: 'git <command> [<revision>...] -- [<file>...]' getrevision.sh: line 115: [: -ge: unary operator expected getrevision.sh: line 115: [: 0: unary operator expected http://git.chromium.org/chromiumos/third_party/flashrom.git master What about something like: git ls-remote --exit-code --get-url | sed 's/.*\/\///' That looks simpler and works better, at least in my testing... > > scm_url() { > @@ -142,16 +149,26 @@ timestamp() { > echo ${t} > } > > -# Retrieve local SCM revision info. This is useful if we're working in > -# a even different SCM than upstream. > + > +# Retrieve local SCM revision info. This is useful if we're working in a > different SCM than upstream and/or > +# have local changes. > # > -# If local copy is svn, then there is nothing to do here. > -# If local copy is git, then retrieve useful git revision info > local_revision() { > local r > > - if [ -d ".git" ] ; then > - r=$(git_revision) > + if [ -d ".svn" ] ; then > + r=$(svn_has_local_changes && echo "-dirty") > + elif [ -d ".git" ] ; then > + r=$(git rev-parse --short HEAD) > + > + local svn_base=$(git log --grep git-svn-id -1 > --format='%h') > + if [ "$svn_base" != "" ] ; then > + r="$r-$(git rev-list --count $svn_base..HEAD)" > + fi > + > + if git_has_local_changes ; then > + r="$r-dirty" > + fi > fi > > echo ${r} > @@ -168,6 +185,8 @@ upstream_revision() { > r=$(svn_revision) > elif [ -d ".git" ] ; then > r=$(gitsvn_revision) > + else > + r="unknown" > fi > > echo "${r}" > @@ -180,48 +199,49 @@ show_help() { > Options > -h or --help > Display this message. > + -l or --local > + local revision (if different from upstream) and an indicator for > uncommitted changes > -u or --upstream > upstream flashrom revision > - -l or --local > - local revision (if different from upstream) > - -t or --timestamp > - timestamp of most recent modification > -U or --url > url associated with local copy of flashrom > + -t or --timestamp > + timestamp of most recent modification > " > return > } > > -if [ ! -n "${1}" ] > -then > +if [ -z "${1}" ] ; then > show_help; > echo "No options specified"; > - exit ${EXIT_SUCCESS} > + exit ${EXIT_FAILURE} > fi > > # The is the main loop > -while [[ ${1} = -* ]]; > +while [ $# -gt 0 ]; > do > case ${1} in > -h|--help) > show_help; > shift;; > - -u|--upstream) > - echo "$(upstream_revision)"; > - shift;; > -l|--local) > echo "$(local_revision)"; > shift;; > - -t|--timestamp) > - echo "$(timestamp)"; > + -u|--upstream) > + echo "$(upstream_revision)"; > shift;; > -U|--url) > echo "$(scm_url)"; > shift;; > - *) > + -t|--timestamp) > + echo "$(timestamp)"; > + shift;; > + -*) > show_help; > echo "invalid option: ${1}" > - exit ${EXIT_FAILURE} > + exit ${EXIT_FAILURE};; > + *) > + shift;; # ignore arguments not starting with - > esac; > done > > -- > Kind regards, Stefan Tauner > > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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[PATCH 2/2] Improve getrevision.sh.
by Stefan Tauner 07 Aug '13

07 Aug '13

- remove bashism - simplify some git-related code - there is only one sane time format. - vastly improve git_url() to print the correct remote url and "nearest" branch - add "-dirty" to local revisions if there are uncommitted changes - indicate in local revisions how many git-only commits were done since branching from upstream svn - fix svn_revision() fallback to svn info and remove git-svn - print leading r in script instead of hardcode it in the makefile; no more "0.9.7-runknown" Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 2 +- util/getrevision.sh | 156 +++++++++++++++++++++++++++++----------------------- 2 files changed, 89 insertions(+), 69 deletions(-) diff --git a/Makefile b/Makefile index da0d0da..e1a4474 100644 --- a/Makefile +++ b/Makefile @@ -329,7 +329,7 @@ CLI_OBJS = cli_classic.o cli_output.o print.o SVNVERSION := $(shell ./util/getrevision.sh -u) RELEASE := 0.9.6.1 -VERSION := $(RELEASE)-r$(SVNVERSION) +VERSION := $(RELEASE)-$(SVNVERSION) RELEASENAME ?= $(VERSION) SVNDEF := -D'FLASHROM_VERSION="$(VERSION)"' diff --git a/util/getrevision.sh b/util/getrevision.sh index 678d66b..95a57fe 100755 --- a/util/getrevision.sh +++ b/util/getrevision.sh @@ -5,6 +5,7 @@ # Copyright (C) 2005 coresystems GmbH <stepan(a)coresystems.de> # Copyright (C) 2009,2010 Carl-Daniel Hailfinger # Copyright (C) 2010 Chromium OS Authors +# Copyright (C) 2013 Stefan Tauner # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -23,18 +24,17 @@ EXIT_SUCCESS=0 EXIT_FAILURE=1 +date_format="+%Y-%m-%dT%H:%M:%S%z" # There is only one valid timeformat FFS! ISO 8601 svn_revision() { LC_ALL=C svnversion -cn . 2>/dev/null | \ - sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | \ - grep "[0-9]" || + sed -e "s/.*://" -e "s/$[0-9]*$.*/r\1/" | \ + grep "r[0-9]" || LC_ALL=C svn info . 2>/dev/null | \ - awk '/^Revision:/ {print $$2 }' | \ - grep "[0-9]" || - LC_ALL=C git svn info . 2>/dev/null | \ - awk '/^Revision:/ {print $$2 }' | \ - grep "[0-9]" || - echo '' + grep "Last Changed Rev:" | \ + sed -e "s/^Last Changed Rev: *//" -e "s/$[0-9]*$.*/r\1/" | \ + grep "r[0-9]" || + echo "unknown" } svn_url() { @@ -45,74 +45,81 @@ svn_url() { ) } +svn_has_local_changes() { + svn status | egrep '^ *[ADMR] *' > /dev/null +} + svn_timestamp() { - local date_format="+%Y-%m-%d %H:%M:%S" local timestamp - # are there local changes in the client? - if svn status | egrep '^ *[ADMR] *' > /dev/null ; then - timestamp=$(date "${date_format} +") + if svn_has_local_changes ; then + timestamp=$(date "${date_format}") else # No local changes, get date of the last log record. local last_commit_date=$(svn info | grep '^Last Changed Date:' | \ awk '{print $4" "$5" "$6}') - timestamp=$(date --utc --date "${last_commit_date}" \ - "${date_format} UTC") + timestamp=$(date -d "${last_commit_date}" "${date_format}") fi echo "${timestamp}" } -git_revision() { - echo $(git log --oneline | head -1 | awk '{print $1}') -} - -# Retrieve svn revision using git log data (for git mirrors) +# Retrieve svn revision using git log data (for git-svn mirrors) gitsvn_revision() { local r - git log| - grep git-svn-id| - sed 's/.*git-svn-id:[[:blank:]]*$[^@]\+$@[0-9]\+[[:blank:]]\+$[^[:blank:]]\+$/\1 \2/'| - sort| - uniq| - read url uuid - - r=$(git log --grep="git-svn-id.*$uuid"| grep git-svn-id | \ - sed 's/.*@//;s/[[:blank:]].*//'| \ - sort -n | \ - tail -1) + # If this is a "native" git-svn clone we could use git svn log like so + # if [ -e .git/svn/.metadata ]; then + # r=$(git svn log --oneline -1 | sed 's/^r//;s/[[:blank:]].*//') + # else + r=$(git log --grep git-svn-id -1 | \ + grep git-svn-id | \ + sed 's/.*@/r/;s/[[:blank:]].*//') + # fi echo "${r}" } +git_has_local_changes() { + git update-index -q --refresh + ! git diff-index --quiet HEAD -- +} + git_timestamp() { - local date_format="+%b %d %Y %H:%M:%S" local timestamp - # are there local changes in the client? - if git status | \ - egrep '^# Change(s to be committed|d but not updated):$' > /dev/null - then - timestamp=$(date "${date_format} +") + # are there local changes? + if git_has_local_changes ; then + timestamp=$(date "${date_format}") else - # No local changes, get date of the last log record. - local last_commit_date=$(git log | head -3 | grep '^Date:' | \ - awk '{print $3" "$4" "$6" "$5" "$7}') - timestamp=$(date --utc --date "${last_commit_date}" \ - "${date_format} UTC") + # No local changes, get date of the last commit + timestamp=$(date -d "$(git log --pretty=format:"%cD" -1)" "${date_format}") fi echo "${timestamp}" } git_url() { - # Only the first line of `git remote' is considered. - echo $(LC_ALL=C git remote show origin 2>/dev/null | - grep 'Fetch URL:' | - sed 's/.*URL:[[:blank:]]*//' | - grep ^. - ) + # get all remote branches containing the last commit + branches=$(git branch -r --contains HEAD | cut -c 3-) + if [ -z "$branches" ] ; then + echo "No remote branch contains current HEAD">&2 + return + fi + + # find "nearest" branch + local diff=9000 + local target= + for branch in $branches ; do + curdiff=$(git rev-list --count HEAD..$branch) + if [ $curdiff -ge $diff ] ; then + continue + fi + diff=$curdiff + target=$branch + done + + echo "$(git ls-remote --exit-code --get-url ${target%/*}) ${target#*/}" } scm_url() { @@ -142,16 +149,26 @@ timestamp() { echo ${t} } -# Retrieve local SCM revision info. This is useful if we're working in -# a even different SCM than upstream. + +# Retrieve local SCM revision info. This is useful if we're working in a different SCM than upstream and/or +# have local changes. # -# If local copy is svn, then there is nothing to do here. -# If local copy is git, then retrieve useful git revision info local_revision() { local r - if [ -d ".git" ] ; then - r=$(git_revision) + if [ -d ".svn" ] ; then + r=$(svn_has_local_changes && echo "-dirty") + elif [ -d ".git" ] ; then + r=$(git rev-parse --short HEAD) + + local svn_base=$(git log --grep git-svn-id -1 --format='%h') + if [ "$svn_base" != "" ] ; then + r="$r-$(git rev-list --count $svn_base..HEAD)" + fi + + if git_has_local_changes ; then + r="$r-dirty" + fi fi echo ${r} @@ -168,6 +185,8 @@ upstream_revision() { r=$(svn_revision) elif [ -d ".git" ] ; then r=$(gitsvn_revision) + else + r="unknown" fi echo "${r}" @@ -180,48 +199,49 @@ show_help() { Options -h or --help Display this message. + -l or --local + local revision (if different from upstream) and an indicator for uncommitted changes -u or --upstream upstream flashrom revision - -l or --local - local revision (if different from upstream) - -t or --timestamp - timestamp of most recent modification -U or --url url associated with local copy of flashrom + -t or --timestamp + timestamp of most recent modification " return } -if [ ! -n "${1}" ] -then +if [ -z "${1}" ] ; then show_help; echo "No options specified"; - exit ${EXIT_SUCCESS} + exit ${EXIT_FAILURE} fi # The is the main loop -while [[ ${1} = -* ]]; +while [ $# -gt 0 ]; do case ${1} in -h|--help) show_help; shift;; - -u|--upstream) - echo "$(upstream_revision)"; - shift;; -l|--local) echo "$(local_revision)"; shift;; - -t|--timestamp) - echo "$(timestamp)"; + -u|--upstream) + echo "$(upstream_revision)"; shift;; -U|--url) echo "$(scm_url)"; shift;; - *) + -t|--timestamp) + echo "$(timestamp)"; + shift;; + -*) show_help; echo "invalid option: ${1}" - exit ${EXIT_FAILURE} + exit ${EXIT_FAILURE};; + *) + shift;; # ignore arguments not starting with - esac; done -- Kind regards, Stefan Tauner

1 0

Re: [flashrom] FAILED
by David Hendricks 06 Aug '13

06 Aug '13

On Mon, Aug 5, 2013 at 4:04 PM, Joseph Smith <josephasmith1(a)gmail.com>wrote: > Samsung 550 chromebook > Probably due to the management engine: http://flashrom.org/ME How are you invoking flashrom? Did you compile flashrom yourself? If so, where did you get the sources? -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

1 0

FAILED
by Joseph Smith 06 Aug '13

06 Aug '13

Samsung 550 chromebook

1 0

P4R8L - Asus Pundit R - READ OK (looks like) ERASE FAILED
by Gianluigi Tiesi 05 Aug '13

05 Aug '13

I've got a barebone pc from asus: http://www.asus.com/Barebone_PCs/PunditR/ read flash looks ok perhaps dumps are a bit different I've attached both from flashrom, original from asus in roms.tar.xz other files: info.tar.xz => lspci/lsusb/dmesg/dmidecode read.log.xz => flashrom -r write.log.xz => flashrom -w Hope it helps Regards -- Gianluigi Tiesi <sherpya(a)netfarm.it> EDP Project Leade Netfarm S.r.l. - http://www.netfarm.it/ Free Software: http://oss.netfarm.it/ Q: Because it reverses the logical flow of conversation. A: Why is putting a reply at the top of the message frowned upon? A non-text attachment roms.tar.xz has been stripped. It is available at http://paste.flashrom.org/view.php?id=1709

2 1

Re: [flashrom] Intel DQ45CB - flashrom -V - ouput
by Stefan Tauner 05 Aug '13

05 Aug '13

Hello Kurtis, thanks for your report! The main problem is the locked ME region as seen in the log. For more details please see http://flashrom.org/ME I have added the board to our list of (un)supported boards (with an appropriate note) and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

[PATCH] Detect AMD Yangtze (found in Kabini and Tamesh).
by Stefan Tauner 04 Aug '13

04 Aug '13

The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and Yangtze (Kabini/Temash) but the SPI interface does. Bail out in case we detect Yangtze and add infrastructure to distinguish other families too for further refactorings. Also, add ASRock IMB-A180 to the laptop whitelist. Tested on ASRock IMB-A180 with and w/o USE_YANGTZE_HEURISTICS. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- board_enable.c | 2 ++ chipset_enable.c | 2 +- sb600spi.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 3 files changed, 65 insertions(+), 3 deletions(-) diff --git a/board_enable.c b/board_enable.c index d60f9cb..074cabb 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2234,6 +2234,7 @@ static int it8718f_gpio63_raise(void) /* * Suited for all boards with ambiguous DMI chassis information, which should be * whitelisted because they are known to work: + * - ASRock IMB-A180(-H) * - Intel D945GCNL * - MSC Q7 Tunnel Creek Module (Q7-TCTC) */ @@ -2322,6 +2323,7 @@ const struct board_match board_matches[] = { {0x8086, 0x27b9, 0xa0a0, 0x0632, 0x8086, 0x27da, 0xa0a0, 0x0632, NULL, NULL, NULL, P3, "AOpen", "i945GMx-VFX", 0, OK, intel_ich_gpio38_raise}, {0x8086, 0x277c, 0xa0a0, 0x060b, 0x8086, 0x27da, 0xa0a0, 0x060b, NULL, NULL, NULL, P3, "AOpen", "i975Xa-YDG", 0, OK, board_aopen_i975xa_ydg}, {0x8086, 0x27b8, 0x1849, 0x27b8, 0x8086, 0x27da, 0x1849, 0x27da, "^ConRoeXFire-eSATA2", NULL, NULL, P3, "ASRock", "ConRoeXFire-eSATA2", 0, OK, intel_ich_gpio16_raise}, + {0x1022, 0x1536, 0x1849, 0x1536, 0x1022, 0x780e, 0x1849, 0x780e, "^Kabini CRB$", NULL, NULL, P2, "ASRock", "IMB-A180(-H)", 0, OK, p2_not_a_laptop}, {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e}, {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41GX$", NULL, NULL, P3, "ASRock", "K7S41GX", 0, OK, w836xx_memw_enable_2e}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, diff --git a/chipset_enable.c b/chipset_enable.c index e1a74ae..6c5e34b 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1304,7 +1304,7 @@ const struct penable chipset_enables[] = { {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, - {0x1022, 0x780e, OK, "AMD", "Hudson", enable_flash_sb600}, + {0x1022, 0x780e, OK, "AMD", "FCH", enable_flash_sb600}, {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501}, {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496}, {0x1039, 0x0530, OK, "SiS", "530", enable_flash_sis530}, diff --git a/sb600spi.c b/sb600spi.c index 74106c2..168e910 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -44,6 +44,59 @@ */ static uint8_t *sb600_spibar = NULL; +enum amd_chipset { + CHIPSET_AMD_UNKNOWN, + CHIPSET_SB6XX, + CHIPSET_SB7XX, /* SP5100 too */ + CHIPSET_SB89XX, /* Hudson-1 too */ + CHIPSET_HUDSON234, + CHIPSET_YANGTZE, +}; +static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; + +static void determine_generation(struct pci_dev *dev) +{ + amd_gen = CHIPSET_AMD_UNKNOWN; + msg_pdbg2("Trying to determine the generation of the SPI interface.\n"); + if (dev->device_id == 0x780e) { + /* The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and Yangtze (Kabini/Temash) + * although they use different SPI interfaces. */ +#ifdef USE_YANGTZE_HEURISTICS + /* This heuristic accesses the SPI interface MMIO BAR at locations beyond those supported by + * Hudson in the hope of getting 0xff readback on older chipsets and non-0xff readback on + * Yangtze (and newer, compatible chipsets). */ + int i; + msg_pdbg("Checking for AMD Yangtze (Kabini/Temash) or later... "); + for (i = 0x20; i <= 0x4f; i++) { + if (mmio_readb(sb600_spibar + i) != 0xff) { + amd_gen = CHIPSET_YANGTZE; + msg_pdbg("found.\n"); + return; + } + } + msg_pdbg("not found. Assuming Hudson.\n"); + amd_gen = CHIPSET_HUDSON234; +#else + struct pci_dev *smbus_dev = pci_dev_find(0x1022, 0x780B); + if (smbus_dev == NULL) { + msg_pdbg("No SMBus device with ID 1022:780B found.\n"); + return; + } + uint8_t rev = pci_read_byte(smbus_dev, PCI_REVISION_ID); + if (rev >= 0x11 && rev <= 0x15) { + amd_gen = CHIPSET_HUDSON234; + msg_pdbg("Hudson-2/3/4 detected.\n"); + } else if (rev >= 0x39 && rev <= 0x3A) { + amd_gen = CHIPSET_YANGTZE; + msg_pdbg("Yangtze detected.\n"); + } else { + msg_pwarn("FCH device found but SMBus revision 0x%02x does not match known values.\n" + "Please report this to flashrom(a)flashrom.org and include this log and\n" + "the output of lspci -nnvx, thanks!.\n", rev); + } +#endif + } +} static void reset_internal_fifo_pointer(void) { @@ -281,6 +334,14 @@ int sb600_probe_spi(struct pci_dev *dev) */ sb600_spibar += tmp & 0xfff; + determine_generation(dev); + + if (amd_gen == CHIPSET_YANGTZE) { + msg_perr("SPI on Kabini/Temash and newer chipsets are not yet supported.\n" + "Please try a newer version of flashrom.\n"); + return ERROR_NONFATAL; + } + tmp = pci_read_long(dev, 0xa0); msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, @@ -312,9 +373,8 @@ int sb600_probe_spi(struct pci_dev *dev) /* Look for the SMBus device. */ smbus_dev = pci_dev_find(0x1002, 0x4385); - if (!smbus_dev) { - smbus_dev = pci_dev_find(0x1022, 0x780b); /* AMD Hudson */ + smbus_dev = pci_dev_find(0x1022, 0x780b); /* AMD FCH */ if (!smbus_dev) { msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); return ERROR_NONFATAL; -- Kind regards, Stefan Tauner

1 0

[PATCH] Detect AMD Yangtze (found in Kabini and Tamesh).
by Stefan Tauner 03 Aug '13

03 Aug '13

The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and Yangtze (Kabini/Temash) but the SPI interface does. Bail out in case we detect Yangtze and add infrastructure to distinguish other families too for further refactorings. Also, add ASRock IMB-A180 to the laptop whitelist. Tested on ASRock IMB-A180 with and w/o USE_YANGTZE_HEURISTIC. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- board_enable.c | 3 +++ chipset_enable.c | 2 +- sb600spi.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 68 insertions(+), 1 deletion(-) diff --git a/board_enable.c b/board_enable.c index a565c15..074cabb 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2234,6 +2234,8 @@ static int it8718f_gpio63_raise(void) /* * Suited for all boards with ambiguous DMI chassis information, which should be * whitelisted because they are known to work: + * - ASRock IMB-A180(-H) + * - Intel D945GCNL * - MSC Q7 Tunnel Creek Module (Q7-TCTC) */ static int p2_not_a_laptop(void) @@ -2321,6 +2323,7 @@ const struct board_match board_matches[] = { {0x8086, 0x27b9, 0xa0a0, 0x0632, 0x8086, 0x27da, 0xa0a0, 0x0632, NULL, NULL, NULL, P3, "AOpen", "i945GMx-VFX", 0, OK, intel_ich_gpio38_raise}, {0x8086, 0x277c, 0xa0a0, 0x060b, 0x8086, 0x27da, 0xa0a0, 0x060b, NULL, NULL, NULL, P3, "AOpen", "i975Xa-YDG", 0, OK, board_aopen_i975xa_ydg}, {0x8086, 0x27b8, 0x1849, 0x27b8, 0x8086, 0x27da, 0x1849, 0x27da, "^ConRoeXFire-eSATA2", NULL, NULL, P3, "ASRock", "ConRoeXFire-eSATA2", 0, OK, intel_ich_gpio16_raise}, + {0x1022, 0x1536, 0x1849, 0x1536, 0x1022, 0x780e, 0x1849, 0x780e, "^Kabini CRB$", NULL, NULL, P2, "ASRock", "IMB-A180(-H)", 0, OK, p2_not_a_laptop}, {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e}, {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41GX$", NULL, NULL, P3, "ASRock", "K7S41GX", 0, OK, w836xx_memw_enable_2e}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, diff --git a/chipset_enable.c b/chipset_enable.c index b52a5b4..2706be4 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1304,7 +1304,7 @@ const struct penable chipset_enables[] = { {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, - {0x1022, 0x780e, OK, "AMD", "Hudson", enable_flash_sb600}, + {0x1022, 0x780e, OK, "AMD", "FCH", enable_flash_sb600}, {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501}, {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496}, {0x1039, 0x0530, OK, "SiS", "530", enable_flash_sis530}, diff --git a/sb600spi.c b/sb600spi.c index e76c04a..ec70ffc 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -44,6 +44,62 @@ */ static uint8_t *sb600_spibar = NULL; +enum amd_chipset { + CHIPSET_AMD_UNKNOWN, + CHIPSET_SB6XX, + CHIPSET_SB7XX, /* SP5100 too */ + CHIPSET_SB89XX, /* Hudson-1 too */ + CHIPSET_HUDSON234, + CHIPSET_YANGTZE, +}; +static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; + +static void determine_generation(struct pci_dev *dev) +{ + amd_gen = CHIPSET_AMD_UNKNOWN; + msg_pdbg2("Trying to determine the generation of the SPI interface.\n"); + if (dev->device_id == 0x780e) { + /* The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and Yangtze (Kabini/Temash) + * although they use different SPI interfaces. */ +#ifdef USE_YANGTZE_HEURISTIC + /* This heuristic accesses the SPI interface MMIO BAR at locations beyond those supported by + * Hudson in the hope of getting 0xff readback on older chipsets and non-0xff readback on + * Yangtze (and newer, compatible chipsets). */ + int i; + msg_pdbg("Checking for AMD Yangtze (Kabini/Temash) or later... "); + for (i = 0x20; i <= 0x4f; i++) { + if (mmio_readb(sb600_spibar + i) != 0xff) { + amd_gen = CHIPSET_YANGTZE; + msg_pdbg("found.\n"); + return; + } + } + msg_pdbg("not found. Assuming Hudson.\n"); + amd_gen = CHIPSET_HUDSON234; +#else + struct pci_dev *smbus_dev = pci_dev_find(0x1022, 0x780B); + if (smbus_dev == NULL) { + msg_pdbg("No SMBus device with ID 1022:780B found.\n"); + return; + } + uint8_t rev = pci_read_byte(smbus_dev, PCI_REVISION_ID); + if (rev >= 0x11 && rev <= 0x15) { + amd_gen = CHIPSET_HUDSON234; + msg_pdbg("Hudson-2/3/4 detected.\n"); + } else if (rev >= 0x39 && rev <= 0x3A) { + amd_gen = CHIPSET_YANGTZE; + msg_pdbg("Yangtze detected.\n"); + } else { + msg_pwarn("FCH device found but SMBus revision 0x%02x does not match known values.\n" + "Please report this to flashrom(a)flashrom.org and include this log and\n" + "the output of lspci -nnvx, thanks!.\n", rev); + } +#endif + } else + msg_perr("%s: Unknown LPC device %" PRIx16 ":%" PRIx16 ".\n", + __func__, dev->vendor_id, dev->device_id); +} + static void reset_internal_fifo_pointer(void) { @@ -281,6 +337,14 @@ int sb600_probe_spi(struct pci_dev *dev) */ sb600_spibar += tmp & 0xfff; + determine_generation(dev); + + if (amd_gen == CHIPSET_YANGTZE) { + msg_perr("SPI on Kabini/Temash and newer chipsets are not yet supported.\n" + "Please try a newer version of flashrom.\n"); + return ERROR_NONFATAL; + } + tmp = pci_read_long(dev, 0xa0); msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, -- Kind regards, Stefan Tauner

1 0

Intel DQ45CB - flashrom -V - ouput
by Kurtis W 03 Aug '13

03 Aug '13

flashrom v0.9.5.2-r1517 on Linux 3.2.0-51-generic-pae (i686), built with libpci 3.1.8, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 2994M loops per second, 10 myus = 10 us, 100 myus = 101 us, 1000 myus = 999 us, 10000 myus = 10007 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "" DMI string system-product-name: "" DMI string system-version: "000" DMI string baseboard-manufacturer: "Intel Corporation" DMI string baseboard-product-name: "DQ45CB" DMI string baseboard-version: "AAE30148-303" DMI string chassis-type: "Desktop" Found chipset "Intel ICH10DO" with PCI ID 8086:3a14. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x2 Root Complex Register Block address = 0xfed1c000 GCS = 0x1465: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 WARNING: SPI Configuration Lockdown activated. Reading OPCODES... done 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x00001a1b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x1a, BRRA 0x1b 0x54: 0x00000000 FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x03ff0280 FREG1: BIOS region (0x00280000-0x003fffff) is read-write. 0x5C: 0x02770003 FREG2: WARNING: Management Engine region (0x00003000-0x00277fff) is locked. 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write. 0x64: 0x027f0278 FREG4: Platform Data region (0x00278000-0x0027ffff) is read-write. Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled. You can enforce write support with the ich_spi_force programmer option, but it will most likely harm your hardware! If you force flashrom you will get no support if something breaks. 0x90: 0x04 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0x004240 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=2, SME=0, SCF=0 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x0000019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00000000 (LVSCC) LVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=0 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) SPI Read Configuration: prefetching disabled, caching enabled, OK. The following protocols are supported: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25LF080A, 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25VF010, 128 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF040, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF040B.REMS, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Chip status register is 00 Found Winbond flash chip "W25Q32" (4096 kB, SPI) at physical address 0xffc00000. Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Unknown SFDP-capable chip, 0 kB: Invalid OPCODE 0x5a, will not execute. Receiving SFDP signature failed. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (REMS), 0 kB: Invalid OPCODE 0x90, will not execute. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0x0f, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xe7, id2 0xca, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0x0f, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xe7, id2 0xca, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0x0f, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x30, id2 0xeb, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xe7, id2 0xca, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xe7, id2 0xca, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xe7, id2 0xca, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xe7, id2 0xca, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0x0f, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xe7, id2 0xca, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0x0f, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xe7, id2 0xca, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x2f, id2 0x8c, id1 is normal flash content, id2 is normal flash content Found Winbond flash chip "W25Q32" (4096 kB, SPI). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). No operations were specified. Restoring MMIO space at 0xb77618a0 Restoring PCI config space for 00:1f:0 reg 0xdc

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flashrom -V Dell XPS L702X
by Don Alexander 01 Aug '13

01 Aug '13

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 - -- CUT -- flashrom -V flashrom v0.9.5.2-r1546 on Linux 3.2.0-4-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.7, GCC 4.6.2, little endian Command line (1 args): flashrom -V Calibrating delay loop... OS timer resolution is 1 usecs, 3017M loops per second, 10 myus = 10 us, 100 myus = 115 us, 1000 myus = 992 us, 10000 myus = 9922 us, 4 myus = 13 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Dell Inc. " DMI string system-product-name: "Dell System XPS L702X" DMI string system-version: "Not Specified" DMI string baseboard-manufacturer: "Dell Inc. " DMI string baseboard-product-name: "03RG89" DMI string baseboard-version: "FAB1" DMI string chassis-type: "Portable" Laptop detected via DMI. W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 85. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found ITE EC, ID 0x8518,Rev 0x02 on port 0x4e. ======================================================================== WARNING! You seem to be running flashrom on an unsupported laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Aborting. - -- CUT -- - -- == Don Alexander It's a tough job, but some mug has to do it... RooSoft Ltd -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iEYEARECAAYFAlH6Y+4ACgkQuipFNInZ6etJJgCeOwunO2DdppKh3RbSExvBZXem 9BUAniT+UHsGKRlGXNKO3jaie2nYb8mD =C01L -----END PGP SIGNATURE-----

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Re: [flashrom] A quick hack to support AMD Family 16h SOC
by Carl-Daniel Hailfinger 31 Jul '13

31 Jul '13

Am 30.07.2013 23:22 schrieb Wei Hu: > On Tue, Jul 30, 2013 at 1:59 PM, Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2006(a)gmx.net> wrote: >> This patch should work at normal speed and use the correct FIFO pointer >> registers on Kabini. >> The code is not exactly pretty, but functional and should (in theory) >> need no functional changes before commit. >> >> Please check if read/write works at the expected speed. -VV is >> sufficient this time. > > Reading the 4MB flash took 18 seconds, whereas writing took almost 3 > minutes. Is it normal? On another system with Intel PCH writes were > way faster. There's another FIFO register at offset 0x80 in the new > Kabini interface, which can hopefully speed up things, but the > description is quite dense. > > I'm attaching two -VV logs, one from reading and the other from writing. Thanks! This means my code works well. The following timings are straight from the W25Q32BV datasheet. They may be completely unrealistic. Typical erase time for that chip is around 30 seconds for a sectorwise chip erase (without overhead). The typical write time for that chip (using 5-byte chunks due to the short FIFO for SB600) would be around 600 seconds. Typical write time for that chip with the long Kabini FIFO would be 45 seconds. Add initial read time, sectorwise chip erase time, erase-verify time (full chip read), write time, write-verify time (full chip read) and the write time suddenly looks pretty reasonable. Most important for me was to get the FIFO pointers right for Kabini. Speed issues can be dealt with after the flashrom 0.9.7 release (right now I'm just trying to fix things). That said, the datasheet is rather unclear about the effect of UseSpi100=1, and I'd like to set it to 0. By the way, the data which enabled me to fix the FIFO stuff for Kabini (because the datasheets have room for improvement) is here: http://paste.flashrom.org/view.php?id=1718 Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

Re: [flashrom] A quick hack to support AMD Family 16h SOC
by Carl-Daniel Hailfinger 30 Jul '13

30 Jul '13

Am 30.07.2013 20:55 schrieb Wei Hu: > Attached is a log from flashrom -VVV -p internal -o /tmp/flashrom.log. > Please let me know what else you want to collect. Thanks! > On Sun, Jul 28, 2013 at 3:38 PM, Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2006(a)gmx.net> wrote: >> Am 26.07.2013 23:31 schrieb Stefan Tauner: >>> On Fri, 26 Jul 2013 12:28:48 -0700 >>> Wei Hu <wei(a)aristanetworks.com> wrote: >>>> On Fri, Jul 26, 2013 at 12:18 AM, Carl-Daniel Hailfinger >>>> <c-d.hailfinger.devel.2006(a)gmx.net> wrote: >>>>>> I'll give you modified patch a test tomorrow. >>>>> Please note that I expect problems with my patch. Not all of the FIFO >>>>> management has been changed, and this might be the cause of error >>>>> messages. Updated patch with more debugging at the end of this mail. >>>> After changing the device ID to match 0x780e, your patch works for >>>> both reading and writing. Writing is extremely slow though. I feel >>>> like on this new FCH we should ditch the SB600 interface and >>>> investigate the new programming interface. My current patch is more >>>> like a band aid workaround. >>> I plan to do that but for now it would be better than nothing, *but* >>> this will break Hudson-2... I talked to Martin Roth from sage and he >>> confirmed that although AMD changed PCI IDs with Hudson-1 the >>> interface did only really change with Kabini/Temash. >>> >>> That explains also why Hudson-2 worked fine previously: >>> http://marc.info/?l=flashrom&m=131853263731000 >>> Wang Qing Pei has tested his Hudson patch too probably before sending >>> it to us but I don't know which system he used exactly. >>> >>> I'll try to get the Hudson-2 datasheets, but ATM I don't have them. >>> We need a way to distinguish Kabini from the rest... since it is a SoC, >>> we could match the pci ids of the root complex >>> (00:00.0 Host bridge [0600]: Advanced Micro Devices [AMD] Family 16h >>> Processor Root Complex [1022:1536] in my case), but we would need to >>> maintain that for future models... Martin told me that they just read >>> if the new registers are (non-)0xff and infer from that if they need to >>> use the new interface. >> New patch. Better heuristic (Martin's variant) for Kabini, more debug >> prints. >> The big challenge is to check whether this breaks Hudson variants before >> Kabini. >> >> Please get some -VVV logs for a simple probe. Thanks! >> # flashrom -o logfile.txt -VVV >> >> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> This patch should work at normal speed and use the correct FIFO pointer registers on Kabini. The code is not exactly pretty, but functional and should (in theory) need no functional changes before commit. Please check if read/write works at the expected speed. -VV is sufficient this time. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-kabini/sb600spi.c =================================================================== --- flashrom-kabini/sb600spi.c (Revision 1704) +++ flashrom-kabini/sb600spi.c (Arbeitskopie) @@ -4,7 +4,7 @@ * Copyright (C) 2008 Wang Qingpei <Qingpei.Wang(a)amd.com> * Copyright (C) 2008 Joe Bao <Zheng.Bao(a)amd.com> * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger + * Copyright (C) 2009, 2010, 2013 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -45,6 +45,8 @@ static uint8_t *sb600_spibar = NULL; +static int kabini_method = 0; + static void reset_internal_fifo_pointer(void) { mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2); @@ -54,33 +56,67 @@ msg_pspew("reset\n"); } -static int compare_internal_fifo_pointer(uint8_t want) +static int check_internal_fifo_pointer(uint8_t have, uint8_t want) { + if (have != want) { + msg_perr("AMD SPI FIFO pointer corruption! Pointer is %d, wanted %d\n", have, want); + msg_perr("Something else is accessing the flash chip and causes random corruption.\n" + "Please stop all applications and drivers and IPMI which access the flash chip.\n"); + return 1; + } + msg_pspew("AMD SPI FIFO pointer is %d, wanted %d\n", have, want); + return 0; +} + +static int compare_internal_kabini_fifo_write_pointer(uint8_t want) +{ uint8_t tmp; + tmp = mmio_readb(sb600_spibar + 0x4d) & 0x7f; + return check_internal_fifo_pointer(tmp, want); +} + +static int compare_internal_kabini_fifo_read_pointer(uint8_t want) +{ + uint8_t tmp; + + tmp = mmio_readb(sb600_spibar + 0x4e) & 0x7f; + return check_internal_fifo_pointer(tmp, want); +} + +static int compare_internal_sb600_fifo_pointer(uint8_t want) +{ + uint8_t tmp; + tmp = mmio_readb(sb600_spibar + 0xd) & 0x07; want &= 0x7; - if (want != tmp) { - msg_perr("FIFO pointer corruption! Pointer is %d, wanted %d\n", tmp, want); - msg_perr("Something else is accessing the flash chip and " - "causes random corruption.\nPlease stop all " - "applications and drivers and IPMI which access the " - "flash chip.\n"); - return 1; - } else { - msg_pspew("SB600 FIFO pointer is %d, wanted %d\n", tmp, want); - return 0; - } + return check_internal_fifo_pointer(tmp, want); } +#if 0 static int reset_compare_internal_fifo_pointer(uint8_t want) { int ret; +#if 0 + if (kabini_method) { + uint8_t tmp1; + mmio_writeb(7, sb600_spibar + 0x1e); + tmp = mmio_readb(sb600_spibar + 0x1f); + msg_pspew("Kabini SPIDataFifoPtr %d/%d, ", tmp, want); + tmp = mmio_readb(sb600_spibar + 0xd) & 0x07; + msg_pspew("FifoPtr %d/%d, ", tmp, want & 0x07); + tmp = mmio_readb(sb600_spibar + 0x4d) & 0x7f; + tmp1 = mmio_readb(sb600_spibar + 0x4e) & 0x7f; + msg_pspew("FifoWrPtr/FifoRdPtr %d/%d\n", tmp, tmp1); + } +#endif + ret = compare_internal_fifo_pointer(want); reset_internal_fifo_pointer(); return ret; } +#endif static void execute_command(void) { @@ -99,7 +135,7 @@ /* First byte is cmd which can not being sent through FIFO. */ unsigned char cmd = *writearr++; unsigned int readoffby1; - unsigned char readwrite; + unsigned char readwrite = 0; writecnt--; @@ -118,15 +154,21 @@ return SPI_INVALID_LENGTH; } - /* This is a workaround for a bug in SB600 and SB700. If we only send - * an opcode and no additional data/address, the SPI controller will - * read one byte too few from the chip. Basically, the last byte of - * the chip response is discarded and will not end up in the FIFO. - * It is unclear if the CS# line is set high too early as well. - */ - readoffby1 = (writecnt) ? 0 : 1; - readwrite = (readcnt + readoffby1) << 4 | (writecnt); - mmio_writeb(readwrite, sb600_spibar + 1); + if (kabini_method) { + /* Use the extended TxByteCount and RxByteCount register. */ + mmio_writeb(writecnt, sb600_spibar + 0x48); + mmio_writeb(readcnt, sb600_spibar + 0x4b); + } else { + /* This is a workaround for a bug in SB600 and SB700. If we only send + * an opcode and no additional data/address, the SPI controller will + * read one byte too few from the chip. Basically, the last byte of + * the chip response is discarded and will not end up in the FIFO. + * It is unclear if the CS# line is set high too early as well. + */ + readoffby1 = (writecnt) ? 0 : 1; + readwrite = (readcnt + readoffby1) << 4 | (writecnt); + mmio_writeb(readwrite, sb600_spibar + 1); + } mmio_writeb(cmd, sb600_spibar + 0); /* Before we use the FIFO, reset it first. */ @@ -139,16 +181,29 @@ mmio_writeb(*writearr, sb600_spibar + 0xC); } msg_pspew("\n"); + if (kabini_method) { + if (compare_internal_kabini_fifo_write_pointer(writecnt)) + return SPI_PROGRAMMER_ERROR; + } else { + if (compare_internal_sb600_fifo_pointer(writecnt)) + return SPI_PROGRAMMER_ERROR; + } /* * We should send the data by sequence, which means we need to reset * the FIFO pointer to the first byte we want to send. */ - if (reset_compare_internal_fifo_pointer(writecnt)) - return SPI_PROGRAMMER_ERROR; + reset_internal_fifo_pointer(); msg_pspew("Executing: \n"); execute_command(); + if (kabini_method) { + if (compare_internal_kabini_fifo_write_pointer(writecnt + readcnt)) + return SPI_PROGRAMMER_ERROR; + } else { + if (compare_internal_sb600_fifo_pointer(writecnt + readcnt)) + return SPI_PROGRAMMER_ERROR; + } /* * After the command executed, we should find out the index of the @@ -161,8 +216,7 @@ * the opcode, the FIFO already stores the response from the chip. * Usually, the chip will respond with 0x00 or 0xff. */ - if (reset_compare_internal_fifo_pointer(writecnt + readcnt)) - return SPI_PROGRAMMER_ERROR; + reset_internal_fifo_pointer(); /* Skip the bytes we sent. */ msg_pspew("Skipping: "); @@ -171,27 +225,53 @@ msg_pspew("[%02x]", cmd); } msg_pspew("\n"); - if (compare_internal_fifo_pointer(writecnt)) - return SPI_PROGRAMMER_ERROR; + if (kabini_method) { + if (compare_internal_kabini_fifo_read_pointer(writecnt)) + return SPI_PROGRAMMER_ERROR; + } else { + if (compare_internal_sb600_fifo_pointer(writecnt)) + return SPI_PROGRAMMER_ERROR; + } + msg_pspew("Reading: "); for (count = 0; count < readcnt; count++, readarr++) { *readarr = mmio_readb(sb600_spibar + 0xC); msg_pspew("[%02x]", *readarr); } msg_pspew("\n"); - if (reset_compare_internal_fifo_pointer(readcnt + writecnt)) - return SPI_PROGRAMMER_ERROR; - if (mmio_readb(sb600_spibar + 1) != readwrite) { - msg_perr("Unexpected change in SB600 read/write count!\n"); - msg_perr("Something else is accessing the flash chip and " - "causes random corruption.\nPlease stop all " - "applications and drivers and IPMI which access the " - "flash chip.\n"); - return SPI_PROGRAMMER_ERROR; + if (kabini_method) { + if (compare_internal_kabini_fifo_read_pointer(writecnt + readcnt)) + return SPI_PROGRAMMER_ERROR; + } else { + if (compare_internal_sb600_fifo_pointer(writecnt + readcnt)) + return SPI_PROGRAMMER_ERROR; } + reset_internal_fifo_pointer(); + if (kabini_method) { + uint8_t tmp_wc = mmio_readb(sb600_spibar + 0x48); + uint8_t tmp_rc = mmio_readb(sb600_spibar + 0x4b); + if ((tmp_rc != readcnt) || (tmp_wc != writecnt)) { + msg_perr("Unexpected change in Kabini read/write count: %i/%i instead of %i/%i!\n", + tmp_rc, tmp_wc, readcnt, writecnt); + msg_perr("Something else is accessing the flash chip and causes random corruption.\n" + "Please stop all applications and drivers and IPMI which access the flash " + "chip.\n"); + return SPI_PROGRAMMER_ERROR; + } + } else { + uint8_t tmp_rw = mmio_readb(sb600_spibar + 1); + if (tmp_rw != readwrite) { + msg_perr("Unexpected change in SB600 read/write count: %i instead of %i!\n", tmp_rw, + readwrite); + msg_perr("Something else is accessing the flash chip and causes random corruption.\n" + "Please stop all applications and drivers and IPMI which access the flash " + "chip.\n"); + return SPI_PROGRAMMER_ERROR; + } + } return 0; } @@ -245,8 +325,8 @@ uint32_t tmp; uint8_t reg; bool amd_imc_force = false; - static const char *const speed_names[4] = { - "66/reserved", "33", "22", "16.5" + static const char *const speed_names[8] = { + "66 MHz", "33 MHz", "22 MHz", "16.6 MHz", "100 MHz", "Reserved", "Reserved", "800 kHz" }; char *arg = extract_programmer_param("amd_imc_force"); @@ -281,6 +361,30 @@ */ sb600_spibar += tmp & 0xfff; + /* AMD Kabini has a different SPI interface. */ + kabini_method = 0; + if (dev->device_id == 0x780e) { + /* The PCI ID of the LPC bridge doesn't change between Hudson-2 and Kabini (Hudson-3) although + * they use different SPI interfaces. ID 0x780e is common for all Hudson variants. This + * heuristic accesses the SPI interface MMIO BAR at locations beyond those supported by + * Hudson-2 and earlier in the hope of getting 0xff readback on older chipsets and non-0xff + * readback on Kabini and newer chipsets. + */ + int i; + msg_pdbg("Checking for AMD Kabini or later... "); + for (i = 0x20; i <= 0x4f; i++) { + if (mmio_readb(sb600_spibar + i) != 0xff) { + kabini_method = 1; + break; + } + } + if (kabini_method) + msg_pdbg("using AMD Kabini SPI access method.\n"); + else + msg_pdbg("not found.\n"); + } + + /* FIXME: Check all accesses below for Kabini incompatibilities. */ tmp = pci_read_long(dev, 0xa0); msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, @@ -300,15 +404,28 @@ * SB700 or later, reads and writes will be corrupted. Abort in this * case. Make sure to avoid this check on SB600. */ - msg_pdbg("(0x%08" PRIx32 ") fastReadEnable=%u, SpiArbEnable=%i, SpiAccessMacRomEn=%i, " + msg_pdbg("(0x%08" PRIx32 ") SpiReadMode/FastReadEnable=%i, SpiArbEnable=%i, SpiAccessMacRomEn=%i, " "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " - "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", - tmp, (tmp >> 18) & 0x1, + "SpiBridgeDisable=%i, SpiClkGate/DropOneClkOnRd=%i\n", + tmp, ((tmp >> 28) & 0x6) | ((tmp >> 18) & 0x1), (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); - tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; - msg_pdbg("NormSpeed is %s MHz\n", speed_names[tmp]); + if (kabini_method) { + tmp = mmio_readb(sb600_spibar + 0x20) & 0x1; + msg_pdbg("UseSpi100 is %i (%s)\n", tmp, tmp ? "unsupported" : "OK"); + tmp = mmio_readw(sb600_spibar + 0x22); + msg_pdbg("TpmSpeedNew is %s\n", speed_names[tmp & 0xf]); + tmp >>= 4; + msg_pdbg("AltSpeedNew is %s\n", speed_names[tmp & 0xf]); + tmp >>= 4; + msg_pdbg("FastSpeedNew is %s\n", speed_names[tmp & 0xf]); + tmp >>= 4; + msg_pdbg("NormSpeedNew is %s\n", speed_names[tmp & 0xf]); + } else { + tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; + msg_pdbg("NormSpeed is %s MHz\n", speed_names[tmp]); + } /* Look for the SMBus device. */ smbus_dev = pci_dev_find(0x1002, 0x4385); -- http://www.hailfinger.org/

2 1

MSI H87-G43 flash success :)
by Marek Zakrzewski 30 Jul '13

30 Jul '13

flashrom v0.9.6.1-r1564 on Linux 2.6.18-348.12.1.el5 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel Lynx Point". This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... enable_flash_ich_dc_spi: unknown ICH generation. Please report! WARNING: SPI Configuration Lockdown activated. Enabling hardware sequencing because some important opcode is locked. OK. Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) at physical address 0x0. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. flashrom v0.9.6.1-r1564 on Linux 2.6.18-348.12.1.el5 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.7, GCC 4.1.2 20080704 (Red Hat 4.1.2-54), little endian Command line (2 args): flashrom -V --programmer=internal Calibrating delay loop... OS timer resolution is 1 usecs, 3365M loops per second, 10 myus = 10 us, 100 myus = 106 us, 1000 myus = 1014 us, 10000 myus = 10006 us, 4 myus = 6 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "MSI" DMI string system-product-name: "MS-7816" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "MSI" DMI string baseboard-product-name: "H87-G43 (MS-7816)" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" Found chipset "Intel Lynx Point" with PCI ID 8086:8c4a. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... enable_flash_ich_dc_spi: unknown ICH generation. Please report! 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x4 0x7fffffff/0x7fffffff FWH IDSEL: 0x5 0x7fffffff/0x7fffffff FWH IDSEL: 0x6 0x7fffffff/0x7fffffff FWH IDSEL: 0x7 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x8 Root Complex Register Block address = 0xfed1c000 GCS = 0xc65: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (unknown) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xf008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 WARNING: SPI Configuration Lockdown activated. Reading OPCODES... done 0x06: 0x3f00 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0 0x08: 0x00ffffc0 (FADDR) 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write. 0x58: 0x0fff0a00 FREG1: BIOS region (0x00a00000-0x00ffffff) is read-write. 0x5C: 0x09ff0001 FREG2: Management Engine region (0x00001000-0x009fffff) is read-write. 0x90: 0xc0 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0x91: 0xfc4010 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=0, SME=0, SCF=4 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05203b02 (OPMENU) 0x9C: 0x0000019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x80802025 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xC8: 0x00002025 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x50444653 (FPB) Enabling hardware sequencing because some important opcode is locked. SPI Read Configuration: prefetching enabled, caching enabled, OK. The following protocols are supported: FWH, Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Found 1 attached SPI flash chip with a density of 16384 kB. The flash address space (0x000000 - 0x9acfff) is divided at address 0x653000 in two partitions. The first partition ranges from 0x000000 to 0x652fff. In that range are 1619 erase blocks with 4096 B each. The second partition ranges from 0x653000 to 0x9acfff. In that range are 2477 erase blocks with 4096 B each. Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) at physical address 0x0. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x00, id2 0x03, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x2d, id2 0xbd, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x2d, id2 0xbd, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xed, id2 0x88, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific). No operations were specified. Restoring MMIO space at 0x2b92ee7ee8a0 Restoring PCI config space for 00:1f:0 reg 0xdc

2 7

Re: [flashrom] A quick hack to support AMD Family 16h SOC
by Stefan Tauner 30 Jul '13

30 Jul '13

On Fri, 26 Jul 2013 12:28:48 -0700 Wei Hu <wei(a)aristanetworks.com> wrote: > On Fri, Jul 26, 2013 at 12:18 AM, Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2006(a)gmx.net> wrote: > >> I'll give you modified patch a test tomorrow. > > > > Please note that I expect problems with my patch. Not all of the FIFO > > management has been changed, and this might be the cause of error > > messages. Updated patch with more debugging at the end of this mail. > > After changing the device ID to match 0x780e, your patch works for > both reading and writing. Writing is extremely slow though. I feel > like on this new FCH we should ditch the SB600 interface and > investigate the new programming interface. My current patch is more > like a band aid workaround. I plan to do that but for now it would be better than nothing, *but* this will break Hudson-2... I talked to Martin Roth from sage and he confirmed that although AMD changed PCI IDs with Hudson-1 the interface did only really change with Kabini/Temash. That explains also why Hudson-2 worked fine previously: http://marc.info/?l=flashrom&m=131853263731000 Wang Qing Pei has tested his Hudson patch too probably before sending it to us but I don't know which system he used exactly. I'll try to get the Hudson-2 datasheets, but ATM I don't have them. We need a way to distinguish Kabini from the rest... since it is a SoC, we could match the pci ids of the root complex (00:00.0 Host bridge [0600]: Advanced Micro Devices [AMD] Family 16h Processor Root Complex [1022:1536] in my case), but we would need to maintain that for future models... Martin told me that they just read if the new registers are (non-)0xff and infer from that if they need to use the new interface. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[PATCH] Fix dediprog crash if usb_open() fails
by David Woodhouse 30 Jul '13

30 Jul '13

Signed-off-by: David Woodhouse <David.Woodhouse(a)intel.com> --- Ick. You made me touch Subversion, even if only through 'git svn clone'. diff --git a/dediprog.c b/dediprog.c index fb95d10..2640808 100644 --- a/dediprog.c +++ b/dediprog.c @@ -884,6 +884,10 @@ int dediprog_init(void) msg_pdbg("Found USB device (%04x:%04x).\n", dev->descriptor.idVendor, dev->descriptor.idProduct); dediprog_handle = usb_open(dev); + if (!dediprog_handle) { + msg_perr("Could not open USB device: %s\n", usb_strerror()); + return 1; + } ret = usb_set_configuration(dediprog_handle, 1); if (ret < 0) { msg_perr("Could not set USB device configuration: %i %s\n", -- David Woodhouse Open Source Technology Centre David.Woodhouse(a)intel.com Intel Corporation

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[commit] r1705 - trunk
by repository service 30 Jul '13

30 Jul '13

Author: stefanct Date: Tue Jul 30 11:34:44 2013 New Revision: 1705 URL: http://flashrom.org/trac/flashrom/changeset/1705 Log: dediprog: Fix crash if usb_open() fails. Signed-off-by: David Woodhouse <David.Woodhouse(a)intel.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/dediprog.c Modified: trunk/dediprog.c ============================================================================== --- trunk/dediprog.c Fri Jul 26 00:58:56 2013 (r1704) +++ trunk/dediprog.c Tue Jul 30 11:34:44 2013 (r1705) @@ -884,6 +884,10 @@ msg_pdbg("Found USB device (%04x:%04x).\n", dev->descriptor.idVendor, dev->descriptor.idProduct); dediprog_handle = usb_open(dev); + if (!dediprog_handle) { + msg_perr("Could not open USB device: %s\n", usb_strerror()); + return 1; + } ret = usb_set_configuration(dediprog_handle, 1); if (ret < 0) { msg_perr("Could not set USB device configuration: %i %s\n",

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/dev/mem mmap failed : Operation not permitted
by WON-JUN SONG 30 Jul '13

30 Jul '13

Hi. I tried to read the contents of BIOS via flashrom. the main board is TYAN s8230. when I executed read command (such as sudo ./flashrom -r backup.bin -p internal), the error message are below "Error accessing flash chip, 0x2000000 bytes at 0x00000000fe000000 /dev/mem mmap failed: Operation not permitted" this message is derived from "probe_flash()" function. I don't understand why this error message occurs? anyway I modified the source code to skip some vendors and chip which cause above error message. then another error message are below "Reading flash.. SB600 FIFO pointer corruption! Pointer is 0, wanted 3 Something else is accessing the flash chip and causes random corruption. Please stop all applications and drivers and IPMI which access the flash chip Read operation failed! FAILED" I dont understand why IPMI is related to flashing BIOS. thanks.

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Re: [flashrom] E350M1 Winbond W25Q32BVAIG and bus pirate
by Stefan Tauner 29 Jul '13

29 Jul '13

On Sun, 28 Jul 2013 23:47:40 +0200 Marek <mlf.conv(a)gmail.com> wrote: > It seems that both hold and write-protect should be connected to 3.3V > but I'm not sure how to achieve it with BP 3.6. Why? Just connect them to Vcc. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] E350M1 Winbond W25Q32BVAIG and bus pirate
by Stefan Tauner 28 Jul '13

28 Jul '13

On Sun, 28 Jul 2013 21:45:01 +0200 Marek <mlf.conv(a)gmail.com> wrote: > Hi Stefan, > > thanks for your response, I checked that webpage but it seems that the > suggestions apply to chips while they're still "sitting on" motherboards > where as in my case the chip is pulled out and connected via Probe kit(no > modifications). They do, but most parts of it do apply as well to directly connected chips. Also... be sure to connect ALL (input) pins. http://flashrom.org/Bus_Pirate -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] E350M1 Winbond W25Q32BVAIG and bus pirate
by Stefan Tauner 28 Jul '13

28 Jul '13

On Sun, 28 Jul 2013 20:28:25 +0200 Marek <mlf.conv(a)gmail.com> wrote: > Hi, > > I'd like to ask whether someone has got some experience with flashing a > Winbond W25Q32BVAIG found on a E350M1 Asrock board using flashrom > and Bus Pirate +Bus Pirate Probe kit. > Currently I'm getting the following message: > > Found Generic flash chip "unknown SPI chip (RDID)" (0 kB, SPI). Check your cabling and see some more details here: http://flashrom.org/ISP -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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E350M1 Winbond W25Q32BVAIG and bus pirate
by Marek 28 Jul '13

28 Jul '13

Hi, I'd like to ask whether someone has got some experience with flashing a Winbond W25Q32BVAIG found on a E350M1 Asrock board using flashrom and Bus Pirate +Bus Pirate Probe kit. Currently I'm getting the following message: Found Generic flash chip "unknown SPI chip (RDID)" (0 kB, SPI). === This flash part has status NOT WORKING for operations: PROBE READ ERASE WRITE BP bootloader 4.4 firmware v6.1 flashrom v0.9.6.1-r1704 on Linux 3.9.11_1 (i686) thanks, Marek

1 0

MSI k9N6SGM-V (ms-7309)
by Joakim Junttila 28 Jul '13

28 Jul '13

Hello! I was trying to update my bios with flashrom but ran into this and was told to mail you about it. http://pastebin.com/dFanGufc ------------------------------------------------------------------------ Regards, Joakim Junttila <http://pastebin.com/dFanGufc>

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Re: [flashrom] Flashrom fails on write. P4 motherboard
by Stefan Tauner 27 Jul '13

27 Jul '13

On Thu, 25 Jul 2013 20:23:32 +0200 san <san(a)plusnet.pl> wrote: > Just uploaded lspci -nn here: http://e-san.info/Flashrom-P4/lspci-nn.txt > How to lower GPIO by hand (before patch)? Ah I forgot... I need one verbose flag too for the final patch, so that we see the subsystem IDs too, sorry. So it should have been lspci -nnv. I have prepared a preliminary patch that should at least verify if the reverse engineering is correct, see the attachment. You can also set this somehow with pciset as you know, I am just not entirely sure about the exact commands. you would need to get the gpiobase first with setpci -s 00:1f.0 58.l (only bits 6-15 are the base address see datasheet) and then fetch the old value with setpci -s 0:1f.0 gpiobase+0x0c and set it with setpci -s 0:1f.0 gpiobase+0x0c=... I would rather just try the patch. :) Sometimes there happen errors while reverse engineering the code so it is possible that you actually need to raise the pin instead or that the pin number is off by one. If you are a bit into programming then I am sure you can figure out how to refine the patch if necessary, but we can help you too of course. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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WG: SB600, shutting down IMC failed
by Trunzer Markus 26 Jul '13

26 Jul '13

>Can you tell us more about your system's firmware? =>What kind of information do you mean concretely? >Should the IMC be active and responsive? =>I'm not sure what the consequence is in detail when the IMC is inactive. But I gues it doesn't need to be active. >Rudolf: Let's assume the IMC is set up but does not respond in time (btw I guess a longer timeout won't help? =>Can you please tell me where I can increase this time? Best regards Markus On Thu, 11 Jul 2013 13:50 >Hello together, >I'm very sorry...I didn't verified the output at the display and the logfile content. Yes, your absolutely right, the message "IMC MBOX: Timeout!" is printed after the line "EC MBOX is at 0x3e". >And at the end there are 3 more lines: > >"FATAL ERROR! >Unhandled programmer parameters: amd_imc_force=yes >Error: Programmer initialization failed." > >Best regards >Markus_T On Thu, 11 Jul 2013 12:24:47 +0200 > Hello again, > I used this source code > http://download.flashrom.org/snapshots/flashrom-0.9.6.1-r1643.tar.bz2 and patched it with patch 3894 "patch<AMD---SP5100---take-SPI-ownership-1-2.patch". The patching and compiling was without errors. > > The execution of flashrom with "flashrom -VVV -p internal:amd_imc_force=yes" resulted in following error message. > > > flashrom v0.9.6.1-r1643 on Linux 3.0.1pae (i686) flashrom is free > software, get the source code at http://www.flashrom.org > > flashrom was built with libpci 3.1.7, GCC 4.4.5, little endian Command > line (3 args): flashrom -VVV -p internal:amd_imc_force=yes Calibrating > delay loop... OS timer resolution is 1 usecs, 824M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 1000 us, 10000 myus = 10008 us, 4 myus = 4 us, OK. > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "To be filled by O.E.M." > DMI string system-product-name: "To be filled by O.E.M." > DMI string system-version: "To be filled by O.E.M." > DMI string baseboard-manufacturer: "abc" > DMI string baseboard-product-name: "123" > DMI string baseboard-version: "1.1.0" > DMI string chassis-type: "Desktop" > Found chipset "AMD SB7x0/SB8x0/SB9x0" with PCI ID 1002:439d. Enabling flash write... > EC SIO is at 0x6e > EC MBOX is at 0x3e > (Shutting down IMC failed!) > FAILED! > > > Do you have an idea what the problem could be? > I have no idea what the underlying problem is, but can it be that you did only paste the output to stdout and not to stderr (which can happen if you redirect the output of flashrom with ">/some/logfile" instead of using the -o option or directing with ">/some/logfile 2>&1")? I am asking because I am pretty sure that there is "IMC MBOX: Timeout!" in the original output (to stderr). And in that case it is clearly not an error introduced by me refinement of the patch, and I would like to continue/test/fix my current version (3979) on top of current HEAD (or at least r1680) instead of the original one, because we want to merge the new version eventually of course. Can you tell us more about your system's firmware? Should the IMC be active and responsive? Rudolf: Let's assume the IMC is set up but does not respond in time (btw I guess a longer timeout won't help? how did you choose the timeout value?), should we bail out like we do or presume that it is ok to write to flash? I guess it could make quite a lot of sense to be able to rewrite the IMC image in case the current image is broken (and hence does not respond to shutdown requests :) but this hopefully wont happen on end user systems. Also, note my comments in the refinement patch about IMCEnable and EcEnable. Do you have any opinion/knowledge about that? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] Add support for Loongson-3A.
by Stefan Tauner 26 Jul '13

26 Jul '13

On Fri, 26 Jul 2013 12:47:39 -0700 David Hendricks <dhendrix(a)google.com> wrote: > Hmmm, that return statement seems to be getting rather unwieldy especially > since we can probably expect a lot more variants. Maybe you can take this > opportunity to re-factor the code a bit, make a table of known strings, and > use a loop instead? You could also annotate the table entries to indicate > whether the processor is known-working and print a warning if not. > > Alternately, perhaps it would be sufficient to use strstr() to find > "GodsonV2", "Loongson-2", and "Loongson-3"? Yes it's awful... but I want to know if it works first and even then I think I don't care enough ATM. I had enough string handling in C this week already :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Re: [flashrom] [PATCH] Add support for Loongson-3A.
by David Hendricks 26 Jul '13

26 Jul '13

Hmmm, that return statement seems to be getting rather unwieldy especially since we can probably expect a lot more variants. Maybe you can take this opportunity to re-factor the code a bit, make a table of known strings, and use a loop instead? You could also annotate the table entries to indicate whether the processor is known-working and print a warning if not. Alternately, perhaps it would be sufficient to use strstr() to find "GodsonV2", "Loongson-2", and "Loongson-3"? On Thu, Jul 25, 2013 at 8:33 AM, Stefan Tauner < stefan.tauner(a)student.tuwien.ac.at> wrote: > Also be less restrictive regarding Loongson 2, because these strings seem > to be rather volatile: > http://www.linux-mips.org/archives/linux-mips/2013-04/msg00179.html > > http://www.loongson.cn/dev/gitweb/?p=linux-loongson-all;a=history;f=arch/mi… > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > > Let's pretend I know what I am doing here... if I read the chinese > data sheets correctly then Loongson-3B has moved to use SPI primarily > for its firmware but there is always a chipset attached too... > In any case I would rather not touch it yet. 3A OTOH seems to be > more similar to Loongson-2 so this might actually work. > > This patch applies w/o conflicts to r1565 and later. > > processor_enable.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/processor_enable.c b/processor_enable.c > index 1361dd5..92c6b18 100644 > --- a/processor_enable.c > +++ b/processor_enable.c > @@ -58,8 +58,9 @@ static int is_loongson(void) > while (*ptr && isspace((unsigned char)*ptr)) > ptr++; > fclose(cpuinfo); > - return (strncmp(ptr, "ICT Loongson-2 V0.3", strlen("ICT > Loongson-2 V0.3")) == 0) || > - (strncmp(ptr, "Godson2 V0.3 FPU V0.1", > strlen("Godson2 V0.3 FPU V0.1")) == 0); > + return (strncmp(ptr, "ICT Loongson-2", strlen("ICT > Loongson-2")) == 0) || > + (strncmp(ptr, "Godson2 V0.3 FPU V0.1", > strlen("Godson2 V0.3 FPU V0.1")) == 0) || > + (strncmp(ptr, "ICT Loongson-3A", strlen("ICT > Loongson-3A")) == 0); > } > fclose(cpuinfo); > return 0; > -- > Kind regards, Stefan Tauner > > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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Re: [flashrom] A quick hack to support AMD Family 16h SOC
by Carl-Daniel Hailfinger 26 Jul '13

26 Jul '13

Hi Wei, thanks for the link. I didn't search for processor BKDG, only for chipset BKDG. That's why I missed the Family 16h BKDG which includes the SPI controller documentation. Am 26.07.2013 07:18 schrieb Wei Hu: > Have you checked the public BKDG > http://support.amd.com/us/Processor_TechDocs/48751_BKDG_Fam_16h_Mod_00h-0Fh… > It actually does talk about the SPI registers in Section 3.26.9.2. Thanks. > I'm not very familiar with AMD's code names, but I think Kabini's FCH > is called Yangtze? Hudson seems to be previous generations. Yes, I will have to fix this. > I'll give you modified patch a test tomorrow. Please note that I expect problems with my patch. Not all of the FIFO management has been changed, and this might be the cause of error messages. Updated patch with more debugging at the end of this mail. > On Thu, Jul 25, 2013 at 7:21 PM, Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2006(a)gmx.net> wrote: >> Hello Wei Hu, >> >> thanks for your patch! >> >> Am 27.06.2013 02:34 schrieb Wei Hu: >>> In the past I posted a question at >>> http://www.flashrom.org/pipermail/flashrom/2013-April/010924.html >>> about failure to run flashrom on the new AMD SOC. It turns out the SPI >>> flash interface has introduced incompatible changes from SB600. I have >>> created a quick hack and made it available at >>> http://blogs.coreboot.org/blog/2013/06/26/gsoc-2013-flashrom-week-1-while1/. >>> Based on the discussion there I'm posting the patch here as well. Hope >>> it will be helpful. >>> >>> A quick hack to support AMD Family 16h SOC (Kabini). >>> This patch is just a proof of concept and incompatible with previous generations of AMD chipset. >>> Tested reading and writing on ASRock IMB-A180. >>> >>> Signed-off-by: Wei Hu <wei(a)aristanetworks.com> >> I have tried to change the patch in a way which keeps compatibility with >> older AMD chipsets. >> Please test with and without USE_THE_EXTENDED_SPIDataFifoPtr_REGISTER >> #defined. If any errors crop up, please send them to the mailing list in >> reply to this mail. I still have to search/replace Hudson with Yangtze, but this patch will help a lot finding out more about the various FIFO related registers. Signed-off-by: Wei Hu <wei(a)aristanetworks.com> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-kabini/sb600spi.c =================================================================== --- flashrom-kabini/sb600spi.c (Revision 1704) +++ flashrom-kabini/sb600spi.c (Arbeitskopie) @@ -45,6 +45,8 @@ static uint8_t *sb600_spibar = NULL; +static int hudson_method = 0; + static void reset_internal_fifo_pointer(void) { mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2); @@ -58,14 +60,29 @@ { uint8_t tmp; + if (hudson_method) { + uint8_t tmp1; + mmio_writeb(7, sb600_spibar + 0x1e); + tmp = mmio_readb(sb600_spibar + 0x1f); + msg_pspew("Kabini SPIDataFifoPtr %d/%d, ", tmp, want); + tmp = mmio_readb(sb600_spibar + 0xd) & 0x07; + msg_pspew("FifoPtr %d/%d, ", tmp, want & 0x07); + tmp = mmio_readb(sb600_spibar + 0x4d) & 0x7f; + tmp1 = mmio_readb(sb600_spibar + 0x4e) & 0x7f; + msg_pspew("FifoWrPtr/FifoRdPtr %d/%d\n", tmp, tmp1); + } + +#ifdef USE_THE_EXTENDED_SPIDataFifoPtr_REGISTER + mmio_writeb(7, sb600_spibar + 0x1e); + tmp = mmio_readb(sb600_spibar + 0x1f); +#else /* either way works */ tmp = mmio_readb(sb600_spibar + 0xd) & 0x07; want &= 0x7; +#endif if (want != tmp) { msg_perr("FIFO pointer corruption! Pointer is %d, wanted %d\n", tmp, want); - msg_perr("Something else is accessing the flash chip and " - "causes random corruption.\nPlease stop all " - "applications and drivers and IPMI which access the " - "flash chip.\n"); + msg_perr("Something else is accessing the flash chip and causes random corruption.\n" + "Please stop all applications and drivers and IPMI which access the flash chip.\n"); return 1; } else { msg_pspew("SB600 FIFO pointer is %d, wanted %d\n", tmp, want); @@ -99,7 +116,7 @@ /* First byte is cmd which can not being sent through FIFO. */ unsigned char cmd = *writearr++; unsigned int readoffby1; - unsigned char readwrite; + unsigned char readwrite = 0; writecnt--; @@ -118,15 +135,21 @@ return SPI_INVALID_LENGTH; } - /* This is a workaround for a bug in SB600 and SB700. If we only send - * an opcode and no additional data/address, the SPI controller will - * read one byte too few from the chip. Basically, the last byte of - * the chip response is discarded and will not end up in the FIFO. - * It is unclear if the CS# line is set high too early as well. - */ - readoffby1 = (writecnt) ? 0 : 1; - readwrite = (readcnt + readoffby1) << 4 | (writecnt); - mmio_writeb(readwrite, sb600_spibar + 1); + if (hudson_method) { + /* Use the extended TxByteCount and RxByteCount register. */ + mmio_writeb(writecnt, sb600_spibar + 0x48); + mmio_writeb(readcnt, sb600_spibar + 0x4b); + } else { + /* This is a workaround for a bug in SB600 and SB700. If we only send + * an opcode and no additional data/address, the SPI controller will + * read one byte too few from the chip. Basically, the last byte of + * the chip response is discarded and will not end up in the FIFO. + * It is unclear if the CS# line is set high too early as well. + */ + readoffby1 = (writecnt) ? 0 : 1; + readwrite = (readcnt + readoffby1) << 4 | (writecnt); + mmio_writeb(readwrite, sb600_spibar + 1); + } mmio_writeb(cmd, sb600_spibar + 0); /* Before we use the FIFO, reset it first. */ @@ -171,27 +194,58 @@ msg_pspew("[%02x]", cmd); } msg_pspew("\n"); - if (compare_internal_fifo_pointer(writecnt)) - return SPI_PROGRAMMER_ERROR; + /* Reading from the FIFO apparently doesn't advance the FIFO pointer on Hudson, but it does so on all + * chipsets before Hudson. + */ + if (hudson_method) { + if (compare_internal_fifo_pointer(0)) + return SPI_PROGRAMMER_ERROR; + } else { + if (compare_internal_fifo_pointer(writecnt)) + return SPI_PROGRAMMER_ERROR; + } + msg_pspew("Reading: "); for (count = 0; count < readcnt; count++, readarr++) { *readarr = mmio_readb(sb600_spibar + 0xC); msg_pspew("[%02x]", *readarr); } msg_pspew("\n"); - if (reset_compare_internal_fifo_pointer(readcnt + writecnt)) - return SPI_PROGRAMMER_ERROR; - if (mmio_readb(sb600_spibar + 1) != readwrite) { - msg_perr("Unexpected change in SB600 read/write count!\n"); - msg_perr("Something else is accessing the flash chip and " - "causes random corruption.\nPlease stop all " - "applications and drivers and IPMI which access the " - "flash chip.\n"); - return SPI_PROGRAMMER_ERROR; + /* Reading from the FIFO apparently doesn't advance the FIFO pointer on Hudson, but it does so on all + * chipsets before Hudson. + */ + if (hudson_method) { + if (compare_internal_fifo_pointer(0)) + return SPI_PROGRAMMER_ERROR; + } else { + if (reset_compare_internal_fifo_pointer(readcnt + writecnt)) + return SPI_PROGRAMMER_ERROR; } + if (hudson_method) { + uint8_t tmp_wc = mmio_readb(sb600_spibar + 0x48); + uint8_t tmp_rc = mmio_readb(sb600_spibar + 0x4b); + if ((tmp_rc != readcnt) || (tmp_wc != writecnt)) { + msg_perr("Unexpected change in Hudson read/write count: %i/%i instead of %i/%i!\n", + tmp_rc, tmp_wc, readcnt, writecnt); + msg_perr("Something else is accessing the flash chip and causes random corruption.\n" + "Please stop all applications and drivers and IPMI which access the flash " + "chip.\n"); + return SPI_PROGRAMMER_ERROR; + } + } else { + uint8_t tmp_rw = mmio_readb(sb600_spibar + 1); + if (tmp_rw != readwrite) { + msg_perr("Unexpected change in SB600 read/write count: %i instead of %i!\n", tmp_rw, + readwrite); + msg_perr("Something else is accessing the flash chip and causes random corruption.\n" + "Please stop all applications and drivers and IPMI which access the flash " + "chip.\n"); + return SPI_PROGRAMMER_ERROR; + } + } return 0; } @@ -310,6 +364,14 @@ tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; msg_pdbg("NormSpeed is %s MHz\n", speed_names[tmp]); + /* AMD Hudson apparently requires use of a different SPI registers for read/write counts. */ + if (dev->device_id == 0x438d) { + msg_pdbg("Using AMD Hudson SPI access method.\n"); + hudson_method = 1; + } else { + hudson_method = 0; + } + /* Look for the SMBus device. */ smbus_dev = pci_dev_find(0x1002, 0x4385); -- http://www.hailfinger.org/

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Re: [flashrom] FCH code names (was: A quick hack to support AMD Family 16h SOC)
by Stefan Tauner 26 Jul '13

26 Jul '13

On Fri, 26 Jul 2013 11:39:19 -0700 Wei Hu <wei(a)aristanetworks.com> wrote: > Stefan, > > AMD internal documents also suggest A45/A50M/A55E FCH (Hudson-1) use > device ID 438D. Not sure if it's wrong since I don't have a test > system. I am. :) The ASRock E350M1 uses the A50M and has 439D (it is well supported by coreboot and it would be easy to find someone to test it): http://www.coreboot.org/pipermail/coreboot/2011-June/065421.html > According to AMD document A55/A60M/A68/A68M/A70M/A75/A85X use device > ID 780E. There's also this A77E FCH (codename Bolton) which also uses > 780E. OK, thanks > (Please cc me on your future emails since I'm not subscribed to the list) sorry! -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] FCH code names (was: A quick hack to support AMD Family 16h SOC)
by Wei Hu 26 Jul '13

26 Jul '13

Stefan, AMD internal documents also suggest A45/A50M/A55E FCH (Hudson-1) use device ID 438D. Not sure if it's wrong since I don't have a test system. According to AMD document A55/A60M/A68/A68M/A70M/A75/A85X use device ID 780E. There's also this A77E FCH (codename Bolton) which also uses 780E. (Please cc me on your future emails since I'm not subscribed to the list) On Fri, Jul 26, 2013 at 10:29 AM, Wei Hu <wei(a)aristanetworks.com> wrote: > On Fri, Jul 26, 2013 at 6:12 AM, Stefan Tauner > <stefan.tauner(a)student.tuwien.ac.at> wrote: >> The code names are complicated. >> >> Jaguar describes the CPU(APU) architecture (succeeding Bobcat), while >> Kabini (embedded, htpc, laptops) and Temash (tablets) describe SoC >> families with those cores. >> >> Hudson seems to be the generic code name(!?) for all FCH aka >> southbridges since sb9xx which came to be when they started with their >> fusion aka APU development, hence there are multiple generations of >> Hudson (3 AFAIK, where Yangtze/Salton are #3). >> >> The integrated FCH for Kabini and Temash are codenamed "Yangtze" and >> "Salton" respectively. I am not aware of the previous code names... >> The only other FCH name i could find is Yuba but that was never >> released because it was cancelled together with Krishna/Wichita. > > Is it right to call out Hudson for incompatible SPI changes though? We > might need to call it hudson3 or something. What I seem to see in > coreboot is they try to bundle compatible changes into hudson and for > incompatible changes just call it yangtze.

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Re: [flashrom] [PATCH] sbxxx: Handle active IMCs in AMD chipsets.
by Carl-Daniel Hailfinger 26 Jul '13

26 Jul '13

Hi Stefan, sorry for the late sending of this review (falling asleep a few times due to the intense heat didn't really help me get this sent). I believe the issues I raise are only cosmetic and the patch is technically solid. Am 18.07.2013 23:50 schrieb Stefan Tauner: > Detect and temporarily disable the IMC while accessing the flash. > Disable writes on default, but allow the user to enforce it. > > Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Thanks a lot for the patch! I believe it will fix pretty much every case of IMC interference we saw. > diff --git a/amd_imc.c b/amd_imc.c > new file mode 100644 > index 0000000..b05390c > --- /dev/null > +++ b/amd_imc.c > @@ -0,0 +1,159 @@ > [...] > +static uint16_t get_sio_port(struct pci_dev *dev) > +{ > + uint16_t ec_port; > + > + if (!dev) { > + return 0; > + } > + > + ec_port = pci_read_word(dev, 0xa4); > + > + /* EcPortActive? */ > + if (!(ec_port & 0x1)) > + return 0; > + > + ec_port &= ~0x1; > + > + return ec_port; > +} > + > [...] > +static uint16_t mbox_get_port(uint16_t sio_port) > +{ > + uint16_t mbox_port; > + > + enter_conf_mode_ec(sio_port); > + > + /* Go to LDN 9, mailbox */ > + sio_write(sio_port, 7, 9); > + > + /* MBOX inactive? */ > + if ((sio_read(sio_port, 0x30) & 1) == 0) { > + exit_conf_mode_ec(sio_port); > + return 0; > + } > + > + mbox_port = sio_read(sio_port, 0x60) << 8; > + mbox_port |= sio_read(sio_port, 0x61); > + > + exit_conf_mode_ec(sio_port); > + return mbox_port; > +} > + > +/* Returns negative values when IMC is inactive, positive values on errors */ > +static int imc_send_cmd(struct pci_dev *dev, uint8_t cmd) > +{ > + uint16_t sio_port; > + uint16_t mbox_port; > + > + /* IntegratedEcPresent? */ > + if (!(pci_read_byte(dev, 0x40) & (1 << 7))) > + return -1; > + > + sio_port = get_sio_port(dev); > + if (!sio_port) > + return -1; > + > + msg_pdbg2("IMC SIO is at 0x%x.\n", sio_port); > + mbox_port = mbox_get_port(sio_port); > + if (!mbox_port) > + return -1; > + msg_pdbg2("IMC MBOX is at 0x%x.\n", mbox_port); > + > + sio_write(mbox_port, 0x82, 0x0); > + sio_write(mbox_port, 0x83, cmd); > + sio_write(mbox_port, 0x84, 0x0); > + /* trigger transfer 0x96 with subcommand cmd */ > + sio_write(mbox_port, 0x80, 0x96); > + > + return mbox_wait_ack(mbox_port); > +} > + > [...] > +int amd_imc_shutdown(struct pci_dev *dev) > +{ > + /* Try to put IMC to sleep */ > + int ret = imc_send_cmd(dev, 0xb4); > + > + /* No IMC activity detectable, assume we are fine */ > + if (ret < 0) { > + msg_pdbg2("No IMC found.\n"); The message above is printed after the message "Writes have been disabled for safety reasons because the IMC is active" from sb600_handle_imc(). AFAICS this mesage can only happen if the IMC is marked as present but any of the SIO port or MBOX port are zero, i.e. inaccessible. May I suggest the following message instead? "IMC inactive or unreachable.\n" > + return 0; > + } > + > + if (ret != 0) { > + msg_perr("Shutting down IMC failed.\n"); > + return ret; > + } > + msg_pdbg2("Shutting down IMC successful.\n"); > + > + if (register_shutdown(imc_resume, dev)) > + return 1; > + > + return ret; > +} > + > +#endif > diff --git a/programmer.h b/programmer.h > index db914cb..f03eac3 100644 > --- a/programmer.h > +++ b/programmer.h > @@ -572,6 +572,9 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > enum ich_chipset ich_generation); > int via_init_spi(struct pci_dev *dev, uint32_t mmio_base); > > +/* imc.c */ Should be amd_imc.c > +int amd_imc_shutdown(struct pci_dev *dev); > + > /* it85spi.c */ > int it85xx_spi_init(struct superio s); > > diff --git a/sb600spi.c b/sb600spi.c > index a5c00d8..e76c04a 100644 > --- a/sb600spi.c > +++ b/sb600spi.c > @@ -194,6 +195,39 @@ static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, > return 0; > } > > +static int sb600_handle_imc(struct pci_dev *dev, bool amd_imc_force) > +{ > + /* Handle IMC everywhere but sb600 which does not have one. */ > + if (dev->device_id == 0x438d) > + return 0; > + > + /* TODO: we should not only look at IntegratedImcPresent (LPC Dev 20, Func 3, 40h) but also at > + * IMCEnable(Strap) and Override EcEnable(Strap) (sb8xx, sb9xx?, a50: Misc_Reg: 80h-87h; > + * sb7xx, sp5100: PM_Reg: B0h-B1h) etc. */ > + uint8_t reg = pci_read_byte(dev, 0x40); > + if ((reg & (1 << 7)) == 0) { > + msg_pdbg("IMC is not active.\n"); > + return 0; > + } This is the point where we assume the IMC is active. Given that we only check for the IntegratedImcPresent bit, would "IMC is not present" be a better message? Or do we want to keep the message and eventually look at the straps as well? > + > + if (!amd_imc_force) > + programmer_may_write = 0; > + msg_pinfo("Writes have been disabled for safety reasons because the IMC is active\n" It's present, but does it have to be active? > + "and it could interfere with accessing flash memory. Flashrom will try\n" > + "to disable it temporarily but even then this might not be safe:\n" > + "when it is reenabled and after a reboot it expects to find working code\n" > + "in the flash and it is unpredictable what happens if there is none.\n" > + "\n" > + "To be safe make sure that there is a working IMC firmware at the right\n" > + "location in the image you intend to write and do not attempt to erase.\n" > + "\n" > + "You can enforce write support with the amd_imc_force programmer option.\n"); > + if (amd_imc_force) > + msg_pinfo("Continuing with write support because the user forced us to!\n"); > + > + return amd_imc_shutdown(dev); Call to shutdown the IMC, done after printing that the IMC is active, but inside amd_imc_shutdown() we may print the message that no IMC was found. This is a bit contradictory in some cases. > +} > + > static const struct spi_programmer spi_programmer_sb600 = { > .type = SPI_CONTROLLER_SB600, > .max_data_read = 8, I just noticed the patch has been committed an hour ago, but throwing away the review seemed a waste. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] A quick hack to support AMD Family 16h SOC
by Carl-Daniel Hailfinger 26 Jul '13

26 Jul '13

Hello Wei Hu, thanks for your patch! Am 27.06.2013 02:34 schrieb Wei Hu: > In the past I posted a question at > http://www.flashrom.org/pipermail/flashrom/2013-April/010924.html > about failure to run flashrom on the new AMD SOC. It turns out the SPI > flash interface has introduced incompatible changes from SB600. I have > created a quick hack and made it available at > http://blogs.coreboot.org/blog/2013/06/26/gsoc-2013-flashrom-week-1-while1/. > Based on the discussion there I'm posting the patch here as well. Hope > it will be helpful. > > A quick hack to support AMD Family 16h SOC (Kabini). > This patch is just a proof of concept and incompatible with previous generations of AMD chipset. > Tested reading and writing on ASRock IMB-A180. > > Signed-off-by: Wei Hu <wei(a)aristanetworks.com> I have tried to change the patch in a way which keeps compatibility with older AMD chipsets. Please test with and without USE_THE_EXTENDED_SPIDataFifoPtr_REGISTER #defined. If any errors crop up, please send them to the mailing list in reply to this mail. The biggest problem was the missing register reference guide (RRG) for AMD FCH. I had to guess the way to identify affected chipsets, and I now test for PCI device ID 0x438d (Hudson FCH, probably too broad match). I really hope this is the right ID. It would be great if you could confirm that the FIFO pointer management change affects all FCH with this PCI device ID. Is there a way to get access to the RRG for Kabini or the integrated FCH? Right now my changes are guesses Signed-off-by: Wei Hu <wei(a)aristanetworks.com> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-kabini/sb600spi.c =================================================================== --- flashrom-kabini/sb600spi.c (Revision 1704) +++ flashrom-kabini/sb600spi.c (Arbeitskopie) @@ -45,6 +45,8 @@ static uint8_t *sb600_spibar = NULL; +static int hudson_method = 0; + static void reset_internal_fifo_pointer(void) { mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2); @@ -58,14 +60,17 @@ { uint8_t tmp; +#ifdef USE_THE_EXTENDED_SPIDataFifoPtr_REGISTER + mmio_writeb(7, sb600_spibar + 0x1e); + tmp = mmio_readb(sb600_spibar + 0x1f); +#else /* either way works */ tmp = mmio_readb(sb600_spibar + 0xd) & 0x07; want &= 0x7; +#endif if (want != tmp) { msg_perr("FIFO pointer corruption! Pointer is %d, wanted %d\n", tmp, want); - msg_perr("Something else is accessing the flash chip and " - "causes random corruption.\nPlease stop all " - "applications and drivers and IPMI which access the " - "flash chip.\n"); + msg_perr("Something else is accessing the flash chip and causes random corruption.\n" + "Please stop all applications and drivers and IPMI which access the flash chip.\n"); return 1; } else { msg_pspew("SB600 FIFO pointer is %d, wanted %d\n", tmp, want); @@ -99,7 +104,7 @@ /* First byte is cmd which can not being sent through FIFO. */ unsigned char cmd = *writearr++; unsigned int readoffby1; - unsigned char readwrite; + unsigned char readwrite = 0; writecnt--; @@ -118,15 +123,21 @@ return SPI_INVALID_LENGTH; } - /* This is a workaround for a bug in SB600 and SB700. If we only send - * an opcode and no additional data/address, the SPI controller will - * read one byte too few from the chip. Basically, the last byte of - * the chip response is discarded and will not end up in the FIFO. - * It is unclear if the CS# line is set high too early as well. - */ - readoffby1 = (writecnt) ? 0 : 1; - readwrite = (readcnt + readoffby1) << 4 | (writecnt); - mmio_writeb(readwrite, sb600_spibar + 1); + if (hudson_method) { + /* Use the extended TxByteCount and RxByteCount register. */ + mmio_writeb(writecnt, sb600_spibar + 0x48); + mmio_writeb(readcnt, sb600_spibar + 0x4b); + } else { + /* This is a workaround for a bug in SB600 and SB700. If we only send + * an opcode and no additional data/address, the SPI controller will + * read one byte too few from the chip. Basically, the last byte of + * the chip response is discarded and will not end up in the FIFO. + * It is unclear if the CS# line is set high too early as well. + */ + readoffby1 = (writecnt) ? 0 : 1; + readwrite = (readcnt + readoffby1) << 4 | (writecnt); + mmio_writeb(readwrite, sb600_spibar + 1); + } mmio_writeb(cmd, sb600_spibar + 0); /* Before we use the FIFO, reset it first. */ @@ -171,27 +182,58 @@ msg_pspew("[%02x]", cmd); } msg_pspew("\n"); - if (compare_internal_fifo_pointer(writecnt)) - return SPI_PROGRAMMER_ERROR; + /* Reading from the FIFO apparently doesn't advance the FIFO pointer on Hudson, but it does so on all + * chipsets before Hudson. + */ + if (hudson_method) { + if (compare_internal_fifo_pointer(0)) + return SPI_PROGRAMMER_ERROR; + } else { + if (compare_internal_fifo_pointer(writecnt)) + return SPI_PROGRAMMER_ERROR; + } + msg_pspew("Reading: "); for (count = 0; count < readcnt; count++, readarr++) { *readarr = mmio_readb(sb600_spibar + 0xC); msg_pspew("[%02x]", *readarr); } msg_pspew("\n"); - if (reset_compare_internal_fifo_pointer(readcnt + writecnt)) - return SPI_PROGRAMMER_ERROR; - if (mmio_readb(sb600_spibar + 1) != readwrite) { - msg_perr("Unexpected change in SB600 read/write count!\n"); - msg_perr("Something else is accessing the flash chip and " - "causes random corruption.\nPlease stop all " - "applications and drivers and IPMI which access the " - "flash chip.\n"); - return SPI_PROGRAMMER_ERROR; + /* Reading from the FIFO apparently doesn't advance the FIFO pointer on Hudson, but it does so on all + * chipsets before Hudson. + */ + if (hudson_method) { + if (compare_internal_fifo_pointer(0)) + return SPI_PROGRAMMER_ERROR; + } else { + if (reset_compare_internal_fifo_pointer(readcnt + writecnt)) + return SPI_PROGRAMMER_ERROR; } + if (hudson_method) { + uint8_t tmp_wc = mmio_readb(sb600_spibar + 0x48); + uint8_t tmp_rc = mmio_readb(sb600_spibar + 0x4b); + if ((tmp_rc != readcnt) || (tmp_wc != writecnt)) { + msg_perr("Unexpected change in Hudson read/write count: %i/%i instead of %i/%i!\n", + tmp_rc, tmp_wc, readcnt, writecnt); + msg_perr("Something else is accessing the flash chip and causes random corruption.\n" + "Please stop all applications and drivers and IPMI which access the flash " + "chip.\n"); + return SPI_PROGRAMMER_ERROR; + } + } else { + uint8_t tmp_rw = mmio_readb(sb600_spibar + 1); + if (tmp_rw != readwrite) { + msg_perr("Unexpected change in SB600 read/write count: %i instead of %i!\n", tmp_rw, + readwrite); + msg_perr("Something else is accessing the flash chip and causes random corruption.\n" + "Please stop all applications and drivers and IPMI which access the flash " + "chip.\n"); + return SPI_PROGRAMMER_ERROR; + } + } return 0; } @@ -310,6 +352,14 @@ tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; msg_pdbg("NormSpeed is %s MHz\n", speed_names[tmp]); + /* AMD Hudson apparently requires use of a different SPI registers for read/write counts. */ + if (dev->device_id == 0x438d) { + msg_pdbg("Using AMD Hudson SPI access method.\n"); + hudson_method = 1; + } else { + hudson_method = 0; + } + /* Look for the SMBus device. */ smbus_dev = pci_dev_find(0x1002, 0x4385); -- http://www.hailfinger.org/

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flashrom 0.9.7
by Carl-Daniel Hailfinger 26 Jul '13

26 Jul '13

First of all, a big thank you to Stefan Tauner for single-handedly getting all required patches for 0.9.7 in. While there was a discussion about serial port fixes over the last few days (mostly on IRC), I believe the risk/benefit balance of any serial port changes right now is definitely on the risk side and we should postpone that. The only critical thing that possibly remains would be the Kabini fix/workaround proposed by Wei Hu. With its #ifdefs it's not mergeable right now, but it should be possible to use if() instead if we're lucky enough to make that decision dependent on detecting Kabini. I was unable to find a relevant Register Reference Guide for the affected southbridge. I sent a modified patch for Kabini a few seconds ago in the hope it will help us fix/debug this issue further. Another option with probably less impact would be to refuse flash access on the affected chipset. I'm a bit torn here. Right now I hope my patch will either work or at least give us more insight on what to expect. Stefan, if you have any other patches you deem relevant for the release (e.g. board enables currently waiting for a test), please commit them once you think they are ready. I'd like to have some band-aid solution for the Kabini problem before it causes corruption somewhere, but if you want to release now (without any Kabini related patch), I agree. Stefan, if you make a release now, I'll sign it. If you decide to wait, OK. You are in charge of the release as agreed upon. If there are any problems with svn or the release process, holler. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH 09/10] Rename Numonyx and ST (SGS/Thomson) chips to Micron.
by Carl-Daniel Hailfinger 26 Jul '13

26 Jul '13

Am 10.07.2013 21:17 schrieb Stefan Tauner: > Micron acquired Numonyx and asked us to change the vendor names to > "Micron". For the chips clearly emerging from the former > manufacturers we (will) use "Micron/Numonyx/ST" and the original > name for the rest. Resorting the chip entries makes the diff > unreadable, hence the stand-alone commit. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> That's a lot of churn and verifying it is difficult. Can we postpone this? Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH 07/10] Add a bunch of new/tested stuff and various small changes 18.
by Carl-Daniel Hailfinger 26 Jul '13

26 Jul '13

Am 10.07.2013 21:17 schrieb Stefan Tauner: > Tested mainboards: > OK: > - ASUS C60M1-I > http://www.flashrom.org/pipermail/flashrom/2013-February/010578.html > - ASUS P8H77-I > http://www.flashrom.org/pipermail/flashrom/2013-March/010607.html > - ASUS P8H77-M > http://www.flashrom.org/pipermail/flashrom/2013-May/010994.html > - ASUS P8P67 LE (B2) > http://www.flashrom.org/pipermail/flashrom/2013-May/010972.html > - Elitegroup GeForce6100PM-M2 (V3.0) > http://www.flashrom.org/pipermail/flashrom/2013-July/011177.html > - MSI B75MA-E33 (MS-7808) > http://www.flashrom.org/pipermail/flashrom/2013-March/010659.html > - MSI H77MA-G43 (MS-7756) > http://www.flashrom.org/pipermail/flashrom/2013-April/010853.html > - MSI KA780G (MS-7551) > http://paste.flashrom.org/view.php?id=1617 > NOT OK: > - ASRock Fatal1ty Z77 Performance > http://www.flashrom.org/pipermail/flashrom/2013-January/010467.html > - ASRock Z68 Extreme4 > http://www.flashrom.org/pipermail/flashrom/2013-May/010984.html > - ASUS P8B75-M LE > http://www.flashrom.org/pipermail/flashrom/2013-April/010867.html > - ASUS P8P67-M PRO > http://www.flashrom.org/pipermail/flashrom/2013-February/010541.html > - ASUS P8Z68-V LE > http://www.flashrom.org/pipermail/flashrom/2013-February/010582.html > - Intel DQ77MK > http://paste.flashrom.org/view.php?id=1603 > - Supermicro X9DRD-7LN4F > http://paste.flashrom.org/view.php?id=1582 > - Supermicro X9SCE-F > http://www.flashrom.org/pipermail/flashrom/2013-February/010588.html > - Supermicro X9SCM-F > http://www.flashrom.org/pipermail/flashrom/2013-February/010527.html > - Tyan S7066 > http://www.flashrom.org/pipermail/flashrom/2013-March/010630.html > > Chipsets: > - Marked Intel B75 as tested > http://www.flashrom.org/pipermail/flashrom/2013-March/010659.html > - Marked Intel H77 as tested > http://www.flashrom.org/pipermail/flashrom/2013-March/010607.html > - Removed 10de:03e2 because it is apparently the MCP61 host bridge. > It was reclassified to Host Bridge in the PCI device ID database and there > is at least one report suggesting this configuration too: > http://www.flashrom.org/pipermail/flashrom/2012-August/009716.html > - Added MCP89 which hopefully works with the code for previous versions. > Thanks to James Laird for submitting this change. > > Tested flash chips: > - Atmel AT25DF641(A) to PREW (+PREW) > http://www.flashrom.org/pipermail/flashrom/2013-June/011113.html > - Atmel AT25F512 to PREW (+PREW) > http://www.flashrom.org/pipermail/flashrom/2013-April/010904.html > Also, change its ID according to Modification of PCN SC040401A: > "There has been a change in the returned value of the Product Identification > (RDID) command, the AT25F512A RDID code is 65h compared to 60h from > the AT25F512 product." > It seems to be quite likely that all AT25F512 are fully functional relabeled > AT25F1024 chips. There are even some hints in the datasheet: > in table 6 they stress that address pin 16 needs to be low under all circum- > stances; while continuous reads can wrap around on the AT25F1024 the DS > notes "For the AT25F512, the read command must be terminated when the > highest address (00FFFF) is reached." OTOH the lock bit semantics are > different, but this has not been tested thoroughly > - Atmel AT25F512A to PREW (+PREW) > http://paste.flashrom.org/view.php?id=1569 > - Eon EN25F05 to PREW (+PREW) > http://paste.flashrom.org/view.php?id=1571 > - Macronix MX25L12805(D) to PREW (+REW) > http://www.flashrom.org/pipermail/flashrom/2013-April/010913.html > - Spansion S25FL256S......0 and S25FL512S to P/!R!E!W (+P) > Tested by Stefan Tauner > - Micron/Numonyx/ST M25PX80 to PREW (+PREW) > Tested by Stefan Tauner > - Micron/Numonyx/ST N25Q032..3E and N25Q128..3E to PREW (+PREW) > Tested by Stefan Tauner > - Micron/Numonyx/ST N25Q256..3E and N25Q512..3G to P/!R!E!W (+P) > Tested by Stefan Tauner > - SST SST25VF040B to PREW (+PREW) > http://paste.flashrom.org/view.php?id=1574 > - SST SST25VF040B.REMS to PREW (+EW) > http://paste.flashrom.org/view.php?id=1575 > - ST M25P05-A to PREW (+PREW) > http://paste.flashrom.org/view.php?id=1576 > - ST M29W512B to PREW (+W) > http://www.flashrom.org/pipermail/flashrom/2013-March/010635.html > - Winbond W25Q64.W to PREW (+PREW) > Tested by the chromiumos guys. > - Winbond W25Q128.V to PREW (+REW) > http://www.flashrom.org/pipermail/flashrom/2013-June/011108.html > - Winbond W25X20 to PREW (+PREW) > http://www.flashrom.org/pipermail/flashrom/2013-May/010990.html > > Miscellaneous: > - Add Lenovo X201 to the laptop whitelist. > - Add chip IDs for the ESMT F25L..QA family. > - Add chip IDs for a few Macronix MX25 models. > - The list of flashchips is not sorted strictly alphabetically and should not be > either. Refine the comment explaining the scheme on top of the list. > - Support -L output of chip sizes with up to 6 decimal places (up to 4 Gb). > - Add explanations at the top of the flash chip table in the wiki. > - Escape mainboard notes in the wiki output with <nowiki> (this became > necessary because MediaWiki started to convert <mark(a)zl2tod.net> to <mark>). > - Tiny other stuff. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH] sbxxx: Handle active IMCs in AMD chipsets.
by Stefan Tauner 26 Jul '13

26 Jul '13

On Thu, 25 Jul 2013 15:59:06 -0700 David Hendricks <dhendrix(a)google.com> wrote: > This is pretty vital for AMD platforms with an IMC, so: > Acked-by: David Hendricks <dhendrix(a)google.com> > Thanks, r1704 Let's hope it doesnt kill too many kittens. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 1/7] sbxxx: Add spispeed parameter.
by David Hendricks 26 Jul '13

26 Jul '13

Acked-by: David Hendricks <dhendrix(a)google.com> -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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Re: [flashrom] [PATCH] sbxxx: Handle active IMCs in AMD chipsets.
by David Hendricks 26 Jul '13

26 Jul '13

This is pretty vital for AMD platforms with an IMC, so: Acked-by: David Hendricks <dhendrix(a)google.com> -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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[commit] r1704 - trunk
by repository service 26 Jul '13

26 Jul '13

Author: stefanct Date: Fri Jul 26 00:58:56 2013 New Revision: 1704 URL: http://flashrom.org/trac/flashrom/changeset/1704 Log: sbxxx: Handle active IMCs in AMD chipsets. Detect and temporarily disable the IMC while accessing the flash. Disable writes on default, but allow the user to enforce it. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: David Hendricks <dhendrix(a)google.com> Added: trunk/amd_imc.c (contents, props changed) Modified: trunk/Makefile trunk/flashrom.8 trunk/programmer.h trunk/sb600spi.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Fri Jul 26 00:58:51 2013 (r1703) +++ trunk/Makefile Fri Jul 26 00:58:56 2013 (r1704) @@ -433,7 +433,7 @@ FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o ifeq ($(ARCH), x86) -PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o amd_imc.o wbsio_spi.o mcp6x_spi.o PROGRAMMER_OBJS += ichspi.o ich_descriptors.o else endif Added: trunk/amd_imc.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/amd_imc.c Fri Jul 26 00:58:56 2013 (r1704) @@ -0,0 +1,159 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2013 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2013 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) + +#include "flash.h" +#include "programmer.h" +#include "hwaccess.h" +#include "spi.h" + +/* same as serverengines */ +static void enter_conf_mode_ec(uint16_t port) +{ + OUTB(0x5a, port); +} + +static void exit_conf_mode_ec(uint16_t port) +{ + OUTB(0xa5, port); +} + +static uint16_t get_sio_port(struct pci_dev *dev) +{ + uint16_t ec_port; + + if (!dev) { + return 0; + } + + ec_port = pci_read_word(dev, 0xa4); + + /* EcPortActive? */ + if (!(ec_port & 0x1)) + return 0; + + ec_port &= ~0x1; + + return ec_port; +} + +/* Wait for up to 10 ms for a response. */ +static int mbox_wait_ack(uint16_t mbox_port) +{ + int i = 10; + while (sio_read(mbox_port, 0x82) != 0xfa) { + if (--i == 0) { + msg_pwarn("IMC MBOX: Timeout!\n"); + return 1; + } + programmer_delay(1000); + } + return 0; +} + +static uint16_t mbox_get_port(uint16_t sio_port) +{ + uint16_t mbox_port; + + enter_conf_mode_ec(sio_port); + + /* Go to LDN 9, mailbox */ + sio_write(sio_port, 7, 9); + + /* MBOX inactive? */ + if ((sio_read(sio_port, 0x30) & 1) == 0) { + exit_conf_mode_ec(sio_port); + return 0; + } + + mbox_port = sio_read(sio_port, 0x60) << 8; + mbox_port |= sio_read(sio_port, 0x61); + + exit_conf_mode_ec(sio_port); + return mbox_port; +} + +/* Returns negative values when IMC is inactive, positive values on errors */ +static int imc_send_cmd(struct pci_dev *dev, uint8_t cmd) +{ + uint16_t sio_port; + uint16_t mbox_port; + + /* IntegratedEcPresent? */ + if (!(pci_read_byte(dev, 0x40) & (1 << 7))) + return -1; + + sio_port = get_sio_port(dev); + if (!sio_port) + return -1; + + msg_pdbg2("IMC SIO is at 0x%x.\n", sio_port); + mbox_port = mbox_get_port(sio_port); + if (!mbox_port) + return -1; + msg_pdbg2("IMC MBOX is at 0x%x.\n", mbox_port); + + sio_write(mbox_port, 0x82, 0x0); + sio_write(mbox_port, 0x83, cmd); + sio_write(mbox_port, 0x84, 0x0); + /* trigger transfer 0x96 with subcommand cmd */ + sio_write(mbox_port, 0x80, 0x96); + + return mbox_wait_ack(mbox_port); +} + +static int imc_resume(void *data) +{ + struct pci_dev *dev = data; + int ret = imc_send_cmd(dev, 0xb5); + + if (ret != 0) + msg_pinfo("Resuming IMC failed)\n"); + else + msg_pdbg2("IMC resumed.\n"); + return ret; +} + +int amd_imc_shutdown(struct pci_dev *dev) +{ + /* Try to put IMC to sleep */ + int ret = imc_send_cmd(dev, 0xb4); + + /* No IMC activity detectable, assume we are fine */ + if (ret < 0) { + msg_pdbg2("No IMC found.\n"); + return 0; + } + + if (ret != 0) { + msg_perr("Shutting down IMC failed.\n"); + return ret; + } + msg_pdbg2("Shutting down IMC successful.\n"); + + if (register_shutdown(imc_resume, dev)) + return 1; + + return ret; +} + +#endif Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Fri Jul 26 00:58:51 2013 (r1703) +++ trunk/flashrom.8 Fri Jul 26 00:58:56 2013 (r1704) @@ -329,6 +329,23 @@ report so we can diagnose the problem. .sp .TP +.B AMD chipsets +.sp +Beginning with the SB700 chipset there is an integrated microcontroller (IMC) based on the 8051 embedded in +every AMD southbridge. Its firmware resides in the same flash chip as the host's which makes writing to the +flash risky if the IMC is active. Flashrom tries to temporarily disable the IMC but even then changing the +contents of the flash can have unwanted effects: when the IMC continues (at the latest after a reboot) it will +continue executing code from the flash. If the code was removed or changed in an unfortunate way it is +unpredictable what the IMC will do. Therefore, if flashrom detects an active IMC it will disable write support +unless the user forces it with the +.sp +.B " flashrom \-p internal:amd_imc_force=yes" +.sp +syntax. The user is responsible for supplying a suitable image or leaving out the IMC region with the help of +a layout file. This limitation might be removed in the future when we understand the details better and have +received enough feedback from users. Please report the outcome if you had to use this option to write a chip. +.sp +.TP .B Intel chipsets .sp If you have an Intel chipset with an ICH8 or later southbridge with SPI flash Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Fri Jul 26 00:58:51 2013 (r1703) +++ trunk/programmer.h Fri Jul 26 00:58:56 2013 (r1704) @@ -572,6 +572,9 @@ enum ich_chipset ich_generation); int via_init_spi(struct pci_dev *dev, uint32_t mmio_base); +/* imc.c */ +int amd_imc_shutdown(struct pci_dev *dev); + /* it85spi.c */ int it85xx_spi_init(struct superio s); Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Fri Jul 26 00:58:51 2013 (r1703) +++ trunk/sb600spi.c Fri Jul 26 00:58:56 2013 (r1704) @@ -23,6 +23,8 @@ #if defined(__i386__) || defined(__x86_64__) +#include <string.h> +#include <stdlib.h> #include "flash.h" #include "programmer.h" #include "hwaccess.h" @@ -47,7 +49,7 @@ { mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2); - /* FIXME: This loop makes no sense at all. */ + /* FIXME: This loop needs a timeout and a clearer message. */ while (mmio_readb(sb600_spibar + 0xD) & 0x7) msg_pspew("reset\n"); } @@ -59,8 +61,7 @@ tmp = mmio_readb(sb600_spibar + 0xd) & 0x07; want &= 0x7; if (want != tmp) { - msg_perr("SB600 FIFO pointer corruption! Pointer is %d, wanted " - "%d\n", tmp, want); + msg_perr("FIFO pointer corruption! Pointer is %d, wanted %d\n", tmp, want); msg_perr("Something else is accessing the flash chip and " "causes random corruption.\nPlease stop all " "applications and drivers and IPMI which access the " @@ -194,6 +195,39 @@ return 0; } +static int sb600_handle_imc(struct pci_dev *dev, bool amd_imc_force) +{ + /* Handle IMC everywhere but sb600 which does not have one. */ + if (dev->device_id == 0x438d) + return 0; + + /* TODO: we should not only look at IntegratedImcPresent (LPC Dev 20, Func 3, 40h) but also at + * IMCEnable(Strap) and Override EcEnable(Strap) (sb8xx, sb9xx?, a50: Misc_Reg: 80h-87h; + * sb7xx, sp5100: PM_Reg: B0h-B1h) etc. */ + uint8_t reg = pci_read_byte(dev, 0x40); + if ((reg & (1 << 7)) == 0) { + msg_pdbg("IMC is not active.\n"); + return 0; + } + + if (!amd_imc_force) + programmer_may_write = 0; + msg_pinfo("Writes have been disabled for safety reasons because the IMC is active\n" + "and it could interfere with accessing flash memory. Flashrom will try\n" + "to disable it temporarily but even then this might not be safe:\n" + "when it is reenabled and after a reboot it expects to find working code\n" + "in the flash and it is unpredictable what happens if there is none.\n" + "\n" + "To be safe make sure that there is a working IMC firmware at the right\n" + "location in the image you intend to write and do not attempt to erase.\n" + "\n" + "You can enforce write support with the amd_imc_force programmer option.\n"); + if (amd_imc_force) + msg_pinfo("Continuing with write support because the user forced us to!\n"); + + return amd_imc_shutdown(dev); +} + static const struct spi_programmer spi_programmer_sb600 = { .type = SPI_CONTROLLER_SB600, .max_data_read = 8, @@ -210,10 +244,26 @@ struct pci_dev *smbus_dev; uint32_t tmp; uint8_t reg; + bool amd_imc_force = false; static const char *const speed_names[4] = { "66/reserved", "33", "22", "16.5" }; + char *arg = extract_programmer_param("amd_imc_force"); + if (arg && !strcmp(arg, "yes")) { + amd_imc_force = true; + msg_pspew("amd_imc_force enabled.\n"); + } else if (arg && !strlen(arg)) { + msg_perr("Missing argument for amd_imc_force.\n"); + free(arg); + return ERROR_FATAL; + } else if (arg) { + msg_perr("Unknown argument for amd_imc_force: \"%s\" (not \"yes\").\n", arg); + free(arg); + return ERROR_FATAL; + } + free(arg); + /* Read SPI_BaseAddr */ tmp = pci_read_long(dev, 0xa0); tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ @@ -300,23 +350,8 @@ return 0; } - reg = pci_read_byte(dev, 0x40); - msg_pdbg("SB700 IMC is %sactive.\n", (reg & (1 << 7)) ? "" : "not "); - if (reg & (1 << 7)) { - /* If we touch any region used by the IMC, the IMC and the SPI - * interface will lock up, and the only way to recover is a - * hard reset, but that is a bad choice for a half-erased or - * half-written flash chip. - * There appears to be an undocumented register which can freeze - * or disable the IMC, but for now we want to play it safe. - */ - msg_perr("The SB700 IMC is active and may interfere with SPI " - "commands. Disabling write.\n"); - /* FIXME: Should we only disable SPI writes, or will the lockup - * affect LPC/FWH chips as well? - */ - programmer_may_write = 0; - } + if (sb600_handle_imc(dev, amd_imc_force) != 0) + return ERROR_FATAL; /* Bring the FIFO to a clean state. */ reset_internal_fifo_pointer();

1 0

[commit] r1703 - trunk
by repository service 26 Jul '13

26 Jul '13

Author: stefanct Date: Fri Jul 26 00:58:51 2013 New Revision: 1703 URL: http://flashrom.org/trac/flashrom/changeset/1703 Log: Rename Numonyx and ST (SGS/Thomson) chips to Micron. Micron acquired Numonyx and asked us to change the vendor names to "Micron". For the chips clearly emerging from the former manufacturers we (will) use "Micron/Numonyx/ST" and the original name for the rest. Resorting the chip entries makes the diff unreadable, hence the stand-alone commit. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashchips.c Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Fri Jul 26 00:54:25 2013 (r1702) +++ trunk/flashchips.c Fri Jul 26 00:58:51 2013 (r1703) @@ -4079,44 +4079,6 @@ { .vendor = "Eon", - .name = "EN25QH256", - .bustype = BUS_SPI, - .manufacture_id = EON_ID_NOPREFIX, - .model_id = EON_EN25QH256, - .total_size = 32768, - .page_size = 256, - /* supports SFDP */ - /* OTP: 512B total; enter 0x3A */ - /* QPI enable 0x38, disable 0xFF */ - /* EN4B: 0xB7, EX4B: 0xE9 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, - .tested = TEST_BAD_REW, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = { - { - .eraseblocks = { {4 * 1024, 8192} }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {64 * 1024, 512} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { { 32768 * 1024, 1} }, - .block_erase = spi_block_erase_60, - }, { - .eraseblocks = { { 32768 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, - .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, - }, - - { - .vendor = "Eon", .name = "EN25S10", .bustype = BUS_SPI, .manufacture_id = EON_ID_NOPREFIX, @@ -6599,392 +6561,389 @@ }, { - .vendor = "MoselVitelic", - .name = "V29C51000B", - .bustype = BUS_PARALLEL, - .manufacture_id = SYNCMOS_MVC_ID, - .model_id = MVC_V29C51000B, + .vendor = "Micron/Numonyx/ST", + .name = "M25P05-A", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M25P05A, .total_size = 64, - .page_size = 512, - .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_UNTESTED, - .probe = probe_jedec, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {512, 128} }, - .block_erase = erase_sector_jedec, + .eraseblocks = { {32 * 1024, 2} }, + .block_erase = spi_block_erase_d8, }, { .eraseblocks = { {64 * 1024, 1} }, - .block_erase = erase_chip_block_jedec, - }, + .block_erase = spi_block_erase_c7, + } }, - .write = write_jedec_1, - .read = read_memmapped, - .voltage = {4500, 5500}, + .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, }, + /* The ST M25P05 is a bit of a problem. It has the same ID as the + * ST M25P05-A in RES mode, but supports only 128 byte writes instead + * of 256 byte writes. We rely heavily on the fact that probe_spi_res1 + * only is successful if RDID does not work. + */ { - .vendor = "MoselVitelic", - .name = "V29C51000T", - .bustype = BUS_PARALLEL, - .manufacture_id = SYNCMOS_MVC_ID, - .model_id = MVC_V29C51000T, + .vendor = "Micron/Numonyx/ST", + .name = "M25P05", + .bustype = BUS_SPI, + .manufacture_id = 0, /* Not used. */ + .model_id = ST_M25P05_RES, .total_size = 64, - .page_size = 512, - .feature_bits = FEATURE_EITHER_RESET, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, - .probe = probe_jedec, + .probe = probe_spi_res1, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {512, 128} }, - .block_erase = erase_sector_jedec, + .eraseblocks = { {32 * 1024, 2} }, + .block_erase = spi_block_erase_d8, }, { .eraseblocks = { {64 * 1024, 1} }, - .block_erase = erase_chip_block_jedec, - }, + .block_erase = spi_block_erase_c7, + } }, - .write = write_jedec_1, - .read = read_memmapped, - .voltage = {4500, 5500}, + .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_1, /* 128 */ + .read = spi_chip_read, + .voltage = {2700, 3600}, }, { - .vendor = "MoselVitelic", - .name = "V29C51400B", - .bustype = BUS_PARALLEL, - .manufacture_id = SYNCMOS_MVC_ID, - .model_id = MVC_V29C51400B, - .total_size = 512, - .page_size = 1024, - .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_UNTESTED, - .probe = probe_jedec, + .vendor = "Micron/Numonyx/ST", + .name = "M25P10-A", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M25P10A, + .total_size = 128, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PRE, + .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {1024, 512} }, - .block_erase = erase_sector_jedec, + .eraseblocks = { {32 * 1024, 4} }, + .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {512 * 1024, 1} }, - .block_erase = erase_chip_block_jedec, - }, + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } }, - .write = write_jedec_1, - .read = read_memmapped, - .voltage = {4500, 5500}, + .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, }, + /* The ST M25P10 has the same problem as the M25P05. */ { - .vendor = "MoselVitelic", - .name = "V29C51400T", - .bustype = BUS_PARALLEL, - .manufacture_id = SYNCMOS_MVC_ID, - .model_id = MVC_V29C51400T, - .total_size = 512, - .page_size = 1024, - .feature_bits = FEATURE_EITHER_RESET, + .vendor = "Micron/Numonyx/ST", + .name = "M25P10", + .bustype = BUS_SPI, + .manufacture_id = 0, /* Not used. */ + .model_id = ST_M25P10_RES, + .total_size = 128, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, - .probe = probe_jedec, + .probe = probe_spi_res1, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {1024, 512} }, - .block_erase = erase_sector_jedec, + .eraseblocks = { {32 * 1024, 4} }, + .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {512 * 1024, 1} }, - .block_erase = erase_chip_block_jedec, - }, + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } }, - .write = write_jedec_1, - .read = read_memmapped, - .voltage = {4500, 5500}, + .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_1, /* 128 */ + .read = spi_chip_read, + .voltage = {2700, 3600}, }, { - .vendor = "MoselVitelic", - .name = "V29LC51000", - .bustype = BUS_PARALLEL, - .manufacture_id = SYNCMOS_MVC_ID, - .model_id = MVC_V29LC51000, - .total_size = 64, - .page_size = 512, - .feature_bits = FEATURE_EITHER_RESET, + .vendor = "Micron/Numonyx/ST", /* Numonyx */ + .name = "M25P20", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M25P20, + .total_size = 256, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, - .probe = probe_jedec, + .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {512, 128} }, - .block_erase = erase_sector_jedec, + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {64 * 1024, 1} }, - .block_erase = erase_chip_block_jedec, - }, + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } }, - .write = write_jedec_1, - .read = read_memmapped, - .voltage = {4500, 5500}, + .printlock = spi_prettyprint_status_register_default_bp1, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, }, { - .vendor = "MoselVitelic", - .name = "V29LC51001", - .bustype = BUS_PARALLEL, - .manufacture_id = SYNCMOS_MVC_ID, - .model_id = MVC_V29LC51001, - .total_size = 128, - .page_size = 512, - .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_UNTESTED, - .probe = probe_jedec, + .vendor = "Micron/Numonyx/ST", + .name = "M25P20-old", + .bustype = BUS_SPI, + .manufacture_id = 0, /* Not used. */ + .model_id = ST_M25P20_RES, + .total_size = 256, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_res1, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {512, 256} }, - .block_erase = erase_sector_jedec, + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {128 * 1024, 1} }, - .block_erase = erase_chip_block_jedec, - }, + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } }, - .write = write_jedec_1, - .read = read_memmapped, - .voltage = {4500, 5500}, + .printlock = spi_prettyprint_status_register_default_bp1, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, }, { - .vendor = "MoselVitelic", - .name = "V29LC51002", - .bustype = BUS_PARALLEL, - .manufacture_id = SYNCMOS_MVC_ID, - .model_id = MVC_V29LC51002, - .total_size = 256, - .page_size = 512, - .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_UNTESTED, - .probe = probe_jedec, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {512, 512} }, - .block_erase = erase_sector_jedec, + .vendor = "Micron/Numonyx/ST", /* Numonyx */ + .name = "M25P40", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M25P40, + .total_size = 512, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {256 * 1024, 1} }, - .block_erase = erase_chip_block_jedec, - }, + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } }, - .write = write_jedec_1, - .read = read_memmapped, - .voltage = {4500, 5500}, + .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, }, { - .vendor = "Nantronics", - .name = "N25S10", + .vendor = "Micron/Numonyx/ST", + .name = "M25P40-old", .bustype = BUS_SPI, - .manufacture_id = NANTRONICS_ID_NOPREFIX, - .model_id = NANTRONICS_N25S10, - .total_size = 128, + .manufacture_id = 0, /* Not used. */ + .model_id = ST_M25P40_RES, + .total_size = 512, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, - .probe = probe_spi_rdid, + .probe = probe_spi_res1, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {4 * 1024, 32} }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {4 * 1024, 32} }, - .block_erase = spi_block_erase_d7, - }, { - .eraseblocks = { {32 * 1024, 4} }, - .block_erase = spi_block_erase_52, - }, { - .eraseblocks = { {64 * 1024, 2} }, + .eraseblocks = { {64 * 1024, 8} }, .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {128 * 1024, 1} }, - .block_erase = spi_block_erase_60, + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Micron/Numonyx/ST", + .name = "M25P80", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M25P80, + .total_size = 1024, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {128 * 1024, 1} }, + .eraseblocks = { {1024 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp3, - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B), dual I/O read (0x3B) supported */ + .read = spi_chip_read, .voltage = {2700, 3600}, }, { - .vendor = "Nantronics", - .name = "N25S20", + .vendor = "Micron/Numonyx/ST", + .name = "M25P16", .bustype = BUS_SPI, - .manufacture_id = NANTRONICS_ID_NOPREFIX, - .model_id = NANTRONICS_N25S20, - .total_size = 256, + .manufacture_id = ST_ID, + .model_id = ST_M25P16, + .total_size = 2048, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PR, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {4 * 1024, 64} }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {4 * 1024, 64} }, - .block_erase = spi_block_erase_d7, - }, { - .eraseblocks = { {32 * 1024, 8} }, - .block_erase = spi_block_erase_52, - }, { - .eraseblocks = { {64 * 1024, 4} }, + .eraseblocks = { {64 * 1024, 32} }, .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {256 * 1024, 1} }, - .block_erase = spi_block_erase_60, - }, { - .eraseblocks = { {256 * 1024, 1} }, + .eraseblocks = { {2 * 1024 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp3, - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B), dual I/O read (0x3B) supported */ + .read = spi_chip_read, .voltage = {2700, 3600}, }, { - .vendor = "Nantronics", - .name = "N25S40", + .vendor = "Micron/Numonyx/ST", + .name = "M25P32", .bustype = BUS_SPI, - .manufacture_id = NANTRONICS_ID_NOPREFIX, - .model_id = NANTRONICS_N25S40, - .total_size = 512, + .manufacture_id = ST_ID, + .model_id = ST_M25P32, + .total_size = 4096, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {4 * 1024, 128} }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {4 * 1024, 128} }, - .block_erase = spi_block_erase_d7, - }, { - .eraseblocks = { {32 * 1024, 16} }, - .block_erase = spi_block_erase_52, - }, { - .eraseblocks = { {64 * 1024, 8} }, + .eraseblocks = { {64 * 1024, 64} }, .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {512 * 1024, 1} }, - .block_erase = spi_block_erase_60, - }, { - .eraseblocks = { {512 * 1024, 1} }, + .eraseblocks = { {4 * 1024 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp3, - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B), dual I/O read (0x3B) supported */ + .read = spi_chip_read, .voltage = {2700, 3600}, }, { - .vendor = "Nantronics", - .name = "N25S80", + .vendor = "Micron/Numonyx/ST", + .name = "M25P64", .bustype = BUS_SPI, - .manufacture_id = NANTRONICS_ID_NOPREFIX, - .model_id = NANTRONICS_N25S80, - .total_size = 1024, + .manufacture_id = ST_ID, + .model_id = ST_M25P64, + .total_size = 8192, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {4 * 1024, 256} }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {32 * 1024, 32} }, - .block_erase = spi_block_erase_52, - }, { - .eraseblocks = { {64 * 1024, 16} }, + .eraseblocks = { {64 * 1024, 128} }, .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {1024 * 1024, 1} }, - .block_erase = spi_block_erase_60, - }, { - .eraseblocks = { {1024 * 1024, 1} }, + .eraseblocks = { {8 * 1024 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp3, - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B), dual I/O read (0x3B) supported */ + .read = spi_chip_read, .voltage = {2700, 3600}, }, { - .vendor = "Nantronics", - .name = "N25S16", + .vendor = "Micron/Numonyx/ST", + .name = "M25P128", .bustype = BUS_SPI, - .manufacture_id = NANTRONICS_ID_NOPREFIX, - .model_id = NANTRONICS_N25S16, - .total_size = 2048, + .manufacture_id = ST_ID, + .model_id = ST_M25P128, + .total_size = 16384, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {4 * 1024, 512} }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {64 * 1024, 32} }, + .eraseblocks = { {256 * 1024, 64} }, .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {2048 * 1024, 1} }, - .block_erase = spi_block_erase_60, - }, { - .eraseblocks = { {2048 * 1024, 1} }, + .eraseblocks = { {16 * 1024 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp3, - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B), dual I/O read (0x3B) supported */ + .read = spi_chip_read, .voltage = {2700, 3600}, }, { - .vendor = "Numonyx", + .vendor = "Micron/Numonyx/ST", .name = "M25PE10", .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -7016,7 +6975,7 @@ }, { - .vendor = "Numonyx", + .vendor = "Micron/Numonyx/ST", .name = "M25PE20", .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -7048,7 +7007,7 @@ }, { - .vendor = "Numonyx", + .vendor = "Micron/Numonyx/ST", .name = "M25PE40", .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -7080,7 +7039,7 @@ }, { - .vendor = "Numonyx", + .vendor = "Micron/Numonyx/ST", .name = "M25PE80", .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -7112,7 +7071,7 @@ }, { - .vendor = "Numonyx", + .vendor = "Micron/Numonyx/ST", .name = "M25PE16", .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -7144,47 +7103,176 @@ }, { - .vendor = "Numonyx", - .name = "M45PE10", + .vendor = "Micron/Numonyx/ST", + .name = "M25PX80", .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_M45PE10, - .total_size = 128, + .model_id = ST_M25PX80, + .total_size = 1024, .page_size = 256, - .tested = TEST_UNTESTED, + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {256, 512} }, - .block_erase = spi_block_erase_db, + .eraseblocks = { { 4 * 1024, 256 } }, + .block_erase = spi_block_erase_20, }, { - .eraseblocks = { {64 * 1024, 2} }, + .eraseblocks = { {64 * 1024, 16} }, .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_welwip, - .unlock = NULL, /* #WP pin write-protects lower 64kB. */ - .write = spi_chip_write_256, /* Page write (similar to PP but allows 0->1 changes) */ - .read = spi_chip_read, /* Fast read (0x0B) supported */ + .printlock = spi_prettyprint_status_register_default_bp2, /* bit5: T/B */ + .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, + .read = spi_chip_read, .voltage = {2700, 3600}, }, { - .vendor = "Numonyx", - .name = "M45PE20", + .vendor = "Micron/Numonyx/ST", + .name = "M25PX16", .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_M45PE20, - .total_size = 256, + .model_id = ST_M25PX16, + .total_size = 2048, .page_size = 256, - .tested = TEST_UNTESTED, + /* OTP: 64B total; read 0x4B; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { - .eraseblocks = { {256, 1024} }, - .block_erase = spi_block_erase_db, + .eraseblocks = { { 4 * 1024, 512 } }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, /* bit5: T/B */ + .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Micron/Numonyx/ST", + .name = "M25PX32", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M25PX32, + .total_size = 4096, + .page_size = 256, + /* OTP: 64B total; read 0x4B; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PRE, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 4 * 1024, 1024 } }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, /* bit5: T/B */ + .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron/Numonyx/ST", + .name = "M25PX64", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M25PX64, + .total_size = 8192, + .page_size = 256, + /* OTP: 64B total; read 0x4B; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PRE, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 4 * 1024, 2048 } }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, /* bit5: T/B */ + .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Micron/Numonyx/ST", + .name = "M45PE10", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M45PE10, + .total_size = 128, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {256, 512} }, + .block_erase = spi_block_erase_db, + }, { + .eraseblocks = { {64 * 1024, 2} }, + .block_erase = spi_block_erase_d8, + } + }, + .printlock = spi_prettyprint_status_register_default_welwip, + .unlock = NULL, /* #WP pin write-protects lower 64kB. */ + .write = spi_chip_write_256, /* Page write (similar to PP but allows 0->1 changes) */ + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron/Numonyx/ST", + .name = "M45PE20", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M45PE20, + .total_size = 256, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {256, 1024} }, + .block_erase = spi_block_erase_db, }, { .eraseblocks = { {64 * 1024, 4} }, .block_erase = spi_block_erase_d8, @@ -7198,7 +7286,7 @@ }, { - .vendor = "Numonyx", + .vendor = "Micron/Numonyx/ST", .name = "M45PE40", .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -7225,7 +7313,7 @@ }, { - .vendor = "Numonyx", + .vendor = "Micron/Numonyx/ST", .name = "M45PE80", .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -7252,7 +7340,7 @@ }, { - .vendor = "Numonyx", + .vendor = "Micron/Numonyx/ST", .name = "M45PE16", .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -7279,7 +7367,7 @@ }, { - .vendor = "Numonyx", + .vendor = "Micron/Numonyx/ST", .name = "N25Q016", .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -7316,7 +7404,7 @@ }, { - .vendor = "Numonyx", + .vendor = "Micron/Numonyx/ST", .name = "N25Q032..1E", .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -7350,7 +7438,7 @@ }, { - .vendor = "Numonyx", + .vendor = "Micron/Numonyx/ST", .name = "N25Q032..3E", .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -7384,7 +7472,7 @@ }, { - .vendor = "Numonyx", + .vendor = "Micron/Numonyx/ST", .name = "N25Q064..1E", /* ..1E = 1.8V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -7418,7 +7506,7 @@ }, { - .vendor = "Numonyx", + .vendor = "Micron/Numonyx/ST", .name = "N25Q064..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -7452,7 +7540,7 @@ }, { - .vendor = "Numonyx", + .vendor = "Micron/Numonyx/ST", .name = "N25Q128..1E", /* ..1E = 1.8V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -7485,7 +7573,7 @@ }, { - .vendor = "Numonyx", + .vendor = "Micron/Numonyx/ST", .name = "N25Q128..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -7518,257 +7606,200 @@ }, { - .vendor = "Numonyx", - .name = "N25Q256..1E", /* ..1E = 1.8V, uniform 64KB/4KB blocks/sectors */ - .bustype = BUS_SPI, - .manufacture_id = ST_ID, - .model_id = ST_N25Q256__1E, - .total_size = 32768, - .page_size = 256, - /* supports SFDP */ - /* OTP: 64B total; read 0x4B, write 0x42 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_BAD_REW, - .probe = probe_spi_rdid, + .vendor = "MoselVitelic", + .name = "V29C51000B", + .bustype = BUS_PARALLEL, + .manufacture_id = SYNCMOS_MVC_ID, + .model_id = MVC_V29C51000B, + .total_size = 64, + .page_size = 512, + .feature_bits = FEATURE_EITHER_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { - .eraseblocks = { {4 * 1024, 8192 } }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {64 * 1024, 512} }, - .block_erase = spi_block_erase_d8, + .eraseblocks = { {512, 128} }, + .block_erase = erase_sector_jedec, }, { - .eraseblocks = { {32768 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, }, - .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ - .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ - .write = spi_chip_write_256, /* Multi I/O supported */ - .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ - .voltage = {1700, 2000}, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {4500, 5500}, }, { - .vendor = "Numonyx", - .name = "N25Q256..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ - .bustype = BUS_SPI, - .manufacture_id = ST_ID, - .model_id = ST_N25Q256__3E, - .total_size = 32768, - .page_size = 256, - /* supports SFDP */ - /* OTP: 64B total; read 0x4B, write 0x42 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_OK_PROBE | TEST_BAD_REW, - .probe = probe_spi_rdid, + .vendor = "MoselVitelic", + .name = "V29C51000T", + .bustype = BUS_PARALLEL, + .manufacture_id = SYNCMOS_MVC_ID, + .model_id = MVC_V29C51000T, + .total_size = 64, + .page_size = 512, + .feature_bits = FEATURE_EITHER_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { - .eraseblocks = { {4 * 1024, 8192 } }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {64 * 1024, 512} }, - .block_erase = spi_block_erase_d8, + .eraseblocks = { {512, 128} }, + .block_erase = erase_sector_jedec, }, { - .eraseblocks = { {32768 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, }, - .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ - .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ - .write = spi_chip_write_256, /* Multi I/O supported */ - .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ - .voltage = {2700, 3600}, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {4500, 5500}, }, { - .vendor = "Numonyx", - .name = "N25Q512..1E", /* ..1E = 1.8V, uniform 64KB/4KB blocks/sectors */ - .bustype = BUS_SPI, - .manufacture_id = ST_ID, - .model_id = ST_N25Q512__1E, - .total_size = 65536, - .page_size = 256, - /* supports SFDP */ - /* OTP: 64B total; read 0x4B, write 0x42 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_BAD_REW, - .probe = probe_spi_rdid, + .vendor = "MoselVitelic", + .name = "V29C51400B", + .bustype = BUS_PARALLEL, + .manufacture_id = SYNCMOS_MVC_ID, + .model_id = MVC_V29C51400B, + .total_size = 512, + .page_size = 1024, + .feature_bits = FEATURE_EITHER_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { - .eraseblocks = { {4 * 1024, 16384 } }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {64 * 1024, 1024 } }, - .block_erase = spi_block_erase_d8, + .eraseblocks = { {1024, 512} }, + .block_erase = erase_sector_jedec, }, { - .eraseblocks = { {32 * 1024 * 1024, 2 } }, - .block_erase = spi_block_erase_c4, - }, { /* Some models have a bulk erase command too. */ - .eraseblocks = { {64 * 1024 * 1024, 1 } }, - .block_erase = spi_block_erase_c7, - } + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, }, - .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ - .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ - .write = spi_chip_write_256, /* Multi I/O supported */ - .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ - .voltage = {1700, 2000}, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {4500, 5500}, }, { - .vendor = "Numonyx", - .name = "N25Q512..3G", /* ..3G = 3V, uniform 64KB/4KB blocks/sectors */ - .bustype = BUS_SPI, - .manufacture_id = ST_ID, - .model_id = ST_N25Q512__3E, - .total_size = 65536, - .page_size = 256, - /* supports SFDP */ - /* OTP: 64B total; read 0x4B, write 0x42 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_OK_PROBE | TEST_BAD_REW, - .probe = probe_spi_rdid, + .vendor = "MoselVitelic", + .name = "V29C51400T", + .bustype = BUS_PARALLEL, + .manufacture_id = SYNCMOS_MVC_ID, + .model_id = MVC_V29C51400T, + .total_size = 512, + .page_size = 1024, + .feature_bits = FEATURE_EITHER_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { - .eraseblocks = { {4 * 1024, 16384 } }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {64 * 1024, 1024 } }, - .block_erase = spi_block_erase_d8, + .eraseblocks = { {1024, 512} }, + .block_erase = erase_sector_jedec, }, { - .eraseblocks = { {32 * 1024 * 1024, 2 } }, - .block_erase = spi_block_erase_c4, - }, { /* Some models have a bulk erase command too. */ - .eraseblocks = { {64 * 1024 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, }, - .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ - .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ - .write = spi_chip_write_256, /* Multi I/O supported */ - .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ - .voltage = {2700, 3600}, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {4500, 5500}, }, { - .vendor = "Numonyx", - .name = "N25Q00A..3G", /* ..3G = 3V, uniform 64KB/4KB blocks/sectors */ - .bustype = BUS_SPI, - .manufacture_id = ST_ID, - .model_id = ST_N25Q00A__3E, - .total_size = 131072, - .page_size = 256, - /* supports SFDP */ - /* OTP: 64B total; read 0x4B, write 0x42 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_BAD_REW, - .probe = probe_spi_rdid, + .vendor = "MoselVitelic", + .name = "V29LC51000", + .bustype = BUS_PARALLEL, + .manufacture_id = SYNCMOS_MVC_ID, + .model_id = MVC_V29LC51000, + .total_size = 64, + .page_size = 512, + .feature_bits = FEATURE_EITHER_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { - .eraseblocks = { {4 * 1024, 32768 } }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {64 * 1024, 2048 } }, - .block_erase = spi_block_erase_d8, + .eraseblocks = { {512, 128} }, + .block_erase = erase_sector_jedec, }, { - .eraseblocks = { {32 * 1024 * 1024, 4 } }, - .block_erase = spi_block_erase_c4, - } + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, }, - .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ - .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ - .write = spi_chip_write_256, /* Multi I/O supported */ - .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ - .voltage = {2700, 3600}, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {4500, 5500}, }, { - .vendor = "PMC", - .name = "Pm25LD256C", - .bustype = BUS_SPI, - .manufacture_id = PMC_ID, - .model_id = PMC_PM25LD256C, - .total_size = 32, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + .vendor = "MoselVitelic", + .name = "V29LC51001", + .bustype = BUS_PARALLEL, + .manufacture_id = SYNCMOS_MVC_ID, + .model_id = MVC_V29LC51001, + .total_size = 128, + .page_size = 512, + .feature_bits = FEATURE_EITHER_RESET, .tested = TEST_UNTESTED, - .probe = probe_spi_rdid, + .probe = probe_jedec, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {4 * 1024, 8} }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {4 * 1024, 8} }, - .block_erase = spi_block_erase_d7, - }, { - .eraseblocks = { {32 * 1024, 1} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {32 * 1024, 1} }, - .block_erase = spi_block_erase_60, + .eraseblocks = { {512, 256} }, + .block_erase = erase_sector_jedec, }, { - .eraseblocks = { {32 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, }, - .printlock = spi_prettyprint_status_register_default_bp2, - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ - .voltage = {2700, 3600}, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {4500, 5500}, }, + { - .vendor = "PMC", - .name = "Pm25LD512(C)", - .bustype = BUS_SPI, - .manufacture_id = PMC_ID, - .model_id = PMC_PM25LD512, - .total_size = 64, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PREW, - .probe = probe_spi_rdid, + .vendor = "MoselVitelic", + .name = "V29LC51002", + .bustype = BUS_PARALLEL, + .manufacture_id = SYNCMOS_MVC_ID, + .model_id = MVC_V29LC51002, + .total_size = 256, + .page_size = 512, + .feature_bits = FEATURE_EITHER_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {4 * 1024, 16} }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {4 * 1024, 16} }, - .block_erase = spi_block_erase_d7, - }, { - .eraseblocks = { {32 * 1024, 2} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {64 * 1024, 1} }, - .block_erase = spi_block_erase_60, + .eraseblocks = { {512, 512} }, + .block_erase = erase_sector_jedec, }, { - .eraseblocks = { {64 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, }, - .printlock = spi_prettyprint_status_register_default_bp2, - .unlock = spi_disable_blockprotect, /* FIXME: C version supports "Safe Guard" */ - .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ - .voltage = {2300, 3600}, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {4500, 5500}, }, { - .vendor = "PMC", - .name = "Pm25LD010(C)", + .vendor = "Nantronics", + .name = "N25S10", .bustype = BUS_SPI, - .manufacture_id = PMC_ID, - .model_id = PMC_PM25LD010, + .manufacture_id = NANTRONICS_ID_NOPREFIX, + .model_id = NANTRONICS_N25S10, .total_size = 128, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, @@ -7785,6 +7816,9 @@ .block_erase = spi_block_erase_d7, }, { .eraseblocks = { {32 * 1024, 4} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 2} }, .block_erase = spi_block_erase_d8, }, { .eraseblocks = { {128 * 1024, 1} }, @@ -7794,19 +7828,19 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp2, - .unlock = spi_disable_blockprotect, /* FIXME: C version supports "Safe Guard" */ + .printlock = spi_prettyprint_status_register_default_bp3, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ - .voltage = {2700, 3600}, /* 2.3-3.6V for Pm25LD010 */ + .read = spi_chip_read, /* Fast read (0x0B), dual I/O read (0x3B) supported */ + .voltage = {2700, 3600}, }, { - .vendor = "PMC", - .name = "Pm25LD020(C)", + .vendor = "Nantronics", + .name = "N25S20", .bustype = BUS_SPI, - .manufacture_id = PMC_ID, - .model_id = PMC_PM25LD020, + .manufacture_id = NANTRONICS_ID_NOPREFIX, + .model_id = NANTRONICS_N25S20, .total_size = 256, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, @@ -7822,6 +7856,9 @@ .eraseblocks = { {4 * 1024, 64} }, .block_erase = spi_block_erase_d7, }, { + .eraseblocks = { {32 * 1024, 8} }, + .block_erase = spi_block_erase_52, + }, { .eraseblocks = { {64 * 1024, 4} }, .block_erase = spi_block_erase_d8, }, { @@ -7832,19 +7869,19 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp2, - .unlock = spi_disable_blockprotect, /* FIXME: C version supports "Safe Guard" */ + .printlock = spi_prettyprint_status_register_default_bp3, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ - .voltage = {2700, 3600}, /* 2.3-3.6V for Pm25LD020 */ + .read = spi_chip_read, /* Fast read (0x0B), dual I/O read (0x3B) supported */ + .voltage = {2700, 3600}, }, { - .vendor = "PMC", - .name = "Pm25LD040(C)", + .vendor = "Nantronics", + .name = "N25S40", .bustype = BUS_SPI, - .manufacture_id = PMC_ID, - .model_id = PMC_PM25LV040, + .manufacture_id = NANTRONICS_ID_NOPREFIX, + .model_id = NANTRONICS_N25S40, .total_size = 512, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, @@ -7860,6 +7897,9 @@ .eraseblocks = { {4 * 1024, 128} }, .block_erase = spi_block_erase_d7, }, { + .eraseblocks = { {32 * 1024, 16} }, + .block_erase = spi_block_erase_52, + }, { .eraseblocks = { {64 * 1024, 8} }, .block_erase = spi_block_erase_d8, }, { @@ -7870,180 +7910,206 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp2, - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp3, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ - .voltage = {2700, 3600}, /* 2.3-3.6V for Pm25LD040 */ + .read = spi_chip_read, /* Fast read (0x0B), dual I/O read (0x3B) supported */ + .voltage = {2700, 3600}, }, -{ - .vendor = "PMC", - .name = "Pm25LV512(A)", + { + .vendor = "Nantronics", + .name = "N25S80", .bustype = BUS_SPI, - .manufacture_id = PMC_ID, - .model_id = PMC_PM25LV512, - .total_size = 64, + .manufacture_id = NANTRONICS_ID_NOPREFIX, + .model_id = NANTRONICS_N25S80, + .total_size = 1024, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, - .probe = probe_spi_res3, + .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {4 * 1024, 16} }, - .block_erase = spi_block_erase_d7, + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, }, { - .eraseblocks = { {32 * 1024, 2} }, + .eraseblocks = { {32 * 1024, 32} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {64 * 1024, 1} }, + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp1, - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp3, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B) supported */ + .read = spi_chip_read, /* Fast read (0x0B), dual I/O read (0x3B) supported */ .voltage = {2700, 3600}, }, { - .vendor = "PMC", - .name = "Pm25LV010", + .vendor = "Nantronics", + .name = "N25S16", .bustype = BUS_SPI, - .manufacture_id = PMC_ID, - .model_id = PMC_PM25LV010, - .total_size = 128, + .manufacture_id = NANTRONICS_ID_NOPREFIX, + .model_id = NANTRONICS_N25S16, + .total_size = 2048, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, - .probe = probe_spi_res3, + .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {4 * 1024, 32} }, - .block_erase = spi_block_erase_d7, + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, }, { - .eraseblocks = { {32 * 1024, 4} }, + .eraseblocks = { {64 * 1024, 32} }, .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {128 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_default_bp1, - .unlock = spi_disable_blockprotect, + .eraseblocks = { {2048 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2048 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp3, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B) supported */ + .read = spi_chip_read, /* Fast read (0x0B), dual I/O read (0x3B) supported */ .voltage = {2700, 3600}, }, { .vendor = "PMC", - .name = "Pm25LV010A", + .name = "Pm25LD256C", .bustype = BUS_SPI, .manufacture_id = PMC_ID, - .model_id = PMC_PM25LV010, - .total_size = 128, + .model_id = PMC_PM25LD256C, + .total_size = 32, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PREW, + .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {4 * 1024, 32} }, + .eraseblocks = { {4 * 1024, 8} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {4 * 1024, 8} }, .block_erase = spi_block_erase_d7, }, { - .eraseblocks = { {32 * 1024, 4} }, + .eraseblocks = { {32 * 1024, 1} }, .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {128 * 1024, 1} }, + .eraseblocks = { {32 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp1, + .printlock = spi_prettyprint_status_register_default_bp2, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B) supported */ + .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ .voltage = {2700, 3600}, }, - { .vendor = "PMC", - .name = "Pm25LV020", + .name = "Pm25LD512(C)", .bustype = BUS_SPI, .manufacture_id = PMC_ID, - .model_id = PMC_PM25LV020, - .total_size = 256, + .model_id = PMC_PM25LD512, + .total_size = 64, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {4 * 1024, 64} }, + .eraseblocks = { {4 * 1024, 16} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {4 * 1024, 16} }, .block_erase = spi_block_erase_d7, }, { - .eraseblocks = { {64 * 1024, 4} }, + .eraseblocks = { {32 * 1024, 2} }, .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {256 * 1024, 1} }, + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {64 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, .printlock = spi_prettyprint_status_register_default_bp2, - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect, /* FIXME: C version supports "Safe Guard" */ .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, + .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ + .voltage = {2300, 3600}, }, { .vendor = "PMC", - .name = "Pm25LV040", + .name = "Pm25LD010(C)", .bustype = BUS_SPI, .manufacture_id = PMC_ID, - .model_id = PMC_PM25LV040, - .total_size = 512, + .model_id = PMC_PM25LD010, + .total_size = 128, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PREW, + .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {4 * 1024, 128} }, + .eraseblocks = { {4 * 1024, 32} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {4 * 1024, 32} }, .block_erase = spi_block_erase_d7, }, { - .eraseblocks = { {64 * 1024, 8} }, + .eraseblocks = { {32 * 1024, 4} }, .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {512 * 1024, 1} }, + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {128 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, .printlock = spi_prettyprint_status_register_default_bp2, - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect, /* FIXME: C version supports "Safe Guard" */ .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B) supported */ - .voltage = {2700, 3600}, + .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ + .voltage = {2700, 3600}, /* 2.3-3.6V for Pm25LD010 */ }, { .vendor = "PMC", - .name = "Pm25LV080B", + .name = "Pm25LD020(C)", .bustype = BUS_SPI, .manufacture_id = PMC_ID, - .model_id = PMC_PM25LV080B, - .total_size = 1024, + .model_id = PMC_PM25LD020, + .total_size = 256, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, @@ -8052,36 +8118,36 @@ .block_erasers = { { - .eraseblocks = { {4 * 1024, 256} }, - .block_erase = spi_block_erase_d7, - }, { - .eraseblocks = { {4 * 1024, 256} }, + .eraseblocks = { {4 * 1024, 64} }, .block_erase = spi_block_erase_20, }, { - .eraseblocks = { {64 * 1024, 16} }, + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = spi_block_erase_d7, + }, { + .eraseblocks = { {64 * 1024, 4} }, .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {1024 * 1024, 1} }, + .eraseblocks = { {256 * 1024, 1} }, .block_erase = spi_block_erase_60, }, { - .eraseblocks = { {1024 * 1024, 1} }, + .eraseblocks = { {256 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, .printlock = spi_prettyprint_status_register_default_bp2, - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect, /* FIXME: C version supports "Safe Guard" */ .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B) supported */ - .voltage = {2700, 3600}, + .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ + .voltage = {2700, 3600}, /* 2.3-3.6V for Pm25LD020 */ }, { .vendor = "PMC", - .name = "Pm25LV016B", + .name = "Pm25LD040(C)", .bustype = BUS_SPI, .manufacture_id = PMC_ID, - .model_id = PMC_PM25LV016B, - .total_size = 2048, + .model_id = PMC_PM25LV040, + .total_size = 512, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, @@ -8090,119 +8156,355 @@ .block_erasers = { { - .eraseblocks = { {4 * 1024, 512} }, - .block_erase = spi_block_erase_d7, - }, { - .eraseblocks = { {4 * 1024, 512} }, + .eraseblocks = { {4 * 1024, 128} }, .block_erase = spi_block_erase_20, }, { - .eraseblocks = { {64 * 1024, 32} }, + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_d7, + }, { + .eraseblocks = { {64 * 1024, 8} }, .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {2 * 1024 * 1024, 1} }, + .eraseblocks = { {512 * 1024, 1} }, .block_erase = spi_block_erase_60, }, { - .eraseblocks = { {2 * 1024 * 1024, 1} }, + .eraseblocks = { {512 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, .printlock = spi_prettyprint_status_register_default_bp2, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B) supported */ - .voltage = {2700, 3600}, + .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ + .voltage = {2700, 3600}, /* 2.3-3.6V for Pm25LD040 */ }, - { +{ .vendor = "PMC", - .name = "Pm29F002T", - .bustype = BUS_PARALLEL, - .manufacture_id = PMC_ID_NOPREFIX, - .model_id = PMC_PM29F002T, - .total_size = 256, - .page_size = 8 * 1024, - .feature_bits = FEATURE_ADDR_2AA | FEATURE_EITHER_RESET, - .tested = TEST_OK_PREW, - .probe = probe_jedec, - .probe_timing = TIMING_FIXME, + .name = "Pm25LV512(A)", + .bustype = BUS_SPI, + .manufacture_id = PMC_ID, + .model_id = PMC_PM25LV512, + .total_size = 64, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_res3, + .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { - {128 * 1024, 1}, - {96 * 1024, 1}, - {8 * 1024, 2}, - {16 * 1024, 1}, - }, - .block_erase = erase_sector_jedec, + .eraseblocks = { {4 * 1024, 16} }, + .block_erase = spi_block_erase_d7, }, { - .eraseblocks = { {256 * 1024, 1} }, - .block_erase = erase_chip_block_jedec, - }, + .eraseblocks = { {32 * 1024, 2} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } }, - .write = write_jedec_1, - .read = read_memmapped, - .voltage = {4500, 5500}, + .printlock = spi_prettyprint_status_register_default_bp1, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, }, { .vendor = "PMC", - .name = "Pm29F002B", - .bustype = BUS_PARALLEL, - .manufacture_id = PMC_ID_NOPREFIX, - .model_id = PMC_PM29F002B, - .total_size = 256, - .page_size = 8 * 1024, - .feature_bits = FEATURE_ADDR_2AA | FEATURE_EITHER_RESET, + .name = "Pm25LV010", + .bustype = BUS_SPI, + .manufacture_id = PMC_ID, + .model_id = PMC_PM25LV010, + .total_size = 128, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, - .probe = probe_jedec, - .probe_timing = TIMING_FIXME, + .probe = probe_spi_res3, + .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { - {16 * 1024, 1}, - {8 * 1024, 2}, - {96 * 1024, 1}, - {128 * 1024, 1}, - }, - .block_erase = erase_sector_jedec, + .eraseblocks = { {4 * 1024, 32} }, + .block_erase = spi_block_erase_d7, }, { - .eraseblocks = { {256 * 1024, 1} }, - .block_erase = erase_chip_block_jedec, - }, + .eraseblocks = { {32 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } }, - .write = write_jedec_1, - .read = read_memmapped, - .voltage = {4500, 5500}, + .printlock = spi_prettyprint_status_register_default_bp1, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, }, { .vendor = "PMC", - .name = "Pm39LV010", - .bustype = BUS_PARALLEL, - .manufacture_id = PMC_ID_NOPREFIX, - .model_id = PMC_PM39F010, /* Pm39LV010 and Pm39F010 have identical IDs but different voltage */ + .name = "Pm25LV010A", + .bustype = BUS_SPI, + .manufacture_id = PMC_ID, + .model_id = PMC_PM25LV010, .total_size = 128, - .page_size = 4096, - .feature_bits = FEATURE_ADDR_2AA | FEATURE_EITHER_RESET, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_OK_PREW, - .probe = probe_jedec, - .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, .block_erasers = { { .eraseblocks = { {4 * 1024, 32} }, - .block_erase = erase_sector_jedec, + .block_erase = spi_block_erase_d7, }, { - .eraseblocks = { {64 * 1024, 2} }, - .block_erase = erase_block_jedec, + .eraseblocks = { {32 * 1024, 4} }, + .block_erase = spi_block_erase_d8, }, { .eraseblocks = { {128 * 1024, 1} }, - .block_erase = erase_chip_block_jedec, + .block_erase = spi_block_erase_c7, } }, - .write = write_jedec_1, + .printlock = spi_prettyprint_status_register_default_bp1, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "PMC", + .name = "Pm25LV020", + .bustype = BUS_SPI, + .manufacture_id = PMC_ID, + .model_id = PMC_PM25LV020, + .total_size = 256, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = spi_block_erase_d7, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "PMC", + .name = "Pm25LV040", + .bustype = BUS_SPI, + .manufacture_id = PMC_ID, + .model_id = PMC_PM25LV040, + .total_size = 512, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_d7, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "PMC", + .name = "Pm25LV080B", + .bustype = BUS_SPI, + .manufacture_id = PMC_ID, + .model_id = PMC_PM25LV080B, + .total_size = 1024, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_d7, + }, { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "PMC", + .name = "Pm25LV016B", + .bustype = BUS_SPI, + .manufacture_id = PMC_ID, + .model_id = PMC_PM25LV016B, + .total_size = 2048, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_d7, + }, { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "PMC", + .name = "Pm29F002T", + .bustype = BUS_PARALLEL, + .manufacture_id = PMC_ID_NOPREFIX, + .model_id = PMC_PM29F002T, + .total_size = 256, + .page_size = 8 * 1024, + .feature_bits = FEATURE_ADDR_2AA | FEATURE_EITHER_RESET, + .tested = TEST_OK_PREW, + .probe = probe_jedec, + .probe_timing = TIMING_FIXME, + .block_erasers = + { + { + .eraseblocks = { + {128 * 1024, 1}, + {96 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {4500, 5500}, + }, + + { + .vendor = "PMC", + .name = "Pm29F002B", + .bustype = BUS_PARALLEL, + .manufacture_id = PMC_ID_NOPREFIX, + .model_id = PMC_PM29F002B, + .total_size = 256, + .page_size = 8 * 1024, + .feature_bits = FEATURE_ADDR_2AA | FEATURE_EITHER_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_FIXME, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {96 * 1024, 1}, + {128 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {4500, 5500}, + }, + + { + .vendor = "PMC", + .name = "Pm39LV010", + .bustype = BUS_PARALLEL, + .manufacture_id = PMC_ID_NOPREFIX, + .model_id = PMC_PM39F010, /* Pm39LV010 and Pm39F010 have identical IDs but different voltage */ + .total_size = 128, + .page_size = 4096, + .feature_bits = FEATURE_ADDR_2AA | FEATURE_EITHER_RESET, + .tested = TEST_OK_PREW, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32} }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {64 * 1024, 2} }, + .block_erase = erase_block_jedec, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + }, + .write = write_jedec_1, .read = read_memmapped, .voltage = {2700, 3600}, }, @@ -8864,91 +9166,21 @@ }, { - .vendor = "Spansion", - .name = "S25FL256S......0", /* uniform 256kB sectors */ + .vendor = "SST", + .name = "SST25LF040A", .bustype = BUS_SPI, - .manufacture_id = SPANSION_ID, - .model_id = SPANSION_S25FL256, - .total_size = 32768, + .manufacture_id = SST_ID, + .model_id = SST_SST25VF040_REMS, + .total_size = 512, .page_size = 256, - /* supports 4B addressing */ - /* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_OK_PROBE | TEST_BAD_REW, - .probe = probe_spi_rdid, + .feature_bits = FEATURE_WRSR_EWSR, + .tested = TEST_OK_PREW, + .probe = probe_spi_res2, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { - .eraseblocks = { {4 * 1024, 8192} }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {256 * 1024, 128} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { { 32768 * 1024, 1} }, - .block_erase = spi_block_erase_60, - }, { - .eraseblocks = { { 32768 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_bp2_ep_srwd, /* TODO: SR2 and many others */ - .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: various other locks */ - .write = spi_chip_write_256, /* Multi I/O supported */ - .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ - .voltage = {2700, 3600}, - }, - - { - .vendor = "Spansion", - .name = "S25FL512S", - .bustype = BUS_SPI, - .manufacture_id = SPANSION_ID, - .model_id = SPANSION_S25FL512, - .total_size = 65536, - .page_size = 256, - /* supports 4B addressing */ - /* supports SFDP */ - /* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_OK_PROBE | TEST_BAD_REW, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = { - { - .eraseblocks = { {256 * 1024, 256} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { { 65536 * 1024, 1} }, - .block_erase = spi_block_erase_60, - }, { - .eraseblocks = { { 65536 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_bp2_ep_srwd, /* TODO: SR2 and many others */ - .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: various other locks */ - .write = spi_chip_write_256, /* Multi I/O supported */ - .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ - .voltage = {2700, 3600}, - }, - - { - .vendor = "SST", - .name = "SST25LF040A", - .bustype = BUS_SPI, - .manufacture_id = SST_ID, - .model_id = SST_SST25VF040_REMS, - .total_size = 512, - .page_size = 256, - .feature_bits = FEATURE_WRSR_EWSR, - .tested = TEST_OK_PREW, - .probe = probe_spi_res2, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {4 * 1024, 128} }, + .eraseblocks = { {4 * 1024, 128} }, .block_erase = spi_block_erase_20, }, { .eraseblocks = { {32 * 1024, 16} }, @@ -10216,517 +10448,6 @@ }, { - .vendor = "ST", - .name = "M25P05-A", - .bustype = BUS_SPI, - .manufacture_id = ST_ID, - .model_id = ST_M25P05A, - .total_size = 64, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PREW, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {32 * 1024, 2} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {64 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, - }, - - /* The ST M25P05 is a bit of a problem. It has the same ID as the - * ST M25P05-A in RES mode, but supports only 128 byte writes instead - * of 256 byte writes. We rely heavily on the fact that probe_spi_res1 - * only is successful if RDID does not work. - */ - { - .vendor = "ST", - .name = "M25P05", - .bustype = BUS_SPI, - .manufacture_id = 0, /* Not used. */ - .model_id = ST_M25P05_RES, - .total_size = 64, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, - .probe = probe_spi_res1, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {32 * 1024, 2} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {64 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_1, /* 128 */ - .read = spi_chip_read, - .voltage = {2700, 3600}, - }, - - { - .vendor = "ST", - .name = "M25P10-A", - .bustype = BUS_SPI, - .manufacture_id = ST_ID, - .model_id = ST_M25P10A, - .total_size = 128, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PRE, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {32 * 1024, 4} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {128 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, - }, - - /* The ST M25P10 has the same problem as the M25P05. */ - { - .vendor = "ST", - .name = "M25P10", - .bustype = BUS_SPI, - .manufacture_id = 0, /* Not used. */ - .model_id = ST_M25P10_RES, - .total_size = 128, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, - .probe = probe_spi_res1, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {32 * 1024, 4} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {128 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_1, /* 128 */ - .read = spi_chip_read, - .voltage = {2700, 3600}, - }, - - { - .vendor = "ST", /* Numonyx */ - .name = "M25P20", - .bustype = BUS_SPI, - .manufacture_id = ST_ID, - .model_id = ST_M25P20, - .total_size = 256, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {64 * 1024, 4} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {256 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_default_bp1, - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B) supported */ - .voltage = {2700, 3600}, - }, - - { - .vendor = "ST", - .name = "M25P20-old", - .bustype = BUS_SPI, - .manufacture_id = 0, /* Not used. */ - .model_id = ST_M25P20_RES, - .total_size = 256, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PREW, - .probe = probe_spi_res1, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {64 * 1024, 4} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {256 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_default_bp1, - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B) supported */ - .voltage = {2700, 3600}, - }, - - { - .vendor = "ST", /* Numonyx */ - .name = "M25P40", - .bustype = BUS_SPI, - .manufacture_id = ST_ID, - .model_id = ST_M25P40, - .total_size = 512, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PREW, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {64 * 1024, 8} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {512 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, - }, - - { - .vendor = "ST", - .name = "M25P40-old", - .bustype = BUS_SPI, - .manufacture_id = 0, /* Not used. */ - .model_id = ST_M25P40_RES, - .total_size = 512, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, - .probe = probe_spi_res1, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {64 * 1024, 8} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {512 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, - }, - - { - .vendor = "ST", - .name = "M25P80", - .bustype = BUS_SPI, - .manufacture_id = ST_ID, - .model_id = ST_M25P80, - .total_size = 1024, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PREW, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {64 * 1024, 16} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {1024 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, - }, - - { - .vendor = "ST", - .name = "M25P16", - .bustype = BUS_SPI, - .manufacture_id = ST_ID, - .model_id = ST_M25P16, - .total_size = 2048, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PR, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {64 * 1024, 32} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {2 * 1024 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, - }, - - { - .vendor = "ST", - .name = "M25P32", - .bustype = BUS_SPI, - .manufacture_id = ST_ID, - .model_id = ST_M25P32, - .total_size = 4096, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PREW, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {64 * 1024, 64} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {4 * 1024 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, - }, - - { - .vendor = "ST", - .name = "M25P64", - .bustype = BUS_SPI, - .manufacture_id = ST_ID, - .model_id = ST_M25P64, - .total_size = 8192, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PREW, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {64 * 1024, 128} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {8 * 1024 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, - }, - - { - .vendor = "ST", - .name = "M25P128", - .bustype = BUS_SPI, - .manufacture_id = ST_ID, - .model_id = ST_M25P128, - .total_size = 16384, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PREW, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {256 * 1024, 64} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {16 * 1024 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, - }, - - { - .vendor = "ST", - .name = "M25PX80", - .bustype = BUS_SPI, - .manufacture_id = ST_ID, - .model_id = ST_M25PX80, - .total_size = 1024, - .page_size = 256, - /* OTP: 64B total; read 0x4B, write 0x42 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_OK_PREW, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = { - { - .eraseblocks = { { 4 * 1024, 256 } }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {64 * 1024, 16} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {1024 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_default_bp2, /* bit5: T/B */ - .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: per 64kB sector lock registers */ - .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, - }, - - { - .vendor = "ST", - .name = "M25PX16", - .bustype = BUS_SPI, - .manufacture_id = ST_ID, - .model_id = ST_M25PX16, - .total_size = 2048, - .page_size = 256, - /* OTP: 64B total; read 0x4B; write 0x42 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_OK_PREW, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { { 4 * 1024, 512 } }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {64 * 1024, 32} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {2 * 1024 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_default_bp2, /* bit5: T/B */ - .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: per 64kB sector lock registers */ - .write = spi_chip_write_256, - .read = spi_chip_read, - }, - - { - .vendor = "ST", - .name = "M25PX32", - .bustype = BUS_SPI, - .manufacture_id = ST_ID, - .model_id = ST_M25PX32, - .total_size = 4096, - .page_size = 256, - /* OTP: 64B total; read 0x4B; write 0x42 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_OK_PRE, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { { 4 * 1024, 1024 } }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {64 * 1024, 64} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {4 * 1024 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_default_bp2, /* bit5: T/B */ - .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: per 64kB sector lock registers */ - .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, - }, - - { - .vendor = "ST", - .name = "M25PX64", - .bustype = BUS_SPI, - .manufacture_id = ST_ID, - .model_id = ST_M25PX64, - .total_size = 8192, - .page_size = 256, - /* OTP: 64B total; read 0x4B; write 0x42 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_OK_PRE, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { { 4 * 1024, 2048 } }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {64 * 1024, 128} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {8 * 1024 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .printlock = spi_prettyprint_status_register_default_bp2, /* bit5: T/B */ - .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: per 64kB sector lock registers */ - .write = spi_chip_write_256, - .read = spi_chip_read, - }, - - { .vendor = "ST", .name = "M29F002B", .bustype = BUS_PARALLEL,

1 0

[commit] r1702 - trunk
by repository service 26 Jul '13

26 Jul '13

Author: stefanct Date: Fri Jul 26 00:54:25 2013 New Revision: 1702 URL: http://flashrom.org/trac/flashrom/changeset/1702 Log: Add a bunch of new/tested stuff and various small changes 18. Tested mainboards: OK: - ASUS C60M1-I http://www.flashrom.org/pipermail/flashrom/2013-February/010578.html - ASUS P8H77-I http://www.flashrom.org/pipermail/flashrom/2013-March/010607.html - ASUS P8H77-M http://www.flashrom.org/pipermail/flashrom/2013-May/010994.html - ASUS P8P67 LE (B2) http://www.flashrom.org/pipermail/flashrom/2013-May/010972.html - Elitegroup GeForce6100PM-M2 (V3.0) http://www.flashrom.org/pipermail/flashrom/2013-July/011177.html - GIGABYTE GA-P55A-UD7 http://www.flashrom.org/pipermail/flashrom/2013-July/011302.html - MSI B75MA-E33 (MS-7808) http://www.flashrom.org/pipermail/flashrom/2013-March/010659.html - MSI H77MA-G43 (MS-7756) http://www.flashrom.org/pipermail/flashrom/2013-April/010853.html - MSI KA780G (MS-7551) http://paste.flashrom.org/view.php?id=1617 - SAPPHIRE IPC-E350M1 Reported by xvilka on IRC - Supermicro X8DTG-D http://www.flashrom.org/pipermail/flashrom/2013-July/011305.html NOT OK: - ASRock Fatal1ty Z77 Performance http://www.flashrom.org/pipermail/flashrom/2013-January/010467.html - ASRock Z68 Extreme4 http://www.flashrom.org/pipermail/flashrom/2013-May/010984.html - ASUS P8B75-M LE http://www.flashrom.org/pipermail/flashrom/2013-April/010867.html - ASUS P8P67-M PRO http://www.flashrom.org/pipermail/flashrom/2013-February/010541.html - ASUS P8Z68-V LE http://www.flashrom.org/pipermail/flashrom/2013-February/010582.html - Intel DQ77MK http://paste.flashrom.org/view.php?id=1603 - Supermicro X9DRD-7LN4F http://paste.flashrom.org/view.php?id=1582 - Supermicro X9SCE-F http://www.flashrom.org/pipermail/flashrom/2013-February/010588.html - Supermicro X9SCM-F http://www.flashrom.org/pipermail/flashrom/2013-February/010527.html - Tyan S7066 http://www.flashrom.org/pipermail/flashrom/2013-March/010630.html Chipsets: - Marked Intel B75 as tested http://www.flashrom.org/pipermail/flashrom/2013-March/010659.html - Marked Intel H77 as tested http://www.flashrom.org/pipermail/flashrom/2013-March/010607.html - Removed 10de:03e2 because it is apparently the MCP61 host bridge. It was reclassified to Host Bridge in the PCI device ID database and there is at least one report suggesting this configuration too: http://www.flashrom.org/pipermail/flashrom/2012-August/009716.html - Added MCP89 which hopefully works with the code for previous versions. Thanks to James Laird for submitting this change. Tested flash chips: - Atmel AT25DF641(A) to PREW (+PREW) http://www.flashrom.org/pipermail/flashrom/2013-June/011113.html - Atmel AT25F512 to PREW (+PREW) http://www.flashrom.org/pipermail/flashrom/2013-April/010904.html Also, change its ID according to Modification of PCN SC040401A: "There has been a change in the returned value of the Product Identification (RDID) command, the AT25F512A RDID code is 65h compared to 60h from the AT25F512 product." It seems to be quite likely that all AT25F512 are fully functional relabeled AT25F1024 chips. There are even some hints in the datasheet: in table 6 they stress that address pin 16 needs to be low under all circum- stances; while continuous reads can wrap around on the AT25F1024 the DS notes "For the AT25F512, the read command must be terminated when the highest address (00FFFF) is reached." OTOH the lock bit semantics are different, but this has not been tested thoroughly - Atmel AT25F512A to PREW (+PREW) http://paste.flashrom.org/view.php?id=1569 - Eon EN25F05 to PREW (+PREW) http://paste.flashrom.org/view.php?id=1571 - Macronix MX25L12805(D) to PREW (+REW) http://www.flashrom.org/pipermail/flashrom/2013-April/010913.html - Spansion S25FL256S......0 and S25FL512S to P/!R!E!W (+P) Tested by Stefan Tauner - Micron/Numonyx/ST M25PX80 to PREW (+PREW) Tested by Stefan Tauner - Micron/Numonyx/ST N25Q032..3E and N25Q128..3E to PREW (+PREW) Tested by Stefan Tauner - Micron/Numonyx/ST N25Q256..3E and N25Q512..3G to P/!R!E!W (+P) Tested by Stefan Tauner - SST SST25VF040B to PREW (+PREW) http://paste.flashrom.org/view.php?id=1574 - SST SST25VF040B.REMS to PREW (+EW) http://paste.flashrom.org/view.php?id=1575 - ST M25P05-A to PREW (+PREW) http://paste.flashrom.org/view.php?id=1576 - ST M29W512B to PREW (+W) http://www.flashrom.org/pipermail/flashrom/2013-March/010635.html - Winbond W25Q64.W to PREW (+PREW) Tested by the chromiumos guys. - Winbond W25Q128.V to PREW (+REW) http://www.flashrom.org/pipermail/flashrom/2013-June/011108.html - Winbond W25X20 to PREW (+PREW) http://www.flashrom.org/pipermail/flashrom/2013-May/010990.html Miscellaneous: - Add Lenovo X201 to the laptop whitelist. - Add chip IDs for the ESMT F25L..QA family. - Add chip IDs for a few Macronix MX25 models. - The list of flashchips is not sorted strictly alphabetically and should not be either. Refine the comment explaining the scheme on top of the list. - Support -L output of chip sizes with up to 6 decimal places (up to 4 Gb). - Use z length modifier in (more) prints for size_t types. - Remove chips >16MB again because our current implementation of memory mapping the flash chip violates common rules by mapping a window as large as the chip. This leads to failing mmaps as can be seen here: http://paste.flashrom.org/view.php?id=1695 - Document spispeed parameter of linux_spi (and fix some leaks). - Rephrase the "multiple chips detected" message because it was confusing. - Skip verification step if the image is equal to the flash contents. - Tiny other stuff. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Most parts are also Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c trunk/chipset_enable.c trunk/cli_classic.c trunk/cli_output.c trunk/dummyflasher.c trunk/flash.h trunk/flashchips.c trunk/flashchips.h trunk/flashrom.8 trunk/flashrom.c trunk/hwaccess.h trunk/ich_descriptors.c trunk/jedec.c trunk/linux_spi.c trunk/physmap.c trunk/print.c trunk/serprog.c trunk/spi25_statusreg.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Thu Jul 18 01:46:44 2013 (r1701) +++ trunk/board_enable.c Fri Jul 26 00:54:25 2013 (r1702) @@ -2415,6 +2415,7 @@ {0x8086, 0x27a0, 0x17aa, 0x2015, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "Lenovo", "T60", 0, OK, p2_whitelist_laptop}, {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "Lenovo", "T60(s)", 0, OK, p2_whitelist_laptop}, {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad X60", NULL, NULL, P2, "Lenovo", "X60(s)", 0, OK, p2_whitelist_laptop}, + {0x8086, 0x3B07, 0x17AA, 0x2166, 0x8086, 0x3B30, 0x17AA, 0x2167, "^Lenovo X201", NULL, NULL, P2, "Lenovo", "X201", 0, OK, p2_whitelist_laptop}, {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, {0x8086, 0x8186, 0x8086, 0x8186, 0x8086, 0x8800, 0, 0, "^MSC Vertriebs GmbH$", NULL, NULL, P2, "MSC", "Q7-TCTC", 0, OK, p2_not_a_laptop}, {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, P3, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, /* TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html. */ Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Thu Jul 18 01:46:44 2013 (r1701) +++ trunk/chipset_enable.c Fri Jul 26 00:54:25 2013 (r1702) @@ -1366,7 +1366,6 @@ {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */ {0x10de, 0x03e0, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, {0x10de, 0x03e1, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, - {0x10de, 0x03e2, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, {0x10de, 0x0440, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, {0x10de, 0x0441, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, @@ -1380,6 +1379,7 @@ {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, + {0x10de, 0x0d80, NT, "NVIDIA", "MCP89", enable_flash_mcp6x_7x}, /* VIA northbridges */ {0x1106, 0x0585, NT, "VIA", "VT82C585VPX", via_no_byte_merge}, {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge}, @@ -1428,8 +1428,8 @@ {0x8086, 0x1e46, NT, "Intel", "Z75", enable_flash_pch7}, {0x8086, 0x1e47, NT, "Intel", "Q77", enable_flash_pch7}, {0x8086, 0x1e48, NT, "Intel", "Q75", enable_flash_pch7}, - {0x8086, 0x1e49, NT, "Intel", "B75", enable_flash_pch7}, - {0x8086, 0x1e4a, NT, "Intel", "H77", enable_flash_pch7}, + {0x8086, 0x1e49, OK, "Intel", "B75", enable_flash_pch7}, + {0x8086, 0x1e4a, OK, "Intel", "H77", enable_flash_pch7}, {0x8086, 0x1e53, NT, "Intel", "C216", enable_flash_pch7}, {0x8086, 0x1e55, OK, "Intel", "QM77", enable_flash_pch7}, {0x8086, 0x1e56, NT, "Intel", "QS77", enable_flash_pch7}, Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Thu Jul 18 01:46:44 2013 (r1701) +++ trunk/cli_classic.c Fri Jul 26 00:54:25 2013 (r1702) @@ -435,10 +435,11 @@ } if (chipcount > 1) { - msg_cinfo("Multiple flash chips were detected: \"%s\"", flashes[0].chip->name); + msg_cinfo("Multiple flash chip definitions match the detected chip(s): \"%s\"", + flashes[0].chip->name); for (i = 1; i < chipcount; i++) msg_cinfo(", \"%s\"", flashes[i].chip->name); - msg_cinfo("\nPlease specify which chip to use with the -c <chipname> option.\n"); + msg_cinfo("\nPlease specify which chip definition to use with the -c <chipname> option.\n"); ret = 1; goto out_shutdown; } else if (!chipcount) { Modified: trunk/cli_output.c ============================================================================== --- trunk/cli_output.c Thu Jul 18 01:46:44 2013 (r1701) +++ trunk/cli_output.c Fri Jul 26 00:54:25 2013 (r1702) @@ -46,7 +46,7 @@ int open_logfile(const char * const filename) { if (!filename) { - msg_gerr("No filename specified.\n"); + msg_gerr("No logfile name specified.\n"); return 1; } if ((logfile = fopen(filename, "w")) == NULL) { Modified: trunk/dummyflasher.c ============================================================================== --- trunk/dummyflasher.c Thu Jul 18 01:46:44 2013 (r1701) +++ trunk/dummyflasher.c Fri Jul 26 00:54:25 2013 (r1702) @@ -414,15 +414,14 @@ void *dummy_map(const char *descr, uintptr_t phys_addr, size_t len) { - msg_pspew("%s: Mapping %s, 0x%lx bytes at 0x%*" PRIxPTR "\n", - __func__, descr, (unsigned long)len, PRIxPTR_WIDTH, phys_addr); + msg_pspew("%s: Mapping %s, 0x%zx bytes at 0x%*" PRIxPTR "\n", + __func__, descr, len, PRIxPTR_WIDTH, phys_addr); return (void *)phys_addr; } void dummy_unmap(void *virt_addr, size_t len) { - msg_pspew("%s: Unmapping 0x%lx bytes at %p\n", - __func__, (unsigned long)len, virt_addr); + msg_pspew("%s: Unmapping 0x%zx bytes at %p\n", __func__, len, virt_addr); } static void dummy_chip_writeb(const struct flashctx *flash, uint8_t val, @@ -447,8 +446,7 @@ chipaddr addr, size_t len) { size_t i; - msg_pspew("%s: addr=0x%" PRIxPTR ", len=0x%08lx, writing data (hex):", - __func__, addr, (unsigned long)len); + msg_pspew("%s: addr=0x%" PRIxPTR ", len=0x%zx, writing data (hex):", __func__, addr, len); for (i = 0; i < len; i++) { if ((i % 16) == 0) msg_pspew("\n"); @@ -480,8 +478,7 @@ static void dummy_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len) { - msg_pspew("%s: addr=0x%" PRIxPTR ", len=0x%lx, returning array of 0xff\n", - __func__, addr, (unsigned long)len); + msg_pspew("%s: addr=0x%" PRIxPTR ", len=0x%zx, returning array of 0xff\n", __func__, addr, len); memset(buf, 0xff, len); return; } Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Thu Jul 18 01:46:44 2013 (r1701) +++ trunk/flash.h Fri Jul 26 00:54:25 2013 (r1702) @@ -93,6 +93,7 @@ */ #define NUM_ERASEFUNCTIONS 6 +/* Feature bits used for non-SPI only */ #define FEATURE_REGISTERMAP (1 << 0) #define FEATURE_BYTEWRITES (1 << 1) #define FEATURE_LONG_RESET (0 << 4) @@ -104,11 +105,12 @@ #define FEATURE_ADDR_2AA (1 << 2) #define FEATURE_ADDR_AAA (2 << 2) #define FEATURE_ADDR_SHIFTED (1 << 5) +/* Feature bits used for SPI only */ #define FEATURE_WRSR_EWSR (1 << 6) #define FEATURE_WRSR_WREN (1 << 7) +#define FEATURE_WRSR_EITHER (FEATURE_WRSR_EWSR | FEATURE_WRSR_WREN) #define FEATURE_OTP (1 << 8) #define FEATURE_QPI (1 << 9) -#define FEATURE_WRSR_EITHER (FEATURE_WRSR_EWSR | FEATURE_WRSR_WREN) struct flashctx; typedef int (erasefunc_t)(struct flashctx *flash, unsigned int addr, unsigned int blocklen); Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Thu Jul 18 01:46:44 2013 (r1701) +++ trunk/flashchips.c Fri Jul 26 00:54:25 2013 (r1702) @@ -29,8 +29,8 @@ /** * List of supported flash chips. * - * Please keep the list sorted by vendor name and chip name, so that - * the output of 'flashrom -L' is alphabetically sorted. + * Please keep the list sorted by vendor name and chip family, so that the output of 'flashrom -L' is roughly + * alphabetically sorted. Within families keep them in order of density. */ const struct flashchip flashchips[] = { @@ -1297,7 +1297,7 @@ .block_erasers = { { - .eraseblocks = { + .eraseblocks = { {16 * 1024, 1}, {8 * 1024, 2}, {32 * 1024, 1}, @@ -1329,7 +1329,7 @@ .block_erasers = { { - .eraseblocks = { + .eraseblocks = { {64 * 1024, 3}, {32 * 1024, 1}, {8 * 1024, 2}, @@ -1678,7 +1678,7 @@ .total_size = 8192, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -1755,7 +1755,7 @@ .total_size = 64, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_at25f, .probe_timing = TIMING_ZERO, .block_erasers = @@ -1784,7 +1784,7 @@ .total_size = 64, .page_size = 128, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_at25f, .probe_timing = TIMING_ZERO, .block_erasers = @@ -2809,7 +2809,7 @@ .block_erasers = { { - .eraseblocks = { + .eraseblocks = { {128 * 1024, 1}, {96 * 1024, 1}, {8 * 1024, 2}, @@ -3426,7 +3426,7 @@ .total_size = 64, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -4503,7 +4503,7 @@ .block_erasers = { { - .eraseblocks = { + .eraseblocks = { {16 * 1024, 1}, {8 * 1024, 2}, {32 * 1024, 1}, @@ -4535,7 +4535,7 @@ .block_erasers = { { - .eraseblocks = { + .eraseblocks = { {64 * 1024, 7}, {32 * 1024, 1}, {8 * 1024, 2}, @@ -4568,7 +4568,7 @@ .block_erasers = { { - .eraseblocks = { + .eraseblocks = { {16 * 1024, 1}, {8 * 1024, 2}, {32 * 1024, 1}, @@ -4600,7 +4600,7 @@ .block_erasers = { { - .eraseblocks = { + .eraseblocks = { {64 * 1024, 7}, {32 * 1024, 1}, {8 * 1024, 2}, @@ -5375,7 +5375,7 @@ .block_erasers = { { - .eraseblocks = { + .eraseblocks = { {8 * 1024, 1}, {4 * 1024, 2}, {112 * 1024, 1}, @@ -5479,7 +5479,7 @@ .block_erasers = { { - .eraseblocks = { + .eraseblocks = { {16 * 1024, 1}, {8 * 1024, 2}, {96 * 1024, 1}, @@ -5506,7 +5506,7 @@ .block_erasers = { { - .eraseblocks = { + .eraseblocks = { {128 * 1024, 3}, {96 * 1024, 1}, {8 * 1024, 2}, @@ -5534,7 +5534,7 @@ .block_erasers = { { - .eraseblocks = { + .eraseblocks = { {16 * 1024, 1}, {8 * 1024, 2}, {96 * 1024, 1}, @@ -5562,7 +5562,7 @@ .block_erasers = { { - .eraseblocks = { + .eraseblocks = { {128 * 1024, 3}, {96 * 1024, 1}, {8 * 1024, 2}, @@ -6263,7 +6263,7 @@ .page_size = 256, /* MX25L12805D has 64B of OTP; enter 0xB1, exit 0xC1 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_OK_PROBE, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -6429,7 +6429,7 @@ .block_erasers = { { - .eraseblocks = { + .eraseblocks = { {8 * 1024, 1}, {4 * 1024, 2}, {8 * 1024, 2}, @@ -6462,7 +6462,7 @@ .block_erasers = { { - .eraseblocks = { + .eraseblocks = { {64 * 1024, 1}, {32 * 1024, 1}, {8 * 1024, 2}, @@ -7360,7 +7360,7 @@ /* supports SFDP */ /* OTP: 64B total; read 0x4B, write 0x42 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -7495,7 +7495,7 @@ /* supports SFDP */ /* OTP: 64B total; read 0x4B, write 0x42 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -7561,7 +7561,7 @@ /* supports SFDP */ /* OTP: 64B total; read 0x4B, write 0x42 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_BAD_REW, + .tested = TEST_OK_PROBE | TEST_BAD_REW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -7621,7 +7621,7 @@ { .vendor = "Numonyx", - .name = "N25Q512..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ + .name = "N25Q512..3G", /* ..3G = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, .model_id = ST_N25Q512__3E, @@ -7630,7 +7630,7 @@ /* supports SFDP */ /* OTP: 64B total; read 0x4B, write 0x42 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_BAD_REW, + .tested = TEST_OK_PROBE | TEST_BAD_REW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -8874,7 +8874,7 @@ /* supports 4B addressing */ /* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_BAD_REW, + .tested = TEST_OK_PROBE | TEST_BAD_REW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -8911,7 +8911,7 @@ /* supports SFDP */ /* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_BAD_REW, + .tested = TEST_OK_PROBE | TEST_BAD_REW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -9184,7 +9184,7 @@ .total_size = 512, .page_size = 256, .feature_bits = FEATURE_WRSR_EWSR, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -9222,7 +9222,7 @@ .total_size = 512, .page_size = 256, .feature_bits = FEATURE_WRSR_EWSR, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_spi_rems, .probe_timing = TIMING_ZERO, .block_erasers = @@ -9470,7 +9470,7 @@ .feature_bits = FEATURE_LONG_RESET, .tested = TEST_OK_PR, .probe = probe_jedec, - .probe_timing = 10, + .probe_timing = 10, .block_erasers = { { @@ -9494,7 +9494,7 @@ .feature_bits = FEATURE_LONG_RESET, .tested = TEST_UNTESTED, .probe = probe_jedec, - .probe_timing = 10, + .probe_timing = 10, .block_erasers = { { @@ -9542,7 +9542,7 @@ .feature_bits = FEATURE_LONG_RESET, .tested = TEST_OK_PRE, .probe = probe_jedec, - .probe_timing = 10, + .probe_timing = 10, .block_erasers = { { @@ -9918,7 +9918,7 @@ .eraseblocks = { {4 * 1024, 128} }, .block_erase = erase_sector_49lfxxxc, }, { - .eraseblocks = { + .eraseblocks = { {64 * 1024, 7}, {32 * 1024, 1}, {8 * 1024, 2}, @@ -9983,7 +9983,7 @@ .eraseblocks = { {4 * 1024, 256} }, .block_erase = erase_sector_49lfxxxc, }, { - .eraseblocks = { + .eraseblocks = { {64 * 1024, 15}, {32 * 1024, 1}, {8 * 1024, 2}, @@ -10016,7 +10016,7 @@ .eraseblocks = { {4 * 1024, 512} }, .block_erase = erase_sector_49lfxxxc, }, { - .eraseblocks = { + .eraseblocks = { {64 * 1024, 31}, {32 * 1024, 1}, {8 * 1024, 2}, @@ -10163,7 +10163,7 @@ .feature_bits = FEATURE_EITHER_RESET, .tested = TEST_OK_PREW, .probe = probe_jedec, - .probe_timing = TIMING_FIXME, + .probe_timing = TIMING_FIXME, .block_erasers = { { @@ -10200,7 +10200,7 @@ .eraseblocks = { {4 * 1024, 512} }, .block_erase = erase_sector_49lfxxxc, }, { - .eraseblocks = { + .eraseblocks = { {64 * 1024, 31}, {32 * 1024, 1}, {8 * 1024, 2}, @@ -10224,7 +10224,7 @@ .total_size = 64, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -10607,7 +10607,7 @@ .page_size = 256, /* OTP: 64B total; read 0x4B, write 0x42 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -10945,7 +10945,7 @@ .total_size = 64, .page_size = 64 * 1024, .feature_bits = FEATURE_ADDR_2AA | FEATURE_EITHER_RESET, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = TIMING_ZERO, .block_erasers = @@ -11677,7 +11677,7 @@ /* supports SFDP */ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_OK_PROBE, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -11914,7 +11914,7 @@ /* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ /* QPI enable 0x38, disable 0xFF */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -11984,7 +11984,7 @@ .total_size = 256, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -12266,7 +12266,7 @@ .feature_bits = FEATURE_LONG_RESET, .tested = TEST_UNTESTED, .probe = probe_jedec, - .probe_timing = 10, + .probe_timing = 10, .block_erasers = { { @@ -12524,7 +12524,7 @@ .feature_bits = FEATURE_REGISTERMAP | FEATURE_EITHER_RESET, .tested = TEST_OK_PREW, .probe = probe_jedec, - .probe_timing = 10, + .probe_timing = 10, .block_erasers = { { Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Thu Jul 18 01:46:44 2013 (r1701) +++ trunk/flashchips.h Fri Jul 26 00:54:25 2013 (r1702) @@ -141,7 +141,7 @@ #define ATMEL_AT25DL161 0x4603 /* EDI 0x0100 */ #define ATMEL_AT25DQ161 0x8600 /* EDI 0x0100 */ #define ATMEL_AT25DQ321 0x8700 /* EDI 0x0100 */ -#define ATMEL_AT25F512 0x65 /* guessed, no device ID in datasheet. Needs AT25F_RDID */ +#define ATMEL_AT25F512 0x60 /* Needs AT25F_RDID. ID from PCN and actual HW. Seems to be a relabeled AT25F1024. */ #define ATMEL_AT25F512A 0x65 /* Needs AT25F_RDID */ #define ATMEL_AT25F512B 0x6500 #define ATMEL_AT25F1024 0x60 /* Needs AT25F_RDID */ @@ -208,6 +208,11 @@ #define ESMT_ID 0x8C /* Elite Semiconductor Memory Technology (ESMT) / EFST Elite Flash Storage */ #define ESMT_F25L008A 0x2014 #define ESMT_F25D08QA 0x2534 +#define ESMT_F25L16QA2S 0x4015 +#define ESMT_F25L32QA 0x4016 +#define ESMT_F25L32QA2S 0x4116 +#define ESMT_F25L64QA 0x4117 +#define ESMT_F25L128QA 0x4118 #define ESMT_F49B002UA 0x00 /* @@ -271,6 +276,8 @@ #define EON_EN25S16 0x3815 #define EON_EN25S32 0x3816 #define EON_EN25S64 0x3817 +#define EON_EN25T80 0x5114 +#define EON_EN25T16 0x5115 #define EON_EN29F512 0x7F21 #define EON_EN29F010 0x20 #define EON_EN29F040A 0x7F04 @@ -280,6 +287,12 @@ #define EON_EN29F002T 0x7F92 /* Same as EN29F002A */ #define EON_EN29F002B 0x7F97 /* Same as EN29F002AN */ +#define EXCEL_ID 0x7F7F7F7F4A /* Excel Semiconductor Inc. (ESI) resides in bank 5 */ +#define EXCEL_ID_NOPREFIX 0x4A /* ESI, missing 0x7F prefix */ +#define EXCEL_ES25P40 0x2013 +#define EXCEL_ES25P80 0x2014 +#define EXCEL_ES25P16 0x2015 + #define FIDELIX_ID 0xF8 /* Fidelix */ #define FIDELIX_FM25M16 0x4215 #define FIDELIX_FM25M32 0x4216 @@ -423,11 +436,14 @@ #define MACRONIX_MX25L3205 0x2016 /* MX25L3205, MX25L3205A (64k 0x20); MX25L3205D/MX25L3208D (4k 0x20); MX25L3206E (4k 0x20, 64k 0x52) */ #define MACRONIX_MX25L6405 0x2017 /* MX25L6405, MX25L6405D (64k 0x20); MX25L6406E/MX25L6436E (4k 0x20); MX25L6445E (4k 0x20, 64k 0x52) */ #define MACRONIX_MX25L12805 0x2018 /* Same as MX25L12805D */ +#define MACRONIX_MX25L25635F 0x2019 /* Same as MX25L25639F, but the latter seems to not support REMS */ #define MACRONIX_MX25L1635D 0x2415 #define MACRONIX_MX25L1635E 0x2515 /* MX25L1635{E} */ #define MACRONIX_MX25U1635E 0x2535 #define MACRONIX_MX25U3235E 0x2536 /* Same as MX25U6435F */ #define MACRONIX_MX25U6435E 0x2537 /* Same as MX25U6435F */ +#define MACRONIX_MX25U12835E 0x2538 /* Same as MX25U12835F */ +#define MACRONIX_MX25U25635F 0x2539 #define MACRONIX_MX25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */ #define MACRONIX_MX29F001B 0x19 #define MACRONIX_MX29F001T 0x18 Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Thu Jul 18 01:46:44 2013 (r1701) +++ trunk/flashrom.8 Fri Jul 26 00:54:25 2013 (r1702) @@ -1,4 +1,4 @@ -.TH FLASHROM 8 "Dec, 2012" +.TH FLASHROM 8 "Jul, 2013" .SH NAME flashrom \- detect, read, write, verify and erase flash chips .SH SYNOPSIS @@ -590,7 +590,9 @@ is the serial number of the device (which can be found for example in the output of lsusb -v). .sp All models supported by the ft2232_spi driver can configure the SPI clock rate by setting a divisor. The -expressible divisors are all even numbers between 2 and 2^17 (=131072) resulting in SPI clock frequencies of +expressible divisors are all +.B even +numbers between 2 and 2^17 (=131072) resulting in SPI clock frequencies of 6 MHz down to about 92 Hz for 12 MHz inputs. The default divisor is set to 2, but you can use another one by specifying the optional .B divisor @@ -615,12 +617,12 @@ instead. In case the device supports it, you can set the SPI clock frequency with the optional .B spispeed -parameter. The frequency is parsed as Hertz, unless an +parameter. The frequency is parsed as hertz, unless an .BR M ", or " k suffix is given, then megahertz or kilohertz are used respectively. Example that sets the frequency to 2 MHz: .sp -.B "flashrom \-p serprog:dev=/dev/device:baud,spispeed=2M" +.B " flashrom \-p serprog:dev=/dev/device:baud,spispeed=2M" .sp More information about serprog is available in .B serprog-protocol.txt @@ -797,6 +799,13 @@ .B /dev/spidevX.Y is the Linux device node for your SPI controller. .sp +In case the device supports it, you can set the SPI clock frequency with the optional +.B spispeed +parameter. The frequency is parsed as kilohertz. +Example that sets the frequency to 8 MHz: +.sp +.B " flashrom \-p linux_spi:dev=/dev/spidevX.Y,spispeed=8000" +.sp Please note that the linux_spi driver only works on Linux. .SH EXAMPLES To back up and update your BIOS, run Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Thu Jul 18 01:46:44 2013 (r1701) +++ trunk/flashrom.c Fri Jul 26 00:54:25 2013 (r1702) @@ -1995,7 +1995,7 @@ } } - if (verify_it) { + if (verify_it && !all_skipped) { msg_cinfo("Verifying flash... "); if (write_it) { Modified: trunk/hwaccess.h ============================================================================== --- trunk/hwaccess.h Thu Jul 18 01:46:44 2013 (r1701) +++ trunk/hwaccess.h Fri Jul 26 00:54:25 2013 (r1702) @@ -240,19 +240,19 @@ #if defined(__i386__) || defined(__x86_64__) #include <sys/types.h> #include <machine/sysarch.h> -#if defined(__NetBSD__) - #if defined(__i386__) - #define iopl i386_iopl - #elif defined(__x86_64__) - #define iopl x86_64_iopl + #if defined(__NetBSD__) + #if defined(__i386__) + #define iopl i386_iopl + #elif defined(__x86_64__) + #define iopl x86_64_iopl + #endif + #elif defined (__OpenBSD__) + #if defined(__i386__) + #define iopl i386_iopl + #elif defined(__amd64__) + #define iopl amd64_iopl + #endif #endif -#elif defined (__OpenBSD__) - #if defined(__i386__) - #define iopl i386_iopl - #elif defined(__amd64__) - #define iopl amd64_iopl - #endif -#endif static inline void outb(uint8_t value, uint16_t port) { Modified: trunk/ich_descriptors.c ============================================================================== --- trunk/ich_descriptors.c Thu Jul 18 01:46:44 2013 (r1701) +++ trunk/ich_descriptors.c Fri Jul 26 00:54:25 2013 (r1702) @@ -188,12 +188,12 @@ nr); return; } - for (i = 0; i <= nr; i++) + for (i = 0; i < 5; i++) msg_pdbg2("FLREG%d 0x%08x\n", i, desc->region.FLREGs[i]); msg_pdbg2("\n"); msg_pdbg2("--- Details ---\n"); - for (i = 0; i <= nr; i++) + for (i = 0; i < 5; i++) pprint_freg(&desc->region, i); msg_pdbg2("\n"); } @@ -805,7 +805,7 @@ __func__, nr); return ICH_RET_ERR; } - for (i = 0; i <= nr; i++) + for (i = 0; i < 5; i++) desc->region.FLREGs[i] = read_descriptor_reg(2, i, spibar); /* master section */ Modified: trunk/jedec.c ============================================================================== --- trunk/jedec.c Thu Jul 18 01:46:44 2013 (r1701) +++ trunk/jedec.c Fri Jul 26 00:54:25 2013 (r1702) @@ -381,8 +381,8 @@ return failed; } -int write_page_write_jedec_common(struct flashctx *flash, uint8_t *src, - unsigned int start, unsigned int page_size) +static int write_page_write_jedec_common(struct flashctx *flash, uint8_t *src, + unsigned int start, unsigned int page_size) { int i, tried = 0, failed; uint8_t *s = src; Modified: trunk/linux_spi.c ============================================================================== --- trunk/linux_spi.c Thu Jul 18 01:46:44 2013 (r1701) +++ trunk/linux_spi.c Fri Jul 26 00:54:25 2013 (r1702) @@ -66,28 +66,33 @@ const uint8_t mode = SPI_MODE_0; const uint8_t bits = 8; - dev = extract_programmer_param("dev"); - if (!dev || !strlen(dev)) { - msg_perr("No SPI device given. Use flashrom -p " - "linux_spi:dev=/dev/spidevX.Y\n"); - return 1; - } - - p = extract_programmer_param("speed"); + p = extract_programmer_param("spispeed"); if (p && strlen(p)) { speed = (uint32_t)strtoul(p, &endp, 10) * 1024; if (p == endp) { msg_perr("%s: invalid clock: %s kHz\n", __func__, p); + free(p); return 1; } } + free(p); + + dev = extract_programmer_param("dev"); + if (!dev || !strlen(dev)) { + msg_perr("No SPI device given. Use flashrom -p " + "linux_spi:dev=/dev/spidevX.Y\n"); + free(dev); + return 1; + } msg_pdbg("Using device %s\n", dev); if ((fd = open(dev, O_RDWR)) == -1) { msg_perr("%s: failed to open %s: %s\n", __func__, dev, strerror(errno)); + free(dev); return 1; } + free(dev); if (register_shutdown(linux_spi_shutdown, NULL)) return 1; Modified: trunk/physmap.c ============================================================================== --- trunk/physmap.c Thu Jul 18 01:46:44 2013 (r1701) +++ trunk/physmap.c Fri Jul 26 00:54:25 2013 (r1702) @@ -220,13 +220,13 @@ } if ((getpagesize() - 1) & len) { - msg_perr("Mapping %s at 0x%0*" PRIxPTR ", unaligned size 0x%lx.\n", - descr, PRIxPTR_WIDTH, phys_addr, (unsigned long)len); + msg_perr("Mapping %s at 0x%0*" PRIxPTR ", unaligned size 0x%zx.\n", + descr, PRIxPTR_WIDTH, phys_addr, len); } if ((getpagesize() - 1) & phys_addr) { - msg_perr("Mapping %s, 0x%lx bytes at unaligned 0x%0*" PRIxPTR ".\n", - descr, (unsigned long)len, PRIxPTR_WIDTH, phys_addr); + msg_perr("Mapping %s, 0x%zx bytes at unaligned 0x%0*" PRIxPTR ".\n", + descr, len, PRIxPTR_WIDTH, phys_addr); } if (readonly) @@ -237,8 +237,8 @@ if (ERROR_PTR == virt_addr) { if (NULL == descr) descr = "memory"; - msg_perr("Error accessing %s, 0x%lx bytes at 0x%0*" PRIxPTR "\n", - descr, (unsigned long)len, PRIxPTR_WIDTH, phys_addr); + msg_perr("Error accessing %s, 0x%zx bytes at 0x%0*" PRIxPTR "\n", + descr, len, PRIxPTR_WIDTH, phys_addr); msg_perr(MEM_DEV " mmap failed: %s\n", strerror(errno)); #ifdef __linux__ if (EINVAL == errno) { Modified: trunk/print.c ============================================================================== --- trunk/print.c Thu Jul 18 01:46:44 2013 (r1701) +++ trunk/print.c Fri Jul 26 00:54:25 2013 (r1702) @@ -160,7 +160,7 @@ msg_ginfo("Known"); for (i = 0; i < border; i++) msg_ginfo(" "); - msg_ginfo(" Size"); + msg_ginfo(" Size "); for (i = 0; i < border; i++) msg_ginfo(" "); @@ -178,7 +178,7 @@ msg_ginfo("Broken"); for (i = 0; i < border; i++) msg_ginfo(" "); - msg_ginfo("[kB]"); + msg_ginfo("[kB] "); for (i = 0; i < border + maxtypelen; i++) msg_ginfo(" "); msg_gdbg("range [V]"); @@ -287,7 +287,7 @@ for (i = 0; i < border + 1; i++) msg_ginfo(" "); - msg_ginfo("%5d", chip->total_size); + msg_ginfo("%6d", chip->total_size); for (i = 0; i < border; i++) msg_ginfo(" "); @@ -565,9 +565,10 @@ B("ASRock", "A780FullHD", OK, "http://www.asrock.com/mb/overview.asp?Model=A780FullHD", "While flashrom is working correctly, there might be problems with the firmware images themselves. Please see http://www.flashrom.org/pipermail/flashrom/2012-July/009600.html for details."), B("ASRock", "ALiveNF6G-DVI", OK, "http://www.asrock.com/mb/overview.asp?Model=ALiveNF6G-DVI", NULL), B("ASRock", "AM2NF6G-VSTA", OK, "http://www.asrock.com/mb/overview.asp?Model=AM2NF6G-VSTA", NULL), + B("ASRock", "ConRoeXFire-eSATA2", OK, "http://www.asrock.com/mb/overview.asp?model=conroexfire-esata2", NULL), B("ASRock", "E350M1/USB3", OK, "http://www.asrock.com/mb/overview.asp?model=e350m1/usb3", NULL), + B("ASRock", "Fatal1ty Z77 Performance", BAD, "http://www.asrock.com/mb/overview.asp?Model=Fatal1ty%20Z77%20Performance", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASRock", "G31M-S rev 2.0", OK, "http://www.asrock.com/mb/overview.asp?model=G31M-S", NULL), - B("ASRock", "ConRoeXFire-eSATA2", OK, "http://www.asrock.com/mb/overview.asp?model=conroexfire-esata2", NULL), B("ASRock", "H61M-ITX", BAD, "http://www.asrock.com/mb/overview.asp?Model=H61M-ITX", "Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASRock", "H67M", BAD, "http://www.asrock.com/mb/overview.asp?Model=H67M", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASRock", "K7S41", OK, "http://www.asrock.com/mb/overview.asp?Model=K7S41", NULL), @@ -577,6 +578,7 @@ B("ASRock", "M3A790GXH/128M", OK, "http://www.asrock.com/mb/overview.asp?Model=M3A790GXH/128M", NULL), B("ASRock", "N61P-S", OK, "http://www.asrock.com/mb/overview.asp?Model=N61P-S", NULL), B("ASRock", "P4i65GV", OK, "http://www.asrock.com/mb/overview.asp?Model=P4i65GV", NULL), + B("ASRock", "Z68 Extreme4", BAD, "http://www.asrock.com/mb/overview.asp?Model=Z68%20Extreme4", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "A7N8X Deluxe", OK, "http://www.asus.com/Motherboards/AMD_Socket_A/A7N8X_Deluxe/", NULL), B("ASUS", "A7N8X-E Deluxe", OK, "http://www.asus.com/Motherboards/AMD_Socket_A/A7N8XE_Deluxe/", NULL), B("ASUS", "A7N8X-VM/400", OK, "http://www.asus.com/Motherboards/AMD_Socket_A/A7N8XVM400/", NULL), @@ -600,6 +602,7 @@ B("ASUS", "A8V Deluxe", OK, "http://www.asus.com/Motherboards/AMD_Socket_939/A8V_Deluxe/", NULL), B("ASUS", "A8V-E Deluxe", OK, "http://www.asus.com/Motherboards/AMD_Socket_939/A8VE_Deluxe/", NULL), B("ASUS", "A8V-E SE", OK, "http://www.asus.com/Motherboards/AMD_Socket_939/A8VE_SE/", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html"), + B("ASUS", "C60M1-I", OK, "http://www.asus.com/Motherboards/C60M1I/", "The MAC address of the onboard network card is stored in flash."), B("ASUS", "Crosshair II Formula", OK, "http://www.asus.com/Motherboards/AMD_AM2Plus/Crosshair_II_Formula/", NULL), B("ASUS", "Crosshair IV Extreme", OK, "http://www.asus.com/Motherboards/AMD_AM3/Crosshair_IV_Extreme/", NULL), B("ASUS", "DSAN-DX", NT, "http://www.asus.com/Server_Workstation/Server_Motherboards/DSANDX/", NULL), @@ -711,13 +714,19 @@ B("ASUS", "P7H55-M LX", BAD, NULL, "flashrom works correctly, but GbE LAN is nonworking (probably due to a missing/bogus MAC address; see http://www.flashrom.org/pipermail/flashrom/2011-July/007432.html and http://ubuntuforums.org/showthread.php?t=1534389 for a possible workaround)"), B("ASUS", "P8B-E/4L", BAD, NULL, "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8B WS", BAD, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("ASUS", "P8B75-M LE", BAD, NULL, "Probing works (2x 8192 kB via hwseq), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8H61 PRO", BAD, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8H61-M LE/USB3", BAD, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8H67-M PRO", BAD, NULL, "Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("ASUS", "P8H77-I", OK, "http://www.asus.com/Motherboards/P8H77I/", NULL), + B("ASUS", "P8H77-M", OK, "http://www.asus.com/Motherboards/P8H77M/", NULL), B("ASUS", "P8P67 (rev. 3.1)", BAD, NULL, "Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), - B("ASUS", "P8P67 LE", BAD, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("ASUS", "P8P67 LE (B2)", OK, NULL, NULL), + B("ASUS", "P8P67 LE (B3)", BAD, NULL, "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8P67 PRO (rev. 3.0)", OK, "http://www.asus.com/Motherboards/Intel_Socket_1155/P8P67_PRO/", NULL), + B("ASUS", "P8P67-M PRO", BAD, NULL, "Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8Z68-V", OK, "http://www.asus.com/Motherboards/Intel_Socket_1155/P8Z68V/", "Warning: MAC address of LOM is stored at 0x1000 - 0x1005 of the image."), + B("ASUS", "P8Z68-V LE", BAD, NULL, "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8Z68-V PRO", BAD, NULL, "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("ASUS", "P8Z68-V PRO/GEN3", OK, "http://www.asus.com/Motherboards/Intel_Socket_1155/P8Z68V_PROGEN3/", "Warning: MAC address of LOM is stored at 0x1000 - 0x1005 of the image."), B("ASUS", "SABERTOOTH 990FX", OK, "http://www.asus.com/Motherboards/AMD_AM3Plus/SABERTOOTH_990FX/", NULL), @@ -751,6 +760,7 @@ B("DFI", "AD77", NT, NULL, "Untested board enable."), B("DFI", "Blood-Iron P35 T2RL", OK, "http://lp.lanparty.com.tw/portal/CM/cmproduct/XX_cmproddetail/XX_WbProdsWin…", NULL), B("Elitegroup", "848P-A7", OK, NULL, NULL), + B("Elitegroup", "GeForce6100PM-M2 (V3.0)", OK, NULL, NULL), B("Elitegroup", "GeForce6100SM-M", OK, NULL, NULL), B("Elitegroup", "GF7100PVT-M3 (V1.0)", OK, NULL, NULL), B("Elitegroup", "GF8200A", OK, NULL, NULL), @@ -830,6 +840,7 @@ B("GIGABYTE", "GA-MA790GP-DS4H", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2887", NULL), B("GIGABYTE", "GA-MA790XT-UD4P (rev. 1.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3010", NULL), B("GIGABYTE", "GA-P55A-UD4 (rev. 1.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3436", NULL), + B("GIGABYTE", "GA-P55A-UD7" , OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3324", NULL), B("GIGABYTE", "GA-P67A-UD3P", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3649", NULL), B("GIGABYTE", "GA-X58A-UD3R (rev. 2.0)", OK, NULL, NULL), B("GIGABYTE", "GA-X58A-UD7 (rev. 2.0)", OK, NULL, NULL), @@ -865,6 +876,7 @@ B("Intel", "DH67CF", BAD, NULL, "H67 with BIOS lock enable and locked ME region, see http://www.flashrom.org/pipermail/flashrom/2011-September/007789.html"), B("Intel", "DH67CL", BAD, NULL, "H67 with BIOS lock enable and locked ME region, see http://www.flashrom.org/pipermail/flashrom/2012-November/010112.html"), B("Intel", "DN2800MT (Marshalltown)", BAD, NULL, "BIOS locked via BIOS_CNTL."), + B("Intel", "DQ77MK", BAD, NULL, "Q77 with BIOS lock enable and locked ME region, see http://paste.flashrom.org/view.php?id=1603"), B("Intel", "EP80759", OK, NULL, NULL), B("Intel", "Foxhollow", OK, NULL, "Intel reference board."), B("Intel", "Greencity", OK, NULL, "Intel reference board."), @@ -918,6 +930,7 @@ B("MSI", "MS-7529 (G31M3-L(S) V2)", OK, "http://www.msi.com/product/mb/G31M3-L-V2---G31M3-LS-V2.html", NULL), B("MSI", "MS-7529 (G31TM-P21)", OK, "http://www.msi.com/product/mb/G31TM-P21.html", NULL), B("MSI", "MS-7548 (Aspen-GL8E)", OK, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c01635688&lc=en&cc=us&d…", NULL), + B("MSI", "MS-7551 (KA780G)", OK, "http://www.msi.com/product/mb/KA780G.html", NULL), B("MSI", "MS-7596 (785GM-E51)", OK, "http://www.msi.com/product/mb/785GM-E51.html", NULL), B("MSI", "MS-7597 (GF615M-P33)", BAD, NULL, "Missing board enable/SIO support (Fintek F71889), see http://www.flashrom.org/pipermail/flashrom/2012-March/008956.html"), B("MSI", "MS-7599 (870-C45)", OK, "http://www.msi.com/product/mb/870-C45.html", NULL), @@ -929,7 +942,9 @@ B("MSI", "MS-7676 (Z68MA-G45 (B3))", OK, "http://www.msi.com/product/mb/Z68MA-G45--B3-.html", NULL), B("MSI", "MS-7696 (A75MA-G55)", OK, "http://www.msi.com/product/mb/A75MA-G55.html", NULL), B("MSI", "MS-7698 (E350IA-E45)", OK, "http://www.msi.com/product/mb/E350IA-E45.html", NULL), - B("MSI", "MS-7740 (H61MA-E35(B3))", OK, "http://www.msi.com/product/mb/H61MA-E35--B3-.html", NULL), + B("MSI", "MS-7740 (H61MA-E35(B3))", OK, "http://www.msi.com/product/mb/H61MA-E35--B3-.html", NULL), + B("MSI", "MS-7756 (H77MA-G43)", OK, "http://www.msi.com/product/mb/H77MA-G43.html", NULL), + B("MSI", "MS-7808 (B75MA-E33)", OK, "http://www.msi.com/product/mb/B75MA-E33.html", NULL), B("NEC", "PowerMate 2000", OK, "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/", NULL), B("Nokia", "IP530", OK, NULL, NULL), B("Palit", "N61S", OK, NULL, NULL), @@ -946,6 +961,7 @@ B("Portwell", "PEB-4700VLA", OK, "http://www.portwell.com/products/detail.asp?CUSTCHAR1=PEB-4700VLA", NULL), B("RCA", "RM4100", OK, "http://www.settoplinux.org/index.php?title=RCA_RM4100", NULL), B("Samsung", "Polaris 32", OK, NULL, NULL), + B("SAPPHIRE", "IPC-E350M1", OK, "http://www.sapphiretech.com/presentation/product/?pid=1034&lid=1", NULL), B("Shuttle", "AK31", OK, "http://www.motherboard.cz/mb/shuttle/AK31.htm", NULL), B("Shuttle", "AK38N", OK, "http://eu.shuttle.com/en/desktopdefault.aspx/tabid-36/558_read-9889/", NULL), B("Shuttle", "AV11V30", OK, NULL, NULL), @@ -971,6 +987,7 @@ B("Supermicro", "X7SPA-HF", OK, "http://www.supermicro.com/products/motherboard/ATOM/ICH9/X7SPA.cfm?typ=H&IP…", NULL), B("Supermicro", "X8DT3", OK, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DT3.cfm", NULL), B("Supermicro", "X8DTE-F", OK, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DT6-F.cfm?IPMI=Y&…", NULL), + B("Supermicro", "X8DTG-D", OK, "http://www.supermicro.com/products/motherboard/qpi/5500/x8dtg-df.cfm", NULL), B("Supermicro", "X8DTH-6F", OK, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTH-6F.cfm", NULL), B("Supermicro", "X8DTT-F", OK, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTT-F.cfm", NULL), B("Supermicro", "X8DTT-HIBQF", OK, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTT-H.cfm", NULL), @@ -979,11 +996,14 @@ B("Supermicro", "X8SIE(-F)", BAD, "http://www.supermicro.com/products/motherboard/Xeon3000/3400/X8SIE.cfm?IPMI…", "Requires unlocking the ME although the registers are set up correctly by the descriptor/BIOS already (tested with swseq and hwseq)."), B("Supermicro", "X8STi", OK, "http://www.supermicro.com/products/motherboard/Xeon3000/X58/X8STi.cfm", NULL), B("Supermicro", "X9DR3-F", BAD, "http://www.supermicro.com/products/motherboard/xeon/c600/x9dr3-f.cfm", "Probing works (Numonyx N25Q128 (supported by SFDP only atm), 16384 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("Supermicro", "X9DRD-7LN4F", BAD, "http://www.supermicro.com/products/motherboard/xeon/c600/x9drd-7ln4f.cfm", "Probing works (Numonyx N25Q128 (supported by SFDP only atm), 16384 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("Supermicro", "X9DRT-HF+", BAD, NULL, "Probing works (Numonyx N25Q128 (supported by SFDP only atm), 16384 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked; SMM protection enabled."), B("Supermicro", "X9DRW", BAD, NULL, "Probing works (Numonyx N25Q128 (supported by SFDP only atm), 16384 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("Supermicro", "X9QRi-F+", BAD, "http://www.supermicro.com/products/motherboard/Xeon/C600/X9QRi-F_.cfm", "Probing works (Macronix MX25L12805, 16384 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked; SMM protection enabled."), B("Supermicro", "X9SCA-F", BAD, "http://www.supermicro.com/products/motherboard/Xeon/C202_C204/X9SCA-F.cfm", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("Supermicro", "X9SCE-F", BAD, "http://www.supermicro.com/products/motherboard/Xeon/C202_C204/X9SCE-F.cfm", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("Supermicro", "X9SCL", BAD, "http://www.supermicro.com/products/motherboard/Xeon/C202_C204/X9SCL.cfm", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), + B("Supermicro", "X9SCM-F", BAD, "http://www.supermicro.com/products/motherboard/Xeon/C202_C204/X9SCM-F.cfm", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("T-Online", "S-100", OK, "http://wiki.freifunk-hannover.de/T-Online_S_100", NULL), B("Tekram", "P6Pro-A5", OK, "http://www.motherboard.cz/mb/tekram/P6Pro-A5.htm", NULL), B("Termtek", "TK-3370 (Rev:2.5B)", OK, NULL, NULL), @@ -1020,6 +1040,7 @@ B("Tyan", "S5377 (Tempest i5100T)", OK, "http://www.tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=642&SKU=600000…", NULL), B("Tyan", "S5382 (Tempest i5000PW)", OK, "http://www.tyan.com/product_board_detail.aspx?pid=439", NULL), B("Tyan", "S5397 (Tempest i5400PW)", OK, "http://www.tyan.com/product_board_detail.aspx?pid=560", NULL), + B("Tyan", "S7066 (S7066WGM3NR)", BAD, "http://www.tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=790&SKU=600000…", "Probing works (Winbond W25Q64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("VIA", "EITX-3000", OK, "http://www.viaembedded.com/en/products/boards/810/1/EITX-3000.html", NULL), B("VIA", "EPIA M/MII/...", OK, "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…", NULL), /* EPIA-MII link for now */ B("VIA", "EPIA SP", OK, "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…", NULL), Modified: trunk/serprog.c ============================================================================== --- trunk/serprog.c Thu Jul 18 01:46:44 2013 (r1701) +++ trunk/serprog.c Fri Jul 26 00:54:25 2013 (r1702) @@ -797,7 +797,7 @@ static void sp_do_read_n(uint8_t * buf, const chipaddr addr, size_t len) { unsigned char sbuf[6]; - msg_pspew("%s: addr=0x%" PRIxPTR " len=%lu\n", __func__, addr, (unsigned long)len); + msg_pspew("%s: addr=0x%" PRIxPTR " len=%zu\n", __func__, addr, len); /* Stream the read-n -- as above. */ if ((sp_opbuf_usage) || (sp_max_write_n && sp_write_n_bytes)) sp_execute_opbuf_noflush(); Modified: trunk/spi25_statusreg.c ============================================================================== --- trunk/spi25_statusreg.c Thu Jul 18 01:46:44 2013 (r1701) +++ trunk/spi25_statusreg.c Fri Jul 26 00:54:25 2013 (r1702) @@ -640,7 +640,7 @@ int spi_prettyprint_status_register_bp2_ep_srwd(struct flashctx *flash) { uint8_t status = spi_read_status_register(flash); - msg_cdbg("Chip status register is %02x\n", status); + msg_cdbg("Chip status register is 0x%02x\n", status); spi_prettyprint_status_register_srwd(status); msg_cdbg("Chip status register: Program Fail Flag (P_FAIL) is %sset\n",

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Re: [flashrom] Flashrom fails on write. P4 motherboard
by san 25 Jul '13

25 Jul '13

Just uploaded lspci -nn here: http://e-san.info/Flashrom-P4/lspci-nn.txt How to lower GPIO by hand (before patch)? 2013/7/25 san <san(a)plusnet.pl> > In few hours ill send You lspci -nn info. Meanwhile, can You tell me how > to enable rom write by hand and before patch? > 23 lip 2013 23:37, "Stefan Tauner" <stefan.tauner(a)student.tuwien.ac.at> > napisał(a): > > On Fri, 19 Jul 2013 10:55:31 +0200 >> san <san(a)plusnet.pl> wrote: >> >> > Yes, i did try it, but can not find any useful informations. Still can >> not >> > write. Can not find any gpio ports and anything to use with pciset. >> Found >> > lpt port and files according to this page are uploaded on server. >> > >> > Please, help. >> >> According to what our community found out so far you need to lower GPIO >> 19. Please send/upload the output of lspci -nn too so that I can >> prepare a proper patch for you to test. >> -- >> Kind regards/Mit freundlichen Grüßen, Stefan Tauner >> > -- [ e-San.info | San(a)plusnet.pl ]

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