Re: [flashrom] A quick hack to support AMD Family 16h SOC

[Carl-Daniel Hailfinger]

Am 30.07.2013 23:22 schrieb Wei Hu:
> On Tue, Jul 30, 2013 at 1:59 PM, Carl-Daniel Hailfinger
> <[e-mail]> wrote:
> > This patch should work at normal speed and use the correct FIFO pointer
> > registers on Kabini.
> > The code is not exactly pretty, but functional and should (in theory)
> > need no functional changes before commit.
> >
> > Please check if read/write works at the expected speed. -VV is
> > sufficient this time.
>
> Reading the 4MB flash took 18 seconds, whereas writing took almost 3
> minutes. Is it normal? On another system with Intel PCH writes were
> way faster. There's another FIFO register at offset 0x80 in the new
> Kabini interface, which can hopefully speed up things, but the
> description is quite dense.
>
> I'm attaching two -VV logs, one from reading and the other from writing.

Thanks! This means my code works well.

The following timings are straight from the W25Q32BV datasheet. They may
be completely unrealistic. Typical erase time for that chip is around 30
seconds for a sectorwise chip erase (without overhead). The typical
write time for that chip (using 5-byte chunks due to the short FIFO for
SB600) would be around 600 seconds. Typical write time for that chip
with the long Kabini FIFO would be 45 seconds.
Add initial read time, sectorwise chip erase time, erase-verify time
(full chip read), write time, write-verify time (full chip read) and the
write time suddenly looks pretty reasonable.

Most important for me was to get the FIFO pointers right for Kabini.
Speed issues can be dealt with after the flashrom 0.9.7 release (right
now I'm just trying to fix things).

That said, the datasheet is rather unclear about the effect of
UseSpi100=1, and I'd like to set it to 0.

By the way, the data which enabled me to fix the FIFO stuff for Kabini
(because the datasheets have room for improvement) is here:
http://paste.flashrom.org/view.php?id=1718

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/

A quick hack to support AMD Family 16h SOC

[Wei Hu]

On Tue, Jul 30, 2013 at 3:08 PM, Carl-Daniel Hailfinger
<[e-mail]> wrote:
> The following timings are straight from the W25Q32BV datasheet. They may
> be completely unrealistic. Typical erase time for that chip is around 30
> seconds for a sectorwise chip erase (without overhead). The typical
> write time for that chip (using 5-byte chunks due to the short FIFO for
> SB600) would be around 600 seconds. Typical write time for that chip
> with the long Kabini FIFO would be 45 seconds.
> Add initial read time, sectorwise chip erase time, erase-verify time
> (full chip read), write time, write-verify time (full chip read) and the
> write time suddenly looks pretty reasonable.

Thanks for looking up the datasheet! I totally forgot the differences
between flash chips.