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Add URLs for three boards, fix a typo and add a note
by Idwer Vollering 28 Jul '10

28 Jul '10

Add URLs for boards ASUS K8V, ASUS K8V SE Deluxe, Elitegroup K7S5A. FIxes a typo, adds a note for ASUS M2N-E. Signed-off-by: Idwer Vollering <vidwer(a)gmail.com>

3 2

[PATCH] Split off programmer.h from flash.h
by Carl-Daniel Hailfinger 28 Jul '10

28 Jul '10

Split off programmer.h from flash.h. Programmer specific functions are of absolutely no interest to any file except those dealing with programmer specific actions (special SPI commands and the generic core). The new header structure is as follows (and yes, improvements are possible): flashchips.h flash chip IDs chipdrivers.h chip-specific read/write/... functions flash.h common header for all stuff that doesn't fit elsewhere hwaccess.h hardware access functions programmer.h programmer specific functions coreboot_tables.h inherited header from coreboot, internal programmer only spi.h SPI command definitions (do we want the same for JEDEC?) NOTE: This patch was created after running svn cp flash.h programmer.h and if you want to apply it, please run the same command before running patch. Due to this, the diff for programmer.h is not about what I added to programmer.c, but rather about what I removed from flash.h to get programmer.c. Compile tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-programmer_h/flash.h =================================================================== --- flashrom-programmer_h/flash.h (Revision 1108) +++ flashrom-programmer_h/flash.h (Arbeitskopie) @@ -35,88 +35,7 @@ typedef unsigned long chipaddr; -enum programmer { -#if CONFIG_INTERNAL == 1 - PROGRAMMER_INTERNAL, -#endif -#if CONFIG_DUMMY == 1 - PROGRAMMER_DUMMY, -#endif -#if CONFIG_NIC3COM == 1 - PROGRAMMER_NIC3COM, -#endif -#if CONFIG_NICREALTEK == 1 - PROGRAMMER_NICREALTEK, - PROGRAMMER_NICREALTEK2, -#endif -#if CONFIG_NICNATSEMI == 1 - PROGRAMMER_NICNATSEMI, -#endif -#if CONFIG_GFXNVIDIA == 1 - PROGRAMMER_GFXNVIDIA, -#endif -#if CONFIG_DRKAISER == 1 - PROGRAMMER_DRKAISER, -#endif -#if CONFIG_SATASII == 1 - PROGRAMMER_SATASII, -#endif -#if CONFIG_ATAHPT == 1 - PROGRAMMER_ATAHPT, -#endif -#if CONFIG_INTERNAL == 1 -#if defined(__i386__) || defined(__x86_64__) - PROGRAMMER_IT87SPI, -#endif -#endif -#if CONFIG_FT2232_SPI == 1 - PROGRAMMER_FT2232_SPI, -#endif -#if CONFIG_SERPROG == 1 - PROGRAMMER_SERPROG, -#endif -#if CONFIG_BUSPIRATE_SPI == 1 - PROGRAMMER_BUSPIRATE_SPI, -#endif -#if CONFIG_DEDIPROG == 1 - PROGRAMMER_DEDIPROG, -#endif -#if CONFIG_RAYER_SPI == 1 - PROGRAMMER_RAYER_SPI, -#endif - PROGRAMMER_INVALID /* This must always be the last entry. */ -}; - -extern enum programmer programmer; - -struct programmer_entry { - const char *vendor; - const char *name; - - int (*init) (void); - int (*shutdown) (void); - - void * (*map_flash_region) (const char *descr, unsigned long phys_addr, - size_t len); - void (*unmap_flash_region) (void *virt_addr, size_t len); - - void (*chip_writeb) (uint8_t val, chipaddr addr); - void (*chip_writew) (uint16_t val, chipaddr addr); - void (*chip_writel) (uint32_t val, chipaddr addr); - void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len); - uint8_t (*chip_readb) (const chipaddr addr); - uint16_t (*chip_readw) (const chipaddr addr); - uint32_t (*chip_readl) (const chipaddr addr); - void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len); - void (*delay) (int usecs); -}; - -extern const struct programmer_entry programmer_table[]; - int register_shutdown(void (*function) (void *data), void *data); - -int programmer_init(char *param); -int programmer_shutdown(void); void *programmer_map_flash_region(const char *descr, unsigned long phys_addr, size_t len); void programmer_unmap_flash_region(void *virt_addr, size_t len); @@ -130,23 +49,6 @@ void chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void programmer_delay(int usecs); -enum bitbang_spi_master_type { - BITBANG_SPI_INVALID = 0, /* This must always be the first entry. */ -#if CONFIG_RAYER_SPI == 1 - BITBANG_SPI_MASTER_RAYER, -#endif -}; - -struct bitbang_spi_master { - enum bitbang_spi_master_type type; - - /* Note that CS# is active low, so val=0 means the chip is active. */ - void (*set_cs) (int val); - void (*set_sck) (int val); - void (*set_mosi) (int val); - int (*get_miso) (void); -}; - #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) enum chipbustype { @@ -263,308 +165,11 @@ extern struct flashchip flashchips[]; -#if CONFIG_INTERNAL == 1 -struct penable { - uint16_t vendor_id; - uint16_t device_id; - int status; - const char *vendor_name; - const char *device_name; - int (*doit) (struct pci_dev *dev, const char *name); -}; - -extern const struct penable chipset_enables[]; - -struct board_pciid_enable { - /* Any device, but make it sensible, like the ISA bridge. */ - uint16_t first_vendor; - uint16_t first_device; - uint16_t first_card_vendor; - uint16_t first_card_device; - - /* Any device, but make it sensible, like - * the host bridge. May be NULL. - */ - uint16_t second_vendor; - uint16_t second_device; - uint16_t second_card_vendor; - uint16_t second_card_device; - - /* Pattern to match DMI entries */ - const char *dmi_pattern; - - /* The vendor / part name from the coreboot table. */ - const char *lb_vendor; - const char *lb_part; - - const char *vendor_name; - const char *board_name; - - int max_rom_decode_parallel; - int status; - int (*enable) (void); -}; - -extern const struct board_pciid_enable board_pciid_enables[]; - -struct board_info { - const char *vendor; - const char *name; - const int working; -#ifdef CONFIG_PRINT_WIKI - const char *url; - const char *note; -#endif -}; - -extern const struct board_info boards_known[]; -extern const struct board_info laptops_known[]; - -#endif - -/* udelay.c */ -void myusec_delay(int usecs); -void myusec_calibrate_delay(void); -void internal_delay(int usecs); - -#if NEED_PCI == 1 -/* pcidev.c */ - -extern uint32_t io_base_addr; -extern struct pci_access *pacc; -extern struct pci_dev *pcidev_dev; -struct pcidev_status { - uint16_t vendor_id; - uint16_t device_id; - int status; - const char *vendor_name; - const char *device_name; -}; -uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, const struct pcidev_status *devs); -uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, const struct pcidev_status *devs); -#endif - /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); void print_supported(void); -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1 -void print_supported_pcidevs(const struct pcidev_status *devs); -#endif void print_supported_wiki(void); -/* board_enable.c */ -void w836xx_ext_enter(uint16_t port); -void w836xx_ext_leave(uint16_t port); -int it8705f_write_enable(uint8_t port); -uint8_t sio_read(uint16_t port, uint8_t reg); -void sio_write(uint16_t port, uint8_t reg, uint8_t data); -void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); -int board_flash_enable(const char *vendor, const char *part); - -/* chipset_enable.c */ -int chipset_flash_enable(void); - -/* processor_enable.c */ -int processor_flash_enable(void); - -/* physmap.c */ -void *physmap(const char *descr, unsigned long phys_addr, size_t len); -void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len); -void physunmap(void *virt_addr, size_t len); -int setup_cpu_msr(int cpu); -void cleanup_cpu_msr(void); - -/* cbtable.c */ -void lb_vendor_dev_from_string(char *boardstring); -int coreboot_init(void); -extern char *lb_part, *lb_vendor; -extern int partvendor_from_cbtable; - -/* dmi.c */ -extern int has_dmi_support; -void dmi_init(void); -int dmi_match(const char *pattern); - -/* internal.c */ -#if NEED_PCI == 1 -struct superio { - uint16_t vendor; - uint16_t port; - uint16_t model; -}; -extern struct superio superio; -#define SUPERIO_VENDOR_NONE 0x0 -#define SUPERIO_VENDOR_ITE 0x1 -struct pci_dev *pci_dev_find_filter(struct pci_filter filter); -struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class); -struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); -struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device, - uint16_t card_vendor, uint16_t card_device); -#endif -void get_io_perms(void); -void release_io_perms(void); -#if CONFIG_INTERNAL == 1 -extern int is_laptop; -extern int force_boardenable; -extern int force_boardmismatch; -void probe_superio(void); -int internal_init(void); -int internal_shutdown(void); -void internal_chip_writeb(uint8_t val, chipaddr addr); -void internal_chip_writew(uint16_t val, chipaddr addr); -void internal_chip_writel(uint32_t val, chipaddr addr); -uint8_t internal_chip_readb(const chipaddr addr); -uint16_t internal_chip_readw(const chipaddr addr); -uint32_t internal_chip_readl(const chipaddr addr); -void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -#endif -void mmio_writeb(uint8_t val, void *addr); -void mmio_writew(uint16_t val, void *addr); -void mmio_writel(uint32_t val, void *addr); -uint8_t mmio_readb(void *addr); -uint16_t mmio_readw(void *addr); -uint32_t mmio_readl(void *addr); -void mmio_le_writeb(uint8_t val, void *addr); -void mmio_le_writew(uint16_t val, void *addr); -void mmio_le_writel(uint32_t val, void *addr); -uint8_t mmio_le_readb(void *addr); -uint16_t mmio_le_readw(void *addr); -uint32_t mmio_le_readl(void *addr); - -/* programmer.c */ -int noop_shutdown(void); -void *fallback_map(const char *descr, unsigned long phys_addr, size_t len); -void fallback_unmap(void *virt_addr, size_t len); -uint8_t noop_chip_readb(const chipaddr addr); -void noop_chip_writeb(uint8_t val, chipaddr addr); -void fallback_chip_writew(uint16_t val, chipaddr addr); -void fallback_chip_writel(uint32_t val, chipaddr addr); -void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len); -uint16_t fallback_chip_readw(const chipaddr addr); -uint32_t fallback_chip_readl(const chipaddr addr); -void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); - -/* dummyflasher.c */ -#if CONFIG_DUMMY == 1 -int dummy_init(void); -int dummy_shutdown(void); -void *dummy_map(const char *descr, unsigned long phys_addr, size_t len); -void dummy_unmap(void *virt_addr, size_t len); -void dummy_chip_writeb(uint8_t val, chipaddr addr); -void dummy_chip_writew(uint16_t val, chipaddr addr); -void dummy_chip_writel(uint32_t val, chipaddr addr); -void dummy_chip_writen(uint8_t *buf, chipaddr addr, size_t len); -uint8_t dummy_chip_readb(const chipaddr addr); -uint16_t dummy_chip_readw(const chipaddr addr); -uint32_t dummy_chip_readl(const chipaddr addr); -void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); -#endif - -/* nic3com.c */ -#if CONFIG_NIC3COM == 1 -int nic3com_init(void); -int nic3com_shutdown(void); -void nic3com_chip_writeb(uint8_t val, chipaddr addr); -uint8_t nic3com_chip_readb(const chipaddr addr); -extern const struct pcidev_status nics_3com[]; -#endif - -/* gfxnvidia.c */ -#if CONFIG_GFXNVIDIA == 1 -int gfxnvidia_init(void); -int gfxnvidia_shutdown(void); -void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr); -uint8_t gfxnvidia_chip_readb(const chipaddr addr); -extern const struct pcidev_status gfx_nvidia[]; -#endif - -/* drkaiser.c */ -#if CONFIG_DRKAISER == 1 -int drkaiser_init(void); -int drkaiser_shutdown(void); -void drkaiser_chip_writeb(uint8_t val, chipaddr addr); -uint8_t drkaiser_chip_readb(const chipaddr addr); -extern const struct pcidev_status drkaiser_pcidev[]; -#endif - -/* nicrealtek.c */ -#if CONFIG_NICREALTEK == 1 -int nicrealtek_init(void); -int nicsmc1211_init(void); -int nicrealtek_shutdown(void); -void nicrealtek_chip_writeb(uint8_t val, chipaddr addr); -uint8_t nicrealtek_chip_readb(const chipaddr addr); -extern const struct pcidev_status nics_realtek[]; -extern const struct pcidev_status nics_realteksmc1211[]; -#endif - -/* nicnatsemi.c */ -#if CONFIG_NICNATSEMI == 1 -int nicnatsemi_init(void); -int nicnatsemi_shutdown(void); -void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr); -uint8_t nicnatsemi_chip_readb(const chipaddr addr); -extern const struct pcidev_status nics_natsemi[]; -#endif - -/* satasii.c */ -#if CONFIG_SATASII == 1 -int satasii_init(void); -int satasii_shutdown(void); -void satasii_chip_writeb(uint8_t val, chipaddr addr); -uint8_t satasii_chip_readb(const chipaddr addr); -extern const struct pcidev_status satas_sii[]; -#endif - -/* atahpt.c */ -#if CONFIG_ATAHPT == 1 -int atahpt_init(void); -int atahpt_shutdown(void); -void atahpt_chip_writeb(uint8_t val, chipaddr addr); -uint8_t atahpt_chip_readb(const chipaddr addr); -extern const struct pcidev_status ata_hpt[]; -#endif - -/* ft2232_spi.c */ -#define FTDI_FT2232H 0x6010 -#define FTDI_FT4232H 0x6011 -int ft2232_spi_init(void); -int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); - -/* rayer_spi.c */ -#if CONFIG_RAYER_SPI == 1 -int rayer_spi_init(void); -#endif - -/* bitbang_spi.c */ -int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); -int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); - -/* buspirate_spi.c */ -struct buspirate_spispeeds { - const char *name; - const int speed; -}; -int buspirate_spi_init(void); -int buspirate_spi_shutdown(void); -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); - -/* dediprog.c */ -int dediprog_init(void); -int dediprog_shutdown(void); -int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); - /* flashrom.c */ enum write_granularity { write_gran_1bit, @@ -572,15 +177,6 @@ write_gran_256bytes, }; extern enum chipbustype buses_supported; -struct decode_sizes { - uint32_t parallel; - uint32_t lpc; - uint32_t fwh; - uint32_t spi; -}; -extern struct decode_sizes max_rom_decode; -extern int programmer_may_write; -extern unsigned long flashbase; extern int verbose; extern const char * const flashrom_version; extern char *chip_to_probe; @@ -589,12 +185,9 @@ int erase_flash(struct flashchip *flash); struct flashchip *probe_flash(struct flashchip *first_flash, int force); int read_flash_to_file(struct flashchip *flash, char *filename); -void check_chip_supported(struct flashchip *flash); -int check_max_decode(enum chipbustype buses, uint32_t size); int min(int a, int b); int max(int a, int b); char *extract_param(char **haystack, char *needle, char *delim); -char *extract_programmer_param(char *param_name); int check_erased_range(struct flashchip *flash, int start, int len); int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, char *message); int need_erase(uint8_t *have, uint8_t *want, int len, enum write_granularity gran); @@ -634,130 +227,20 @@ int cli_classic(int argc, char *argv[]); /* layout.c */ -int show_id(uint8_t *bios, int size, int force); int read_romlayout(char *name); int find_romentry(char *name); int handle_romentries(uint8_t *buffer, struct flashchip *flash); /* spi.c */ -enum spi_controller { - SPI_CONTROLLER_NONE, -#if CONFIG_INTERNAL == 1 -#if defined(__i386__) || defined(__x86_64__) - SPI_CONTROLLER_ICH7, - SPI_CONTROLLER_ICH9, - SPI_CONTROLLER_IT87XX, - SPI_CONTROLLER_SB600, - SPI_CONTROLLER_VIA, - SPI_CONTROLLER_WBSIO, -#endif -#endif -#if CONFIG_FT2232_SPI == 1 - SPI_CONTROLLER_FT2232, -#endif -#if CONFIG_DUMMY == 1 - SPI_CONTROLLER_DUMMY, -#endif -#if CONFIG_BUSPIRATE_SPI == 1 - SPI_CONTROLLER_BUSPIRATE, -#endif -#if CONFIG_DEDIPROG == 1 - SPI_CONTROLLER_DEDIPROG, -#endif -#if CONFIG_RAYER_SPI == 1 - SPI_CONTROLLER_RAYER, -#endif - SPI_CONTROLLER_INVALID /* This must always be the last entry. */ -}; -extern const int spi_programmer_count; struct spi_command { unsigned int writecnt; unsigned int readcnt; const unsigned char *writearr; unsigned char *readarr; }; -struct spi_programmer { - int (*command)(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); - int (*multicommand)(struct spi_command *cmds); - - /* Optimized functions for this programmer */ - int (*read)(struct flashchip *flash, uint8_t *buf, int start, int len); - int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len); -}; - -extern enum spi_controller spi_controller; -extern const struct spi_programmer spi_programmer[]; int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int spi_send_multicommand(struct spi_command *cmds); -int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int default_spi_send_multicommand(struct spi_command *cmds); uint32_t spi_get_valid_read_addr(void); -/* ichspi.c */ -#if CONFIG_INTERNAL == 1 -extern uint32_t ichspi_bbar; -int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, - int ich_generation); -int via_init_spi(struct pci_dev *dev); -int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len); -int ich_spi_send_multicommand(struct spi_command *cmds); -#endif - -/* it87spi.c */ -void enter_conf_mode_ite(uint16_t port); -void exit_conf_mode_ite(uint16_t port); -struct superio probe_superio_ite(void); -int init_superio_ite(void); -int it87spi_init(void); -int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); - -/* sb600spi.c */ -#if CONFIG_INTERNAL == 1 -int sb600_probe_spi(struct pci_dev *dev); -int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); -#endif - -/* wbsio_spi.c */ -#if CONFIG_INTERNAL == 1 -int wbsio_check_for_spi(void); -int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -#endif - -/* serprog.c */ -int serprog_init(void); -int serprog_shutdown(void); -void serprog_chip_writeb(uint8_t val, chipaddr addr); -uint8_t serprog_chip_readb(const chipaddr addr); -void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -void serprog_delay(int delay); - -/* serial.c */ -#if _WIN32 -typedef HANDLE fdtype; -#else -typedef int fdtype; -#endif - -void sp_flush_incoming(void); -fdtype sp_openserport(char *dev, unsigned int baud); -void __attribute__((noreturn)) sp_die(char *msg); -extern fdtype sp_fd; -int serialport_shutdown(void); -int serialport_write(unsigned char *buf, unsigned int writecnt); -int serialport_read(unsigned char *buf, unsigned int readcnt); - #endif /* !__FLASH_H__ */ Index: flashrom-programmer_h/drkaiser.c =================================================================== --- flashrom-programmer_h/drkaiser.c (Revision 1108) +++ flashrom-programmer_h/drkaiser.c (Arbeitskopie) @@ -20,6 +20,7 @@ #include <stdlib.h> #include "flash.h" +#include "programmer.h" #define PCI_VENDOR_ID_DRKAISER 0x1803 Index: flashrom-programmer_h/it87spi.c =================================================================== --- flashrom-programmer_h/it87spi.c (Revision 1108) +++ flashrom-programmer_h/it87spi.c (Arbeitskopie) @@ -29,6 +29,7 @@ #include <stdlib.h> #include "flash.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" #define ITE_SUPERIO_PORT1 0x2e Index: flashrom-programmer_h/pcidev.c =================================================================== --- flashrom-programmer_h/pcidev.c (Revision 1108) +++ flashrom-programmer_h/pcidev.c (Arbeitskopie) @@ -22,6 +22,7 @@ #include <string.h> #include <sys/types.h> #include "flash.h" +#include "programmer.h" uint32_t io_base_addr; struct pci_access *pacc; Index: flashrom-programmer_h/gfxnvidia.c =================================================================== --- flashrom-programmer_h/gfxnvidia.c (Revision 1108) +++ flashrom-programmer_h/gfxnvidia.c (Arbeitskopie) @@ -22,6 +22,7 @@ #include <string.h> #include <sys/types.h> #include "flash.h" +#include "programmer.h" #define PCI_VENDOR_ID_NVIDIA 0x10de Index: flashrom-programmer_h/nicrealtek.c =================================================================== --- flashrom-programmer_h/nicrealtek.c (Revision 1108) +++ flashrom-programmer_h/nicrealtek.c (Arbeitskopie) @@ -22,6 +22,7 @@ #include <stdlib.h> #include "flash.h" +#include "programmer.h" #define PCI_VENDOR_ID_REALTEK 0x10ec #define PCI_VENDOR_ID_SMC1211 0x1113 Index: flashrom-programmer_h/serprog.c =================================================================== --- flashrom-programmer_h/serprog.c (Revision 1108) +++ flashrom-programmer_h/serprog.c (Arbeitskopie) @@ -22,7 +22,6 @@ #include <stdio.h> #include <stdlib.h> #include <unistd.h> -#include "flash.h" #include <string.h> #include <ctype.h> #include <fcntl.h> @@ -36,6 +35,8 @@ #include <errno.h> #include <inttypes.h> #include <termios.h> +#include "flash.h" +#include "programmer.h" #define MSGHEADER "serprog:" Index: flashrom-programmer_h/bitbang_spi.c =================================================================== --- flashrom-programmer_h/bitbang_spi.c (Revision 1108) +++ flashrom-programmer_h/bitbang_spi.c (Arbeitskopie) @@ -24,6 +24,7 @@ #include <ctype.h> #include "flash.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" /* Length of half a clock period in usecs. */ Index: flashrom-programmer_h/dummyflasher.c =================================================================== --- flashrom-programmer_h/dummyflasher.c (Revision 1108) +++ flashrom-programmer_h/dummyflasher.c (Arbeitskopie) @@ -24,6 +24,7 @@ #include <sys/types.h> #include "flash.h" #include "chipdrivers.h" +#include "programmer.h" static void tolower_string(char *str) { Index: flashrom-programmer_h/cli_classic.c =================================================================== --- flashrom-programmer_h/cli_classic.c (Revision 1108) +++ flashrom-programmer_h/cli_classic.c (Arbeitskopie) @@ -30,6 +30,7 @@ #include <getopt.h> #include "flash.h" #include "flashchips.h" +#include "programmer.h" static void cli_classic_usage(const char *name) { Index: flashrom-programmer_h/dmi.c =================================================================== --- flashrom-programmer_h/dmi.c (Revision 1108) +++ flashrom-programmer_h/dmi.c (Arbeitskopie) @@ -23,6 +23,7 @@ #include <stdlib.h> #include "flash.h" +#include "programmer.h" int has_dmi_support = 0; Index: flashrom-programmer_h/internal.c =================================================================== --- flashrom-programmer_h/internal.c (Revision 1108) +++ flashrom-programmer_h/internal.c (Arbeitskopie) @@ -23,6 +23,7 @@ #include <stdlib.h> #include <sys/types.h> #include "flash.h" +#include "programmer.h" #if NEED_PCI == 1 struct pci_dev *pci_dev_find_filter(struct pci_filter filter) Index: flashrom-programmer_h/layout.c =================================================================== --- flashrom-programmer_h/layout.c (Revision 1108) +++ flashrom-programmer_h/layout.c (Arbeitskopie) @@ -23,6 +23,7 @@ #include <string.h> #include <ctype.h> #include "flash.h" +#include "programmer.h" #if CONFIG_INTERNAL == 1 char *mainboard_vendor = NULL; Index: flashrom-programmer_h/print_wiki.c =================================================================== --- flashrom-programmer_h/print_wiki.c (Revision 1108) +++ flashrom-programmer_h/print_wiki.c (Arbeitskopie) @@ -25,6 +25,7 @@ #include <time.h> #include "flash.h" #include "flashchips.h" +#include "programmer.h" static const char * const wiki_header = "= Supported devices =\n\n\ <div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ Index: flashrom-programmer_h/ichspi.c =================================================================== --- flashrom-programmer_h/ichspi.c (Revision 1108) +++ flashrom-programmer_h/ichspi.c (Arbeitskopie) @@ -38,6 +38,7 @@ #include <string.h> #include "flash.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" /* ICH9 controller register definition */ Index: flashrom-programmer_h/nicnatsemi.c =================================================================== --- flashrom-programmer_h/nicnatsemi.c (Revision 1108) +++ flashrom-programmer_h/nicnatsemi.c (Arbeitskopie) @@ -22,6 +22,7 @@ #include <stdlib.h> #include "flash.h" +#include "programmer.h" #define PCI_VENDOR_ID_NATSEMI 0x100b Index: flashrom-programmer_h/cbtable.c =================================================================== --- flashrom-programmer_h/cbtable.c (Revision 1108) +++ flashrom-programmer_h/cbtable.c (Arbeitskopie) @@ -28,6 +28,7 @@ #include <sys/types.h> #include <string.h> #include "flash.h" +#include "programmer.h" #include "coreboot_tables.h" char *lb_part = NULL, *lb_vendor = NULL; Index: flashrom-programmer_h/rayer_spi.c =================================================================== --- flashrom-programmer_h/rayer_spi.c (Revision 1108) +++ flashrom-programmer_h/rayer_spi.c (Arbeitskopie) @@ -31,6 +31,7 @@ #if defined(__i386__) || defined(__x86_64__) #include "flash.h" +#include "programmer.h" /* We have two sets of pins, out and in. The numbers for both sets are * independent and are bitshift values, not real pin numbers. Index: flashrom-programmer_h/dediprog.c =================================================================== --- flashrom-programmer_h/dediprog.c (Revision 1108) +++ flashrom-programmer_h/dediprog.c (Arbeitskopie) @@ -21,6 +21,7 @@ #include <usb.h> #include "flash.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" #define DEFAULT_TIMEOUT 3000 Index: flashrom-programmer_h/spi25.c =================================================================== --- flashrom-programmer_h/spi25.c (Revision 1108) +++ flashrom-programmer_h/spi25.c (Arbeitskopie) @@ -26,6 +26,7 @@ #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" void spi_prettyprint_status_register(struct flashchip *flash); Index: flashrom-programmer_h/buspirate_spi.c =================================================================== --- flashrom-programmer_h/buspirate_spi.c (Revision 1108) +++ flashrom-programmer_h/buspirate_spi.c (Arbeitskopie) @@ -24,6 +24,7 @@ #include <ctype.h> #include "flash.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" /* Change this to #define if you want to test without a serial implementation */ Index: flashrom-programmer_h/serial.c =================================================================== --- flashrom-programmer_h/serial.c (Revision 1108) +++ flashrom-programmer_h/serial.c (Arbeitskopie) @@ -22,7 +22,6 @@ #include <stdio.h> #include <stdlib.h> #include <unistd.h> -#include "flash.h" #include <string.h> #include <ctype.h> #include <fcntl.h> @@ -35,6 +34,8 @@ #else #include <termios.h> #endif +#include "flash.h" +#include "programmer.h" fdtype sp_fd; Index: flashrom-programmer_h/atahpt.c =================================================================== --- flashrom-programmer_h/atahpt.c (Revision 1108) +++ flashrom-programmer_h/atahpt.c (Arbeitskopie) @@ -22,6 +22,7 @@ #include <string.h> #include <sys/types.h> #include "flash.h" +#include "programmer.h" #define BIOS_ROM_ADDR 0x90 #define BIOS_ROM_DATA 0x94 Index: flashrom-programmer_h/processor_enable.c =================================================================== --- flashrom-programmer_h/processor_enable.c (Revision 1108) +++ flashrom-programmer_h/processor_enable.c (Arbeitskopie) @@ -22,6 +22,7 @@ */ #include "flash.h" +#include "programmer.h" #if defined(__i386__) || defined(__x86_64__) Index: flashrom-programmer_h/spi.c =================================================================== --- flashrom-programmer_h/spi.c (Revision 1108) +++ flashrom-programmer_h/spi.c (Arbeitskopie) @@ -25,6 +25,7 @@ #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" enum spi_controller spi_controller = SPI_CONTROLLER_NONE; Index: flashrom-programmer_h/nic3com.c =================================================================== --- flashrom-programmer_h/nic3com.c (Revision 1108) +++ flashrom-programmer_h/nic3com.c (Arbeitskopie) @@ -22,6 +22,7 @@ #include <stdlib.h> #include "flash.h" +#include "programmer.h" #define BIOS_ROM_ADDR 0x04 #define BIOS_ROM_DATA 0x08 Index: flashrom-programmer_h/ft2232_spi.c =================================================================== --- flashrom-programmer_h/ft2232_spi.c (Revision 1108) +++ flashrom-programmer_h/ft2232_spi.c (Arbeitskopie) @@ -27,6 +27,7 @@ #include <ctype.h> #include "flash.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" #include <ftdi.h> Index: flashrom-programmer_h/satasii.c =================================================================== --- flashrom-programmer_h/satasii.c (Revision 1108) +++ flashrom-programmer_h/satasii.c (Arbeitskopie) @@ -22,6 +22,7 @@ #include <stdlib.h> #include "flash.h" +#include "programmer.h" #define PCI_VENDOR_ID_SII 0x1095 Index: flashrom-programmer_h/wbsio_spi.c =================================================================== --- flashrom-programmer_h/wbsio_spi.c (Revision 1108) +++ flashrom-programmer_h/wbsio_spi.c (Arbeitskopie) @@ -22,6 +22,7 @@ #include "flash.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" #define WBSIO_PORT1 0x2e Index: flashrom-programmer_h/chipset_enable.c =================================================================== --- flashrom-programmer_h/chipset_enable.c (Revision 1108) +++ flashrom-programmer_h/chipset_enable.c (Arbeitskopie) @@ -32,6 +32,7 @@ #include <sys/types.h> #include <unistd.h> #include "flash.h" +#include "programmer.h" #if defined(__i386__) || defined(__x86_64__) Index: flashrom-programmer_h/sb600spi.c =================================================================== --- flashrom-programmer_h/sb600spi.c (Revision 1108) +++ flashrom-programmer_h/sb600spi.c (Arbeitskopie) @@ -25,6 +25,7 @@ #include "flash.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" /* This struct is unused, but helps visualize the SB600 SPI BAR layout. Index: flashrom-programmer_h/flashrom.c =================================================================== --- flashrom-programmer_h/flashrom.c (Revision 1108) +++ flashrom-programmer_h/flashrom.c (Arbeitskopie) @@ -33,6 +33,7 @@ #endif #include "flash.h" #include "flashchips.h" +#include "programmer.h" const char * const flashrom_version = FLASHROM_VERSION; char *chip_to_probe = NULL; Index: flashrom-programmer_h/programmer.h =================================================================== --- flashrom-programmer_h/programmer.h (Revision 1108) +++ flashrom-programmer_h/programmer.h (Arbeitskopie) @@ -21,20 +21,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __FLASH_H__ -#define __FLASH_H__ 1 +#ifndef __PROGRAMMER_H__ +#define __PROGRAMMER_H__ 1 -#include <stdint.h> -#include <stddef.h> -#include "hwaccess.h" -#ifdef _WIN32 -#include <windows.h> -#undef min -#undef max -#endif - -typedef unsigned long chipaddr; - enum programmer { #if CONFIG_INTERNAL == 1 PROGRAMMER_INTERNAL, @@ -113,22 +102,8 @@ extern const struct programmer_entry programmer_table[]; -int register_shutdown(void (*function) (void *data), void *data); - int programmer_init(char *param); int programmer_shutdown(void); -void *programmer_map_flash_region(const char *descr, unsigned long phys_addr, - size_t len); -void programmer_unmap_flash_region(void *virt_addr, size_t len); -void chip_writeb(uint8_t val, chipaddr addr); -void chip_writew(uint16_t val, chipaddr addr); -void chip_writel(uint32_t val, chipaddr addr); -void chip_writen(uint8_t *buf, chipaddr addr, size_t len); -uint8_t chip_readb(const chipaddr addr); -uint16_t chip_readw(const chipaddr addr); -uint32_t chip_readl(const chipaddr addr); -void chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -void programmer_delay(int usecs); enum bitbang_spi_master_type { BITBANG_SPI_INVALID = 0, /* This must always be the first entry. */ @@ -147,122 +122,6 @@ int (*get_miso) (void); }; -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) - -enum chipbustype { - CHIP_BUSTYPE_NONE = 0, - CHIP_BUSTYPE_PARALLEL = 1 << 0, - CHIP_BUSTYPE_LPC = 1 << 1, - CHIP_BUSTYPE_FWH = 1 << 2, - CHIP_BUSTYPE_SPI = 1 << 3, - CHIP_BUSTYPE_NONSPI = CHIP_BUSTYPE_PARALLEL | CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH, - CHIP_BUSTYPE_UNKNOWN = CHIP_BUSTYPE_PARALLEL | CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI, -}; - -/* - * How many different contiguous runs of erase blocks with one size each do - * we have for a given erase function? - */ -#define NUM_ERASEREGIONS 5 - -/* - * How many different erase functions do we have per chip? - */ -#define NUM_ERASEFUNCTIONS 5 - -#define FEATURE_REGISTERMAP (1 << 0) -#define FEATURE_BYTEWRITES (1 << 1) -#define FEATURE_LONG_RESET (0 << 4) -#define FEATURE_SHORT_RESET (1 << 4) -#define FEATURE_EITHER_RESET FEATURE_LONG_RESET -#define FEATURE_ADDR_FULL (0 << 2) -#define FEATURE_ADDR_MASK (3 << 2) -#define FEATURE_ADDR_2AA (1 << 2) -#define FEATURE_ADDR_AAA (2 << 2) -#define FEATURE_ADDR_SHIFTED (1 << 5) - -struct flashchip { - const char *vendor; - const char *name; - - enum chipbustype bustype; - - /* - * With 32bit manufacture_id and model_id we can cover IDs up to - * (including) the 4th bank of JEDEC JEP106W Standard Manufacturer's - * Identification code. - */ - uint32_t manufacture_id; - uint32_t model_id; - - int total_size; - int page_size; - int feature_bits; - - /* - * Indicate if flashrom has been tested with this flash chip and if - * everything worked correctly. - */ - uint32_t tested; - - int (*probe) (struct flashchip *flash); - - /* Delay after "enter/exit ID mode" commands in microseconds. */ - int probe_timing; - - /* - * Erase blocks and associated erase function. Any chip erase function - * is stored as chip-sized virtual block together with said function. - */ - struct block_eraser { - struct eraseblock{ - unsigned int size; /* Eraseblock size */ - unsigned int count; /* Number of contiguous blocks with that size */ - } eraseblocks[NUM_ERASEREGIONS]; - int (*block_erase) (struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); - } block_erasers[NUM_ERASEFUNCTIONS]; - - int (*printlock) (struct flashchip *flash); - int (*unlock) (struct flashchip *flash); - int (*write) (struct flashchip *flash, uint8_t *buf); - int (*read) (struct flashchip *flash, uint8_t *buf, int start, int len); - - /* Some flash devices have an additional register space. */ - chipaddr virtual_memory; - chipaddr virtual_registers; -}; - -#define TEST_UNTESTED 0 - -#define TEST_OK_PROBE (1 << 0) -#define TEST_OK_READ (1 << 1) -#define TEST_OK_ERASE (1 << 2) -#define TEST_OK_WRITE (1 << 3) -#define TEST_OK_PR (TEST_OK_PROBE | TEST_OK_READ) -#define TEST_OK_PRE (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_ERASE) -#define TEST_OK_PRW (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_WRITE) -#define TEST_OK_PREW (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_ERASE | TEST_OK_WRITE) -#define TEST_OK_MASK 0x0f - -#define TEST_BAD_PROBE (1 << 4) -#define TEST_BAD_READ (1 << 5) -#define TEST_BAD_ERASE (1 << 6) -#define TEST_BAD_WRITE (1 << 7) -#define TEST_BAD_PREW (TEST_BAD_PROBE | TEST_BAD_READ | TEST_BAD_ERASE | TEST_BAD_WRITE) -#define TEST_BAD_MASK 0xf0 - -/* Timing used in probe routines. ZERO is -2 to differentiate between an unset - * field and zero delay. - * - * SPI devices will always have zero delay and ignore this field. - */ -#define TIMING_FIXME -1 -/* this is intentionally same value as fixme */ -#define TIMING_IGNORED -1 -#define TIMING_ZERO -2 - -extern struct flashchip flashchips[]; - #if CONFIG_INTERNAL == 1 struct penable { uint16_t vendor_id; @@ -319,7 +178,6 @@ extern const struct board_info boards_known[]; extern const struct board_info laptops_known[]; - #endif /* udelay.c */ @@ -329,7 +187,6 @@ #if NEED_PCI == 1 /* pcidev.c */ - extern uint32_t io_base_addr; extern struct pci_access *pacc; extern struct pci_dev *pcidev_dev; @@ -345,12 +202,9 @@ #endif /* print.c */ -char *flashbuses_to_text(enum chipbustype bustype); -void print_supported(void); #if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1 void print_supported_pcidevs(const struct pcidev_status *devs); #endif -void print_supported_wiki(void); /* board_enable.c */ void w836xx_ext_enter(uint16_t port); @@ -566,12 +420,6 @@ int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); /* flashrom.c */ -enum write_granularity { - write_gran_1bit, - write_gran_1byte, - write_gran_256bytes, -}; -extern enum chipbustype buses_supported; struct decode_sizes { uint32_t parallel; uint32_t lpc; @@ -581,63 +429,12 @@ extern struct decode_sizes max_rom_decode; extern int programmer_may_write; extern unsigned long flashbase; -extern int verbose; -extern const char * const flashrom_version; -extern char *chip_to_probe; -void map_flash_registers(struct flashchip *flash); -int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); -int erase_flash(struct flashchip *flash); -struct flashchip *probe_flash(struct flashchip *first_flash, int force); -int read_flash_to_file(struct flashchip *flash, char *filename); void check_chip_supported(struct flashchip *flash); int check_max_decode(enum chipbustype buses, uint32_t size); -int min(int a, int b); -int max(int a, int b); -char *extract_param(char **haystack, char *needle, char *delim); char *extract_programmer_param(char *param_name); -int check_erased_range(struct flashchip *flash, int start, int len); -int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, char *message); -int need_erase(uint8_t *have, uint8_t *want, int len, enum write_granularity gran); -char *strcat_realloc(char *dest, const char *src); -void print_version(void); -void print_banner(void); -int selfcheck(void); -int doit(struct flashchip *flash, int force, char *filename, int read_it, int write_it, int erase_it, int verify_it); -#define OK 0 -#define NT 1 /* Not tested */ - -/* Something happened that shouldn't happen, but we can go on */ -#define ERROR_NONFATAL 0x100 - -/* cli_output.c */ -/* Let gcc and clang check for correct printf-style format strings. */ -int print(int type, const char *fmt, ...) __attribute__((format(printf, 2, 3))); -#define MSG_ERROR 0 -#define MSG_INFO 1 -#define MSG_DEBUG 2 -#define MSG_BARF 3 -#define msg_gerr(...) print(MSG_ERROR, __VA_ARGS__) /* general errors */ -#define msg_perr(...) print(MSG_ERROR, __VA_ARGS__) /* programmer errors */ -#define msg_cerr(...) print(MSG_ERROR, __VA_ARGS__) /* chip errors */ -#define msg_ginfo(...) print(MSG_INFO, __VA_ARGS__) /* general info */ -#define msg_pinfo(...) print(MSG_INFO, __VA_ARGS__) /* programmer info */ -#define msg_cinfo(...) print(MSG_INFO, __VA_ARGS__) /* chip info */ -#define msg_gdbg(...) print(MSG_DEBUG, __VA_ARGS__) /* general debug */ -#define msg_pdbg(...) print(MSG_DEBUG, __VA_ARGS__) /* programmer debug */ -#define msg_cdbg(...) print(MSG_DEBUG, __VA_ARGS__) /* chip debug */ -#define msg_gspew(...) print(MSG_BARF, __VA_ARGS__) /* general debug barf */ -#define msg_pspew(...) print(MSG_BARF, __VA_ARGS__) /* programmer debug barf */ -#define msg_cspew(...) print(MSG_BARF, __VA_ARGS__) /* chip debug barf */ - -/* cli_classic.c */ -int cli_classic(int argc, char *argv[]); - /* layout.c */ int show_id(uint8_t *bios, int size, int force); -int read_romlayout(char *name); -int find_romentry(char *name); -int handle_romentries(uint8_t *buffer, struct flashchip *flash); /* spi.c */ enum spi_controller { @@ -670,12 +467,6 @@ SPI_CONTROLLER_INVALID /* This must always be the last entry. */ }; extern const int spi_programmer_count; -struct spi_command { - unsigned int writecnt; - unsigned int readcnt; - const unsigned char *writearr; - unsigned char *readarr; -}; struct spi_programmer { int (*command)(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); @@ -688,13 +479,9 @@ extern enum spi_controller spi_controller; extern const struct spi_programmer spi_programmer[]; -int spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int spi_send_multicommand(struct spi_command *cmds); int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int default_spi_send_multicommand(struct spi_command *cmds); -uint32_t spi_get_valid_read_addr(void); /* ichspi.c */ #if CONFIG_INTERNAL == 1 @@ -760,4 +547,4 @@ int serialport_write(unsigned char *buf, unsigned int writecnt); int serialport_read(unsigned char *buf, unsigned int readcnt); -#endif /* !__FLASH_H__ */ +#endif /* !__PROGRAMMER_H__ */ Index: flashrom-programmer_h/print.c =================================================================== --- flashrom-programmer_h/print.c (Revision 1108) +++ flashrom-programmer_h/print.c (Arbeitskopie) @@ -24,6 +24,7 @@ #include <stdlib.h> #include "flash.h" #include "flashchips.h" +#include "programmer.h" /* * Return a string corresponding to the bustype parameter. Index: flashrom-programmer_h/board_enable.c =================================================================== --- flashrom-programmer_h/board_enable.c (Revision 1108) +++ flashrom-programmer_h/board_enable.c (Arbeitskopie) @@ -26,6 +26,7 @@ #include <string.h> #include "flash.h" +#include "programmer.h" #if defined(__i386__) || defined(__x86_64__) /* -- http://www.hailfinger.org/

2 2

[commit] r1112 - trunk
by repository service 28 Jul '10

28 Jul '10

Author: hailfinger Date: Wed Jul 28 00:41:39 2010 New Revision: 1112 URL: http://flashrom.org/trac/coreboot/changeset/1112 Log: Split off programmer.h from flash.h. Programmer specific functions are of absolutely no interest to any file except those dealing with programmer specific actions (special SPI commands and the generic core). The new header structure is as follows (and yes, improvements are possible): flashchips.h flash chip IDs chipdrivers.h chip-specific read/write/... functions flash.h common header for all stuff that doesn't fit elsewhere hwaccess.h hardware access functions programmer.h programmer specific functions coreboot_tables.h header from coreboot, internal programmer only spi.h SPI command definitions Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/programmer.h - copied, changed from r1111, trunk/flash.h Modified: trunk/atahpt.c trunk/bitbang_spi.c trunk/board_enable.c trunk/buspirate_spi.c trunk/cbtable.c trunk/chipset_enable.c trunk/cli_classic.c trunk/dediprog.c trunk/dmi.c trunk/drkaiser.c trunk/dummyflasher.c trunk/flash.h trunk/flashrom.c trunk/ft2232_spi.c trunk/gfxnvidia.c trunk/ichspi.c trunk/internal.c trunk/it87spi.c trunk/layout.c trunk/nic3com.c trunk/nicnatsemi.c trunk/nicrealtek.c trunk/pcidev.c trunk/print.c trunk/print_wiki.c trunk/processor_enable.c trunk/rayer_spi.c trunk/satasii.c trunk/sb600spi.c trunk/serial.c trunk/serprog.c trunk/spi.c trunk/spi25.c trunk/wbsio_spi.c Modified: trunk/atahpt.c ============================================================================== --- trunk/atahpt.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/atahpt.c Wed Jul 28 00:41:39 2010 (r1112) @@ -22,6 +22,7 @@ #include <string.h> #include <sys/types.h> #include "flash.h" +#include "programmer.h" #define BIOS_ROM_ADDR 0x90 #define BIOS_ROM_DATA 0x94 Modified: trunk/bitbang_spi.c ============================================================================== --- trunk/bitbang_spi.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/bitbang_spi.c Wed Jul 28 00:41:39 2010 (r1112) @@ -24,6 +24,7 @@ #include <ctype.h> #include "flash.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" /* Length of half a clock period in usecs. */ Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/board_enable.c Wed Jul 28 00:41:39 2010 (r1112) @@ -26,6 +26,7 @@ #include <string.h> #include "flash.h" +#include "programmer.h" #if defined(__i386__) || defined(__x86_64__) /* Modified: trunk/buspirate_spi.c ============================================================================== --- trunk/buspirate_spi.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/buspirate_spi.c Wed Jul 28 00:41:39 2010 (r1112) @@ -24,6 +24,7 @@ #include <ctype.h> #include "flash.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" /* Change this to #define if you want to test without a serial implementation */ Modified: trunk/cbtable.c ============================================================================== --- trunk/cbtable.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/cbtable.c Wed Jul 28 00:41:39 2010 (r1112) @@ -28,6 +28,7 @@ #include <sys/types.h> #include <string.h> #include "flash.h" +#include "programmer.h" #include "coreboot_tables.h" char *lb_part = NULL, *lb_vendor = NULL; Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/chipset_enable.c Wed Jul 28 00:41:39 2010 (r1112) @@ -32,6 +32,7 @@ #include <sys/types.h> #include <unistd.h> #include "flash.h" +#include "programmer.h" #define NOT_DONE_YET 1 Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/cli_classic.c Wed Jul 28 00:41:39 2010 (r1112) @@ -30,6 +30,7 @@ #include <getopt.h> #include "flash.h" #include "flashchips.h" +#include "programmer.h" static void cli_classic_usage(const char *name) { Modified: trunk/dediprog.c ============================================================================== --- trunk/dediprog.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/dediprog.c Wed Jul 28 00:41:39 2010 (r1112) @@ -21,6 +21,7 @@ #include <usb.h> #include "flash.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" #define DEFAULT_TIMEOUT 3000 Modified: trunk/dmi.c ============================================================================== --- trunk/dmi.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/dmi.c Wed Jul 28 00:41:39 2010 (r1112) @@ -23,6 +23,7 @@ #include <stdlib.h> #include "flash.h" +#include "programmer.h" int has_dmi_support = 0; Modified: trunk/drkaiser.c ============================================================================== --- trunk/drkaiser.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/drkaiser.c Wed Jul 28 00:41:39 2010 (r1112) @@ -20,6 +20,7 @@ #include <stdlib.h> #include "flash.h" +#include "programmer.h" #define PCI_VENDOR_ID_DRKAISER 0x1803 Modified: trunk/dummyflasher.c ============================================================================== --- trunk/dummyflasher.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/dummyflasher.c Wed Jul 28 00:41:39 2010 (r1112) @@ -24,6 +24,7 @@ #include <sys/types.h> #include "flash.h" #include "chipdrivers.h" +#include "programmer.h" static void tolower_string(char *str) { Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/flash.h Wed Jul 28 00:41:39 2010 (r1112) @@ -35,88 +35,7 @@ typedef unsigned long chipaddr; -enum programmer { -#if CONFIG_INTERNAL == 1 - PROGRAMMER_INTERNAL, -#endif -#if CONFIG_DUMMY == 1 - PROGRAMMER_DUMMY, -#endif -#if CONFIG_NIC3COM == 1 - PROGRAMMER_NIC3COM, -#endif -#if CONFIG_NICREALTEK == 1 - PROGRAMMER_NICREALTEK, - PROGRAMMER_NICREALTEK2, -#endif -#if CONFIG_NICNATSEMI == 1 - PROGRAMMER_NICNATSEMI, -#endif -#if CONFIG_GFXNVIDIA == 1 - PROGRAMMER_GFXNVIDIA, -#endif -#if CONFIG_DRKAISER == 1 - PROGRAMMER_DRKAISER, -#endif -#if CONFIG_SATASII == 1 - PROGRAMMER_SATASII, -#endif -#if CONFIG_ATAHPT == 1 - PROGRAMMER_ATAHPT, -#endif -#if CONFIG_INTERNAL == 1 -#if defined(__i386__) || defined(__x86_64__) - PROGRAMMER_IT87SPI, -#endif -#endif -#if CONFIG_FT2232_SPI == 1 - PROGRAMMER_FT2232_SPI, -#endif -#if CONFIG_SERPROG == 1 - PROGRAMMER_SERPROG, -#endif -#if CONFIG_BUSPIRATE_SPI == 1 - PROGRAMMER_BUSPIRATE_SPI, -#endif -#if CONFIG_DEDIPROG == 1 - PROGRAMMER_DEDIPROG, -#endif -#if CONFIG_RAYER_SPI == 1 - PROGRAMMER_RAYER_SPI, -#endif - PROGRAMMER_INVALID /* This must always be the last entry. */ -}; - -extern enum programmer programmer; - -struct programmer_entry { - const char *vendor; - const char *name; - - int (*init) (void); - int (*shutdown) (void); - - void * (*map_flash_region) (const char *descr, unsigned long phys_addr, - size_t len); - void (*unmap_flash_region) (void *virt_addr, size_t len); - - void (*chip_writeb) (uint8_t val, chipaddr addr); - void (*chip_writew) (uint16_t val, chipaddr addr); - void (*chip_writel) (uint32_t val, chipaddr addr); - void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len); - uint8_t (*chip_readb) (const chipaddr addr); - uint16_t (*chip_readw) (const chipaddr addr); - uint32_t (*chip_readl) (const chipaddr addr); - void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len); - void (*delay) (int usecs); -}; - -extern const struct programmer_entry programmer_table[]; - int register_shutdown(void (*function) (void *data), void *data); - -int programmer_init(char *param); -int programmer_shutdown(void); void *programmer_map_flash_region(const char *descr, unsigned long phys_addr, size_t len); void programmer_unmap_flash_region(void *virt_addr, size_t len); @@ -130,23 +49,6 @@ void chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void programmer_delay(int usecs); -enum bitbang_spi_master_type { - BITBANG_SPI_INVALID = 0, /* This must always be the first entry. */ -#if CONFIG_RAYER_SPI == 1 - BITBANG_SPI_MASTER_RAYER, -#endif -}; - -struct bitbang_spi_master { - enum bitbang_spi_master_type type; - - /* Note that CS# is active low, so val=0 means the chip is active. */ - void (*set_cs) (int val); - void (*set_sck) (int val); - void (*set_mosi) (int val); - int (*get_miso) (void); -}; - #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) enum chipbustype { @@ -263,316 +165,11 @@ extern struct flashchip flashchips[]; -#if CONFIG_INTERNAL == 1 -struct penable { - uint16_t vendor_id; - uint16_t device_id; - int status; - const char *vendor_name; - const char *device_name; - int (*doit) (struct pci_dev *dev, const char *name); -}; - -extern const struct penable chipset_enables[]; - -struct board_pciid_enable { - /* Any device, but make it sensible, like the ISA bridge. */ - uint16_t first_vendor; - uint16_t first_device; - uint16_t first_card_vendor; - uint16_t first_card_device; - - /* Any device, but make it sensible, like - * the host bridge. May be NULL. - */ - uint16_t second_vendor; - uint16_t second_device; - uint16_t second_card_vendor; - uint16_t second_card_device; - - /* Pattern to match DMI entries */ - const char *dmi_pattern; - - /* The vendor / part name from the coreboot table. */ - const char *lb_vendor; - const char *lb_part; - - const char *vendor_name; - const char *board_name; - - int max_rom_decode_parallel; - int status; - int (*enable) (void); -}; - -extern const struct board_pciid_enable board_pciid_enables[]; - -struct board_info { - const char *vendor; - const char *name; - const int working; -#ifdef CONFIG_PRINT_WIKI - const char *url; - const char *note; -#endif -}; - -extern const struct board_info boards_known[]; -extern const struct board_info laptops_known[]; - -#endif - -/* udelay.c */ -void myusec_delay(int usecs); -void myusec_calibrate_delay(void); -void internal_delay(int usecs); - -#if NEED_PCI == 1 -/* pcidev.c */ - -extern uint32_t io_base_addr; -extern struct pci_access *pacc; -extern struct pci_dev *pcidev_dev; -struct pcidev_status { - uint16_t vendor_id; - uint16_t device_id; - int status; - const char *vendor_name; - const char *device_name; -}; -uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, const struct pcidev_status *devs); -uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, const struct pcidev_status *devs); -#endif - /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); void print_supported(void); -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1 -void print_supported_pcidevs(const struct pcidev_status *devs); -#endif void print_supported_wiki(void); -/* board_enable.c */ -void w836xx_ext_enter(uint16_t port); -void w836xx_ext_leave(uint16_t port); -int it8705f_write_enable(uint8_t port); -uint8_t sio_read(uint16_t port, uint8_t reg); -void sio_write(uint16_t port, uint8_t reg, uint8_t data); -void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); -int board_flash_enable(const char *vendor, const char *part); - -/* chipset_enable.c */ -int chipset_flash_enable(void); - -/* processor_enable.c */ -int processor_flash_enable(void); - -/* physmap.c */ -void *physmap(const char *descr, unsigned long phys_addr, size_t len); -void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len); -void physunmap(void *virt_addr, size_t len); -int setup_cpu_msr(int cpu); -void cleanup_cpu_msr(void); - -/* cbtable.c */ -void lb_vendor_dev_from_string(char *boardstring); -int coreboot_init(void); -extern char *lb_part, *lb_vendor; -extern int partvendor_from_cbtable; - -/* dmi.c */ -extern int has_dmi_support; -void dmi_init(void); -int dmi_match(const char *pattern); - -/* internal.c */ -#if NEED_PCI == 1 -struct superio { - uint16_t vendor; - uint16_t port; - uint16_t model; -}; -extern struct superio superio; -#define SUPERIO_VENDOR_NONE 0x0 -#define SUPERIO_VENDOR_ITE 0x1 -struct pci_dev *pci_dev_find_filter(struct pci_filter filter); -struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class); -struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); -struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device, - uint16_t card_vendor, uint16_t card_device); -#endif -void get_io_perms(void); -void release_io_perms(void); -#if CONFIG_INTERNAL == 1 -extern int is_laptop; -extern int force_boardenable; -extern int force_boardmismatch; -void probe_superio(void); -int internal_init(void); -int internal_shutdown(void); -void internal_chip_writeb(uint8_t val, chipaddr addr); -void internal_chip_writew(uint16_t val, chipaddr addr); -void internal_chip_writel(uint32_t val, chipaddr addr); -uint8_t internal_chip_readb(const chipaddr addr); -uint16_t internal_chip_readw(const chipaddr addr); -uint32_t internal_chip_readl(const chipaddr addr); -void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -#endif - -/* hwaccess.c */ -void mmio_writeb(uint8_t val, void *addr); -void mmio_writew(uint16_t val, void *addr); -void mmio_writel(uint32_t val, void *addr); -uint8_t mmio_readb(void *addr); -uint16_t mmio_readw(void *addr); -uint32_t mmio_readl(void *addr); -void mmio_le_writeb(uint8_t val, void *addr); -void mmio_le_writew(uint16_t val, void *addr); -void mmio_le_writel(uint32_t val, void *addr); -uint8_t mmio_le_readb(void *addr); -uint16_t mmio_le_readw(void *addr); -uint32_t mmio_le_readl(void *addr); -#define pci_mmio_writeb mmio_le_writeb -#define pci_mmio_writew mmio_le_writew -#define pci_mmio_writel mmio_le_writel -#define pci_mmio_readb mmio_le_readb -#define pci_mmio_readw mmio_le_readw -#define pci_mmio_readl mmio_le_readl - -/* programmer.c */ -int noop_shutdown(void); -void *fallback_map(const char *descr, unsigned long phys_addr, size_t len); -void fallback_unmap(void *virt_addr, size_t len); -uint8_t noop_chip_readb(const chipaddr addr); -void noop_chip_writeb(uint8_t val, chipaddr addr); -void fallback_chip_writew(uint16_t val, chipaddr addr); -void fallback_chip_writel(uint32_t val, chipaddr addr); -void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len); -uint16_t fallback_chip_readw(const chipaddr addr); -uint32_t fallback_chip_readl(const chipaddr addr); -void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); - -/* dummyflasher.c */ -#if CONFIG_DUMMY == 1 -int dummy_init(void); -int dummy_shutdown(void); -void *dummy_map(const char *descr, unsigned long phys_addr, size_t len); -void dummy_unmap(void *virt_addr, size_t len); -void dummy_chip_writeb(uint8_t val, chipaddr addr); -void dummy_chip_writew(uint16_t val, chipaddr addr); -void dummy_chip_writel(uint32_t val, chipaddr addr); -void dummy_chip_writen(uint8_t *buf, chipaddr addr, size_t len); -uint8_t dummy_chip_readb(const chipaddr addr); -uint16_t dummy_chip_readw(const chipaddr addr); -uint32_t dummy_chip_readl(const chipaddr addr); -void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); -#endif - -/* nic3com.c */ -#if CONFIG_NIC3COM == 1 -int nic3com_init(void); -int nic3com_shutdown(void); -void nic3com_chip_writeb(uint8_t val, chipaddr addr); -uint8_t nic3com_chip_readb(const chipaddr addr); -extern const struct pcidev_status nics_3com[]; -#endif - -/* gfxnvidia.c */ -#if CONFIG_GFXNVIDIA == 1 -int gfxnvidia_init(void); -int gfxnvidia_shutdown(void); -void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr); -uint8_t gfxnvidia_chip_readb(const chipaddr addr); -extern const struct pcidev_status gfx_nvidia[]; -#endif - -/* drkaiser.c */ -#if CONFIG_DRKAISER == 1 -int drkaiser_init(void); -int drkaiser_shutdown(void); -void drkaiser_chip_writeb(uint8_t val, chipaddr addr); -uint8_t drkaiser_chip_readb(const chipaddr addr); -extern const struct pcidev_status drkaiser_pcidev[]; -#endif - -/* nicrealtek.c */ -#if CONFIG_NICREALTEK == 1 -int nicrealtek_init(void); -int nicsmc1211_init(void); -int nicrealtek_shutdown(void); -void nicrealtek_chip_writeb(uint8_t val, chipaddr addr); -uint8_t nicrealtek_chip_readb(const chipaddr addr); -extern const struct pcidev_status nics_realtek[]; -extern const struct pcidev_status nics_realteksmc1211[]; -#endif - -/* nicnatsemi.c */ -#if CONFIG_NICNATSEMI == 1 -int nicnatsemi_init(void); -int nicnatsemi_shutdown(void); -void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr); -uint8_t nicnatsemi_chip_readb(const chipaddr addr); -extern const struct pcidev_status nics_natsemi[]; -#endif - -/* satasii.c */ -#if CONFIG_SATASII == 1 -int satasii_init(void); -int satasii_shutdown(void); -void satasii_chip_writeb(uint8_t val, chipaddr addr); -uint8_t satasii_chip_readb(const chipaddr addr); -extern const struct pcidev_status satas_sii[]; -#endif - -/* atahpt.c */ -#if CONFIG_ATAHPT == 1 -int atahpt_init(void); -int atahpt_shutdown(void); -void atahpt_chip_writeb(uint8_t val, chipaddr addr); -uint8_t atahpt_chip_readb(const chipaddr addr); -extern const struct pcidev_status ata_hpt[]; -#endif - -/* ft2232_spi.c */ -#define FTDI_FT2232H 0x6010 -#define FTDI_FT4232H 0x6011 -int ft2232_spi_init(void); -int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); - -/* rayer_spi.c */ -#if CONFIG_RAYER_SPI == 1 -int rayer_spi_init(void); -#endif - -/* bitbang_spi.c */ -int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); -int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); - -/* buspirate_spi.c */ -struct buspirate_spispeeds { - const char *name; - const int speed; -}; -int buspirate_spi_init(void); -int buspirate_spi_shutdown(void); -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); - -/* dediprog.c */ -int dediprog_init(void); -int dediprog_shutdown(void); -int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); - /* flashrom.c */ enum write_granularity { write_gran_1bit, @@ -580,15 +177,6 @@ write_gran_256bytes, }; extern enum chipbustype buses_supported; -struct decode_sizes { - uint32_t parallel; - uint32_t lpc; - uint32_t fwh; - uint32_t spi; -}; -extern struct decode_sizes max_rom_decode; -extern int programmer_may_write; -extern unsigned long flashbase; extern int verbose; extern const char * const flashrom_version; extern char *chip_to_probe; @@ -597,12 +185,9 @@ int erase_flash(struct flashchip *flash); struct flashchip *probe_flash(struct flashchip *first_flash, int force); int read_flash_to_file(struct flashchip *flash, char *filename); -void check_chip_supported(struct flashchip *flash); -int check_max_decode(enum chipbustype buses, uint32_t size); int min(int a, int b); int max(int a, int b); char *extract_param(char **haystack, char *needle, char *delim); -char *extract_programmer_param(char *param_name); int check_erased_range(struct flashchip *flash, int start, int len); int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, char *message); int need_erase(uint8_t *have, uint8_t *want, int len, enum write_granularity gran); @@ -642,130 +227,20 @@ int cli_classic(int argc, char *argv[]); /* layout.c */ -int show_id(uint8_t *bios, int size, int force); int read_romlayout(char *name); int find_romentry(char *name); int handle_romentries(uint8_t *buffer, struct flashchip *flash); /* spi.c */ -enum spi_controller { - SPI_CONTROLLER_NONE, -#if CONFIG_INTERNAL == 1 -#if defined(__i386__) || defined(__x86_64__) - SPI_CONTROLLER_ICH7, - SPI_CONTROLLER_ICH9, - SPI_CONTROLLER_IT87XX, - SPI_CONTROLLER_SB600, - SPI_CONTROLLER_VIA, - SPI_CONTROLLER_WBSIO, -#endif -#endif -#if CONFIG_FT2232_SPI == 1 - SPI_CONTROLLER_FT2232, -#endif -#if CONFIG_DUMMY == 1 - SPI_CONTROLLER_DUMMY, -#endif -#if CONFIG_BUSPIRATE_SPI == 1 - SPI_CONTROLLER_BUSPIRATE, -#endif -#if CONFIG_DEDIPROG == 1 - SPI_CONTROLLER_DEDIPROG, -#endif -#if CONFIG_RAYER_SPI == 1 - SPI_CONTROLLER_RAYER, -#endif - SPI_CONTROLLER_INVALID /* This must always be the last entry. */ -}; -extern const int spi_programmer_count; struct spi_command { unsigned int writecnt; unsigned int readcnt; const unsigned char *writearr; unsigned char *readarr; }; -struct spi_programmer { - int (*command)(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); - int (*multicommand)(struct spi_command *cmds); - - /* Optimized functions for this programmer */ - int (*read)(struct flashchip *flash, uint8_t *buf, int start, int len); - int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len); -}; - -extern enum spi_controller spi_controller; -extern const struct spi_programmer spi_programmer[]; int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int spi_send_multicommand(struct spi_command *cmds); -int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int default_spi_send_multicommand(struct spi_command *cmds); uint32_t spi_get_valid_read_addr(void); -/* ichspi.c */ -#if CONFIG_INTERNAL == 1 -extern uint32_t ichspi_bbar; -int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, - int ich_generation); -int via_init_spi(struct pci_dev *dev); -int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len); -int ich_spi_send_multicommand(struct spi_command *cmds); -#endif - -/* it87spi.c */ -void enter_conf_mode_ite(uint16_t port); -void exit_conf_mode_ite(uint16_t port); -struct superio probe_superio_ite(void); -int init_superio_ite(void); -int it87spi_init(void); -int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); - -/* sb600spi.c */ -#if CONFIG_INTERNAL == 1 -int sb600_probe_spi(struct pci_dev *dev); -int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); -#endif - -/* wbsio_spi.c */ -#if CONFIG_INTERNAL == 1 -int wbsio_check_for_spi(void); -int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -#endif - -/* serprog.c */ -int serprog_init(void); -int serprog_shutdown(void); -void serprog_chip_writeb(uint8_t val, chipaddr addr); -uint8_t serprog_chip_readb(const chipaddr addr); -void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -void serprog_delay(int delay); - -/* serial.c */ -#if _WIN32 -typedef HANDLE fdtype; -#else -typedef int fdtype; -#endif - -void sp_flush_incoming(void); -fdtype sp_openserport(char *dev, unsigned int baud); -void __attribute__((noreturn)) sp_die(char *msg); -extern fdtype sp_fd; -int serialport_shutdown(void); -int serialport_write(unsigned char *buf, unsigned int writecnt); -int serialport_read(unsigned char *buf, unsigned int readcnt); - #endif /* !__FLASH_H__ */ Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/flashrom.c Wed Jul 28 00:41:39 2010 (r1112) @@ -33,6 +33,7 @@ #endif #include "flash.h" #include "flashchips.h" +#include "programmer.h" const char * const flashrom_version = FLASHROM_VERSION; char *chip_to_probe = NULL; Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/ft2232_spi.c Wed Jul 28 00:41:39 2010 (r1112) @@ -27,6 +27,7 @@ #include <ctype.h> #include "flash.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" #include <ftdi.h> Modified: trunk/gfxnvidia.c ============================================================================== --- trunk/gfxnvidia.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/gfxnvidia.c Wed Jul 28 00:41:39 2010 (r1112) @@ -22,6 +22,7 @@ #include <string.h> #include <sys/types.h> #include "flash.h" +#include "programmer.h" #define PCI_VENDOR_ID_NVIDIA 0x10de Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/ichspi.c Wed Jul 28 00:41:39 2010 (r1112) @@ -38,6 +38,7 @@ #include <string.h> #include "flash.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" /* ICH9 controller register definition */ Modified: trunk/internal.c ============================================================================== --- trunk/internal.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/internal.c Wed Jul 28 00:41:39 2010 (r1112) @@ -23,6 +23,7 @@ #include <stdlib.h> #include <sys/types.h> #include "flash.h" +#include "programmer.h" #if NEED_PCI == 1 struct pci_dev *pci_dev_find_filter(struct pci_filter filter) Modified: trunk/it87spi.c ============================================================================== --- trunk/it87spi.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/it87spi.c Wed Jul 28 00:41:39 2010 (r1112) @@ -29,6 +29,7 @@ #include <stdlib.h> #include "flash.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" #define ITE_SUPERIO_PORT1 0x2e Modified: trunk/layout.c ============================================================================== --- trunk/layout.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/layout.c Wed Jul 28 00:41:39 2010 (r1112) @@ -23,6 +23,7 @@ #include <string.h> #include <ctype.h> #include "flash.h" +#include "programmer.h" #if CONFIG_INTERNAL == 1 char *mainboard_vendor = NULL; Modified: trunk/nic3com.c ============================================================================== --- trunk/nic3com.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/nic3com.c Wed Jul 28 00:41:39 2010 (r1112) @@ -22,6 +22,7 @@ #include <stdlib.h> #include "flash.h" +#include "programmer.h" #define BIOS_ROM_ADDR 0x04 #define BIOS_ROM_DATA 0x08 Modified: trunk/nicnatsemi.c ============================================================================== --- trunk/nicnatsemi.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/nicnatsemi.c Wed Jul 28 00:41:39 2010 (r1112) @@ -22,6 +22,7 @@ #include <stdlib.h> #include "flash.h" +#include "programmer.h" #define PCI_VENDOR_ID_NATSEMI 0x100b Modified: trunk/nicrealtek.c ============================================================================== --- trunk/nicrealtek.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/nicrealtek.c Wed Jul 28 00:41:39 2010 (r1112) @@ -22,6 +22,7 @@ #include <stdlib.h> #include "flash.h" +#include "programmer.h" #define PCI_VENDOR_ID_REALTEK 0x10ec #define PCI_VENDOR_ID_SMC1211 0x1113 Modified: trunk/pcidev.c ============================================================================== --- trunk/pcidev.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/pcidev.c Wed Jul 28 00:41:39 2010 (r1112) @@ -22,6 +22,7 @@ #include <string.h> #include <sys/types.h> #include "flash.h" +#include "programmer.h" uint32_t io_base_addr; struct pci_access *pacc; Modified: trunk/print.c ============================================================================== --- trunk/print.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/print.c Wed Jul 28 00:41:39 2010 (r1112) @@ -24,6 +24,7 @@ #include <stdlib.h> #include "flash.h" #include "flashchips.h" +#include "programmer.h" /* * Return a string corresponding to the bustype parameter. Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/print_wiki.c Wed Jul 28 00:41:39 2010 (r1112) @@ -25,6 +25,7 @@ #include <time.h> #include "flash.h" #include "flashchips.h" +#include "programmer.h" static const char * const wiki_header = "= Supported devices =\n\n\ <div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ Modified: trunk/processor_enable.c ============================================================================== --- trunk/processor_enable.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/processor_enable.c Wed Jul 28 00:41:39 2010 (r1112) @@ -22,6 +22,7 @@ */ #include "flash.h" +#include "programmer.h" #if defined(__i386__) || defined(__x86_64__) Copied and modified: trunk/programmer.h (from r1111, trunk/flash.h) ============================================================================== --- trunk/flash.h Wed Jul 28 00:03:46 2010 (r1111, copy source) +++ trunk/programmer.h Wed Jul 28 00:41:39 2010 (r1112) @@ -21,19 +21,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __FLASH_H__ -#define __FLASH_H__ 1 - -#include <stdint.h> -#include <stddef.h> -#include "hwaccess.h" -#ifdef _WIN32 -#include <windows.h> -#undef min -#undef max -#endif - -typedef unsigned long chipaddr; +#ifndef __PROGRAMMER_H__ +#define __PROGRAMMER_H__ 1 enum programmer { #if CONFIG_INTERNAL == 1 @@ -113,22 +102,8 @@ extern const struct programmer_entry programmer_table[]; -int register_shutdown(void (*function) (void *data), void *data); - int programmer_init(char *param); int programmer_shutdown(void); -void *programmer_map_flash_region(const char *descr, unsigned long phys_addr, - size_t len); -void programmer_unmap_flash_region(void *virt_addr, size_t len); -void chip_writeb(uint8_t val, chipaddr addr); -void chip_writew(uint16_t val, chipaddr addr); -void chip_writel(uint32_t val, chipaddr addr); -void chip_writen(uint8_t *buf, chipaddr addr, size_t len); -uint8_t chip_readb(const chipaddr addr); -uint16_t chip_readw(const chipaddr addr); -uint32_t chip_readl(const chipaddr addr); -void chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -void programmer_delay(int usecs); enum bitbang_spi_master_type { BITBANG_SPI_INVALID = 0, /* This must always be the first entry. */ @@ -147,122 +122,6 @@ int (*get_miso) (void); }; -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) - -enum chipbustype { - CHIP_BUSTYPE_NONE = 0, - CHIP_BUSTYPE_PARALLEL = 1 << 0, - CHIP_BUSTYPE_LPC = 1 << 1, - CHIP_BUSTYPE_FWH = 1 << 2, - CHIP_BUSTYPE_SPI = 1 << 3, - CHIP_BUSTYPE_NONSPI = CHIP_BUSTYPE_PARALLEL | CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH, - CHIP_BUSTYPE_UNKNOWN = CHIP_BUSTYPE_PARALLEL | CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI, -}; - -/* - * How many different contiguous runs of erase blocks with one size each do - * we have for a given erase function? - */ -#define NUM_ERASEREGIONS 5 - -/* - * How many different erase functions do we have per chip? - */ -#define NUM_ERASEFUNCTIONS 5 - -#define FEATURE_REGISTERMAP (1 << 0) -#define FEATURE_BYTEWRITES (1 << 1) -#define FEATURE_LONG_RESET (0 << 4) -#define FEATURE_SHORT_RESET (1 << 4) -#define FEATURE_EITHER_RESET FEATURE_LONG_RESET -#define FEATURE_ADDR_FULL (0 << 2) -#define FEATURE_ADDR_MASK (3 << 2) -#define FEATURE_ADDR_2AA (1 << 2) -#define FEATURE_ADDR_AAA (2 << 2) -#define FEATURE_ADDR_SHIFTED (1 << 5) - -struct flashchip { - const char *vendor; - const char *name; - - enum chipbustype bustype; - - /* - * With 32bit manufacture_id and model_id we can cover IDs up to - * (including) the 4th bank of JEDEC JEP106W Standard Manufacturer's - * Identification code. - */ - uint32_t manufacture_id; - uint32_t model_id; - - int total_size; - int page_size; - int feature_bits; - - /* - * Indicate if flashrom has been tested with this flash chip and if - * everything worked correctly. - */ - uint32_t tested; - - int (*probe) (struct flashchip *flash); - - /* Delay after "enter/exit ID mode" commands in microseconds. */ - int probe_timing; - - /* - * Erase blocks and associated erase function. Any chip erase function - * is stored as chip-sized virtual block together with said function. - */ - struct block_eraser { - struct eraseblock{ - unsigned int size; /* Eraseblock size */ - unsigned int count; /* Number of contiguous blocks with that size */ - } eraseblocks[NUM_ERASEREGIONS]; - int (*block_erase) (struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); - } block_erasers[NUM_ERASEFUNCTIONS]; - - int (*printlock) (struct flashchip *flash); - int (*unlock) (struct flashchip *flash); - int (*write) (struct flashchip *flash, uint8_t *buf); - int (*read) (struct flashchip *flash, uint8_t *buf, int start, int len); - - /* Some flash devices have an additional register space. */ - chipaddr virtual_memory; - chipaddr virtual_registers; -}; - -#define TEST_UNTESTED 0 - -#define TEST_OK_PROBE (1 << 0) -#define TEST_OK_READ (1 << 1) -#define TEST_OK_ERASE (1 << 2) -#define TEST_OK_WRITE (1 << 3) -#define TEST_OK_PR (TEST_OK_PROBE | TEST_OK_READ) -#define TEST_OK_PRE (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_ERASE) -#define TEST_OK_PRW (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_WRITE) -#define TEST_OK_PREW (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_ERASE | TEST_OK_WRITE) -#define TEST_OK_MASK 0x0f - -#define TEST_BAD_PROBE (1 << 4) -#define TEST_BAD_READ (1 << 5) -#define TEST_BAD_ERASE (1 << 6) -#define TEST_BAD_WRITE (1 << 7) -#define TEST_BAD_PREW (TEST_BAD_PROBE | TEST_BAD_READ | TEST_BAD_ERASE | TEST_BAD_WRITE) -#define TEST_BAD_MASK 0xf0 - -/* Timing used in probe routines. ZERO is -2 to differentiate between an unset - * field and zero delay. - * - * SPI devices will always have zero delay and ignore this field. - */ -#define TIMING_FIXME -1 -/* this is intentionally same value as fixme */ -#define TIMING_IGNORED -1 -#define TIMING_ZERO -2 - -extern struct flashchip flashchips[]; - #if CONFIG_INTERNAL == 1 struct penable { uint16_t vendor_id; @@ -319,7 +178,6 @@ extern const struct board_info boards_known[]; extern const struct board_info laptops_known[]; - #endif /* udelay.c */ @@ -329,7 +187,6 @@ #if NEED_PCI == 1 /* pcidev.c */ - extern uint32_t io_base_addr; extern struct pci_access *pacc; extern struct pci_dev *pcidev_dev; @@ -345,12 +202,9 @@ #endif /* print.c */ -char *flashbuses_to_text(enum chipbustype bustype); -void print_supported(void); #if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1 void print_supported_pcidevs(const struct pcidev_status *devs); #endif -void print_supported_wiki(void); /* board_enable.c */ void w836xx_ext_enter(uint16_t port); @@ -574,12 +428,6 @@ int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); /* flashrom.c */ -enum write_granularity { - write_gran_1bit, - write_gran_1byte, - write_gran_256bytes, -}; -extern enum chipbustype buses_supported; struct decode_sizes { uint32_t parallel; uint32_t lpc; @@ -589,63 +437,12 @@ extern struct decode_sizes max_rom_decode; extern int programmer_may_write; extern unsigned long flashbase; -extern int verbose; -extern const char * const flashrom_version; -extern char *chip_to_probe; -void map_flash_registers(struct flashchip *flash); -int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); -int erase_flash(struct flashchip *flash); -struct flashchip *probe_flash(struct flashchip *first_flash, int force); -int read_flash_to_file(struct flashchip *flash, char *filename); void check_chip_supported(struct flashchip *flash); int check_max_decode(enum chipbustype buses, uint32_t size); -int min(int a, int b); -int max(int a, int b); -char *extract_param(char **haystack, char *needle, char *delim); char *extract_programmer_param(char *param_name); -int check_erased_range(struct flashchip *flash, int start, int len); -int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, char *message); -int need_erase(uint8_t *have, uint8_t *want, int len, enum write_granularity gran); -char *strcat_realloc(char *dest, const char *src); -void print_version(void); -void print_banner(void); -int selfcheck(void); -int doit(struct flashchip *flash, int force, char *filename, int read_it, int write_it, int erase_it, int verify_it); - -#define OK 0 -#define NT 1 /* Not tested */ - -/* Something happened that shouldn't happen, but we can go on */ -#define ERROR_NONFATAL 0x100 - -/* cli_output.c */ -/* Let gcc and clang check for correct printf-style format strings. */ -int print(int type, const char *fmt, ...) __attribute__((format(printf, 2, 3))); -#define MSG_ERROR 0 -#define MSG_INFO 1 -#define MSG_DEBUG 2 -#define MSG_BARF 3 -#define msg_gerr(...) print(MSG_ERROR, __VA_ARGS__) /* general errors */ -#define msg_perr(...) print(MSG_ERROR, __VA_ARGS__) /* programmer errors */ -#define msg_cerr(...) print(MSG_ERROR, __VA_ARGS__) /* chip errors */ -#define msg_ginfo(...) print(MSG_INFO, __VA_ARGS__) /* general info */ -#define msg_pinfo(...) print(MSG_INFO, __VA_ARGS__) /* programmer info */ -#define msg_cinfo(...) print(MSG_INFO, __VA_ARGS__) /* chip info */ -#define msg_gdbg(...) print(MSG_DEBUG, __VA_ARGS__) /* general debug */ -#define msg_pdbg(...) print(MSG_DEBUG, __VA_ARGS__) /* programmer debug */ -#define msg_cdbg(...) print(MSG_DEBUG, __VA_ARGS__) /* chip debug */ -#define msg_gspew(...) print(MSG_BARF, __VA_ARGS__) /* general debug barf */ -#define msg_pspew(...) print(MSG_BARF, __VA_ARGS__) /* programmer debug barf */ -#define msg_cspew(...) print(MSG_BARF, __VA_ARGS__) /* chip debug barf */ - -/* cli_classic.c */ -int cli_classic(int argc, char *argv[]); /* layout.c */ int show_id(uint8_t *bios, int size, int force); -int read_romlayout(char *name); -int find_romentry(char *name); -int handle_romentries(uint8_t *buffer, struct flashchip *flash); /* spi.c */ enum spi_controller { @@ -678,12 +475,6 @@ SPI_CONTROLLER_INVALID /* This must always be the last entry. */ }; extern const int spi_programmer_count; -struct spi_command { - unsigned int writecnt; - unsigned int readcnt; - const unsigned char *writearr; - unsigned char *readarr; -}; struct spi_programmer { int (*command)(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); @@ -696,13 +487,9 @@ extern enum spi_controller spi_controller; extern const struct spi_programmer spi_programmer[]; -int spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int spi_send_multicommand(struct spi_command *cmds); int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int default_spi_send_multicommand(struct spi_command *cmds); -uint32_t spi_get_valid_read_addr(void); /* ichspi.c */ #if CONFIG_INTERNAL == 1 @@ -768,4 +555,4 @@ int serialport_write(unsigned char *buf, unsigned int writecnt); int serialport_read(unsigned char *buf, unsigned int readcnt); -#endif /* !__FLASH_H__ */ +#endif /* !__PROGRAMMER_H__ */ Modified: trunk/rayer_spi.c ============================================================================== --- trunk/rayer_spi.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/rayer_spi.c Wed Jul 28 00:41:39 2010 (r1112) @@ -31,6 +31,7 @@ #if defined(__i386__) || defined(__x86_64__) #include "flash.h" +#include "programmer.h" /* We have two sets of pins, out and in. The numbers for both sets are * independent and are bitshift values, not real pin numbers. Modified: trunk/satasii.c ============================================================================== --- trunk/satasii.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/satasii.c Wed Jul 28 00:41:39 2010 (r1112) @@ -22,6 +22,7 @@ #include <stdlib.h> #include "flash.h" +#include "programmer.h" #define PCI_VENDOR_ID_SII 0x1095 Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/sb600spi.c Wed Jul 28 00:41:39 2010 (r1112) @@ -25,6 +25,7 @@ #include "flash.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" /* This struct is unused, but helps visualize the SB600 SPI BAR layout. Modified: trunk/serial.c ============================================================================== --- trunk/serial.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/serial.c Wed Jul 28 00:41:39 2010 (r1112) @@ -22,7 +22,6 @@ #include <stdio.h> #include <stdlib.h> #include <unistd.h> -#include "flash.h" #include <string.h> #include <ctype.h> #include <fcntl.h> @@ -35,6 +34,8 @@ #else #include <termios.h> #endif +#include "flash.h" +#include "programmer.h" fdtype sp_fd; Modified: trunk/serprog.c ============================================================================== --- trunk/serprog.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/serprog.c Wed Jul 28 00:41:39 2010 (r1112) @@ -22,7 +22,6 @@ #include <stdio.h> #include <stdlib.h> #include <unistd.h> -#include "flash.h" #include <string.h> #include <ctype.h> #include <fcntl.h> @@ -36,6 +35,8 @@ #include <errno.h> #include <inttypes.h> #include <termios.h> +#include "flash.h" +#include "programmer.h" #define MSGHEADER "serprog:" Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/spi.c Wed Jul 28 00:41:39 2010 (r1112) @@ -25,6 +25,7 @@ #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" enum spi_controller spi_controller = SPI_CONTROLLER_NONE; Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/spi25.c Wed Jul 28 00:41:39 2010 (r1112) @@ -26,6 +26,7 @@ #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" void spi_prettyprint_status_register(struct flashchip *flash); Modified: trunk/wbsio_spi.c ============================================================================== --- trunk/wbsio_spi.c Wed Jul 28 00:03:46 2010 (r1111) +++ trunk/wbsio_spi.c Wed Jul 28 00:41:39 2010 (r1112) @@ -22,6 +22,7 @@ #include "flash.h" #include "chipdrivers.h" +#include "programmer.h" #include "spi.h" #define WBSIO_PORT1 0x2e

1 0

[commit] r1111 - trunk
by repository service 28 Jul '10

28 Jul '10

Author: hailfinger Date: Wed Jul 28 00:03:46 2010 New Revision: 1111 URL: http://flashrom.org/trac/coreboot/changeset/1111 Log: Convert all PCI-based external programmers to use special little-endian accessors for all MMIO regions of PCI devices. This patch does _not_ touch the internal programmer (which is PCI-based as well). Huge thanks go to Misha Manulis who worked with me to create a first version of this patch for the satasii programmer based on modification of generic code. Huge thanks also go to Segher Boessenkool for suggesting the pci_mmio_ prefix for the abstraction layer. NOTE to package maintainers: With this patch, compilation and usage of flashrom should be safe on x86, x86_64, MIPS (little and big endian) and PowerPC (big endian). The internal programmer is disabled on non-x86/x86_64 (but it compiles). The atahpt, nic3com, nicnatsemi, nicrealtek and rayer_spi can not be compiled on non-x86/x86_64 because port space I/O is not (yet) supported. Please compile with default settings on x86/x86_64 and with the following settings on all other architectures: make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no CONFIG_NICNATSEMI=no CONFIG_RAYER_SPI=no Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Misha Manulis <misha(a)manulis.com> Modified: trunk/chipset_enable.c trunk/drkaiser.c trunk/flash.h trunk/gfxnvidia.c trunk/satasii.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Wed Jul 28 00:00:42 2010 (r1110) +++ trunk/chipset_enable.c Wed Jul 28 00:03:46 2010 (r1111) @@ -33,10 +33,10 @@ #include <unistd.h> #include "flash.h" -#if defined(__i386__) || defined(__x86_64__) - #define NOT_DONE_YET 1 +#if defined(__i386__) || defined(__x86_64__) + static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) { uint8_t tmp; Modified: trunk/drkaiser.c ============================================================================== --- trunk/drkaiser.c Wed Jul 28 00:00:42 2010 (r1110) +++ trunk/drkaiser.c Wed Jul 28 00:03:46 2010 (r1111) @@ -69,10 +69,10 @@ void drkaiser_chip_writeb(uint8_t val, chipaddr addr) { - mmio_writeb(val, drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK)); + pci_mmio_writeb(val, drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK)); } uint8_t drkaiser_chip_readb(const chipaddr addr) { - return mmio_readb(drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK)); + return pci_mmio_readb(drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK)); } Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Wed Jul 28 00:00:42 2010 (r1110) +++ trunk/flash.h Wed Jul 28 00:03:46 2010 (r1111) @@ -418,6 +418,8 @@ uint32_t internal_chip_readl(const chipaddr addr); void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); #endif + +/* hwaccess.c */ void mmio_writeb(uint8_t val, void *addr); void mmio_writew(uint16_t val, void *addr); void mmio_writel(uint32_t val, void *addr); @@ -430,6 +432,12 @@ uint8_t mmio_le_readb(void *addr); uint16_t mmio_le_readw(void *addr); uint32_t mmio_le_readl(void *addr); +#define pci_mmio_writeb mmio_le_writeb +#define pci_mmio_writew mmio_le_writew +#define pci_mmio_writel mmio_le_writel +#define pci_mmio_readb mmio_le_readb +#define pci_mmio_readw mmio_le_readw +#define pci_mmio_readl mmio_le_readl /* programmer.c */ int noop_shutdown(void); Modified: trunk/gfxnvidia.c ============================================================================== --- trunk/gfxnvidia.c Wed Jul 28 00:00:42 2010 (r1110) +++ trunk/gfxnvidia.c Wed Jul 28 00:03:46 2010 (r1111) @@ -100,10 +100,10 @@ void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr) { - mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); + pci_mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); } uint8_t gfxnvidia_chip_readb(const chipaddr addr) { - return mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); + return pci_mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); } Modified: trunk/satasii.c ============================================================================== --- trunk/satasii.c Wed Jul 28 00:00:42 2010 (r1110) +++ trunk/satasii.c Wed Jul 28 00:03:46 2010 (r1111) @@ -61,7 +61,7 @@ sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset; /* Check if ROM cycle are OK. */ - if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26)))) + if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26)))) msg_pinfo("Warning: Flash seems unconnected.\n"); buses_supported = CHIP_BUSTYPE_PARALLEL; @@ -80,32 +80,32 @@ { uint32_t ctrl_reg, data_reg; - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = pci_mmio_readl(sii_bar)) & (1 << 25)) ; /* Mask out unused/reserved bits, set writes and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff); - data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val; - mmio_writel(data_reg, (sii_bar + 4)); - mmio_writel(ctrl_reg, sii_bar); + data_reg = (pci_mmio_readl((sii_bar + 4)) & ~0xff) | val; + pci_mmio_writel(data_reg, (sii_bar + 4)); + pci_mmio_writel(ctrl_reg, sii_bar); - while (mmio_readl(sii_bar) & (1 << 25)) ; + while (pci_mmio_readl(sii_bar) & (1 << 25)) ; } uint8_t satasii_chip_readb(const chipaddr addr) { uint32_t ctrl_reg; - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = pci_mmio_readl(sii_bar)) & (1 << 25)) ; /* Mask out unused/reserved bits, set reads and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff); - mmio_writel(ctrl_reg, sii_bar); + pci_mmio_writel(ctrl_reg, sii_bar); - while (mmio_readl(sii_bar) & (1 << 25)) ; + while (pci_mmio_readl(sii_bar) & (1 << 25)) ; - return (mmio_readl(sii_bar + 4)) & 0xff; + return (pci_mmio_readl(sii_bar + 4)) & 0xff; }

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[PATCH] Add a udev rules file for flashrom
by Uwe Hermann 28 Jul '10

28 Jul '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r1110 - trunk/util
by repository service 28 Jul '10

28 Jul '10

Author: uwe Date: Wed Jul 28 00:00:42 2010 New Revision: 1110 URL: http://flashrom.org/trac/coreboot/changeset/1110 Log: Add a udev rules file for flashrom. This allows USB-based external programmers to be used by non-root users (which are in the 'plugdev' group). The file is to be installed by the distros into the proper place (not sure if this is distro-specific). On Debian the file will end up in /etc/udev/rules.d/z60_flashrom.rules. On some systems the 'plugdev' group might have to adapted to whatever the respective distro uses. The following devices are listed so far: - Amontec JTAGkey(2) - Buspirate - Dediprog SF100 - DLP Design DLP-USB1232H - FTDI FT4232H Mini-Module Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Added: trunk/util/ trunk/util/z60_flashrom.rules Added: trunk/util/z60_flashrom.rules ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/util/z60_flashrom.rules Wed Jul 28 00:00:42 2010 (r1110) @@ -0,0 +1,55 @@ +## +## This file is part of the flashrom project. +## +## Copyright (C) 2010 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +## +## Please keep this list sorted alphabetically by vendor/device name. +## + +## +## This is tested on udev version 154, other versions may need small fixes. +## +## Note that you might want to change the "plugdev" group to whatever is +## suitable for your respective distribution. +## + +ACTION!="add|change", GOTO="flashrom_rules_end" +SUBSYSTEM!="usb|usb_device", GOTO="flashrom_rules_end" + +# Amontec JTAGkey(2) +# http://www.amontec.com/jtagkey.shtml +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="cff8", MODE="664", GROUP="plugdev" + +# Buspirate +# http://dangerousprototypes.com/2009/10/08/bus-pirate-raw-spi-mode/ +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6001", MODE="664", GROUP="plugdev" + +# Dediprog SF100 +# http://www.dediprog.com/SPI-flash-in-circuit-programming/SF100 +ATTRS{idVendor}=="0483", ATTRS{idProduct}=="dada", MODE="664", GROUP="plugdev" + +# DLP Design DLP-USB1232H +# http://www.dlpdesign.com/usb/usb1232h.shtml +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", MODE="664", GROUP="plugdev" + +# FTDI FT4232H Mini-Module +# http://www.ftdichip.com/Products/EvaluationKits/FT4232H_MiniModule.htm +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6011", MODE="664", GROUP="plugdev" + +LABEL="flashrom_rules_end"

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[PATCH] ft2232_spi: JTAGkey support, 3rd try
by Jörg Fischer 27 Jul '10

27 Jul '10

Hi, here is the 3rd version of the JTAGkey patch against trunk. * rename FTDI_2232H to FTDI_2232H_PID, same for FTDI_4232H * add AMONTEC_JTAGKEY_PID to flash.h * add FTDI_VID (0x0403) to flash.h Signed-off-by: Joerg Fischer <turboj(a)gmx.de> Index: flashrom.8 =================================================================== --- flashrom.8 (Revision 1109) +++ flashrom.8 (Arbeitskopie) @@ -177,11 +177,11 @@ .sp .BR "* atahpt" " (for flash ROMs on Highpoint ATA/RAID controllers)" .sp -.BR "* it87spi" " (for flash ROMs behind an ITE IT87xx Super I/O LPC/SPI\ +.BR "* it87spi" " (for flash ROMs behind an ITE IT87xx Super I/O LPC/SPI \ translation unit)" .sp -.BR "* ft2232_spi" " (for SPI flash ROMs attached to a FT2232H/FT4232H based\ -USB SPI programmer)" +.BR "* ft2232_spi" " (for SPI flash ROMs attached to a FT2232H/FT4232H/JTAGkey \ +based USB SPI programmer)" .sp .BR "* serprog" " (for flash ROMs attached to a programmer speaking serprog)" .sp @@ -351,7 +351,7 @@ syntax where .B model can be any of -.BR 2232H ", or " 4232H +.BR 2232H ", "JTAGkey ", or " 4232H and .B interface can be any of Index: flash.h =================================================================== --- flash.h (Revision 1109) +++ flash.h (Arbeitskopie) @@ -530,8 +530,10 @@ #endif /* ft2232_spi.c */ -#define FTDI_FT2232H 0x6010 -#define FTDI_FT4232H 0x6011 +#define FTDI_VID 0x0403 +#define FTDI_FT2232H_PID 0x6010 +#define FTDI_FT4232H_PID 0x6011 +#define AMONTEC_JTAGKEY_PID 0xCFF8 int ft2232_spi_init(void); int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); Index: ft2232_spi.c =================================================================== --- ft2232_spi.c (Revision 1109) +++ ft2232_spi.c (Arbeitskopie) @@ -45,8 +45,29 @@ #define BITMODE_BITBANG_NORMAL 1 #define BITMODE_BITBANG_SPI 2 +/* Set data bits low-byte command: + * value: 0x08 CS=high, DI=low, DO=low, SK=low + * dir: 0x0b CS=output, DI=input, DO=output, SK=output + * + * JTAGkey(2) needs to enable its output via Bit4 / GPIOL0 + * value: 0x18 OE=high, CS=high, DI=low, DO=low, SK=low + * dir: 0x1b OE=output, CS=output, DI=input, DO=output, SK=output + * + */ +static unsigned char cs_bits = 0x08; +static unsigned char pindir = 0x0b; static struct ftdi_context ftdic_context; +static const char * getFT2232name(int ft2232_type) +{ + switch(ft2232_type) { + case FTDI_FT2232H_PID: return "2232H"; + case AMONTEC_JTAGKEY_PID: return "JTAGkey"; + default: return "4232H"; + } + return "4232H"; +} + static int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) { int r; @@ -76,16 +97,22 @@ int f; struct ftdi_context *ftdic = &ftdic_context; unsigned char buf[512]; - int ft2232_type = FTDI_FT4232H; + int ft2232_type = FTDI_FT4232H_PID; enum ftdi_interface ft2232_interface = INTERFACE_B; char *arg; arg = extract_programmer_param("type"); if (arg) { if (!strcasecmp(arg, "2232H")) - ft2232_type = FTDI_FT2232H; + ft2232_type = FTDI_FT2232H_PID; else if (!strcasecmp(arg, "4232H")) - ft2232_type = FTDI_FT4232H; + ft2232_type = FTDI_FT4232H_PID; + else if (!strcasecmp(arg, "jtagkey")) { + ft2232_type = AMONTEC_JTAGKEY_PID; + ft2232_interface = INTERFACE_A; + cs_bits = 0x18; + pindir = 0x1b; + } else { msg_perr("Error: Invalid device type specified.\n"); free(arg); @@ -110,7 +137,7 @@ } free(arg); msg_pdbg("Using device type %s ", - (ft2232_type == FTDI_FT2232H) ? "2232H" : "4232H"); + getFT2232name(ft2232_type)); msg_pdbg("interface %s\n", (ft2232_interface == INTERFACE_A) ? "A" : "B"); @@ -119,7 +146,7 @@ return EXIT_FAILURE; // TODO } - f = ftdi_usb_open(ftdic, 0x0403, ft2232_type); + f = ftdi_usb_open(ftdic, FTDI_VID, ft2232_type); if (f < 0 && f != -5) { msg_perr("Unable to open FTDI device: %d (%s)\n", f, @@ -178,14 +205,9 @@ return -1; msg_pdbg("Set data bits\n"); - /* Set data bits low-byte command: - * value: 0x08 CS=high, DI=low, DO=low, SK=low - * dir: 0x0b CS=output, DI=input, DO=output, SK=output - */ -#define CS_BIT 0x08 buf[0] = SET_BITS_LOW; - buf[1] = CS_BIT; - buf[2] = 0x0b; + buf[1] = cs_bits; + buf[2] = pindir; if (send_buf(ftdic, buf, 3)) return -1; @@ -230,8 +252,8 @@ */ msg_pspew("Assert CS#\n"); buf[i++] = SET_BITS_LOW; - buf[i++] = 0 & ~CS_BIT; /* assertive */ - buf[i++] = 0x0b; + buf[i++] = 0 & ~cs_bits; /* assertive */ + buf[i++] = pindir; if (writecnt) { buf[i++] = 0x11; @@ -272,8 +294,8 @@ msg_pspew("De-assert CS#\n"); buf[i++] = SET_BITS_LOW; - buf[i++] = CS_BIT; - buf[i++] = 0x0b; + buf[i++] = cs_bits; + buf[i++] = pindir; ret = send_buf(ftdic, buf, i); failed |= ret; if (ret)

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netbook hp 2133 mini :(
by Paweł Stawicki 27 Jul '10

27 Jul '10

Hi, I tried flashrom on my netbook with this result No EEPROM/flash device found. :( netbook still works :) I'm attaching the result of: sudo ./flashrom -p internal:laptop=force_I_want_a_brick -V > flashrom.txt flashrom version: ubuntu@ubuntu:~/flashrom$ svn info Path: . URL: svn://coreboot.org/flashrom/trunk Repository Root: svn://coreboot.org/flashrom Repository UUID: 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 Revision: 1109 Node Kind: directory Schedule: normal Last Changed Author: mkarcher Last Changed Rev: 1109 Last Changed Date: 2010-07-25 00:50:54 +0200 (nie, 25 lip 2010) Best Regards Paweł

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[PATCH] ft2232_spi: JTAGKey support, 2nd try
by Jörg Fischer 27 Jul '10

27 Jul '10

Hi, here is the 2nd version of the patch against current trunk. Changes: - renamed some vars - JTAGkey is now displayed as "JTAGkey" instead of "4232H" - and documented in manpage Signed-off-by: Joerg Fischer <turboj(a)gmx.de> Index: flashrom.8 =================================================================== --- flashrom.8 (Revision 1109) +++ flashrom.8 (Arbeitskopie) @@ -177,11 +177,11 @@ .sp .BR "* atahpt" " (for flash ROMs on Highpoint ATA/RAID controllers)" .sp -.BR "* it87spi" " (for flash ROMs behind an ITE IT87xx Super I/O LPC/SPI\ +.BR "* it87spi" " (for flash ROMs behind an ITE IT87xx Super I/O LPC/SPI \ translation unit)" .sp -.BR "* ft2232_spi" " (for SPI flash ROMs attached to a FT2232H/FT4232H based\ -USB SPI programmer)" +.BR "* ft2232_spi" " (for SPI flash ROMs attached to a FT2232H/FT4232H/JTAGkey \ +based USB SPI programmer)" .sp .BR "* serprog" " (for flash ROMs attached to a programmer speaking serprog)" .sp @@ -351,7 +351,7 @@ syntax where .B model can be any of -.BR 2232H ", or " 4232H +.BR 2232H ", "JTAGkey ", or " 4232H and .B interface can be any of Index: ft2232_spi.c =================================================================== --- ft2232_spi.c (Revision 1109) +++ ft2232_spi.c (Arbeitskopie) @@ -45,8 +45,31 @@ #define BITMODE_BITBANG_NORMAL 1 #define BITMODE_BITBANG_SPI 2 + /* Set data bits low-byte command: + * value: 0x08 CS=high, DI=low, DO=low, SK=low + * dir: 0x0b CS=output, DI=input, DO=output, SK=output + * + * Jtagkey(2) needs to enable its output via Bit4 / GPIOL0 + * value: 0x18 OE=high, CS=high, DI=low, DO=low, SK=low + * dir: 0x1b OE=output, CS=output, DI=input, DO=output, SK=output + * + */ +static unsigned char cs_bits = 0x08; +static unsigned char pindir = 0x0b; static struct ftdi_context ftdic_context; +#define AMONTEC_JTAGKEY_PID 0xCFF8 + +static const char * getFT2232name(int ft2232_type) +{ + switch(ft2232_type) { + case FTDI_FT2232H: return "2232H"; + case AMONTEC_JTAGKEY_PID: return "JTAGkey"; + default: return "4232H"; + } + return "4232H"; +} + static int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) { int r; @@ -86,6 +109,12 @@ ft2232_type = FTDI_FT2232H; else if (!strcasecmp(arg, "4232H")) ft2232_type = FTDI_FT4232H; + else if (!strcasecmp(arg, "jtagkey")) { + ft2232_type = AMONTEC_JTAGKEY_PID; + ft2232_interface = INTERFACE_A; + cs_bits = 0x18; + pindir = 0x1b; + } else { msg_perr("Error: Invalid device type specified.\n"); free(arg); @@ -110,7 +139,7 @@ } free(arg); msg_pdbg("Using device type %s ", - (ft2232_type == FTDI_FT2232H) ? "2232H" : "4232H"); + getFT2232name(ft2232_type)); msg_pdbg("interface %s\n", (ft2232_interface == INTERFACE_A) ? "A" : "B"); @@ -178,14 +207,9 @@ return -1; msg_pdbg("Set data bits\n"); - /* Set data bits low-byte command: - * value: 0x08 CS=high, DI=low, DO=low, SK=low - * dir: 0x0b CS=output, DI=input, DO=output, SK=output - */ -#define CS_BIT 0x08 buf[0] = SET_BITS_LOW; - buf[1] = CS_BIT; - buf[2] = 0x0b; + buf[1] = cs_bits; + buf[2] = pindir; if (send_buf(ftdic, buf, 3)) return -1; @@ -230,8 +254,8 @@ */ msg_pspew("Assert CS#\n"); buf[i++] = SET_BITS_LOW; - buf[i++] = 0 & ~CS_BIT; /* assertive */ - buf[i++] = 0x0b; + buf[i++] = 0 & ~cs_bits; /* assertive */ + buf[i++] = pindir; if (writecnt) { buf[i++] = 0x11; @@ -272,8 +296,8 @@ msg_pspew("De-assert CS#\n"); buf[i++] = SET_BITS_LOW; - buf[i++] = CS_BIT; - buf[i++] = 0x0b; + buf[i++] = cs_bits; + buf[i++] = pindir; ret = send_buf(ftdic, buf, i); failed |= ret; if (ret)

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SPI status register writes
by Carl-Daniel Hailfinger 26 Jul '10

26 Jul '10

Quite a few SPI flash chips need a few milliseconds to write the status register (AT25 series etc.), but we do not take care of this at all. The same flash chips ignore any commands sent while the status register write cycle is in progress. Given that we execute WRSR once per write, I think it is pretty OK to have a 100 ms programmer delay after WRSR. An alternative would be to watch the status register contents, but that may or may not work, the datasheets are completely unclear about that case. If we're lucky, this will even solve a few write/erase issues we were seeing. What do you think? Regards, Carl-Daniel -- http://www.hailfinger.org/

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AMD CS5536 now detected twice with r1057
by Guenter 26 Jul '10

26 Jul '10

Hi, board is PC-Engines Alix 2C3: http://www.pcengines.ch/alix2c3.htm while r1001 detects the AMD CS5536 correctly only once: flashrom v0.9.2-r1001 on Linux 2.6.32-1 (i586), built with libpci 3.1.7, GCC 4.4.3 flashrom is free software, get the source code at http://www.flashrom.org No coreboot table found. Found chipset "AMD CS5536", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "AMIC A49LF040A" (512 KB, LPC) at physical address 0xfff80000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Thanks for your help! === No operations were specified. now recent r1057 gives a warning that AMD CS5536 is detected twice: flashrom v0.9.2-r1057 on Linux 2.6.32-1 (i586), built with libpci 3.1.7, GCC 4.4.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. No coreboot table found. Found chipset "AMD CS5536", enabling flash write... OK. WARNING: unexpected second chipset match: "AMD CS5536" ignoring, please report lspci and board URL to flashrom(a)flashrom.org! This chipset supports the following protocols: Non-SPI. Found chip "AMIC A49LF040A" (512 KB, LPC) at physical address 0xfff80000. No operations were specified. lspci -nn 00:01.0 Host bridge [0600]: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge [1022:2080] (rev 33) 00:01.2 Entertainment encryption device [1010]: Advanced Micro Devices [AMD] Geode LX AES Security Block [1022:2082] 00:09.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96) 00:0a.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96) 00:0b.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96) 00:0f.0 ISA bridge [0601]: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA [1022:2090] (rev 03) 00:0f.2 IDE interface [0101]: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE [1022:209a] (rev 01) 00:0f.4 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC [1022:2094] (rev 02) 00:0f.5 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC [1022:2095] (rev 02) Günter.

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Re: [flashrom] [PATCH] Board enable for GA-8IRML
by Carl-Daniel Hailfinger 26 Jul '10

26 Jul '10

Hi idlogin, did this patch work for you? On 12.06.2010 19:50, Michael Karcher wrote: > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > (pending confirmation by idlogin, otherwise please commit as NT) Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH] Board enable for abit NF-M2 nView
by Carl-Daniel Hailfinger 25 Jul '10

25 Jul '10

Hi Michael Stutz, did this patch work for you? You can also download it at http://patchwork.coreboot.org/patch/1505/raw/ I didn't see a response from you, but that may have been because we sent the patch to the e-mail address where your report came from (and we didn't change that address, so if the please-obfuscate-... should have been removed, it may explain why we didn't get a reply). On 13.06.2010 01:17, Michael Karcher wrote: > To be safe, the onboard video of the nView edition of this board has > been included in the match. If other NF-M2 editions have the same board > enable, the match should be broadened > > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > (pending confirmation by Michael Stutz, otherwise please commit as NT) Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[commit] r1109 - trunk
by repository service 25 Jul '10

25 Jul '10

Author: mkarcher Date: Sun Jul 25 00:50:54 2010 New Revision: 1109 URL: http://flashrom.org/trac/coreboot/changeset/1109 Log: Board enable for abit NF-M2 nView To be safe, the onboard video of the nView edition of this board has been included in the match. If other NF-M2 editions have the same board enable, the match should be broadened lspci/superiotool http://www.coreboot.org/pipermail/flashrom/2010-April/002909.html No success report, thus committed as untested. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sun Jul 25 00:43:12 2010 (r1108) +++ trunk/board_enable.c Sun Jul 25 00:50:54 2010 (r1109) @@ -882,6 +882,14 @@ } /** + * Suited for abit NF-M2 nView: Socket AM2 + NVIDIA MCP51. + */ +static int nvidia_mcp_gpio4_lower(void) +{ + return nvidia_mcp_gpio_set(0x04, 0); +} + +/** * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04. */ static int nvidia_mcp_gpio10_raise(void) @@ -1682,6 +1690,7 @@ {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "Abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, "Abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise}, + {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0240, 0x10de, 0x0222, NULL, NULL, NULL, "Abit", "NF-M2 nView", 0, NT, nvidia_mcp_gpio4_lower}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, OK, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sun Jul 25 00:43:12 2010 (r1108) +++ trunk/print.c Sun Jul 25 00:50:54 2010 (r1109) @@ -274,6 +274,7 @@ B("Abit", "IP35", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=LG…", NULL), B("Abit", "IP35 Pro", 1, "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?fMTYPE=LG…", NULL), B("Abit", "IS-10", 0, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), + B("Abit", "NF-M2 nView", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=So…", NULL), B("Abit", "NF7-S", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=So…", NULL), B("Abit", "VT6X4", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=Sl…", NULL), B("Acorp", "6A815EPD", 1, "http://web.archive.org/web/20021206163652/www.acorp.com.tw/English/default.…", NULL),

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Re: [flashrom] [PATCH] Detect IP35 by the SMBus bridge instead of the SATA controller
by Carl-Daniel Hailfinger 25 Jul '10

25 Jul '10

Hi Gunter, did Michael's patch work for you? On 20.06.2010 00:01, Michael Karcher wrote: > The SATA controller matched in the board enable is not always present > with that ID (that's the 2-port ICH9 SATA IDE controller), but (depending > on board revision/edition or BIOS settings an ICH9 SATA RAID controller > appears instead. This patches matches on the SMBus function in the > south bridge instead of the SATA controller. > > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > (pending confirmation by Gunter) Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[commit] r1108 - trunk
by repository service 25 Jul '10

25 Jul '10

Author: mkarcher Date: Sun Jul 25 00:43:12 2010 New Revision: 1108 URL: http://flashrom.org/trac/coreboot/changeset/1108 Log: Detect IP35 by the SMBus bridge instead of the SATA controller The SATA controller matched in the board enable is not always present with that ID (that's the 2-port ICH9 SATA IDE controller), but (depending on board revision/edition or BIOS settings an ICH9 SATA RAID controller appears instead. This patches matches on the SMBus function in the south bridge instead of the SATA controller. Non-working board reported by: Gunter Keilholz <gunter.keilholz(a)googlemail.com> lspci/superiotool: http://www.coreboot.org/pipermail/flashrom/2010-June/003591.html Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sun Jul 25 00:36:01 2010 (r1107) +++ trunk/board_enable.c Sun Jul 25 00:43:12 2010 (r1108) @@ -1678,7 +1678,7 @@ #if defined(__i386__) || defined(__x86_64__) {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, "Abit", "IC7", 0, NT, intel_ich_gpio23_raise}, - {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, + {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "Abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, "Abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise},

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Re: [flashrom] [PATCH] Board enable for Samsung Polaris 32
by Carl-Daniel Hailfinger 25 Jul '10

25 Jul '10

Hi Alex, did Michael's patch work for you? On 12.07.2010 17:42, Michael Karcher wrote: > lspci/superiotool: > http://www.coreboot.org/pipermail/flashrom/2010-July/003889.html > > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > Regards, Carl-Daniel -- http://www.hailfinger.org/

3 3

[commit] r1107 - trunk
by repository service 25 Jul '10

25 Jul '10

Author: mkarcher Date: Sun Jul 25 00:36:01 2010 New Revision: 1107 URL: http://flashrom.org/trac/coreboot/changeset/1107 Log: Board enable for Samsung Polaris 32 lspci/superiotool: http://www.coreboot.org/pipermail/flashrom/2010-July/003889.html Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Tested-by: Alex Loktionoff <oxy-loktionoff(a)mail.ru> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sun Jul 25 00:27:29 2010 (r1106) +++ trunk/board_enable.c Sun Jul 25 00:36:01 2010 (r1107) @@ -1267,6 +1267,7 @@ * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5. * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R. * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5. + * - Samsung Polaris 32: socket478 + 865P + ICH5. */ static int intel_ich_gpio21_raise(void) { @@ -1738,6 +1739,7 @@ {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e}, {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0}, + {0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, NULL}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sun Jul 25 00:27:29 2010 (r1106) +++ trunk/print.c Sun Jul 25 00:36:01 2010 (r1107) @@ -416,6 +416,7 @@ B("PC Engines", "Alix.3d3", 1, "http://pcengines.ch/alix3d3.htm", NULL), B("PC Engines", "WRAP.2E", 1, "http://pcengines.ch/wrap2e1.htm", NULL), B("RCA", "RM4100", 1, "http://www.settoplinux.org/index.php?title=RCA_RM4100", NULL), + B("Samsung", "Polaris 32", 1, "", NULL), B("Shuttle", "AK31", 1, "http://www.motherboard.cz/mb/shuttle/AK31.htm", NULL), B("Shuttle", "AK38N", 1, "http://eu.shuttle.com/en/desktopdefault.aspx/tabid-36/558_read-9889/", NULL), B("Shuttle", "FD37", 1, "http://www.shuttle.eu/products/discontinued/barebones/sd37p2/", NULL),

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[commit] r1106 - trunk
by repository service 25 Jul '10

25 Jul '10

Author: mkarcher Date: Sun Jul 25 00:27:29 2010 New Revision: 1106 URL: http://flashrom.org/trac/coreboot/changeset/1106 Log: Board enable for GA-8IRML Non-working board reported by idlogin / Putlinuxonit <putlinuxonit(a)gmail.com> lspci/superiotool: http://www.coreboot.org/pipermail/flashrom/2010-May/003330.html No success report, so committed as untested. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sun Jul 25 00:18:14 2010 (r1105) +++ trunk/board_enable.c Sun Jul 25 00:27:29 2010 (r1106) @@ -1310,6 +1310,14 @@ } /** + * Suited for Gigabyte GA-8IRML: Intel Socket478 + i845 + ICH2. + */ +static int intel_ich_gpio25_raise(void) +{ + return intel_ich_gpio_set(25, 1); +} + +/** * Suited for IBase MB899: i945GM + ICH7. */ static int intel_ich_gpio26_raise(void) @@ -1705,6 +1713,7 @@ {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, OK, board_epox_ep_bx3}, {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, + {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, "GIGABYTE", "GA-8IRML", 0, NT, intel_ich_gpio25_raise}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", "HP", "DL165 G6", 0, OK, board_hp_dl165_g6_enable}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sun Jul 25 00:18:14 2010 (r1105) +++ trunk/print.c Sun Jul 25 00:27:29 2010 (r1106) @@ -360,6 +360,7 @@ B("GIGABYTE", "GA-6ZMA", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1541", NULL), B("GIGABYTE", "GA-7VT600", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1666", NULL), B("GIGABYTE", "GA-7ZM", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1366", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option."), + B("GIGABYTE", "GA-8IRML", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1343", NULL), B("GIGABYTE", "GA-965P-DS4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2288", NULL), B("GIGABYTE", "GA-EP35-DS3L", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2778", NULL), B("GIGABYTE", "GA-EX58-UD4P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2986", NULL),

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Re: [flashrom] [PATCH] board enable for Abit IC7
by Carl-Daniel Hailfinger 25 Jul '10

25 Jul '10

On 24.07.2010 16:02, anders(a)jenbo.dk wrote: > Hi, I wount be able to test for the next two weeks as I am on hollyday and so don't have access to the hardware. But I will be sure to test it as soon as I get back home. > > Mvh Anders > > ----- Reply message ----- > Fra: "Carl-Daniel Hailfinger" <c-d.hailfinger.devel.2006(a)gmx.net> > Dato: lør., jul. 24, 2010 12:48 > Emne: [flashrom] [PATCH] board enable for Abit IC7 > Til: "Michael Karcher" <flashrom(a)mkarcher.dialup.fu-berlin.de> > Cc: <flashrom(a)flashrom.org>, "Anders Jenbo" <anders(a)jenbo.dk> > > > Hi Anders, > > did this patch work for you? > > On 02.06.2010 09:19, Michael Karcher wrote: > >> (missing signoff) >> > > (pending a confirmation from Anders, otherwise NT) > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > Michael, please signoff and commit as NT. We can still change the status later. I want to get the number of pending board enable patches down to zero. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[commit] r1105 - trunk
by repository service 25 Jul '10

25 Jul '10

Author: mkarcher Date: Sun Jul 25 00:18:14 2010 New Revision: 1105 URL: http://flashrom.org/trac/coreboot/changeset/1105 Log: board enable for Abit IC7 Non-working board reported by: Anders Jenbo <anders(a)jenbo.dk> lspci/superiotool: http://www.coreboot.org/pipermail/flashrom/2010-June/003346.html no success report, so committed as untested. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sun Jul 25 00:07:52 2010 (r1104) +++ trunk/board_enable.c Sun Jul 25 00:18:14 2010 (r1105) @@ -1668,6 +1668,7 @@ /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ #if defined(__i386__) || defined(__x86_64__) {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, + {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, "Abit", "IC7", 0, NT, intel_ich_gpio23_raise}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "Abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sun Jul 25 00:07:52 2010 (r1104) +++ trunk/print.c Sun Jul 25 00:18:14 2010 (r1105) @@ -270,6 +270,7 @@ B("A-Trend", "ATC-6220", 1, "http://www.motherboard.cz/mb/atrend/atc6220.htm", NULL), B("Abit", "AX8", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…", NULL), B("Abit", "Fatal1ty F-I90HD", 1, "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), + B("Abit", "IC7", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), B("Abit", "IP35", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=LG…", NULL), B("Abit", "IP35 Pro", 1, "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?fMTYPE=LG…", NULL), B("Abit", "IS-10", 0, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…", NULL),

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Re: [flashrom] [PATCH] Fix compilation for CONFIG_INTERNAL=no
by Carl-Daniel Hailfinger 25 Jul '10

25 Jul '10

On 25.07.2010 00:01, Michael Karcher wrote: > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Thanks for the quick fix. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[commit] r1104 - trunk
by repository service 25 Jul '10

25 Jul '10

Author: mkarcher Date: Sun Jul 25 00:07:52 2010 New Revision: 1104 URL: http://flashrom.org/trac/coreboot/changeset/1104 Log: Fix compilation for CONFIG_INTERNAL=no broken by r1098 Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flash.h Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Sat Jul 24 20:47:45 2010 (r1103) +++ trunk/flash.h Sun Jul 25 00:07:52 2010 (r1104) @@ -697,6 +697,7 @@ uint32_t spi_get_valid_read_addr(void); /* ichspi.c */ +#if CONFIG_INTERNAL == 1 extern uint32_t ichspi_bbar; int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation); @@ -706,6 +707,7 @@ int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len); int ich_spi_send_multicommand(struct spi_command *cmds); +#endif /* it87spi.c */ void enter_conf_mode_ite(uint16_t port); @@ -719,17 +721,21 @@ int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* sb600spi.c */ +#if CONFIG_INTERNAL == 1 int sb600_probe_spi(struct pci_dev *dev); int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); +#endif /* wbsio_spi.c */ +#if CONFIG_INTERNAL == 1 int wbsio_check_for_spi(void); int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); +#endif /* serprog.c */ int serprog_init(void);

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[PATCH] Fix compilation for CONFIG_INTERNAL=no
by Michael Karcher 25 Jul '10

25 Jul '10

Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- flash.h | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/flash.h b/flash.h index 1827115..8a16396 100644 --- a/flash.h +++ b/flash.h @@ -697,6 +697,7 @@ int default_spi_send_multicommand(struct spi_command *cmds); uint32_t spi_get_valid_read_addr(void); /* ichspi.c */ +#if CONFIG_INTERNAL == 1 extern uint32_t ichspi_bbar; int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation); @@ -706,6 +707,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len); int ich_spi_send_multicommand(struct spi_command *cmds); +#endif /* it87spi.c */ void enter_conf_mode_ite(uint16_t port); @@ -719,17 +721,21 @@ int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* sb600spi.c */ +#if CONFIG_INTERNAL == 1 int sb600_probe_spi(struct pci_dev *dev); int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); +#endif /* wbsio_spi.c */ +#if CONFIG_INTERNAL == 1 int wbsio_check_for_spi(void); int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); +#endif /* serprog.c */ int serprog_init(void); -- 1.7.1

1 0

latest available flashrom -V for giada slim N10 netbook on ubuntu 10.04 release
by Jacques Charles 24 Jul '10

24 Jul '10

flashrom v0.9.2-r1028 on Linux 2.6.32-22-server (x86_64), built with libpci 3.0.0, GCC 4.4.4, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 360M loops per second, 10 myus = 9 us, 100 myus = 90 us, 1000 myus = 1099 us, 10000 myus = 13100 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "nVidia" DMI string system-product-name: "MCP79" DMI string system-version: "To Be Filled By O.E.M." DMI string baseboard-manufacturer: "ASL" DMI string baseboard-product-name: "MCP7A-ION" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP79", enabling flash write... chipset PCI ID is 10de:0aad, This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Guessed flash bus type is SPI Found SMBus device 10de:0aa2 at 00:03:2 SPI BAR is at 0xfae80000, after clearing low bits BAR is at 0xfae80000 Mapping MCP67 SPI at 0xfae80000, unaligned size 0x544. SPI control is 0xc05a, enable=0, idle=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. SPI on this chipset is not supported yet. OK. This chipset supports the following protocols: None. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for ASD AE49F2008, 256 KB: skipped. Probing for Atmel AT25DF021, 256 KB: skipped. Probing for Atmel AT25DF041A, 512 KB: skipped. Probing for Atmel AT25DF081, 1024 KB: skipped. Probing for Atmel AT25DF161, 2048 KB: skipped. Probing for Atmel AT25DF321, 4096 KB: skipped. Probing for Atmel AT25DF321A, 4096 KB: skipped. Probing for Atmel AT25DF641, 8192 KB: skipped. Probing for Atmel AT25F512B, 64 KB: skipped. Probing for Atmel AT25FS010, 128 KB: skipped. Probing for Atmel AT25FS040, 512 KB: skipped. Probing for Atmel AT26DF041, 512 KB: skipped. Probing for Atmel AT26DF081A, 1024 KB: skipped. Probing for Atmel AT26DF161, 2048 KB: skipped. Probing for Atmel AT26DF161A, 2048 KB: skipped. Probing for Atmel AT26F004, 512 KB: skipped. Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: skipped. Probing for Atmel AT45DB011D, 128 KB: skipped. Probing for Atmel AT45DB021D, 256 KB: skipped. Probing for Atmel AT45DB041D, 512 KB: skipped. Probing for Atmel AT45DB081D, 1024 KB: skipped. Probing for Atmel AT45DB161D, 2048 KB: skipped. Probing for Atmel AT45DB321C, 4224 KB: skipped. Probing for Atmel AT45DB321D, 4096 KB: skipped. Probing for Atmel AT45DB642D, 8192 KB: skipped. Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: skipped. Probing for AMIC A25L40PU, 512 KB: skipped. Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for Eon EN25B05, 64 KB: skipped. Probing for Eon EN25B05T, 64 KB: skipped. Probing for Eon EN25B10, 128 KB: skipped. Probing for Eon EN25B10T, 128 KB: skipped. Probing for Eon EN25B20, 256 KB: skipped. Probing for Eon EN25B20T, 256 KB: skipped. Probing for Eon EN25B40, 512 KB: skipped. Probing for Eon EN25B40T, 512 KB: skipped. Probing for Eon EN25B80, 1024 KB: skipped. Probing for Eon EN25B80T, 1024 KB: skipped. Probing for Eon EN25B16, 2048 KB: skipped. Probing for Eon EN25B16T, 2048 KB: skipped. Probing for Eon EN25B32, 4096 KB: skipped. Probing for Eon EN25B32T, 4096 KB: skipped. Probing for Eon EN25B64, 8192 KB: skipped. Probing for Eon EN25B64T, 8192 KB: skipped. Probing for Eon EN25D16, 2048 KB: skipped. Probing for Eon EN25F05, 64 KB: skipped. Probing for Eon EN25F10, 128 KB: skipped. Probing for Eon EN25F20, 256 KB: skipped. Probing for Eon EN25F40, 512 KB: skipped. Probing for Eon EN25F80, 1024 KB: skipped. Probing for Eon EN25F16, 2048 KB: skipped. Probing for Eon EN25F32, 4096 KB: skipped. Probing for Eon EN29F010, 128 KB: skipped. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Intel 28F001BX-B, 128 KB: skipped. Probing for Intel 28F001BX-T, 128 KB: skipped. Probing for Intel 28F004S5, 512 KB: skipped. Probing for Intel 28F004BV/BE-B, 512 KB: skipped. Probing for Intel 28F004BV/BE-T, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-B, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: skipped. Probing for Macronix MX25L1005, 128 KB: skipped. Probing for Macronix MX25L2005, 256 KB: skipped. Probing for Macronix MX25L4005, 512 KB: skipped. Probing for Macronix MX25L8005, 1024 KB: skipped. Probing for Macronix MX25L1605, 2048 KB: skipped. Probing for Macronix MX25L1635D, 2048 KB: skipped. Probing for Macronix MX25L3205, 4096 KB: skipped. Probing for Macronix MX25L3235D, 4096 KB: skipped. Probing for Macronix MX25L6405, 8192 KB: skipped. Probing for Macronix MX25L12805, 16384 KB: skipped. Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for Numonyx M25PE10, 128 KB: skipped. Probing for Numonyx M25PE20, 256 KB: skipped. Probing for Numonyx M25PE40, 512 KB: skipped. Probing for Numonyx M25PE80, 1024 KB: skipped. Probing for Numonyx M25PE16, 2048 KB: skipped. Probing for PMC Pm25LV010, 128 KB: skipped. Probing for PMC Pm25LV016B, 2048 KB: skipped. Probing for PMC Pm25LV020, 256 KB: skipped. Probing for PMC Pm25LV040, 512 KB: skipped. Probing for PMC Pm25LV080B, 1024 KB: skipped. Probing for PMC Pm25LV512, 64 KB: skipped. Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: skipped. Probing for PMC Pm49FL004, 512 KB: skipped. Probing for Sanyo LF25FW203A, 2048 KB: skipped. Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: skipped. Probing for Spansion S25FL016A, 2048 KB: skipped. Probing for SST SST25VF016B, 2048 KB: skipped. Probing for SST SST25VF032B, 4096 KB: skipped. Probing for SST SST25VF040.REMS, 512 KB: skipped. Probing for SST SST25VF040B, 512 KB: skipped. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Probing for SST SST25VF080B, 1024 KB: skipped. Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: skipped. Probing for ST M25P05.RES, 64 KB: skipped. Probing for ST M25P10-A, 128 KB: skipped. Probing for ST M25P10.RES, 128 KB: skipped. Probing for ST M25P20, 256 KB: skipped. Probing for ST M25P40, 512 KB: skipped. Probing for ST M25P40-old, 512 KB: skipped. Probing for ST M25P80, 1024 KB: skipped. Probing for ST M25P16, 2048 KB: skipped. Probing for ST M25P32, 4096 KB: skipped. Probing for ST M25P64, 8192 KB: skipped. Probing for ST M25P128, 16384 KB: skipped. Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: skipped. Probing for ST M50FLW040B, 512 KB: skipped. Probing for ST M50FLW080A, 1024 KB: skipped. Probing for ST M50FLW080B, 1024 KB: skipped. Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS S29C31004T, 512 KB: skipped. Probing for SyncMOS S29C51001T, 128 KB: skipped. Probing for SyncMOS S29C51002T, 256 KB: skipped. Probing for SyncMOS S29C51004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: skipped. Probing for Winbond W25Q16, 2048 KB: skipped. Probing for Winbond W25Q32, 4096 KB: skipped. Probing for Winbond W25x10, 128 KB: skipped. Probing for Winbond W25x20, 256 KB: skipped. Probing for Winbond W25x40, 512 KB: skipped. Probing for Winbond W25x80, 1024 KB: skipped. Probing for Winbond W25x16, 2048 KB: skipped. Probing for Winbond W25x32, 4096 KB: skipped. Probing for Winbond W25x64, 8192 KB: skipped. Probing for Winbond W29C011, 128 KB: skipped. Probing for Winbond W29C020C, 256 KB: skipped. Probing for Winbond W29C040P, 512 KB: skipped. Probing for Winbond W29EE011, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040B, 512 KB: skipped. Probing for Winbond W39V040C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Probing for EON unknown EON SPI chip, 0 KB: skipped. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Probing for SST unknown SST SPI chip, 0 KB: skipped. Probing for ST unknown ST SPI chip, 0 KB: skipped. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically.

1 0

flashrom -V for giada slim N10 netbook
by Jacques Charles 24 Jul '10

24 Jul '10

flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "nVidia" DMI string system-product-name: "MCP79" DMI string system-version: "To Be Filled By O.E.M." DMI string baseboard-manufacturer: "ASL" DMI string baseboard-product-name: "MCP7A-ION" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP79", enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Guessed flash bus type is SPI Found SMBus device 10de:0aa2 at 00:03:2 SPI BAR is at 0xfae80000, after clearing low bits BAR is at 0xfae80000 Mapping MCP67 SPI at 0xfae80000, unaligned size 0x544. SPI control is 0xc05a, enable=0, idle=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. SPI on this chipset is not supported yet. OK. This chipset supports the following protocols: None. Calibrating delay loop... 799M loops per second, 100 myus = 200 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for EMST F49B002UA, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN29F010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Intel 82802AC, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Macronix MX25L512, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for PMC Pm49FL004, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF003A/B, 384 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF004A/B, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF004C, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF008A, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF008C, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF016C, 2048 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF020, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF020A, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF040, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF040B, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF080A, 1024 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF160C, 2048 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for ST M25P05-A, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW040B, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080A, 1024 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080B, 1024 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FW002, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW016, 2048 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW040, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW080, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50LPW116, 2048 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040B, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040C, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040FA, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080A, 1024 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W49F002U, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W49V002FA, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080FA, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically.

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Re: [flashrom] [PATCH] Board enable for ASUS P4SD-LA (HP OEM)
by Carl-Daniel Hailfinger 24 Jul '10

24 Jul '10

Hi csh tmp, I didn't see a response from you for Michael's patch for your P4SD-LA (HP OEM) board. On 24.04.2010 11:13, Michael Karcher wrote: > This one was so easy that I didn't wait for a request. > > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > The patch is available at http://patchwork.coreboot.org/patch/1261/ Download link for the patch: http://patchwork.coreboot.org/patch/1261/raw/ Can you please test and tell us if it works? Regards, Carl-Daniel -- http://www.hailfinger.org/

3 4

[commit] r1103 - trunk
by repository service 24 Jul '10

24 Jul '10

Author: hailfinger Date: Sat Jul 24 20:47:45 2010 New Revision: 1103 URL: http://flashrom.org/trac/coreboot/changeset/1103 Log: Fix compilation which was broken by r1101. Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sat Jul 24 13:14:37 2010 (r1102) +++ trunk/board_enable.c Sat Jul 24 20:47:45 2010 (r1103) @@ -1320,7 +1320,7 @@ /** * Suited for P4SD-LA (HP OEM): i865 + ICH5 */ -static int intel_ich_gpio32_raise(const char *name) +static int intel_ich_gpio32_raise(void) { return intel_ich_gpio_set(32, 1); }

1 0

Multilanguage wiki
by Carl-Daniel Hailfinger 24 Jul '10

24 Jul '10

Hi, right now the flashrom wiki is English-only and that is a big barrier for many people who don't speak English well (or at all). There have been offers by various people to translate key contents of the wiki to Russian and German, and I hope we can integrate multilanguage support in a way that works well and does not need excessive effort from translators. There are two decisions we have to make: 1. URL schema for pages in non-English languages 2. URL schema for pages in English Current schema is www.flashrom.org/$PAGENAME One of the possible future schemata is: www.flashrom.org/$LANG/$PAGENAME The old www.flashrom.org/$PAGENAME would redirect to www.flashrom.org/en/$PAGENAME Alternatives: www.flashrom.org/wiki/$LANG/$PAGENAME www.flashrom.org/$LANG/wiki/$PAGENAME $LANG.flashrom.org/$PAGENAME $LANG.flashrom.org/wiki/$PAGENAME There are probably more options, but I wanted to start a discussion. Feel free to suggest totally different schemata, I'll listen. There is one big caveat: The planned schema needs to be implementable with Mediawiki (and as few hacks as possible). Regards, Carl-Daniel -- http://www.hailfinger.org/

2 2

Re: [flashrom] [PATCH] board enable for Abit IC7
by anders＠jenbo.dk 24 Jul '10

24 Jul '10

Hi, I wount be able to test for the next two weeks as I am on hollyday and so don't have access to the hardware. But I will be sure to test it as soon as I get back home. Mvh Anders ----- Reply message ----- Fra: "Carl-Daniel Hailfinger" <c-d.hailfinger.devel.2006(a)gmx.net> Dato: lør., jul. 24, 2010 12:48 Emne: [flashrom] [PATCH] board enable for Abit IC7 Til: "Michael Karcher" <flashrom(a)mkarcher.dialup.fu-berlin.de> Cc: <flashrom(a)flashrom.org>, "Anders Jenbo" <anders(a)jenbo.dk> Hi Anders, did this patch work for you? On 02.06.2010 09:19, Michael Karcher wrote: > (missing signoff) (pending a confirmation from Anders, otherwise NT) Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

Re: [flashrom] [PATCH] Board enable for HP Puffer2-UL8E
by Mattias Mattsson 24 Jul '10

24 Jul '10

Thanks! I believe the second PCI subsystem ID was wrong in your patch (should be 103c:2a0a). If I change it to this it works. New patch and log attached. -mattias

3 3

[commit] r1102 - trunk
by repository service 24 Jul '10

24 Jul '10

Author: mkarcher Date: Sat Jul 24 13:14:37 2010 New Revision: 1102 URL: http://flashrom.org/trac/coreboot/changeset/1102 Log: Board enable for HP Puffer2-UL8E lspci/superiotool: http://www.coreboot.org/pipermail/flashrom/2010-July/003869.html Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Mattias Mattsson <vitplister(a)gmail.com> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sat Jul 24 13:03:48 2010 (r1101) +++ trunk/board_enable.c Sat Jul 24 13:14:37 2010 (r1102) @@ -1238,6 +1238,14 @@ } /** + * Suited for HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6. + */ +static int intel_ich_gpio18_raise(void) +{ + return intel_ich_gpio_set(18, 1); +} + +/** * Suited for ASUS A8JM: Intel 945 + ICH7 */ static int intel_ich_gpio34_raise(void) @@ -1699,6 +1707,7 @@ {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", "HP", "DL165 G6", 0, OK, board_hp_dl165_g6_enable}, + {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, NULL, NULL, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sat Jul 24 13:03:48 2010 (r1101) +++ trunk/print.c Sat Jul 24 13:14:37 2010 (r1102) @@ -373,6 +373,7 @@ B("GIGABYTE", "GA-MA790FX-DQ6", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2690", NULL), B("GIGABYTE", "GA-MA790GP-DS4H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2887", NULL), B("HP", "DL145 G3", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c008…", NULL), + B("HP", "Puffer2-UL8E", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00300023", NULL), B("HP", "Vectra VL400 PC", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c000…", NULL), B("HP", "Vectra VL420 SFF PC", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c000…", NULL), B("HP", "xw9400", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?lang=en&cc=us&pro…", "Boot block is write protected unless the solder points next to F2 are shorted." ),

1 0

[commit] r1101 - trunk
by repository service 24 Jul '10

24 Jul '10

Author: mkarcher Date: Sat Jul 24 13:03:48 2010 New Revision: 1101 URL: http://flashrom.org/trac/coreboot/changeset/1101 Log: Board enable for ASUS P4SD-LA (HP OEM) No response from reporter - committed as "untested". Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sat Jul 24 12:41:42 2010 (r1100) +++ trunk/board_enable.c Sat Jul 24 13:03:48 2010 (r1101) @@ -1310,6 +1310,14 @@ } /** + * Suited for P4SD-LA (HP OEM): i865 + ICH5 + */ +static int intel_ich_gpio32_raise(const char *name) +{ + return intel_ich_gpio_set(32, 1); +} + +/** * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2. */ static int board_acorp_6a815epd(void) @@ -1678,6 +1686,7 @@ {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise}, {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sat Jul 24 12:41:42 2010 (r1100) +++ trunk/print.c Sat Jul 24 13:03:48 2010 (r1101) @@ -327,6 +327,7 @@ B("ASUS", "P4B266-LM", 1, "http://esupport.sony.com/US/perl/swu-list.pl?mdl=PCVRX650", NULL), B("ASUS", "P4C800-E Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=cFuVCr9bXXCckmcK", NULL), B("ASUS", "P4P800-E Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=INIJUvLlif7LHp3g", NULL), + B("ASUS", "P4SD-LA", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00022505", NULL), B("ASUS", "P5A", 1, "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock7/ali/p5a/", NULL), B("ASUS", "P5B", 1, "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B/", NULL), B("ASUS", "P5B-Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=bswT66IBSb2rEWNa", NULL),

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Re: [flashrom] [PATCH] board enable for Abit IC7
by Carl-Daniel Hailfinger 24 Jul '10

24 Jul '10

Hi Anders, did this patch work for you? On 02.06.2010 09:19, Michael Karcher wrote: > (missing signoff) (pending a confirmation from Anders, otherwise NT) Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

Re: [flashrom] [PATCH] Board enable for ASUS P5PE-VM
by Carl-Daniel Hailfinger 24 Jul '10

24 Jul '10

On 08.07.2010 00:23, Michael Karcher wrote: > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > Tested-by: František Kučera <linux(a)frantovo.cz> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[commit] r1100 - trunk
by repository service 24 Jul '10

24 Jul '10

Author: mkarcher Date: Sat Jul 24 12:41:42 2010 New Revision: 1100 URL: http://flashrom.org/trac/coreboot/changeset/1100 Log: Board enable for ASUS P5PE-VM Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Tested-by: František Kučera <linux(a)frantovo.cz> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Thu Jul 22 20:04:19 2010 (r1099) +++ trunk/board_enable.c Sat Jul 24 12:41:42 2010 (r1100) @@ -1258,6 +1258,7 @@ * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2. * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5. * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R. + * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5. */ static int intel_ich_gpio21_raise(void) { @@ -1679,6 +1680,7 @@ {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, + {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, NULL}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Thu Jul 22 20:04:19 2010 (r1099) +++ trunk/print.c Sat Jul 24 12:41:42 2010 (r1100) @@ -334,6 +334,7 @@ B("ASUS", "P5KC", 1, "http://www.asus.com/product.aspx?P_ID=fFZ8oUIGmLpwNMjj", NULL), B("ASUS", "P5L-MX", 1, "http://www.asus.com/product.aspx?P_ID=X70d3NCzH2DE9vWH", NULL), B("ASUS", "P5ND2-SLI Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=WY7XroDuUImVbgp5", NULL), + B("ASUS", "P5PE-VM", 1, "http://www.asus.com/product.aspx?P_ID=k3h0ZFVu9Lo1dUvk", NULL), B("ASUS", "P6T Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=vXixf82co6Q5v0BZ", NULL), B("ASUS", "P6T Deluxe V2", 1, "http://www.asus.com/product.aspx?P_ID=iRlP8RG9han6saZx", NULL), B("BCOM", "WinNET100", 1, "http://www.coreboot.org/BCOM_WINNET100", "Used in the IGEL-316 thin client."),

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Asus P4SC-E
by Mattias Mattsson 24 Jul '10

24 Jul '10

Hi, I'm trying flashrom (r1099) on an Asus P4SC-E mainboard (originally part of Asus Terminator P4 533A "Barebone" system). No flash chip or super i/o is found. Flash is an SST39SF020A Super I/O is (I think) an ITE IT8707F Latest BIOS: ftp://ftp.asus.com.tw/pub/ASUS/Barebone/Terminator-P4-533/bios/P4sce013.zip Logs attached. Thanks, -mattias

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[PATCH] FT2232_SPI: Support for JTAGkey2
by Jörg Fischer 23 Jul '10

23 Jul '10

Hi, here is the patch I used to flash via an Amontec JTAGkey2, see http://www.amontec.com/jtagkey2.shtml http://www.amontec.com/jtagkey.shtml This FTDI 2232H variant has an additional output enable, which will be set to its "on" (L) when CS is pulled low. But it lacks a power supply - so you need an external 3V3 source. The attached patch adds "jtagkey" as "type" parameter for FT2232_SPI. It should work in theory with all JTAGkeys (JTAGkey, JTAGkey-tiny and JTAGkey2) but I only have a JTAGkey2 here for testing. Signed-off-by: Joerg Fischer <turboj(a)gmx.de> Index: ft2232_spi.c =================================================================== --- ft2232_spi.c (Revision 1099) +++ ft2232_spi.c (Arbeitskopie) @@ -45,6 +45,17 @@ #define BITMODE_BITBANG_NORMAL 1 #define BITMODE_BITBANG_SPI 2 + /* Set data bits low-byte command: + * value: 0x08 CS=high, DI=low, DO=low, SK=low + * dir: 0x0b CS=output, DI=input, DO=output, SK=output + * + * Jtagkey(2) needs to enable its output via Bit4 / GPIOL0 + * value: 0x18 OE=high, CS=high, DI=low, DO=low, SK=low + * dir: 0x1b OE=output, CS=output, DI=input, DO=output, SK=output + * + */ +static unsigned char CS_Bits = 0x08; +static unsigned char Pin_Dir = 0x0b; static struct ftdi_context ftdic_context; static int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) @@ -86,6 +97,12 @@ ft2232_type = FTDI_FT2232H; else if (!strcasecmp(arg, "4232H")) ft2232_type = FTDI_FT4232H; + else if (!strcasecmp(arg, "jtagkey")) { + ft2232_type = 0xCFF8; + ft2232_interface = INTERFACE_A; + CS_Bits = 0x18; + Pin_Dir = 0x1b; + } else { msg_perr("Error: Invalid device type specified.\n"); free(arg); @@ -178,14 +195,9 @@ return -1; msg_pdbg("Set data bits\n"); - /* Set data bits low-byte command: - * value: 0x08 CS=high, DI=low, DO=low, SK=low - * dir: 0x0b CS=output, DI=input, DO=output, SK=output - */ -#define CS_BIT 0x08 buf[0] = SET_BITS_LOW; - buf[1] = CS_BIT; - buf[2] = 0x0b; + buf[1] = CS_Bits; + buf[2] = Pin_Dir; if (send_buf(ftdic, buf, 3)) return -1; @@ -230,8 +242,8 @@ */ msg_pspew("Assert CS#\n"); buf[i++] = SET_BITS_LOW; - buf[i++] = 0 & ~CS_BIT; /* assertive */ - buf[i++] = 0x0b; + buf[i++] = 0 & ~CS_Bits; /* assertive */ + buf[i++] = Pin_Dir; if (writecnt) { buf[i++] = 0x11; @@ -272,8 +284,8 @@ msg_pspew("De-assert CS#\n"); buf[i++] = SET_BITS_LOW; - buf[i++] = CS_BIT; - buf[i++] = 0x0b; + buf[i++] = CS_Bits; + buf[i++] = Pin_Dir; ret = send_buf(ftdic, buf, i); failed |= ret; if (ret)

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Testing MCP SPI patch
by Andrew Morgan 22 Jul '10

22 Jul '10

Attached is the result of flashrom -V with the latest MCP SPI patch. -- Andrew.

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Re: [flashrom] [PATCH] Move SB600 SPI initialization to sb600spi.c
by Carl-Daniel Hailfinger 22 Jul '10

22 Jul '10

On 22.07.2010 18:56, Michael Karcher wrote: > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > > --- a/sb600spi.c > +++ b/sb600spi.c > @@ -152,4 +152,80 @@ int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return 0; > } > > +int sb600_probe_spi(struct pci_dev *dev) > +{ > [...] > + msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); > + msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); > + if (reg != 0x00) > + return 0; > [...] > + msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); > + msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); > + if ((reg & 0x80) != 0x00) > + return 0; > [...] > + msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); > + if (reg != 0x00) > + return 0; > We might want to print a short msg_pdbg("Not enabling SPI"); in each of the cases where we return 0, but that's not strictly required and I want to get this patch in now. Please go ahead. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

Re: [flashrom] [PATCH 1/3] Move Intel SPI initialisation to ichspi.c
by Carl-Daniel Hailfinger 22 Jul '10

22 Jul '10

On 18.07.2010 16:19, Michael Karcher wrote: > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > --- > chipset_enable.c | 202 +-------------------------------------------------- > flash.h | 6 +- > ichspi.c | 214 +++++++++++++++++++++++++++++++++++++++++++++++++++++- > 3 files changed, 218 insertions(+), 204 deletions(-) > > diff --git a/chipset_enable.c b/chipset_enable.c > index dc0e55f..7434d65 100644 > --- a/chipset_enable.c > +++ b/chipset_enable.c > @@ -417,69 +417,15 @@ static int enable_flash_poulsbo(struct pci_dev *dev, const char *name) > > static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) > { > - uint32_t mmio_base; > - > /* Do we really need no write enable? */ > - mmio_base = (pci_read_long(dev, 0xbc)) << 8; > - msg_pdbg("MMIO base at = 0x%x\n", mmio_base); > - ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); > - > - msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", > - mmio_readw(ich_spibar + 0x6c)); > - > - /* Not sure if it speaks all these bus protocols. */ > - buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_VIA; > - ich_init_opcodes(); > - > - return 0; > -} > - > -#define ICH_BMWAG(x) ((x >> 24) & 0xff) > -#define ICH_BMRAG(x) ((x >> 16) & 0xff) > -#define ICH_BRWA(x) ((x >> 8) & 0xff) > -#define ICH_BRRA(x) ((x >> 0) & 0xff) > - > -#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) > -#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) > - > -static void do_ich9_spi_frap(uint32_t frap, int i) > -{ > - const char *access_names[4] = { > - "locked", "read-only", "write-only", "read-write" > - }; > - const char *region_names[5] = { > - "Flash Descriptor", "BIOS", "Management Engine", > - "Gigabit Ethernet", "Platform Data" > - }; > - uint32_t base, limit; > - int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | > - (((ICH_BRRA(frap) >> i) & 1) << 0); > - int offset = 0x54 + i * 4; > - uint32_t freg = mmio_readl(ich_spibar + offset); > - > - msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", > - offset, freg, i, region_names[i]); > - > - base = ICH_FREG_BASE(freg); > - limit = ICH_FREG_LIMIT(freg); > - if (base == 0x1fff && limit == 0) { > - /* this FREG is disabled */ > - msg_pdbg("%s region is unused.\n", region_names[i]); > - return; > - } > - > - msg_pdbg("0x%08x-0x%08x is %s\n", > - (base << 12), (limit << 12) | 0x0fff, > - access_names[rwperms]); > + return via_init_spi(dev); > } > > static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, > int ich_generation) > { > - int ret, i; > - uint8_t old, new, bbs, buc; > - uint16_t spibar_offset, tmp2; > + int ret; > + uint8_t bbs, buc; > uint32_t tmp, gcs; > void *rcrb; > //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line > @@ -518,147 +464,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, > return ret; > } > > - switch (ich_generation) { > - case 7: > - buses_supported = CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_ICH7; > - spibar_offset = 0x3020; > - break; > - case 8: > - buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_ICH9; > - spibar_offset = 0x3020; > - break; > - case 9: > - case 10: > - default: /* Future version might behave the same */ > - buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_ICH9; > - spibar_offset = 0x3800; > - break; > - } > - > - /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ > - msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); > - > - /* Assign Virtual Address */ > - ich_spibar = rcrb + spibar_offset; > - > - switch (spi_controller) { > - case SPI_CONTROLLER_ICH7: > - msg_pdbg("0x00: 0x%04x (SPIS)\n", > - mmio_readw(ich_spibar + 0)); > - msg_pdbg("0x02: 0x%04x (SPIC)\n", > - mmio_readw(ich_spibar + 2)); > - msg_pdbg("0x04: 0x%08x (SPIA)\n", > - mmio_readl(ich_spibar + 4)); > - for (i = 0; i < 8; i++) { > - int offs; > - offs = 8 + (i * 8); > - msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, > - mmio_readl(ich_spibar + offs), i); > - msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, > - mmio_readl(ich_spibar + offs + 4), i); > - } > - ichspi_bbar = mmio_readl(ich_spibar + 0x50); > - msg_pdbg("0x50: 0x%08x (BBAR)\n", > - ichspi_bbar); > - msg_pdbg("0x54: 0x%04x (PREOP)\n", > - mmio_readw(ich_spibar + 0x54)); > - msg_pdbg("0x56: 0x%04x (OPTYPE)\n", > - mmio_readw(ich_spibar + 0x56)); > - msg_pdbg("0x58: 0x%08x (OPMENU)\n", > - mmio_readl(ich_spibar + 0x58)); > - msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", > - mmio_readl(ich_spibar + 0x5c)); > - for (i = 0; i < 4; i++) { > - int offs; > - offs = 0x60 + (i * 4); > - msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, > - mmio_readl(ich_spibar + offs), i); > - } > - msg_pdbg("\n"); > - if (mmio_readw(ich_spibar) & (1 << 15)) { > - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); > - ichspi_lock = 1; > - } > - ich_init_opcodes(); > - break; > - case SPI_CONTROLLER_ICH9: > - tmp2 = mmio_readw(ich_spibar + 4); > - msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); > - msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); > - msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); > - msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); > - msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); > - msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); > - msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); > - msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); > - msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); > - > - tmp = mmio_readl(ich_spibar + 0x50); > - msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); > - msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); > - msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); > - msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); > - msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); > - > - /* print out the FREGx registers along with FRAP access bits */ > - for(i = 0; i < 5; i++) > - do_ich9_spi_frap(tmp, i); > - > - msg_pdbg("0x74: 0x%08x (PR0)\n", > - mmio_readl(ich_spibar + 0x74)); > - msg_pdbg("0x78: 0x%08x (PR1)\n", > - mmio_readl(ich_spibar + 0x78)); > - msg_pdbg("0x7C: 0x%08x (PR2)\n", > - mmio_readl(ich_spibar + 0x7C)); > - msg_pdbg("0x80: 0x%08x (PR3)\n", > - mmio_readl(ich_spibar + 0x80)); > - msg_pdbg("0x84: 0x%08x (PR4)\n", > - mmio_readl(ich_spibar + 0x84)); > - msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", > - mmio_readl(ich_spibar + 0x90)); > - msg_pdbg("0x94: 0x%04x (PREOP)\n", > - mmio_readw(ich_spibar + 0x94)); > - msg_pdbg("0x96: 0x%04x (OPTYPE)\n", > - mmio_readw(ich_spibar + 0x96)); > - msg_pdbg("0x98: 0x%08x (OPMENU)\n", > - mmio_readl(ich_spibar + 0x98)); > - msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", > - mmio_readl(ich_spibar + 0x9C)); > - ichspi_bbar = mmio_readl(ich_spibar + 0xA0); > - msg_pdbg("0xA0: 0x%08x (BBAR)\n", > - ichspi_bbar); > - msg_pdbg("0xB0: 0x%08x (FDOC)\n", > - mmio_readl(ich_spibar + 0xB0)); > - if (tmp2 & (1 << 15)) { > - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); > - ichspi_lock = 1; > - } > - ich_init_opcodes(); > - break; > - default: > - /* Nothing */ > - break; > - } > - > - old = pci_read_byte(dev, 0xdc); > - msg_pdbg("SPI Read Configuration: "); > - new = (old >> 2) & 0x3; > - switch (new) { > - case 0: > - case 1: > - case 2: > - msg_pdbg("prefetching %sabled, caching %sabled, ", > - (new & 0x2) ? "en" : "dis", > - (new & 0x1) ? "dis" : "en"); > - break; > - default: > - msg_pdbg("invalid prefetching/caching settings, "); > - break; > - } > - > + ich_init_spi(dev, tmp, rcrb, ich_generation); > check for the return value? > return ret; > } > > diff --git a/flash.h b/flash.h > index c3302c4..a8ca6d7 100644 > --- a/flash.h > +++ b/flash.h > @@ -680,10 +680,10 @@ int default_spi_send_multicommand(struct spi_command *cmds); > uint32_t spi_get_valid_read_addr(void); > > /* ichspi.c */ > -extern int ichspi_lock; > extern uint32_t ichspi_bbar; > -extern void *ich_spibar; > -int ich_init_opcodes(void); > +void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, > whitespace after * and at the end of the line. > + int ich_generation); > +int via_init_spi(struct pci_dev * dev); > whitespace after * > int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr); > int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > diff --git a/ichspi.c b/ichspi.c > index d6f9118..246f3ae 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -101,11 +101,11 @@ > #define ICH7_REG_OPMENU 0x58 /* 64 Bits */ > > /* ICH SPI configuration lock-down. May be set during chipset enabling. */ > -int ichspi_lock = 0; > +static int ichspi_lock = 0; > > uint32_t ichspi_bbar = 0; > > -void *ich_spibar = NULL; > +static void *ich_spibar = NULL; > > typedef struct _OPCODE { > uint8_t opcode; //This commands spi opcode > @@ -364,7 +364,7 @@ void ich_set_bbar(uint32_t minaddr) > * > * It should be called before ICH sends any spi command. > */ > -int ich_init_opcodes(void) > +static int ich_init_opcodes(void) > { > int rc = 0; > OPCODES *curopcodes_done; > @@ -398,6 +398,214 @@ int ich_init_opcodes(void) > } > } > > +#define ICH_BMWAG(x) ((x >> 24) & 0xff) > +#define ICH_BMRAG(x) ((x >> 16) & 0xff) > +#define ICH_BRWA(x) ((x >> 8) & 0xff) > +#define ICH_BRRA(x) ((x >> 0) & 0xff) > + > +#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) > +#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) > + > +static void do_ich9_spi_frap(uint32_t frap, int i) > +{ > + const char *access_names[4] = { > + "locked", "read-only", "write-only", "read-write" > + }; > + const char *region_names[5] = { > + "Flash Descriptor", "BIOS", "Management Engine", > + "Gigabit Ethernet", "Platform Data" > + }; > + uint32_t base, limit; > + int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | > + (((ICH_BRRA(frap) >> i) & 1) << 0); > + int offset = 0x54 + i * 4; > + uint32_t freg = mmio_readl(ich_spibar + offset); > + > + msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", > + offset, freg, i, region_names[i]); > + > + base = ICH_FREG_BASE(freg); > + limit = ICH_FREG_LIMIT(freg); > + if (base == 0x1fff && limit == 0) { > + /* this FREG is disabled */ > + msg_pdbg("%s region is unused.\n", region_names[i]); > + return; > + } > + > + msg_pdbg("0x%08x-0x%08x is %s\n", > + (base << 12), (limit << 12) | 0x0fff, > + access_names[rwperms]); > +} > Is the FRAP/FREG stuff really SPI specific? If not, it should stay in chipset_enable.c AFAICS. > + > +void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, > whitespace after * and at end of line Can you make this function return an error value? > + int ich_generation) > +{ > + int i; > + uint8_t old, new; > + uint16_t spibar_offset, tmp2; > + uint32_t tmp; > + > + switch (ich_generation) { > + case 7: > + buses_supported = CHIP_BUSTYPE_SPI; > + spi_controller = SPI_CONTROLLER_ICH7; > + spibar_offset = 0x3020; > + break; > + case 8: > + buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > Is adding BUSTYPE_FWH to buses_supported a good idea here in ichspi.c? > + spi_controller = SPI_CONTROLLER_ICH9; > + spibar_offset = 0x3020; > + break; > + case 9: > + case 10: > + default: /* Future version might behave the same */ > + buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > + spi_controller = SPI_CONTROLLER_ICH9; > + spibar_offset = 0x3800; > + break; > + } > + > + /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ > + msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset); > + > + /* Assign Virtual Address */ > + ich_spibar = rcrb + spibar_offset; > + > + switch (spi_controller) { > + case SPI_CONTROLLER_ICH7: > + msg_pdbg("0x00: 0x%04x (SPIS)\n", > + mmio_readw(ich_spibar + 0)); > + msg_pdbg("0x02: 0x%04x (SPIC)\n", > + mmio_readw(ich_spibar + 2)); > + msg_pdbg("0x04: 0x%08x (SPIA)\n", > + mmio_readl(ich_spibar + 4)); > + for (i = 0; i < 8; i++) { > + int offs; > + offs = 8 + (i * 8); > + msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, > + mmio_readl(ich_spibar + offs), i); > + msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, > + mmio_readl(ich_spibar + offs + 4), i); > + } > + ichspi_bbar = mmio_readl(ich_spibar + 0x50); > + msg_pdbg("0x50: 0x%08x (BBAR)\n", > + ichspi_bbar); > + msg_pdbg("0x54: 0x%04x (PREOP)\n", > + mmio_readw(ich_spibar + 0x54)); > + msg_pdbg("0x56: 0x%04x (OPTYPE)\n", > + mmio_readw(ich_spibar + 0x56)); > + msg_pdbg("0x58: 0x%08x (OPMENU)\n", > + mmio_readl(ich_spibar + 0x58)); > + msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", > + mmio_readl(ich_spibar + 0x5c)); > + for (i = 0; i < 4; i++) { > + int offs; > + offs = 0x60 + (i * 4); > + msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, > + mmio_readl(ich_spibar + offs), i); > + } > + msg_pdbg("\n"); > + if (mmio_readw(ich_spibar) & (1 << 15)) { > + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); > + ichspi_lock = 1; > + } > + ich_init_opcodes(); > + break; > + case SPI_CONTROLLER_ICH9: > + tmp2 = mmio_readw(ich_spibar + 4); > + msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); > + msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); > + msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); > + msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); > + msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); > + msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); > + msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); > + msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); > + msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); > + > + tmp = mmio_readl(ich_spibar + 0x50); > + msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); > + msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); > + msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); > + msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); > + msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); > + > + /* print out the FREGx registers along with FRAP access bits */ > + for(i = 0; i < 5; i++) > + do_ich9_spi_frap(tmp, i); > + > + msg_pdbg("0x74: 0x%08x (PR0)\n", > + mmio_readl(ich_spibar + 0x74)); > + msg_pdbg("0x78: 0x%08x (PR1)\n", > + mmio_readl(ich_spibar + 0x78)); > + msg_pdbg("0x7C: 0x%08x (PR2)\n", > + mmio_readl(ich_spibar + 0x7C)); > + msg_pdbg("0x80: 0x%08x (PR3)\n", > + mmio_readl(ich_spibar + 0x80)); > + msg_pdbg("0x84: 0x%08x (PR4)\n", > + mmio_readl(ich_spibar + 0x84)); > + msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", > + mmio_readl(ich_spibar + 0x90)); > + msg_pdbg("0x94: 0x%04x (PREOP)\n", > + mmio_readw(ich_spibar + 0x94)); > + msg_pdbg("0x96: 0x%04x (OPTYPE)\n", > + mmio_readw(ich_spibar + 0x96)); > + msg_pdbg("0x98: 0x%08x (OPMENU)\n", > + mmio_readl(ich_spibar + 0x98)); > + msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", > + mmio_readl(ich_spibar + 0x9C)); > + ichspi_bbar = mmio_readl(ich_spibar + 0xA0); > + msg_pdbg("0xA0: 0x%08x (BBAR)\n", > + ichspi_bbar); > + msg_pdbg("0xB0: 0x%08x (FDOC)\n", > + mmio_readl(ich_spibar + 0xB0)); > + if (tmp2 & (1 << 15)) { > + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); > + ichspi_lock = 1; > + } > + ich_init_opcodes(); > + break; > + default: > + /* Nothing */ > + break; > + } > + > + old = pci_read_byte(dev, 0xdc); > + msg_pdbg("SPI Read Configuration: "); > + new = (old >> 2) & 0x3; > + switch (new) { > + case 0: > + case 1: > + case 2: > + msg_pdbg("prefetching %sabled, caching %sabled, ", > + (new & 0x2) ? "en" : "dis", > + (new & 0x1) ? "dis" : "en"); > + break; > + default: > + msg_pdbg("invalid prefetching/caching settings, "); > + break; > + } > +} > + > +int via_init_spi(struct pci_dev * dev) > whitespace after * > +{ > + uint32_t mmio_base; > + > + mmio_base = (pci_read_long(dev, 0xbc)) << 8; > + msg_pdbg("MMIO base at = 0x%x\n", mmio_base); > + ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); > + > + msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", > + mmio_readw(ich_spibar + 0x6c)); > + > + /* Not sure if it speaks all these bus protocols. */ > + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > + spi_controller = SPI_CONTROLLER_VIA; > + ich_init_opcodes(); > + > + return 0; > +} > + > static int ich7_run_opcode(OPCODE op, uint32_t offset, > uint8_t datalength, uint8_t * data, int maxdata) > { > Looks good otherwise. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 3

[results of]# lspci -vvvnnxxx
by Greg Scantlen 22 Jul '10

22 Jul '10

see attached lspci.txt

1 0

[commit] r1099 - trunk
by repository service 22 Jul '10

22 Jul '10

Author: mkarcher Date: Thu Jul 22 20:04:19 2010 New Revision: 1099 URL: http://flashrom.org/trac/coreboot/changeset/1099 Log: Move SB600 SPI initialization to sb600spi.c Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c trunk/flash.h trunk/sb600spi.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Thu Jul 22 20:04:15 2010 (r1098) +++ trunk/chipset_enable.c Thu Jul 22 20:04:19 2010 (r1099) @@ -693,10 +693,9 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name) { - uint32_t tmp, prot; + uint32_t prot; uint8_t reg; - struct pci_dev *smbus_dev; - int has_spi = 1; + int ret; /* Clear ROM protect 0-3. */ for (reg = 0x50; reg < 0x60; reg += 4) { @@ -720,80 +719,9 @@ (prot & 0xfffffc00) + ((prot & 0x3ff) << 8)); } - /* Read SPI_BaseAddr */ - tmp = pci_read_long(dev, 0xa0); - tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ - msg_pdbg("SPI base address is at 0x%x\n", tmp); - - /* If the BAR has address 0, it is unlikely SPI is used. */ - if (!tmp) - has_spi = 0; - - if (has_spi) { - /* Physical memory has to be mapped at page (4k) boundaries. */ - sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, - 0x1000); - /* The low bits of the SPI base address are used as offset into - * the mapped page. - */ - sb600_spibar += tmp & 0xfff; - - tmp = pci_read_long(dev, 0xa0); - msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " - "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, - (tmp & 0x4) >> 2); - tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; - msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); - - tmp = pci_read_byte(dev, 0xbb); - msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", - tmp & 0x1, (tmp & 0x20) >> 5); - tmp = mmio_readl(sb600_spibar); - msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " - "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " - "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", - (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, - (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, - (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); - } - - /* Look for the SMBus device. */ - smbus_dev = pci_dev_find(0x1002, 0x4385); - - if (has_spi && !smbus_dev) { - msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); - has_spi = 0; - } - if (has_spi) { - /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ - /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ - reg = pci_read_byte(smbus_dev, 0xAB); - reg &= 0xC0; - msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); - msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); - if (reg != 0x00) - has_spi = 0; - /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ - reg = pci_read_byte(smbus_dev, 0x83); - reg &= 0xC0; - msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); - msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); - /* SPI_HOLD is not used on all boards, filter it out. */ - if ((reg & 0x80) != 0x00) - has_spi = 0; - /* GPIO47/SPI_CLK status */ - reg = pci_read_byte(smbus_dev, 0xA7); - reg &= 0x40; - msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); - if (reg != 0x00) - has_spi = 0; - } - buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; - if (has_spi) { - buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_SB600; - } + + ret = sb600_probe_spi(dev); /* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); @@ -830,7 +758,7 @@ OUTB(0x0e, 0xcd7); */ - return 0; + return ret; } static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name) Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Thu Jul 22 20:04:15 2010 (r1098) +++ trunk/flash.h Thu Jul 22 20:04:19 2010 (r1099) @@ -719,11 +719,11 @@ int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* sb600spi.c */ +int sb600_probe_spi(struct pci_dev *dev); int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); -extern uint8_t *sb600_spibar; /* wbsio_spi.c */ int wbsio_check_for_spi(void); Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Thu Jul 22 20:04:15 2010 (r1098) +++ trunk/sb600spi.c Thu Jul 22 20:04:19 2010 (r1099) @@ -40,7 +40,7 @@ *}; */ -uint8_t *sb600_spibar = NULL; +static uint8_t *sb600_spibar = NULL; int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { @@ -152,4 +152,86 @@ return 0; } +int sb600_probe_spi(struct pci_dev *dev) +{ + struct pci_dev *smbus_dev; + uint32_t tmp; + uint8_t reg; + /* Read SPI_BaseAddr */ + tmp = pci_read_long(dev, 0xa0); + tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ + msg_pdbg("SPI base address is at 0x%x\n", tmp); + + /* If the BAR has address 0, it is unlikely SPI is used. */ + if (!tmp) + return 0; + + /* Physical memory has to be mapped at page (4k) boundaries. */ + sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, + 0x1000); + /* The low bits of the SPI base address are used as offset into + * the mapped page. + */ + sb600_spibar += tmp & 0xfff; + + tmp = pci_read_long(dev, 0xa0); + msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " + "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, + (tmp & 0x4) >> 2); + tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; + msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); + + tmp = pci_read_byte(dev, 0xbb); + msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", + tmp & 0x1, (tmp & 0x20) >> 5); + tmp = mmio_readl(sb600_spibar); + msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " + "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " + "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", + (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, + (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, + (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); + + /* Look for the SMBus device. */ + smbus_dev = pci_dev_find(0x1002, 0x4385); + + if (!smbus_dev) { + msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); + return ERROR_NONFATAL; + } + + /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ + /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ + reg = pci_read_byte(smbus_dev, 0xAB); + reg &= 0xC0; + msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); + msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); + if (reg != 0x00) { + msg_pdbg("Not enabling SPI"); + return 0; + } + /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ + reg = pci_read_byte(smbus_dev, 0x83); + reg &= 0xC0; + msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); + msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); + /* SPI_HOLD is not used on all boards, filter it out. */ + if ((reg & 0x80) != 0x00) { + msg_pdbg("Not enabling SPI"); + return 0; + } + /* GPIO47/SPI_CLK status */ + reg = pci_read_byte(smbus_dev, 0xA7); + reg &= 0x40; + msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); + if (reg != 0x00) { + msg_pdbg("Not enabling SPI"); + return 0; + } + + buses_supported |= CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_SB600; + return 0; +} + #endif

1 0

[commit] r1098 - trunk
by repository service 22 Jul '10

22 Jul '10

Author: mkarcher Date: Thu Jul 22 20:04:15 2010 New Revision: 1098 URL: http://flashrom.org/trac/coreboot/changeset/1098 Log: Move Intel SPI initialisation to ichspi.c Smarter version could decide whether SPI is vital or not depending on straps. Straps are currently implemented for ICH7. EP80579 is in the comment, PCH of 5 Series/3400 Series has "LPC, reserved, PCI, SPI". Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c trunk/flash.h trunk/ichspi.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Thu Jul 22 17:20:43 2010 (r1097) +++ trunk/chipset_enable.c Thu Jul 22 20:04:15 2010 (r1098) @@ -417,69 +417,15 @@ static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) { - uint32_t mmio_base; - /* Do we really need no write enable? */ - mmio_base = (pci_read_long(dev, 0xbc)) << 8; - msg_pdbg("MMIO base at = 0x%x\n", mmio_base); - ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); - - msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", - mmio_readw(ich_spibar + 0x6c)); - - /* Not sure if it speaks all these bus protocols. */ - buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_VIA; - ich_init_opcodes(); - - return 0; -} - -#define ICH_BMWAG(x) ((x >> 24) & 0xff) -#define ICH_BMRAG(x) ((x >> 16) & 0xff) -#define ICH_BRWA(x) ((x >> 8) & 0xff) -#define ICH_BRRA(x) ((x >> 0) & 0xff) - -#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) -#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) - -static void do_ich9_spi_frap(uint32_t frap, int i) -{ - const char *access_names[4] = { - "locked", "read-only", "write-only", "read-write" - }; - const char *region_names[5] = { - "Flash Descriptor", "BIOS", "Management Engine", - "Gigabit Ethernet", "Platform Data" - }; - uint32_t base, limit; - int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | - (((ICH_BRRA(frap) >> i) & 1) << 0); - int offset = 0x54 + i * 4; - uint32_t freg = mmio_readl(ich_spibar + offset); - - msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", - offset, freg, i, region_names[i]); - - base = ICH_FREG_BASE(freg); - limit = ICH_FREG_LIMIT(freg); - if (base == 0x1fff && limit == 0) { - /* this FREG is disabled */ - msg_pdbg("%s region is unused.\n", region_names[i]); - return; - } - - msg_pdbg("0x%08x-0x%08x is %s\n", - (base << 12), (limit << 12) | 0x0fff, - access_names[rwperms]); + return via_init_spi(dev); } static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, int ich_generation) { - int ret, i; - uint8_t old, new, bbs, buc; - uint16_t spibar_offset, tmp2; + int ret; + uint8_t bbs, buc; uint32_t tmp, gcs; void *rcrb; //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line @@ -512,152 +458,22 @@ * on ICH7 when the southbridge is strapped to LPC */ - if (ich_generation == 7 && bbs == ICH_STRAP_LPC) { - buses_supported = CHIP_BUSTYPE_FWH; - /* No further SPI initialization required */ - return ret; - } - - switch (ich_generation) { - case 7: - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH7; - spibar_offset = 0x3020; - break; - case 8: - buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH9; - spibar_offset = 0x3020; - break; - case 9: - case 10: - default: /* Future version might behave the same */ - buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH9; - spibar_offset = 0x3800; - break; - } - - /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ - msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); - - /* Assign Virtual Address */ - ich_spibar = rcrb + spibar_offset; - - switch (spi_controller) { - case SPI_CONTROLLER_ICH7: - msg_pdbg("0x00: 0x%04x (SPIS)\n", - mmio_readw(ich_spibar + 0)); - msg_pdbg("0x02: 0x%04x (SPIC)\n", - mmio_readw(ich_spibar + 2)); - msg_pdbg("0x04: 0x%08x (SPIA)\n", - mmio_readl(ich_spibar + 4)); - for (i = 0; i < 8; i++) { - int offs; - offs = 8 + (i * 8); - msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, - mmio_readl(ich_spibar + offs), i); - msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, - mmio_readl(ich_spibar + offs + 4), i); - } - ichspi_bbar = mmio_readl(ich_spibar + 0x50); - msg_pdbg("0x50: 0x%08x (BBAR)\n", - ichspi_bbar); - msg_pdbg("0x54: 0x%04x (PREOP)\n", - mmio_readw(ich_spibar + 0x54)); - msg_pdbg("0x56: 0x%04x (OPTYPE)\n", - mmio_readw(ich_spibar + 0x56)); - msg_pdbg("0x58: 0x%08x (OPMENU)\n", - mmio_readl(ich_spibar + 0x58)); - msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", - mmio_readl(ich_spibar + 0x5c)); - for (i = 0; i < 4; i++) { - int offs; - offs = 0x60 + (i * 4); - msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, - mmio_readl(ich_spibar + offs), i); - } - msg_pdbg("\n"); - if (mmio_readw(ich_spibar) & (1 << 15)) { - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); - ichspi_lock = 1; - } - ich_init_opcodes(); - break; - case SPI_CONTROLLER_ICH9: - tmp2 = mmio_readw(ich_spibar + 4); - msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); - msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); - msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); - msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); - msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); - msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); - msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); - msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); - msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); - - tmp = mmio_readl(ich_spibar + 0x50); - msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); - msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); - msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); - msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); - msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); - - /* print out the FREGx registers along with FRAP access bits */ - for(i = 0; i < 5; i++) - do_ich9_spi_frap(tmp, i); - - msg_pdbg("0x74: 0x%08x (PR0)\n", - mmio_readl(ich_spibar + 0x74)); - msg_pdbg("0x78: 0x%08x (PR1)\n", - mmio_readl(ich_spibar + 0x78)); - msg_pdbg("0x7C: 0x%08x (PR2)\n", - mmio_readl(ich_spibar + 0x7C)); - msg_pdbg("0x80: 0x%08x (PR3)\n", - mmio_readl(ich_spibar + 0x80)); - msg_pdbg("0x84: 0x%08x (PR4)\n", - mmio_readl(ich_spibar + 0x84)); - msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", - mmio_readl(ich_spibar + 0x90)); - msg_pdbg("0x94: 0x%04x (PREOP)\n", - mmio_readw(ich_spibar + 0x94)); - msg_pdbg("0x96: 0x%04x (OPTYPE)\n", - mmio_readw(ich_spibar + 0x96)); - msg_pdbg("0x98: 0x%08x (OPMENU)\n", - mmio_readl(ich_spibar + 0x98)); - msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", - mmio_readl(ich_spibar + 0x9C)); - ichspi_bbar = mmio_readl(ich_spibar + 0xA0); - msg_pdbg("0xA0: 0x%08x (BBAR)\n", - ichspi_bbar); - msg_pdbg("0xB0: 0x%08x (FDOC)\n", - mmio_readl(ich_spibar + 0xB0)); - if (tmp2 & (1 << 15)) { - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); - ichspi_lock = 1; - } - ich_init_opcodes(); - break; - default: - /* Nothing */ - break; - } - - old = pci_read_byte(dev, 0xdc); - msg_pdbg("SPI Read Configuration: "); - new = (old >> 2) & 0x3; - switch (new) { - case 0: - case 1: - case 2: - msg_pdbg("prefetching %sabled, caching %sabled, ", - (new & 0x2) ? "en" : "dis", - (new & 0x1) ? "dis" : "en"); - break; - default: - msg_pdbg("invalid prefetching/caching settings, "); - break; - } + buses_supported = CHIP_BUSTYPE_FWH; + if (ich_generation == 7) { + if(bbs == ICH_STRAP_LPC) { + /* No further SPI initialization required */ + return ret; + } + else + /* Disable LPC/FWH if strapped to PCI or SPI */ + buses_supported = 0; + } + + /* this adds CHIP_BUSTYPE_SPI */ + if (ich_init_spi(dev, tmp, rcrb, ich_generation) != 0) { + if (!ret) + ret = ERROR_NONFATAL; + } return ret; } @@ -1546,6 +1362,8 @@ msg_pinfo("FAILED!\n"); else if(ret == 0) msg_pinfo("OK.\n"); + else if(ret == ERROR_NONFATAL) + msg_pinfo("PROBLEMS, continuing anyway\n"); } msg_pinfo("This chipset supports the following protocols: %s.\n", Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Thu Jul 22 17:20:43 2010 (r1097) +++ trunk/flash.h Thu Jul 22 20:04:15 2010 (r1098) @@ -607,6 +607,9 @@ #define OK 0 #define NT 1 /* Not tested */ +/* Something happened that shouldn't happen, but we can go on */ +#define ERROR_NONFATAL 0x100 + /* cli_output.c */ /* Let gcc and clang check for correct printf-style format strings. */ int print(int type, const char *fmt, ...) __attribute__((format(printf, 2, 3))); @@ -694,10 +697,10 @@ uint32_t spi_get_valid_read_addr(void); /* ichspi.c */ -extern int ichspi_lock; extern uint32_t ichspi_bbar; -extern void *ich_spibar; -int ich_init_opcodes(void); +int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, + int ich_generation); +int via_init_spi(struct pci_dev *dev); int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Thu Jul 22 17:20:43 2010 (r1097) +++ trunk/ichspi.c Thu Jul 22 20:04:15 2010 (r1098) @@ -101,11 +101,11 @@ #define ICH7_REG_OPMENU 0x58 /* 64 Bits */ /* ICH SPI configuration lock-down. May be set during chipset enabling. */ -int ichspi_lock = 0; +static int ichspi_lock = 0; uint32_t ichspi_bbar = 0; -void *ich_spibar = NULL; +static void *ich_spibar = NULL; typedef struct _OPCODE { uint8_t opcode; //This commands spi opcode @@ -364,7 +364,7 @@ * * It should be called before ICH sends any spi command. */ -int ich_init_opcodes(void) +static int ich_init_opcodes(void) { int rc = 0; OPCODES *curopcodes_done; @@ -863,4 +863,211 @@ return ret; } +#define ICH_BMWAG(x) ((x >> 24) & 0xff) +#define ICH_BMRAG(x) ((x >> 16) & 0xff) +#define ICH_BRWA(x) ((x >> 8) & 0xff) +#define ICH_BRRA(x) ((x >> 0) & 0xff) + +#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) +#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) + +static void do_ich9_spi_frap(uint32_t frap, int i) +{ + const char *access_names[4] = { + "locked", "read-only", "write-only", "read-write" + }; + const char *region_names[5] = { + "Flash Descriptor", "BIOS", "Management Engine", + "Gigabit Ethernet", "Platform Data" + }; + uint32_t base, limit; + int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | + (((ICH_BRRA(frap) >> i) & 1) << 0); + int offset = 0x54 + i * 4; + uint32_t freg = mmio_readl(ich_spibar + offset); + + msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", + offset, freg, i, region_names[i]); + + base = ICH_FREG_BASE(freg); + limit = ICH_FREG_LIMIT(freg); + if (base == 0x1fff && limit == 0) { + /* this FREG is disabled */ + msg_pdbg("%s region is unused.\n", region_names[i]); + return; + } + + msg_pdbg("0x%08x-0x%08x is %s\n", + (base << 12), (limit << 12) | 0x0fff, + access_names[rwperms]); +} + +int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, + int ich_generation) +{ + int i; + uint8_t old, new; + uint16_t spibar_offset, tmp2; + uint32_t tmp; + + buses_supported |= CHIP_BUSTYPE_SPI; + switch (ich_generation) { + case 7: + spi_controller = SPI_CONTROLLER_ICH7; + spibar_offset = 0x3020; + break; + case 8: + spi_controller = SPI_CONTROLLER_ICH9; + spibar_offset = 0x3020; + break; + case 9: + case 10: + default: /* Future version might behave the same */ + spi_controller = SPI_CONTROLLER_ICH9; + spibar_offset = 0x3800; + break; + } + + /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ + msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset); + + /* Assign Virtual Address */ + ich_spibar = rcrb + spibar_offset; + + switch (spi_controller) { + case SPI_CONTROLLER_ICH7: + msg_pdbg("0x00: 0x%04x (SPIS)\n", + mmio_readw(ich_spibar + 0)); + msg_pdbg("0x02: 0x%04x (SPIC)\n", + mmio_readw(ich_spibar + 2)); + msg_pdbg("0x04: 0x%08x (SPIA)\n", + mmio_readl(ich_spibar + 4)); + for (i = 0; i < 8; i++) { + int offs; + offs = 8 + (i * 8); + msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, + mmio_readl(ich_spibar + offs), i); + msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, + mmio_readl(ich_spibar + offs + 4), i); + } + ichspi_bbar = mmio_readl(ich_spibar + 0x50); + msg_pdbg("0x50: 0x%08x (BBAR)\n", + ichspi_bbar); + msg_pdbg("0x54: 0x%04x (PREOP)\n", + mmio_readw(ich_spibar + 0x54)); + msg_pdbg("0x56: 0x%04x (OPTYPE)\n", + mmio_readw(ich_spibar + 0x56)); + msg_pdbg("0x58: 0x%08x (OPMENU)\n", + mmio_readl(ich_spibar + 0x58)); + msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", + mmio_readl(ich_spibar + 0x5c)); + for (i = 0; i < 4; i++) { + int offs; + offs = 0x60 + (i * 4); + msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, + mmio_readl(ich_spibar + offs), i); + } + msg_pdbg("\n"); + if (mmio_readw(ich_spibar) & (1 << 15)) { + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); + ichspi_lock = 1; + } + ich_init_opcodes(); + break; + case SPI_CONTROLLER_ICH9: + tmp2 = mmio_readw(ich_spibar + 4); + msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); + msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); + msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); + msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); + msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); + msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); + msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); + msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); + msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); + + tmp = mmio_readl(ich_spibar + 0x50); + msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); + msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); + msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); + msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); + msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); + + /* print out the FREGx registers along with FRAP access bits */ + for(i = 0; i < 5; i++) + do_ich9_spi_frap(tmp, i); + + msg_pdbg("0x74: 0x%08x (PR0)\n", + mmio_readl(ich_spibar + 0x74)); + msg_pdbg("0x78: 0x%08x (PR1)\n", + mmio_readl(ich_spibar + 0x78)); + msg_pdbg("0x7C: 0x%08x (PR2)\n", + mmio_readl(ich_spibar + 0x7C)); + msg_pdbg("0x80: 0x%08x (PR3)\n", + mmio_readl(ich_spibar + 0x80)); + msg_pdbg("0x84: 0x%08x (PR4)\n", + mmio_readl(ich_spibar + 0x84)); + msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", + mmio_readl(ich_spibar + 0x90)); + msg_pdbg("0x94: 0x%04x (PREOP)\n", + mmio_readw(ich_spibar + 0x94)); + msg_pdbg("0x96: 0x%04x (OPTYPE)\n", + mmio_readw(ich_spibar + 0x96)); + msg_pdbg("0x98: 0x%08x (OPMENU)\n", + mmio_readl(ich_spibar + 0x98)); + msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", + mmio_readl(ich_spibar + 0x9C)); + ichspi_bbar = mmio_readl(ich_spibar + 0xA0); + msg_pdbg("0xA0: 0x%08x (BBAR)\n", + ichspi_bbar); + msg_pdbg("0xB0: 0x%08x (FDOC)\n", + mmio_readl(ich_spibar + 0xB0)); + if (tmp2 & (1 << 15)) { + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); + ichspi_lock = 1; + } + ich_init_opcodes(); + break; + default: + /* Nothing */ + break; + } + + old = pci_read_byte(dev, 0xdc); + msg_pdbg("SPI Read Configuration: "); + new = (old >> 2) & 0x3; + switch (new) { + case 0: + case 1: + case 2: + msg_pdbg("prefetching %sabled, caching %sabled, ", + (new & 0x2) ? "en" : "dis", + (new & 0x1) ? "dis" : "en"); + break; + default: + msg_pdbg("invalid prefetching/caching settings, "); + break; + } + return 0; +} + +int via_init_spi(struct pci_dev *dev) +{ + uint32_t mmio_base; + + mmio_base = (pci_read_long(dev, 0xbc)) << 8; + msg_pdbg("MMIO base at = 0x%x\n", mmio_base); + ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); + + msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", + mmio_readw(ich_spibar + 0x6c)); + + /* Not sure if it speaks all these bus protocols. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_VIA; + ich_init_opcodes(); + + return 0; +} + #endif

1 0

[results of]# flashrom -VV
by Greg Scantlen 22 Jul '10

22 Jul '10

[bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Eon EN25F10, 128 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Eon EN25F20, 256 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Eon EN25F40, 512 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Eon EN25F80, 1024 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Eon EN25F16, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Eon EN25F32, 4096 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Eon EN29F010, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F004BV/BE-B, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F004BV/BE-T, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F400BV/CV/CE-B, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F400BV/CV/CE-T, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX25L1005, 128 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX25L2005, 256 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX25L4005, 512 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX25L8005, 1024 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX25L1605, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX25L1635D, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX25L3205, 4096 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX25L3235D, 4096 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX25L6405, 8192 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX25L12805, 16384 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Numonyx M25PE20, 256 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Numonyx M25PE40, 512 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Numonyx M25PE80, 1024 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Numonyx M25PE16, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for PMC Pm25LV010, 128 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for PMC Pm25LV016B, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for PMC Pm25LV020, 256 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for PMC Pm25LV040, 512 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for PMC Pm25LV080B, 1024 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for PMC Pm25LV512, 64 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm39LV020, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm39LV040, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL008A, 1024 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Spansion S25FL016A, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for SST SST25VF016B, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for SST SST25VF032B, 4096 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for SST SST25VF040.REMS, 512 KB: sb600_spi_send_command, cmd=90, writecnt=3, readcnt=2 [0] [0] [0] [ 0][ 0][ 0]The FIFO pointer after skipping is 0. [00][00] REMS returned 00 00. probe_spi_rems: id1 0x0, id2 0x0 Probing for SST SST25VF040B, 512 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for SST SST25VF040B.REMS, 512 KB: sb600_spi_send_command, cmd=90, writecnt=3, readcnt=2 [0] [0] [0] [ 0][ 0][ 0]The FIFO pointer after skipping is 0. [00][00] REMS returned 00 00. probe_spi_rems: id1 0x0, id2 0x0 Probing for SST SST25VF080B, 1024 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for SST SST28SF040A, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for ST M25P05.RES, 64 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for ST M25P10.RES, 128 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for ST M25P40, 512 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for ST M25P40-old, 512 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for ST M25P16, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for ST M25P32, 4096 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for ST M25P64, 8192 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for ST M25P128, 16384 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for ST M29F002B, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W25Q80, 1024 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Winbond W25Q16, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Winbond W25Q32, 4096 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Winbond W25x10, 128 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Winbond W25x20, 256 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Winbond W25x40, 512 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Winbond W25x80, 1024 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Winbond W25x16, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Winbond W25x32, 4096 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Winbond W25x64, 8192 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Winbond W29C011, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel unknown Atmel SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Not unmapping zero size at (nil) Probing for EON unknown EON SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Not unmapping zero size at (nil) Probing for Macronix unknown Macronix SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Not unmapping zero size at (nil) Probing for PMC unknown PMC SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Not unmapping zero size at (nil) Probing for SST unknown SST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Found chip "SST unknown SST SPI chip" (0 KB, SPI) at physical address 0x0. Probing for ST unknown ST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Not unmapping zero size at (nil) Probing for Sanyo unknown Sanyo SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Not unmapping zero size at (nil) Probing for Generic unknown SPI chip (RDID), 0 KB: Not mapping flash chip, zero size at 0x00000000. sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Not unmapping zero size at (nil) Probing for Generic unknown SPI chip (REMS), 0 KB: Not mapping flash chip, zero size at 0x00000000. sb600_spi_send_command, cmd=90, writecnt=3, readcnt=2 [0] [0] [0] [ 0][ 0][ 0]The FIFO pointer after skipping is 0. [00][00] REMS returned 00 00. probe_spi_rems: id1 0x0, id2 0x0 Not unmapping zero size at (nil) === This flash part has status NOT WORKING for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Thanks for your help! === No operations were specified. [root@slinux ~]#

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Re: [flashrom] [PATCH 2/3] Move SB600 SPI initialization to sb600spi.c
by Carl-Daniel Hailfinger 22 Jul '10

22 Jul '10

On 18.07.2010 16:19, Michael Karcher wrote: > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > --- > chipset_enable.c | 79 ++--------------------------------------------------- > flash.h | 2 +- > sb600spi.c | 77 +++++++++++++++++++++++++++++++++++++++++++++++++++- > 3 files changed, 80 insertions(+), 78 deletions(-) > > diff --git a/chipset_enable.c b/chipset_enable.c > index 7434d65..ad3b732 100644 > --- a/chipset_enable.c > +++ b/chipset_enable.c > @@ -683,10 +683,8 @@ static int enable_flash_amd8111(struct pci_dev *dev, const char *name) > > static int enable_flash_sb600(struct pci_dev *dev, const char *name) > { > - uint32_t tmp, prot; > + uint32_t prot; > uint8_t reg; > - struct pci_dev *smbus_dev; > - int has_spi = 1; > > /* Clear ROM protect 0-3. */ > for (reg = 0x50; reg < 0x60; reg += 4) { > @@ -710,80 +708,9 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name) > (prot & 0xfffffc00) + ((prot & 0x3ff) << 8)); > } > > - /* Read SPI_BaseAddr */ > - tmp = pci_read_long(dev, 0xa0); > - tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ > - msg_pdbg("SPI base address is at 0x%x\n", tmp); > - > - /* If the BAR has address 0, it is unlikely SPI is used. */ > - if (!tmp) > - has_spi = 0; > - > - if (has_spi) { > - /* Physical memory has to be mapped at page (4k) boundaries. */ > - sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, > - 0x1000); > - /* The low bits of the SPI base address are used as offset into > - * the mapped page. > - */ > - sb600_spibar += tmp & 0xfff; > - > - tmp = pci_read_long(dev, 0xa0); > - msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " > - "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, > - (tmp & 0x4) >> 2); > - tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; > - msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); > - > - tmp = pci_read_byte(dev, 0xbb); > - msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", > - tmp & 0x1, (tmp & 0x20) >> 5); > - tmp = mmio_readl(sb600_spibar); > - msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " > - "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " > - "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", > - (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, > - (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, > - (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); > - } > - > - /* Look for the SMBus device. */ > - smbus_dev = pci_dev_find(0x1002, 0x4385); > - > - if (has_spi && !smbus_dev) { > - msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); > - has_spi = 0; > - } > - if (has_spi) { > - /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ > - /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ > - reg = pci_read_byte(smbus_dev, 0xAB); > - reg &= 0xC0; > - msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); > - msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); > - if (reg != 0x00) > - has_spi = 0; > - /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ > - reg = pci_read_byte(smbus_dev, 0x83); > - reg &= 0xC0; > - msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); > - msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); > - /* SPI_HOLD is not used on all boards, filter it out. */ > - if ((reg & 0x80) != 0x00) > - has_spi = 0; > - /* GPIO47/SPI_CLK status */ > - reg = pci_read_byte(smbus_dev, 0xA7); > - reg &= 0x40; > - msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); > - if (reg != 0x00) > - has_spi = 0; > - } > - > buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; > - if (has_spi) { > - buses_supported |= CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_SB600; > - } > + > + sb600_probe_spi(dev); > sb600_spi_probe should return an error code which is checked. > > /* Read ROM strap override register. */ > OUTB(0x8f, 0xcd6); > diff --git a/flash.h b/flash.h > index a8ca6d7..8ebea29 100644 > --- a/flash.h > +++ b/flash.h > @@ -702,11 +702,11 @@ int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int > int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* sb600spi.c */ > +void sb600_probe_spi(struct pci_dev * dev); > space after * > int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr); > int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > -extern uint8_t *sb600_spibar; > > /* wbsio_spi.c */ > int wbsio_check_for_spi(void); > diff --git a/sb600spi.c b/sb600spi.c > index caf1a99..e42b20b 100644 > --- a/sb600spi.c > +++ b/sb600spi.c > @@ -40,7 +40,82 @@ > *}; > */ > > -uint8_t *sb600_spibar = NULL; > +static uint8_t *sb600_spibar = NULL; > + > +void sb600_probe_spi(struct pci_dev * dev) > please make it return int, and kill the space after * > +{ > + struct pci_dev *smbus_dev; > + uint32_t tmp; > + uint8_t reg; > + /* Read SPI_BaseAddr */ > + tmp = pci_read_long(dev, 0xa0); > + tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ > + msg_pdbg("SPI base address is at 0x%x\n", tmp); > + > + /* If the BAR has address 0, it is unlikely SPI is used. */ > + if (!tmp) > + return; > that would be return 0 > + > + /* Physical memory has to be mapped at page (4k) boundaries. */ > + sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, > + 0x1000); > + /* The low bits of the SPI base address are used as offset into > + * the mapped page. > + */ > + sb600_spibar += tmp & 0xfff; > + > + tmp = pci_read_long(dev, 0xa0); > + msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " > + "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, > + (tmp & 0x4) >> 2); > + tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; > + msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); > + > + tmp = pci_read_byte(dev, 0xbb); > + msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", > + tmp & 0x1, (tmp & 0x20) >> 5); > + tmp = mmio_readl(sb600_spibar); > + msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " > + "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " > + "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", > + (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, > + (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, > + (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); > + > + /* Look for the SMBus device. */ > + smbus_dev = pci_dev_find(0x1002, 0x4385); > + > + if (!smbus_dev) { > + msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); > + return; > And this should be an error return. Do we want some define for ERROR_NONFATAL and make it some otherwise unusued value? Maybe 0x100 or something? > + } > + > + /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ > + /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ > + reg = pci_read_byte(smbus_dev, 0xAB); > + reg &= 0xC0; > + msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); > + msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); > + if (reg != 0x00) > + return; > Not an error, just a sign that SPI is not used. return 0; > + /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ > + reg = pci_read_byte(smbus_dev, 0x83); > + reg &= 0xC0; > + msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); > + msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); > + /* SPI_HOLD is not used on all boards, filter it out. */ > + if ((reg & 0x80) != 0x00) > + return; > return 0; > + /* GPIO47/SPI_CLK status */ > + reg = pci_read_byte(smbus_dev, 0xA7); > + reg &= 0x40; > + msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); > + if (reg != 0x00) > + return; > return 0; > + > + buses_supported |= CHIP_BUSTYPE_SPI; > + spi_controller = SPI_CONTROLLER_SB600; > +} > > int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > Looks good otherwise. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

Intel SE440BX
by Mattias Mattsson 22 Jul '10

22 Jul '10

Hi, I'm trying latest flashrom (r1082) an an Intel SE440BX. No flashchip is detected. I also tried to reuse the SE440BX-2 board enable but couldn't make it work. The flash on the board is an Intel E28F002BC-T80. Datasheet here: http://www.ezoflash.com/datasheets/flash/Intel/28F002BC.pdf I would like to add the chip to flashchips.c but was unsure how to interpret the datasheet and the corresponding values for probe/read/write function. Logs attached -mattias

4 5

[commit] r1097 - trunk
by repository service 22 Jul '10

22 Jul '10

Author: hailfinger Date: Thu Jul 22 17:20:43 2010 New Revision: 1097 URL: http://flashrom.org/trac/coreboot/changeset/1097 Log: Add support for the Intel 28F002BC-T. Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Thu Jul 22 13:44:38 2010 (r1096) +++ trunk/flashchips.c Thu Jul 22 17:20:43 2010 (r1097) @@ -2814,6 +2814,33 @@ { .vendor = "Intel", + .name = "28F002BC-T", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = INTEL_ID, + .model_id = P28F002BC, + .total_size = 256, + .page_size = 256 * 1024, + .tested = TEST_UNTESTED, + .probe = probe_82802ab, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .block_erasers = + { + { + .eraseblocks = { + {128 * 1024, 1}, + {96 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_block_82802ab, + }, + }, + .write = write_82802ab, + .read = read_memmapped, + }, + + { + .vendor = "Intel", .name = "28F004S5", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Thu Jul 22 13:44:38 2010 (r1096) +++ trunk/flashchips.h Thu Jul 22 17:20:43 2010 (r1097) @@ -274,6 +274,7 @@ #define E_28F016S5 0xAA #define P28F001BXT 0x94 /* 28F001BX-T */ #define P28F001BXB 0x95 /* 28F001BX-B */ +#define P28F002BC 0x7C /* 28F002BC-T */ #define P28F004BT 0x78 /* 28F004BV/BE-T */ #define P28F004BB 0x79 /* 28F004BV/BE-B */ #define P28F400BT 0x70 /* 28F400BV/CV/CE-T */

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[PATCH] Annotate evil twins
by Carl-Daniel Hailfinger 22 Jul '10

22 Jul '10

Evil twins are chips with identical IDs and different/incompatible characteristics (e.g. eraseblock layout, write strategy or size). Annotate them so flashrom can tell the user that it's not a matter of simply picking one of the chips in a list of multiple chips found. This patch only touches the AMIC A25L40PT and A25L40PU. I'm fairly sure there are more evil twins, but those two were touched recently. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-evil_twin/flash.h =================================================================== --- flashrom-evil_twin/flash.h (Revision 1096) +++ flashrom-evil_twin/flash.h (Arbeitskopie) @@ -180,6 +180,14 @@ #define FEATURE_ADDR_2AA (1 << 2) #define FEATURE_ADDR_AAA (2 << 2) #define FEATURE_ADDR_SHIFTED (1 << 5) +/* Evil twins are chips with the same ID and different erase/write + * characteristics. The second macro discards its arguments for now and allows + * human readable annotation while at the same time providing a zero cost + * simplified machine readable annotation. The first macro is there to check + * quickly if the chip has any evil twins. + */ +#define FEATURE_EVIL_TWIN (1 << 6) +#define FEATURE_EVIL_TWIN_OF(a,b) (1 << 6) struct flashchip { const char *vendor; Index: flashrom-evil_twin/flashchips.c =================================================================== --- flashrom-evil_twin/flashchips.c (Revision 1096) +++ flashrom-evil_twin/flashchips.c (Arbeitskopie) @@ -1372,6 +1372,7 @@ .model_id = AMIC_A25L40PT, .total_size = 512, .page_size = 256, + .feature_bits = FEATURE_EVIL_TWIN_OF("AMIC", "A25L40PU"), .tested = TEST_OK_PRW, .probe = probe_spi_rdid4, .probe_timing = TIMING_ZERO, @@ -1404,6 +1405,7 @@ .model_id = AMIC_A25L40PU, .total_size = 512, .page_size = 256, + .feature_bits = FEATURE_EVIL_TWIN_OF("AMIC", "A25L40PT"), .tested = TEST_OK_PRW, .probe = probe_spi_rdid4, .probe_timing = TIMING_ZERO, Index: flashrom-evil_twin/cli_classic.c =================================================================== --- flashrom-evil_twin/cli_classic.c (Revision 1096) +++ flashrom-evil_twin/cli_classic.c (Arbeitskopie) @@ -399,7 +399,8 @@ if (flashes[1]) { printf("Multiple flash chips were detected:"); for (i = 0; i < ARRAY_SIZE(flashes) && flashes[i]; i++) - printf(" %s", flashes[i]->name); + printf("%s %s%s", i ? "," : "", flashes[i]->name, + flashes[i]->feature_bits & FEATURE_EVIL_TWIN ? " (evil twin)" : ""); printf("\nPlease specify which chip to use with the -c <chipname> option.\n"); programmer_shutdown(); exit(1); -- http://www.hailfinger.org/

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Output of "flashrom -V" for E Machines ET1300
by Brett Mahar 22 Jul '10

22 Jul '10

brett@local:~$ sudo flashrom -V flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "eMachines" DMI string system-product-name: "ET1300" DMI string system-version: "R01-A1" DMI string baseboard-manufacturer: "eMachines" DMI string baseboard-product-name: "EMCP61PM-GM" DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found ITE Super I/O, id 8726 Found chipset "NVIDIA MCP61", enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Guessed flash bus type is SPI Found SMBus device 10de:03eb at 00:01:1 SPI BAR is at 0xfec80000, after clearing low bits BAR is at 0xfec80000 Mapping MCP67 SPI at 0xfec80000, unaligned size 0x544. SPI control is 0x000a, enable=0, idle=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. SPI on this chipset is not supported yet. OK. This chipset supports the following protocols: None. Calibrating delay loop... 647M loops per second, 100 myus = 199 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for EMST F49B002UA, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN29F010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Intel 82802AC, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Macronix MX25L512, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for PMC Pm49FL004, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF003A/B, 384 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF004A/B, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF004C, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF008A, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF008C, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF016C, 2048 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF020, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF020A, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF040, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF040B, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF080A, 1024 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF160C, 2048 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for ST M25P05-A, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW040B, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080A, 1024 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080B, 1024 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FW002, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW016, 2048 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW040, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW080, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50LPW116, 2048 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040B, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040C, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040FA, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080A, 1024 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W49F002U, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W49V002FA, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080FA, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. brett@local:~$

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