- flashrom - mail.coreboot.org

[commit] r1373 - trunk
by repository service 16 Jul '11

16 Jul '11

Author: hailfinger Date: Sat Jul 16 01:47:45 2011 New Revision: 1373 URL: http://flashrom.org/trac/flashrom/changeset/1373 Log: Fix and clean up cli_classic.c Don't ignore -i if it is specified before -l Check if image mentioned by -i is present in layout file Consolidate duplicated programmer_shutdown calls Kill outdated comments Finish parameter checking before -L/-z is executed Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: David Hendricks <dhendrix(a)google.com> Modified: trunk/cli_classic.c Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Wed Jul 13 22:48:54 2011 (r1372) +++ trunk/cli_classic.c Sat Jul 16 01:47:45 2011 (r1373) @@ -117,6 +117,7 @@ #endif int operation_specified = 0; int i; + int ret = 0; static const char optstring[] = "r:Rw:v:nVEfc:m:l:i:p:Lzh"; static const struct option long_options[] = { @@ -232,8 +233,14 @@ cli_classic_abort_usage(); break; case 'i': + /* FIXME: -l has to be specified before -i. */ tempstr = strdup(optarg); - find_romentry(tempstr); + if (find_romentry(tempstr)) { + fprintf(stderr, "Error: image %s not found in " + "layout file or -i specified before " + "-l\n", tempstr); + cli_classic_abort_usage(); + } break; case 'L': if (++operation_specified > 1) { @@ -313,6 +320,11 @@ } } + if (optind < argc) { + fprintf(stderr, "Error: Extra parameter found.\n"); + cli_classic_abort_usage(); + } + /* FIXME: Print the actions flashrom will take. */ if (list_supported) { @@ -327,11 +339,6 @@ } #endif - if (optind < argc) { - fprintf(stderr, "Error: Extra parameter found.\n"); - cli_classic_abort_usage(); - } - #if CONFIG_INTERNAL == 1 if ((programmer != PROGRAMMER_INTERNAL) && (lb_part || lb_vendor)) { fprintf(stderr, "Error: --mainboard requires the internal " @@ -360,8 +367,8 @@ if (programmer_init(pparam)) { fprintf(stderr, "Error: Programmer initialization failed.\n"); - programmer_shutdown(); - exit(1); + ret = 1; + goto out_shutdown; } for (i = 0; i < ARRAY_SIZE(flashes); i++) { @@ -377,8 +384,8 @@ for (i = 0; i < chipcount; i++) printf(" %s", flashes[i].name); printf("\nPlease specify which chip to use with the -c <chipname> option.\n"); - programmer_shutdown(); - exit(1); + ret = 1; + goto out_shutdown; } else if (!chipcount) { printf("No EEPROM/flash device found.\n"); if (!force || !chip_to_probe) { @@ -389,15 +396,14 @@ startchip = probe_flash(0, &flashes[0], 1); if (startchip == -1) { printf("Probing for flash chip '%s' failed.\n", chip_to_probe); - programmer_shutdown(); - exit(1); + ret = 1; + goto out_shutdown; } printf("Please note that forced reads most likely contain garbage.\n"); return read_flash_to_file(&flashes[0], filename); } - // FIXME: flash writes stay enabled! - programmer_shutdown(); - exit(1); + ret = 1; + goto out_shutdown; } fill_flash = &flashes[0]; @@ -409,22 +415,19 @@ (!force)) { fprintf(stderr, "Chip is too big for this programmer " "(-V gives details). Use --force to override.\n"); - programmer_shutdown(); - return 1; + ret = 1; + goto out_shutdown; } if (!(read_it | write_it | verify_it | erase_it)) { printf("No operations were specified.\n"); - // FIXME: flash writes stay enabled! - programmer_shutdown(); - exit(0); + goto out_shutdown; } if (!filename && !erase_it) { printf("Error: No filename specified.\n"); - // FIXME: flash writes stay enabled! - programmer_shutdown(); - exit(1); + ret = 1; + goto out_shutdown; } /* Always verify write operations unless -n is used. */ @@ -437,4 +440,8 @@ */ programmer_delay(100000); return doit(fill_flash, force, filename, read_it, write_it, erase_it, verify_it); + +out_shutdown: + programmer_shutdown(); + return ret; }

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Re: [flashrom] Atmel AT49LH002 support missing
by Stefan Tauner 15 Jul '11

15 Jul '11

On Fri, 15 Jul 2011 11:41:12 -0300 Marcos Felipe Rasia de Mello <marcosfrm(a)gmail.com> wrote: > Hi, > > I got another PCCHIPS M863G V5.1A, but this time the board came with > an Atmel AT49LH002 flash, which flashrom v0.9.3-r1362 doesn't detect. jup, this one is not supported yet. the datasheet can for example be found here: http://www.datasheetcatalog.org/datasheet/atmel/doc3377.pdf it supports LPC and FWH so it may share some characteristics with the Pm49FL002. patches are welcome ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

Atmel AT49LH002 support missing
by Marcos Felipe Rasia de Mello 15 Jul '11

15 Jul '11

Hi, I got another PCCHIPS M863G V5.1A, but this time the board came with an Atmel AT49LH002 flash, which flashrom v0.9.3-r1362 doesn't detect. Regards, Marcos

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Re: [flashrom] [PATCH 1/4] ichspi.c: refactor filling and reading the fdata/spid registers
by Carl-Daniel Hailfinger 15 Jul '11

15 Jul '11

Am 15.07.2011 02:39 schrieb Stefan Tauner: > - add ich_fill_data to fill the chipset registers from an array > - add ich_read_data to copy the data from the chipset register into an array > - replace the existing code with calls to those functions > - minor cosmetic changes > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > Excellent, please commit. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH 4/4] ichspi.c: add support for Intel Hardware Sequencing
by Stefan Tauner 15 Jul '11

15 Jul '11

todo: - revise hwseq activation: when should hwseq be used, when swseq? when should swseq be forbidden? etc. - commit message (is a link to my blog post a good idea (additionally)?) - revise (levels of) prints - revise timeout values (for optimal performance) - build upon the upcoming opaque interface framework instead Tested-by: David Hendricks <dhendrix(a)google.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 6 + flashchips.c | 23 ++++- flashchips.h | 2 + ich_descriptors.c | 35 ++++++ ich_descriptors.h | 1 + ichspi.c | 331 +++++++++++++++++++++++++++++++++++++++++++++++++++-- programmer.h | 1 + 7 files changed, 387 insertions(+), 12 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index 92ddbea..f97e2ad 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -84,6 +84,12 @@ void print_status_82802ab(uint8_t status); int unlock_82802ab(struct flashchip *flash); int unlock_28f004s5(struct flashchip *flash); +/* ichspi.c */ +int ich_hwseq_probe(struct flashchip *flash); +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int ich_hwseq_block_erase(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); + /* jedec.c */ uint8_t oddparity(uint8_t val); void toggle_ready_jedec(chipaddr dst); diff --git a/flashchips.c b/flashchips.c index 1b5c88a..1fbdcfe 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8507,7 +8507,27 @@ const struct flashchip flashchips[] = { .write = write_jedec_1, .read = read_memmapped, }, - +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) + { + .vendor = "Intel", + .name = "Hardware Sequencing", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = INTEL_ID, + .model_id = INTEL_HWSEQ, + .total_size = 0, + .page_size = 256, + .tested = TEST_OK_PREW, + .probe = ich_hwseq_probe, + .block_erasers = + { + { /* erase blocks will be set by the probing function */ + .block_erase = ich_hwseq_block_erase, + } + }, + .write = ich_hwseq_write_256, + .read = ich_hwseq_read, + }, +#endif // defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) { .vendor = "AMIC", .name = "unknown AMIC SPI chip", @@ -8640,6 +8660,7 @@ const struct flashchip flashchips[] = { .probe = probe_spi_rdid, .write = NULL, }, + { .vendor = "Generic", .name = "unknown SPI chip (REMS)", diff --git a/flashchips.h b/flashchips.h index 3b2b94f..6b8d574 100644 --- a/flashchips.h +++ b/flashchips.h @@ -340,6 +340,8 @@ #define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ #define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */ +#define INTEL_HWSEQ 0xFFFE /* dummy ID for hardware sequencing */ + #define ISSI_ID 0xD5 /* ISSI Integrated Silicon Solutions */ /* diff --git a/ich_descriptors.c b/ich_descriptors.c index 0281488..c54e710 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -393,6 +393,41 @@ int read_ich_descriptors_from_dump(const uint32_t *dump, enum chipset cs, struct } #else // ICH_DESCRIPTORS_FROM_MMAP_DUMP +/** Returns the integer representation of the component density with index +idx in bytes or 0 if a correct size can not be determined. */ +int getFCBA_component_density(uint8_t idx, const struct flash_descriptors *desc) +{ + uint8_t size_enc; + const int dec_mem[6] = { + 512 * 1024, + 1 * 1024 * 1024, + 2 * 1024 * 1024, + 4 * 1024 * 1024, + 8 * 1024 * 1024, + 16 * 1024 * 1024, + }; + + switch(idx) { + case 0: + size_enc = desc->component.comp1_density; + break; + case 1: + if (desc->content.NC == 0) + return 0; + size_enc = desc->component.comp2_density; + break; + default: + msg_perr("Only component index 0 or 1 are supported yet.\n"); + return 0; + } + if (size_enc > 5) { + msg_perr("Density of component with index %d is invalid. " + "Encoded density is 0x%x.\n", idx, size_enc); + return 0; + } + return dec_mem[size_enc]; +} + static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) { uint32_t control = 0; diff --git a/ich_descriptors.h b/ich_descriptors.h index 1129805..fd56b26 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -452,6 +452,7 @@ int read_ich_descriptors_from_dump(const uint32_t *dump, enum chipset cs, struct #else // ICH_DESCRIPTORS_FROM_MMAP_DUMP void read_ich_descriptors_via_fdo(void *spibar, struct flash_descriptors *desc); +int getFCBA_component_density(uint8_t idx, const struct flash_descriptors *desc); #endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP #endif // __ICH_DESCRIPTORS_H__ diff --git a/ichspi.c b/ichspi.c index edca654..9597c05 100644 --- a/ichspi.c +++ b/ichspi.c @@ -23,10 +23,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if defined(__i386__) || defined(__x86_64__) +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) #include <string.h> #include "flash.h" +#include "flashchips.h" #include "chipdrivers.h" #include "programmer.h" #include "spi.h" @@ -1073,6 +1074,298 @@ static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, return result; } +static struct hwseq { + uint32_t size_comp0; + uint32_t size_comp1; +} hwseq; + +static void ich_hwseq_set_addr(uint32_t addr) +{ + uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF; + REGWRITE32(ICH9_REG_FADDR, (addr & 0x01FFFFFF) | addr_old); +} + +/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes + * of the block containing this address. */ +static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr) +{ + uint8_t enc_berase; + const uint32_t dec_berase[4] = { + 256, + 4 * 1024, + 8 * 1024, + 64 * 1024 + }; + + ich_hwseq_set_addr(addr); + enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> + HSFS_BERASE_OFF; + return dec_berase[enc_berase]; +} + +/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 10 us intervals. + Resets all error flags in HSFS. + Returns 0 if the cycle completes successfully without errors within + timeout us, 1 on errors. */ +static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, + unsigned int len) +{ + uint16_t hsfs; + uint32_t addr; + + while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) & + (HSFS_FDONE | HSFS_FCERR)) == 0) && + --timeout) { + programmer_delay(10); + } + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + if (!timeout) { + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + msg_perr("Timeout error between offset 0x%08x and " + "0x%08x + %d (=0x%08x)!\n", + addr, addr, len - 1, addr + len - 1); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + return 1; + } + + if (hsfs & HSFS_FCERR) { + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + msg_perr("Transaction error between offset 0x%08x and " + "0x%08x + %d (=0x%08x)!\n", + addr, addr, len - 1, addr + len - 1); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + return 1; + } + return 0; +} + +int ich_hwseq_probe(struct flashchip *flash) +{ + uint32_t total_size, boundary; + uint32_t erase_size_low, size_low, erase_size_high, size_high; + struct block_eraser *eraser; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_cerr("This chip (%s) is not supported in hardware" + "sequencing mode and should never have been probed.\n", + flash->name); + msg_cerr("%s: Please report a bug at flashrom(a)flashrom.org\n", + __func__); + return 0; + } + + msg_cdbg("Prerequisites for Intel Hardware Sequencing are "); + if (spi_programmer->type != SPI_CONTROLLER_ICH_HWSEQ) { + msg_cdbg("not met.\n"); + return 0; + } + msg_cdbg("met.\n"); + + total_size = hwseq.size_comp0 + hwseq.size_comp1; + msg_cdbg("Found %d attached SPI flash chip", + (hwseq.size_comp1 != 0) ? 2 : 1); + if (hwseq.size_comp1 != 0) + msg_cdbg("s with a combined"); + else + msg_cdbg(" with a"); + msg_cdbg(" density of %d kB.\n", total_size / 1024); + flash->total_size = total_size / 1024; + + eraser = &(flash->block_erasers[0]); + boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; + size_high = total_size - boundary; + erase_size_high = ich_hwseq_get_erase_block_size(boundary); + + if (boundary == 0) { + msg_cdbg("There is only one partition containing the whole " + "address space (0x%06x - 0x%06x).\n", 0, size_high-1); + eraser->eraseblocks[0].size = erase_size_high; + eraser->eraseblocks[0].count = size_high / erase_size_high; + msg_cdbg("There are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } else { + msg_cdbg("The flash address space (0x%06x - 0x%06x) is divided " + "at address 0x%06x in two partitions.\n", + 0, size_high-1, boundary); + size_low = total_size - size_high; + erase_size_low = ich_hwseq_get_erase_block_size(0); + + eraser->eraseblocks[0].size = erase_size_low; + eraser->eraseblocks[0].count = size_low / erase_size_low; + msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n", + 0, size_low-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_low / erase_size_low, erase_size_low); + + eraser->eraseblocks[1].size = erase_size_high; + eraser->eraseblocks[1].count = size_high / erase_size_high; + msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n", + boundary, size_high-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } + return 1; +} + +static int ich_hwseq_send_command(unsigned int writecnt, + unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + msg_pdbg("skipped. Intel Hardware Sequencing does not support sending " + "arbitrary commands."); + return -1; +} + +int ich_hwseq_block_erase(struct flashchip *flash, + unsigned int addr, + unsigned int len) +{ + uint32_t erase_block; + uint16_t hsfc; + uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + erase_block = ich_hwseq_get_erase_block_size(addr); + if (len != erase_block) { + msg_cerr("Erase block size for address 0x%06x is %d B, " + "but requested erase block size is %d B. " + "Not erasing anything.\n", addr, erase_block, len); + return -1; + } + + /* Although the hardware supports this (it would erase the whole block + * containing the address) we play safe here. */ + if (addr % erase_block != 0) { + msg_cerr("Erase address 0x%06x is not aligned to the erase " + "block boundary (any multiple of %d). " + "Not erasing anything.\n", addr, erase_block); + return -1; + } + + if (addr + len > flash->total_size * 1024) { + msg_perr("Request to erase some inaccessible memory address(es)" + " (addr=0x%x, len=%d). " + "Not erasing anything.\n", addr, len); + return -1; + } + + msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); + + /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFC_FGO; /* start */ + msg_pdbg("HSFC used for block erasing: "); + prettyprint_ich9_reg_hsfc(hsfc); + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, len)) + return -1; + return 0; +} + +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode.\n", flash->name); + return -1; + } + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to read from an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + block_len = min(len, spi_programmer->max_data_read); + ich_hwseq_set_addr(addr); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* set read operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return 1; + ich_read_data(buf, block_len, ICH9_REG_FDATA0); + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to write to an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + ich_hwseq_set_addr(addr); + block_len = min(len, spi_programmer->max_data_write); + ich_fill_data(buf, block_len, ICH9_REG_FDATA0); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return -1; + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + static int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; @@ -1191,6 +1484,16 @@ static const struct spi_programmer spi_programmer_ich9 = { .write_256 = default_spi_write_256, }; +static const struct spi_programmer spi_programmer_ich_hwseq = { + .type = SPI_CONTROLLER_ICH_HWSEQ, + .max_data_read = 64, + .max_data_write = 64, + .command = ich_hwseq_send_command, + .multicommand = default_spi_send_multicommand, + .read = ich_hwseq_read, + .write_256 = ich_hwseq_write_256, +}; + int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation) { @@ -1199,20 +1502,18 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint16_t spibar_offset, tmp2; uint32_t tmp; int ichspi_desc = 0; + struct flash_descriptors desc = {{ 0 }}; switch (ich_generation) { case 7: - register_spi_programmer(&spi_programmer_ich7); spibar_offset = 0x3020; break; case 8: - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3800; break; } @@ -1223,8 +1524,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: + switch (ich_generation) { + case 7: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", @@ -1260,9 +1561,13 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + register_spi_programmer(&spi_programmer_ich7); ich_init_opcodes(); break; - case SPI_CONTROLLER_ICH9: + case 8: + case 9: + case 10: + default: /* Future version might behave the same */ tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); @@ -1338,15 +1643,19 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pdbg("\n"); if (ichspi_desc) { - struct flash_descriptors desc = {{ 0 }}; read_ich_descriptors_via_fdo(ich_spibar, &desc); prettyprint_ich_descriptors(CHIPSET_UNKNOWN, &desc); + if (ichspi_lock || desc.content.NC != 0) { + hwseq.size_comp0 = getFCBA_component_density(0, &desc); + hwseq.size_comp1 = getFCBA_component_density(1, &desc); + register_spi_programmer(&spi_programmer_ich_hwseq); + break; + } } + + register_spi_programmer(&spi_programmer_ich9); ich_init_opcodes(); break; - default: - /* Nothing */ - break; } old = pci_read_byte(dev, 0xdc); diff --git a/programmer.h b/programmer.h index 6a28dbe..6e316d1 100644 --- a/programmer.h +++ b/programmer.h @@ -517,6 +517,7 @@ enum spi_controller { #if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, + SPI_CONTROLLER_ICH_HWSEQ, SPI_CONTROLLER_IT85XX, SPI_CONTROLLER_IT87XX, SPI_CONTROLLER_SB600, -- 1.7.1

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[PATCH 3/4] add ich_descriptor_tool to decode all flash descriptors stored in a flash dump file
by Stefan Tauner 15 Jul '11

15 Jul '11

additionally to what is available via FDOC/FDOD...<TODO> TODO: - fix msg_perr - decode all ibex straps Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ich_descriptors.c | 186 ++++++++++++++++++++ ich_descriptors.h | 200 ++++++++++++++++++++++ util/ich_descriptors_tool/Makefile | 42 +++++ util/ich_descriptors_tool/TODO | 5 + util/ich_descriptors_tool/ich_descriptors_tool.c | 197 +++++++++++++++++++++ 5 files changed, 630 insertions(+), 0 deletions(-) create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c diff --git a/ich_descriptors.c b/ich_descriptors.c index 43b2c52..0281488 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -22,8 +22,21 @@ #if defined(__i386__) || defined(__x86_64__) #include "ich_descriptors.h" + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + +#define DESCRIPTOR_MODE_MAGIC 0x0ff0a55a +#define msg_pdbg printf +#define msg_pspew printf +#define msg_perr printf +#include <stdio.h> + +#else + #include "flash.h" /* for msg_* */ +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP + uint32_t getFCBA(const struct flash_content *cont) { return (cont->FLMAP0 << 4) & 0x00000ff0; @@ -59,12 +72,26 @@ uint32_t getFISBA(const struct flash_content *cont) return (cont->FLMAP1 >> 12) & 0x00000ff0; } +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP +uint32_t getVTBA(const struct flash_upper_map *flumap) +{ /* The bits in FLUMAP1 describe bits 4-11 out of 24 in total; + * others are 0. */ + return (flumap->FLUMAP1 << 4) & 0x0ff0; +} +#endif + void prettyprint_ich_descriptors(enum chipset cs, const struct flash_descriptors *desc) { prettyprint_ich_descriptor_content(&desc->content); prettyprint_ich_descriptor_component(desc); prettyprint_ich_descriptor_region(&desc->region); prettyprint_ich_descriptor_master(&desc->master); +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + if (cs >= CHIPSET_ICH8) { + prettyprint_ich_descriptor_upper_map(&desc->upper); + prettyprint_ich_descriptor_straps(cs, &desc->straps); + } +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP } void prettyprint_ich_descriptor_content(const struct flash_content *cont) @@ -208,6 +235,164 @@ void prettyprint_ich9_reg_vscc(uint32_t reg_val) pprint_reg(VSCC, VCL, reg_val, "\n"); } +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP +void prettyprint_ich_descriptor_straps_ich8(const struct flash_strap *straps) +{ + const char * const str_GPIO12[4] = { + "GPIO12", + "LAN PHY Power Control Function (Native Output)", + "GLAN_DOCK# (Native Input)", + "invalid configuration", + }; + + msg_pdbg1("=== FISBA ===\n"); + msg_pdbg1("STRP0 0x%8.8x\n", straps->ich8.STRPs[0]); + msg_pdbg1("\n"); + + msg_pdbg2("--- FISBA details ---\n"); + msg_pdbg2("ME SMBus addr2 0x%2.2x\n", straps->ich8.ASD2); + msg_pdbg2("ME SMBus addr1 0x%2.2x\n", straps->ich8.ASD); + msg_pdbg2("ME SMBus Controller is connected to %s\n", straps->ich8.MESM2SEL ? "SMLink pins" : "SMBus pins"); + msg_pdbg2("SPI CS1 is used for %s\n", straps->ich8.SPICS1_LANPHYPC_SEL ? "LAN PHY Power Control Function" : "SPI Chip Select"); + msg_pdbg2("GPIO12_SEL is used as %s\n", str_GPIO12[straps->ich8.GPIO12_SEL]); + msg_pdbg2("PCIe Port 6 is used for %s\n", straps->ich8.GLAN_PCIE_SEL ? "integrated GLAN" : "PCI Express"); + msg_pdbg2("Intel AMT SMBus Controller 1 is connected to %s\n", straps->ich8.BMCMODE ? "SMLink" : "SMBus"); + msg_pdbg2("TCO slave is on %s. Intel AMT SMBus Controller 1 is %sabled\n", + straps->ich8.TCOMODE ? "SMBus" : "SMLink", straps->ich8.TCOMODE ? "en" : "dis"); + msg_pdbg2("ME A is %sabled\n", straps->ich8.ME_DISABLE ? "dis" : "en"); + + msg_pdbg2("\n"); + msg_pdbg2("=== FMSBA ===\n"); + msg_pdbg2("STRP1 0x%8.8x\n", straps->ich8.STRPs[1]); + + msg_pdbg2("\n"); + msg_pdbg2("--- FMSBA details ---\n"); + msg_pdbg2("ME B is %sabled\n", straps->ich8.ME_disable_B ? "dis" : "en"); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_straps_ibex(const struct flash_strap *straps) +{ + int i; + msg_pdbg2("=== FPSBA ===\n"); + /* TODO: decode properly */ + for(i = 0; i <= 15; i++) + msg_pdbg2("STRP%-2d = 0x%8.8x\n", i, straps->ibex.STRPs[i]); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_straps(enum chipset cs, const struct flash_strap *straps) +{ + switch (cs) { + case CHIPSET_ICH8: + prettyprint_ich_descriptor_straps_ich8(straps); + break; + case CHIPSET_SERIES_5_IBEX_PEAK: + /* PCH straps only. PROCSTRPs are unknown. */ + prettyprint_ich_descriptor_straps_ibex(straps); + break; + case CHIPSET_UNKNOWN: + break; + default: + msg_pdbg2("The meaning of the descriptor straps are unknown yet.\n"); + msg_pdbg2("\n"); + break; + } +} + +void prettyprint_rdid(uint32_t reg_val) +{ + uint8_t mid = reg_val & 0xFF; + uint16_t did = ((reg_val >> 16) & 0xFF) | (reg_val & 0xFF00); + msg_pdbg2("Manufacturer ID 0x%02x, Device ID 0x%04x\n", mid, did); +} + +void prettyprint_ich_descriptor_upper_map(const struct flash_upper_map *umap) +{ + int i; + msg_pdbg1("=== FLUMAP ===\n"); + msg_pdbg1("FLUMAP1 0x%8.8x\n", umap->FLUMAP1); + msg_pdbg1("\n"); + + msg_pdbg2("--- FLUMAP details ---\n"); + msg_pdbg2("VTL (length) = %d\n", umap->VTL); + msg_pdbg2("VTBA (base address) = 0x%6.6x\n", getVTBA(umap)); + msg_pdbg2("\n"); + + msg_pdbg2("VSCC Table:\n"); + for (i=0; i < umap->VTL/2; i++) + { + uint32_t jid = umap->vscc_table[i].JID; + uint32_t vscc = umap->vscc_table[i].VSCC; + msg_pdbg2(" JID%d = 0x%8.8x\n", i, jid); + msg_pdbg2(" VSCC%d = 0x%8.8x\n", i, vscc); + msg_pdbg2(" "); /* indention */ + prettyprint_rdid(jid); + msg_pdbg2(" "); /* indention */ + prettyprint_ich9_reg_vscc(vscc); + } + msg_pdbg2("\n"); +} + +int read_ich_descriptors_from_dump(const uint32_t *dump, enum chipset cs, struct flash_descriptors *desc) +{ + int i; + uint8_t pch_bug_offset = 0; + if (dump[0] != DESCRIPTOR_MODE_MAGIC) { + if (dump[4] == DESCRIPTOR_MODE_MAGIC) + pch_bug_offset = 4; + else + return -1; + } + + /* map */ + desc->content.FLVALSIG = dump[0 + pch_bug_offset]; + desc->content.FLMAP0 = dump[1 + pch_bug_offset]; + desc->content.FLMAP1 = dump[2 + pch_bug_offset]; + desc->content.FLMAP2 = dump[3 + pch_bug_offset]; + + /* component */ + desc->component.FLCOMP = dump[(getFCBA(&desc->content) >> 2) + 0]; + desc->component.FLILL = dump[(getFCBA(&desc->content) >> 2) + 1]; + desc->component.FLPB = dump[(getFCBA(&desc->content) >> 2) + 2]; + + /* region */ + desc->region.FLREG0 = dump[(getFRBA(&desc->content) >> 2) + 0]; + desc->region.FLREG1 = dump[(getFRBA(&desc->content) >> 2) + 1]; + desc->region.FLREG2 = dump[(getFRBA(&desc->content) >> 2) + 2]; + desc->region.FLREG3 = dump[(getFRBA(&desc->content) >> 2) + 3]; + + /* master */ + desc->master.FLMSTR1 = dump[(getFMBA(&desc->content) >> 2) + 0]; + desc->master.FLMSTR2 = dump[(getFMBA(&desc->content) >> 2) + 1]; + desc->master.FLMSTR3 = dump[(getFMBA(&desc->content) >> 2) + 2]; + + /* upper map */ + desc->upper.FLUMAP1 = dump[(0x0efc >> 2) + 0]; + + for (i=0; i < desc->upper.VTL; i++) + { + desc->upper.vscc_table[i].JID = dump[(getVTBA(&desc->upper) >> 2) + i * 2 + 0]; + desc->upper.vscc_table[i].VSCC = dump[(getVTBA(&desc->upper) >> 2) + i * 2 + 1]; + } + /* straps */ + switch (cs) { + case CHIPSET_ICH8: + desc->straps.ich8.STRPs[0] = dump[(getFISBA(&desc->content) >> 2) + 0]; + desc->straps.ich8.STRPs[1] = dump[(getFMSBA(&desc->content) >> 2) + 0]; + break; + case CHIPSET_SERIES_5_IBEX_PEAK: + for(i = 0; i <= 15; i++) + desc->straps.ibex.STRPs[i] = dump[(getFISBA(&desc->content) >> 2) + i]; + break; + default: + break; + } + + return 0; +} +#else // ICH_DESCRIPTORS_FROM_MMAP_DUMP + static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) { uint32_t control = 0; @@ -247,4 +432,5 @@ void read_ich_descriptors_via_fdo(void *spibar, struct flash_descriptors *desc) msg_pdbg1(" done\n"); } +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP #endif // defined(__i386__) || defined(__x86_64__) diff --git a/ich_descriptors.h b/ich_descriptors.h index 9954149..1129805 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -238,11 +238,202 @@ struct flash_master { }; }; +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP +struct flash_strap { + union { + union { + uint32_t STRPs[2]; + struct { + struct { + uint32_t ME_DISABLE :1; + uint32_t :6; + uint32_t TCOMODE :1; + uint32_t ASD :7; + uint32_t BMCMODE :1; + uint32_t :3; + uint32_t GLAN_PCIE_SEL :1; + uint32_t GPIO12_SEL :2; + uint32_t SPICS1_LANPHYPC_SEL :1; + uint32_t MESM2SEL :1; + uint32_t :1; + uint32_t ASD2 :7; + }; + struct { + uint32_t ME_disable_B :1; + uint32_t :31; + }; + }; + }ich8; + union { + uint32_t STRPs[15]; + struct { + struct { + uint32_t :1; + uint32_t cs_ss2 :1; + uint32_t :5; + uint32_t SMB_EN :1; + uint32_t SML0_EN :1; + uint32_t SML1_EN :1; + uint32_t SML1FRQ :2; + uint32_t SMB0FRQ :2; + uint32_t SML0FRQ :2; + uint32_t :4; + uint32_t LANPHYPC_GP12_SEL :1; + uint32_t cs_ss1 :1; + uint32_t :2; + uint32_t DMI_REQID_DIS :1; + uint32_t :4; + uint32_t BBBS :2; + uint32_t :1; + }; + struct { + uint32_t cs_ss3 :4; + uint32_t :28; + }; + struct { + uint32_t :8; + uint32_t MESMASDEN :1; + uint32_t MESMASDA :7; + uint32_t :8; + uint32_t MESMI2CEN :1; + uint32_t MESMI2CA :7; + }; + struct { + uint32_t :32; + }; + struct { + uint32_t PHYCON :2; + uint32_t :6; + uint32_t GBEMAC_SMBUS_ADDR_EN :1; + uint32_t GBEMAC_SMBUS_ADDR :7; + uint32_t :1; + uint32_t GBEPHY_SMBUS_ADDR :7; + uint32_t :8; + }; + struct { + uint32_t :32; + }; + struct { + uint32_t :32; + }; + struct { + uint32_t MESMA2UDID_DEVICE :16; + uint32_t MESMA2UDID_VENDOR :16; + }; + struct { + uint32_t :32; + }; + struct { + uint32_t PCIEPCS1 :2; + uint32_t PCIEPCS2 :2; + uint32_t PCIELR1 :1; + uint32_t PCIELR2 :1; + uint32_t DMILR :1; + uint32_t :1; + uint32_t PHY_PCIEPORTSEL :3; + uint32_t PHY_PCIE_EN :1; + uint32_t :20; + }; + struct { + uint32_t :1; + uint32_t ME_BOOT_FLASH :1; + uint32_t cs_ss5 :1; + uint32_t VE_EN :1; + uint32_t :4; + uint32_t MMDDE :1; + uint32_t MMADDR :7; + uint32_t cs_ss7 :1; + uint32_t :1; + uint32_t ICC_SEL :3; + uint32_t MER_CL1 :1; + uint32_t :10; + }; + struct { + uint32_t SML1GPAEN :1; + uint32_t SML1GPA :7; + uint32_t :10; + uint32_t SML1I2CAEN :1; + uint32_t SML1I2CA :7; + }; + struct { + uint32_t :32; + }; + struct { + uint32_t :32; + }; + struct { + uint32_t :8; + uint32_t VE_EN2 :1; + uint32_t :5; + uint32_t VE_BOOT_FLASH :1; + uint32_t :1; + uint32_t BW_SSD :1; + uint32_t NVMHCI_EN :1; + uint32_t :14; + }; + struct { + uint32_t :3; + uint32_t cs_ss6 :2; + uint32_t :1; + uint32_t IWL_EN :1; + uint32_t :1; + uint32_t t209min :2; + uint32_t :22; + }; + }; + }ibex; + }; +}; + +struct flash_upper_map { + union { + uint32_t FLUMAP1; + struct { + uint32_t VTBA :8; + uint32_t VTL :8; + uint32_t :16; + }; + }; + struct { + union { + uint32_t JID; + struct { + uint8_t vid :8; + uint8_t cid0 :8; + uint8_t cid1 :8; + uint32_t :8; + }; + }; + union { + uint32_t VSCC; + struct { + uint32_t ubes :2; + uint32_t uwg :1; + uint32_t uwsr :1; + uint32_t uwews :1; + uint32_t :3; + uint32_t ueo :8; + uint32_t lbes :2; + uint32_t lwg :1; + uint32_t lwsr :1; + uint32_t lwews :1; + uint32_t :3; + uint32_t leo :16; + }; + }; + }vscc_table[128]; +}; +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP + struct flash_descriptors { struct flash_content content; struct flash_component component; struct flash_region region; struct flash_master master; +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + struct flash_strap straps; + struct flash_upper_map upper; +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP }; void prettyprint_ich_descriptors(enum chipset, const struct flash_descriptors *desc); @@ -252,7 +443,16 @@ void prettyprint_ich_descriptor_component(const struct flash_descriptors *desc); void prettyprint_ich_descriptor_region(const struct flash_region *region); void prettyprint_ich_descriptor_master(const struct flash_master *master); +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + +void prettyprint_ich_descriptor_upper_map(const struct flash_upper_map *umap); +void prettyprint_ich_descriptor_straps(enum chipset cs, const struct flash_strap *straps); +int read_ich_descriptors_from_dump(const uint32_t *dump, enum chipset cs, struct flash_descriptors *desc); + +#else // ICH_DESCRIPTORS_FROM_MMAP_DUMP + void read_ich_descriptors_via_fdo(void *spibar, struct flash_descriptors *desc); +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP #endif // __ICH_DESCRIPTORS_H__ #endif // defined(__i386__) || defined(__x86_64__) diff --git a/util/ich_descriptors_tool/Makefile b/util/ich_descriptors_tool/Makefile new file mode 100644 index 0000000..1d7f056 --- /dev/null +++ b/util/ich_descriptors_tool/Makefile @@ -0,0 +1,42 @@ +CC ?= gcc + +PROGRAM=ich_descriptors_tool +EXTRAINCDIRS = ../../ . +DEPPATH = .dep +OBJATH = .obj +SHAREDSRC = ich_descriptors.c +SHAREDSRCDIR = ../.. + +SRC = $(wildcard *.c) + +CFLAGS=-Wall +CFLAGS += -MMD -MP -MF $(DEPPATH)/$((a)F).d +# enables functions that populate the descriptor structs from plain binary dumps +CFLAGS += -D ICH_DESCRIPTORS_FROM_MMAP_DUMP +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +OBJ = $(OBJATH)/$(SRC:%.c=%.o) + +SHAREDOBJ = $(OBJATH)/$(notdir $(SHAREDSRC:%.c=%.o)) + +all:$(PROGRAM) + +$(OBJ): $(OBJATH)/%.o : %.c + $(CC) $(CFLAGS) -o $@ -c $< + +# this enables us to share source files without simultaneously sharing .o files +# with flashrom, which would lead to unexpected results (w/o running make clean) +$(SHAREDOBJ): $(OBJATH)/%.o : $(SHAREDSRCDIR)/%.c + $(CC) $(CFLAGS) -o $@ -c $< + +$(PROGRAM): $(OBJ) $(SHAREDOBJ) + $(CC) -o $(PROGRAM) $(OBJ) $(SHAREDOBJ) + +clean: + rm -f $(PROGRAM) + rm -rf $(DEPPATH) $(OBJATH) + +# Include the dependency files. +-include $(shell mkdir -p $(DEPPATH) $(OBJATH) 2>/dev/null) $(wildcard $(DEPPATH)/*) + +.PHONY: all clean diff --git a/util/ich_descriptors_tool/TODO b/util/ich_descriptors_tool/TODO new file mode 100644 index 0000000..e3933ee --- /dev/null +++ b/util/ich_descriptors_tool/TODO @@ -0,0 +1,5 @@ +- reverse the path, as in assemble a descriptormode image from various + blobs (BIOS, GbE, ME, OEM) and a description (xml? custom config? + sane defaults and cmd-line switches?) +- dump 256 OEM bytes +- handle descriptors of various chipsets correctly \ No newline at end of file diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c new file mode 100644 index 0000000..f6fd77a --- /dev/null +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -0,0 +1,197 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (C) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * dump information and binaries from BIOS images that are in descriptor mode + */ +#include <stdio.h> +#include <stdint.h> +#include <stdlib.h> +#include <sys/mman.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <unistd.h> +#include <string.h> +#include <errno.h> +#include "ich_descriptors.h" + +static void dump_file(const char *filename, const char *suf, uint32_t offset, uint32_t length, const uint32_t *dump) +{ + int ret; + char *n = malloc(strlen(filename) + strlen(suf) + 1); + + if (!n) { + fprintf(stderr, "Out of memory!\n"); + exit(1); + } + snprintf(n, strlen(filename) + strlen(suf) + 1, "%s%s", filename, suf); + printf("\n"); + printf("+++ dumping %s... ", n); + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(n); + if (fh < 0) { + fprintf(stderr, + "ERROR: couldn't open(%s): %s\n", n, strerror(errno)); + exit(1); + } + + ret = write(fh, &dump[offset >> 2], length); + if (ret != length) { + fprintf(stderr, "FAILED.\n"); + exit(1); + } + + printf("done.\n"); + close(fh); +} + +void dump_files(const char *n, const uint32_t *fm, struct flash_region *freg) +{ + printf("=== dumping section files ===\n"); + if (freg->reg0_limit) + dump_file(n, ".descr.bin", freg->reg0_base, freg->reg0_limit, fm); + if (freg->reg1_limit) + dump_file(n, ".BIOS.bin", freg->reg1_base, freg->reg1_limit, fm); + if (freg->reg2_limit) + dump_file(n, ".ME.bin", freg->reg2_base, freg->reg2_limit, fm); + if (freg->reg3_limit) { + uint8_t *pMAC = (uint8_t *) &fm[freg->reg3_base >> 2]; + dump_file(n, ".GbE.bin", freg->reg2_base, freg->reg2_limit, fm); + printf("the MAC-address might be: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", + pMAC[0], + pMAC[1], + pMAC[2], + pMAC[3], + pMAC[4], + pMAC[5] + ); + } +} + +static void usage(char *argv[], char *error) +{ + if (error != NULL) { + fprintf(stderr, "%s\n", error); + } + printf("usage: '%s -f <image file name> [-c <chipset name>] [-d]'\n\n" +"where <image file name> points to an image of the contents of the SPI flash.\n" +"In case that image is really in descriptor mode %s\n" +"will pretty print some of the contained information.\n" +"To also print the data stored in the descriptor strap you have to indicate\n" +"the chipset series with the '-c' parameter and one of the possible arguments:\n" +"\t- \"ich8\",\n" +"\t- \"ich9\",\n" +"\t- \"ich10\",\n" +"\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" +"\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" +"\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" +"If '-d' is specified some sections such as the BIOS image as seen by the CPU or\n" +"the GbE blob that is required to initialize the GbE are also dumped to files.\n", + argv[0], argv[0]); + exit(1); +} + +int main(int argc, char *argv[]) +{ + int f; /* file descriptor to flash file */ + unsigned int fs; /* file size */ + uint32_t *fm; /* mmap'd file */ + + int opt; + int dump = 0; + const char *fn = NULL; + const char *csn = NULL; + enum chipset cs = CHIPSET_UNKNOWN; + struct flash_descriptors desc = {{ 0 }}; + + while ((opt = getopt(argc, argv, "df:c:")) != -1) { + switch (opt) { + case 'd': + dump = 1; + break; + case 'f': + fn = optarg; + break; + case 'c': + csn = optarg; + break; + default: /* '?' */ + usage(argv, NULL); + } + } + if (fn == NULL) + usage(argv, + "Need a file name of a descriptor image to read from."); + + f = open(fn, O_RDONLY); + if (f < 0) + usage(argv, "No such file"); + fs = lseek(f, 0, SEEK_END); + if (fs < 0) + usage(argv, "Seeking to the end of the file failed"); + + fm = mmap(NULL, fs, PROT_READ, MAP_PRIVATE, f, 0); + if (fm == (void *) -1) { + /* fallback for stupid OSes like cygwin */ + int ret; + fm = malloc(fs); + if (!fm) + usage(argv, "Could not allocate memory"); + lseek(f, 0, SEEK_SET); + ret = read(f, fm, fs); + if (ret != fs) + usage(argv, "Seeking to the end of the file failed"); + } + printf("flash image has a size of %d [0x%x] bytes.\n", fs, fs); + close(f); + + if (csn != NULL) { + if (strcmp(csn, "ich8") == 0) + cs = CHIPSET_ICH8; + else if (strcmp(csn, "ich9") == 0) + cs = CHIPSET_ICH9; + else if (strcmp(csn, "ich10") == 0) + cs = CHIPSET_ICH10; + else if ((strcmp(csn, "5") == 0) || + (strcmp(csn, "ibex") == 0)) + cs = CHIPSET_SERIES_5_IBEX_PEAK; + else if ((strcmp(csn, "6") == 0) || + (strcmp(csn, "cougar") == 0)) + cs = CHIPSET_SERIES_6_COUGAR_POINT; + else if ((strcmp(csn, "7") == 0) || + (strcmp(csn, "panther") == 0)) + cs = CHIPSET_SERIES_7_PANTHER_POINT; + } + + if(read_ich_descriptors_from_dump(fm, cs, &desc)){ + printf("not in descriptor mode\n"); + exit(1); + } + + prettyprint_ich_descriptors(cs, &desc); + + if (dump == 1) + dump_files(fn, fm, &desc.region); + + return 0; +} + -- 1.7.1

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[PATCH 2/4] add ICH/PCH flash descriptor decoding via FDOC/FDOD
by Stefan Tauner 15 Jul '11

15 Jul '11

based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty printing of those ICH/PCH flash descriptors that are cached/mapped by the chipset (and which are therefore reachable via FDOC/FDOD registers). this includes the following: - content descriptor: describes the image and some generic properties (number of regions, offset of regions, PCH/ICH and MCH/PROC strap offsets and lengths) - component descriptor: identify the different SPI Flash Components and their capabilities. - region descriptor similarly to a partition table this describes the different regions - master descriptor defines access rights of the individual regions this is only a part of the data included in the descriptor. other information can be retreived from a complete binary dump of the descriptor image only. this patch also adds macros and pretty printing for "Vendor Specific Component Capabilities" registers: there are two of them: lower and upper. they describe the properties of the address space divided by FPBA (which allows to use multiple flash chips or partitions with different properties). the properties of flash chips supported by the ME are stored in the same format in a descriptor table. a later patch will uses them outside of ichspi.c which is also the reason why the prettyprinting function and the register bit macros are not defined in ichspi.c but ich_descriptors.h. TODO: - is endianess important? and other questions related to the struct/union pattern used. - file naming and partitioning was not discussed. we may want a ichspi.h. and/or rename ichspi.c to ich_spi.c or similar... - checking derived offsets for OOB errors Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 3 +- ich_descriptors.c | 250 +++++++++++++++++++++++++++++++++++++++++++++++++++ ich_descriptors.h | 258 +++++++++++++++++++++++++++++++++++++++++++++++++++++ ichspi.c | 31 ++++++- 4 files changed, 539 insertions(+), 3 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h diff --git a/Makefile b/Makefile index a35df06..7f73452 100644 --- a/Makefile +++ b/Makefile @@ -308,7 +308,8 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o ifeq ($(ARCH),"x86") -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += ichspi.o ich_descriptors.o else endif NEED_PCI := yes diff --git a/ich_descriptors.c b/ich_descriptors.c new file mode 100644 index 0000000..43b2c52 --- /dev/null +++ b/ich_descriptors.c @@ -0,0 +1,250 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) + +#include "ich_descriptors.h" +#include "flash.h" /* for msg_* */ + +uint32_t getFCBA(const struct flash_content *cont) +{ + return (cont->FLMAP0 << 4) & 0x00000ff0; +} + +uint32_t getFRBA(const struct flash_content *cont) +{ + return (cont->FLMAP0 >> 12) & 0x00000ff0; +} + +uint32_t getFMBA(const struct flash_content *cont) +{ + return (cont->FLMAP1 << 4) & 0x00000ff0; +} + +uint32_t getFMSBA(const struct flash_content *cont) +{ + return (cont->FLMAP2 << 4) & 0x00000ff0; +} + +uint32_t getFLREG_limit(uint32_t flreg) +{ + return (flreg >> 4) & 0x01fff000; +} + +uint32_t getFLREG_base(uint32_t flreg) +{ + return (flreg << 12) & 0x01fff000; +} + +uint32_t getFISBA(const struct flash_content *cont) +{ + return (cont->FLMAP1 >> 12) & 0x00000ff0; +} + +void prettyprint_ich_descriptors(enum chipset cs, const struct flash_descriptors *desc) +{ + prettyprint_ich_descriptor_content(&desc->content); + prettyprint_ich_descriptor_component(desc); + prettyprint_ich_descriptor_region(&desc->region); + prettyprint_ich_descriptor_master(&desc->master); +} + +void prettyprint_ich_descriptor_content(const struct flash_content *cont) +{ + msg_pdbg1("=== Content Section ===\n"); + msg_pdbg1("FLVALSIG 0x%8.8x\n", cont->FLVALSIG); + msg_pdbg1("FLMAP0 0x%8.8x\n", cont->FLMAP0 ); + msg_pdbg1("FLMAP1 0x%8.8x\n", cont->FLMAP1 ); + msg_pdbg1("FLMAP2 0x%8.8x\n", cont->FLMAP2 ); + msg_pdbg1("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("0x%02x NR Number of Regions (%d)\n", cont->NR, cont->NR + 1); + msg_pdbg2("0x%06x FRBA Flash Region Base Address\n", getFRBA(cont)); + msg_pdbg2("0x%02x NC Number of Components (%d)\n", cont->NC, cont->NC + 1); + msg_pdbg2("0x%06x FCBA Flash Component Base Address\n", getFCBA(cont)); + msg_pdbg2("\n"); + msg_pdbg2("0x%02x ISL ICH Strap Length (%d)\n", cont->ISL, cont->ISL); + msg_pdbg2("0x%06x FISBA Flash ICH Strap Base Address\n", getFISBA(cont)); + msg_pdbg2("0x%02x NM Number of Masters (%d)\n", cont->NM, cont->NM + 1); + msg_pdbg2("0x%06x FMBA Flash Master Base Address\n", getFMBA(cont)); + msg_pdbg2("\n"); + msg_pdbg2("0x%02x MSL MCH Strap Length (%d)\n", cont->MSL, cont->MSL); + msg_pdbg2("0x%06x FMSBA Flash MCH Strap Base Address\n", getFMSBA(cont)); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_component(const struct flash_descriptors *desc) +{ + const char * const str_freq[8] = { + "20 MHz", /* 000 */ + "33 MHz", /* 001 */ + "reserved", /* 010 */ + "reserved", /* 011 */ + "50 MHz", /* 100 */ + "reserved", /* 101 */ + "reserved", /* 110 */ + "reserved" /* 111 */ + }; + const char * const str_mem[8] = { + "512kB", + "1 MB", + "2 MB", + "4 MB", + "8 MB", + "16 MB", + "reserved", + "reserved" + }; + + msg_pdbg1("=== Component Section ===\n"); + msg_pdbg1("FLCOMP 0x%8.8x\n", desc->component.FLCOMP); + msg_pdbg1("FLILL 0x%8.8x\n", desc->component.FLILL ); + msg_pdbg1("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("0x%2.2x freq_read_id %s\n", + desc->component.freq_read_id , str_freq[desc->component.freq_read_id ]); + msg_pdbg2("0x%2.2x freq_write %s\n", + desc->component.freq_write , str_freq[desc->component.freq_write ]); + msg_pdbg2("0x%2.2x freq_fastread %s\n", + desc->component.freq_fastread, str_freq[desc->component.freq_fastread]); + msg_pdbg2("0x%2.2x fastread %ssupported\n", + desc->component.fastread, desc->component.fastread ? "" : "not "); + msg_pdbg2("0x%2.2x freq_read %s\n", + desc->component.freq_read, str_freq[desc->component.freq_read ]); + msg_pdbg2("0x%2.2x comp 1 density %s\n", + desc->component.comp1_density, str_mem[desc->component.comp1_density]); + if (desc->content.NC) + msg_pdbg2("0x%2.2x comp 2 density %s\n", + desc->component.comp2_density, str_mem[desc->component.comp2_density]); + else + msg_pdbg2("0x%2.2x comp 2 is not used (FLMAP0.NC=0)\n", + desc->component.comp2_density); + msg_pdbg2("\n"); + msg_pdbg2("0x%2.2x invalid instr 0\n", desc->component.invalid_instr0); + msg_pdbg2("0x%2.2x invalid instr 1\n", desc->component.invalid_instr1); + msg_pdbg2("0x%2.2x invalid instr 2\n", desc->component.invalid_instr2); + msg_pdbg2("0x%2.2x invalid instr 3\n", desc->component.invalid_instr3); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_region(const struct flash_region *reg) +{ + msg_pdbg1("=== Region Section ===\n"); + msg_pdbg1("FLREG0 0x%8.8x\n", reg->FLREG0); + msg_pdbg1("FLREG1 0x%8.8x\n", reg->FLREG1); + msg_pdbg1("FLREG2 0x%8.8x\n", reg->FLREG2); + msg_pdbg1("FLREG3 0x%8.8x\n", reg->FLREG3); + msg_pdbg1("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("0x%8.8x region 0 limit (descr)\n", getFLREG_limit(reg->FLREG0)); + msg_pdbg2("0x%8.8x region 0 base (descr)\n", getFLREG_base(reg->FLREG0)); + msg_pdbg2("0x%8.8x region 1 limit ( BIOS)\n", getFLREG_limit(reg->FLREG1)); + msg_pdbg2("0x%8.8x region 1 base ( BIOS)\n", getFLREG_base(reg->FLREG1)); + msg_pdbg2("0x%8.8x region 2 limit ( ME )\n", getFLREG_limit(reg->FLREG2)); + msg_pdbg2("0x%8.8x region 2 base ( ME )\n", getFLREG_base(reg->FLREG2)); + msg_pdbg2("0x%8.8x region 3 limit ( GbE )\n", getFLREG_limit(reg->FLREG3)); + msg_pdbg2("0x%8.8x region 3 base ( GbE )\n", getFLREG_base(reg->FLREG3)); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_master(const struct flash_master *mstr) +{ + msg_pdbg1("=== Master Section ===\n"); + msg_pdbg1("FLMSTR1 0x%8.8x\n", mstr->FLMSTR1); + msg_pdbg1("FLMSTR2 0x%8.8x\n", mstr->FLMSTR2); + msg_pdbg1("FLMSTR3 0x%8.8x\n", mstr->FLMSTR3); + msg_pdbg1("\n"); + + #define R(r) (r)?'r':' ' + #define W(w) (w)?'w':' ' + msg_pdbg2("--- Details ---\n"); + msg_pdbg2(" Descr. BIOS ME GbE\n"); + msg_pdbg2("BIOS %c%c %c%c %c%c %c%c\n", + R(mstr->BIOS_descr_read), W(mstr->BIOS_descr_write), + R(mstr->BIOS_BIOS_read), W(mstr->BIOS_BIOS_write), + R(mstr->BIOS_ME_read), W(mstr->BIOS_ME_write), + R(mstr->BIOS_GbE_read), W(mstr->BIOS_GbE_write)); + msg_pdbg2("ME %c%c %c%c %c%c %c%c\n", + R(mstr->ME_descr_read), W(mstr->ME_descr_write), + R(mstr->ME_BIOS_read), W(mstr->ME_BIOS_write), + R(mstr->ME_ME_read), W(mstr->ME_ME_write), + R(mstr->ME_GbE_read), W(mstr->ME_GbE_write)); + msg_pdbg2("GbE %c%c %c%c %c%c %c%c\n", + R(mstr->GbE_descr_read), W(mstr->GbE_descr_write), + R(mstr->GbE_BIOS_read), W(mstr->GbE_BIOS_write), + R(mstr->GbE_ME_read), W(mstr->GbE_ME_write), + R(mstr->GbE_GbE_read), W(mstr->GbE_GbE_write)); + msg_pdbg2("\n"); +} + +void prettyprint_ich9_reg_vscc(uint32_t reg_val) +{ + pprint_reg_hex(VSCC, BES, reg_val, ", "); + pprint_reg(VSCC, WG, reg_val, ", "); + pprint_reg(VSCC, WSR, reg_val, ", "); + pprint_reg(VSCC, WEWS, reg_val, ", "); + pprint_reg_hex(VSCC, EO, reg_val, ", "); + pprint_reg(VSCC, VCL, reg_val, "\n"); +} + +static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) +{ + uint32_t control = 0; + control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; + control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; + *(volatile uint32_t *) (spibar + ICH9_REG_FDOC) = control; + return *(volatile uint32_t *)(spibar + ICH9_REG_FDOD); +} + +void read_ich_descriptors_via_fdo(void *spibar, struct flash_descriptors *desc) +{ + msg_pdbg1("Reading flash descriptors " + "mapped by the chipset via FDOC/FDOD..."); + /* content section */ + desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar); + desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar); + desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar); + desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar); + + /* component section */ + desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar); + desc->component.FLILL = read_descriptor_reg(1, 1, spibar); + desc->component.FLPB = read_descriptor_reg(1, 2, spibar); + + /* region section */ + desc->region.FLREG0 = read_descriptor_reg(2, 0, spibar); + desc->region.FLREG1 = read_descriptor_reg(2, 1, spibar); + desc->region.FLREG2 = read_descriptor_reg(2, 2, spibar); + desc->region.FLREG3 = read_descriptor_reg(2, 3, spibar); + + /* master section */ + desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar); + desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar); + desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar); + + /* accessing strap section and upper map is impossible via FDOC/D(?) */ + msg_pdbg1(" done\n"); +} + +#endif // defined(__i386__) || defined(__x86_64__) diff --git a/ich_descriptors.h b/ich_descriptors.h new file mode 100644 index 0000000..9954149 --- /dev/null +++ b/ich_descriptors.h @@ -0,0 +1,258 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) +#ifndef __ICH_DESCRIPTORS_H__ +#define __ICH_DESCRIPTORS_H__ 1 + +#include <stdint.h> + +/* most of the following should probably be in a new file named ichspi.h */ +#define msg_pdbg1 msg_pdbg +#define msg_pdbg2 msg_pspew + +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ + /* 0-1: reserved */ +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) + /* 15-31: reserved */ + +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ + +/* Field locations and semantics for LVSCC, UVSCC and related words in the flash + * descriptor are equal therefore they all share the same macros below. */ +#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */ +#define VSCC_BES (0x3 << VSCC_BES_OFF) +#define VSCC_WG_OFF 2 /* 2: Write Granularity */ +#define VSCC_WG (0x1 << VSCC_WG_OFF) +#define VSCC_WSR_OFF 3 /* 3: Write Status Required */ +#define VSCC_WSR (0x1 << VSCC_WSR_OFF) +#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */ +#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF) + /* 5-7: reserved */ +#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */ +#define VSCC_EO (0xff << VSCC_EO_OFF) + /* 16-22: reserved */ +#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */ +#define VSCC_VCL (0x1 << VSCC_VCL_OFF) + /* 24-31: reserved */ + +#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +#define pprint_reg_hex(reg, bit, val, sep) msg_pdbg("%s=0x%x" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +void prettyprint_ich9_reg_vscc(uint32_t reg_val); + +enum chipset { + CHIPSET_UNKNOWN, + CHIPSET_ICH7 = 7, + CHIPSET_ICH8, + CHIPSET_ICH9, + CHIPSET_ICH10, + CHIPSET_SERIES_5_IBEX_PEAK, + CHIPSET_SERIES_6_COUGAR_POINT, + CHIPSET_SERIES_7_PANTHER_POINT +}; + +struct flash_content { + uint32_t FLVALSIG; /* 0x00 */ + union { /* 0x04 */ + uint32_t FLMAP0; + struct { + uint32_t FCBA :8; + uint32_t NC :2; + uint32_t :6; + uint32_t FRBA :8; + uint32_t NR :3; + uint32_t :5; + }; + }; + union { /* 0x08 */ + uint32_t FLMAP1; + struct { + uint32_t FMBA :8; + uint32_t NM :3; + uint32_t :5; + union { + uint32_t FISBA :8; + uint32_t FPSBA :8; + }; + uint32_t ISL :8; + }; + }; + union { /* 0x0c */ + uint32_t FLMAP2; + struct { + uint32_t FMSBA :8; + uint32_t MSL :8; + uint32_t :16; + }; + }; +}; + +struct flash_component { + union { /* 0x00 */ + uint32_t FLCOMP; + struct { + uint32_t comp1_density :3; + uint32_t comp2_density :3; + uint32_t :11; + uint32_t freq_read :3; + uint32_t fastread :1; + uint32_t freq_fastread :3; + uint32_t freq_write :3; + uint32_t freq_read_id :3; + uint32_t :2; + }; + }; + union { /* 0x04 */ + uint32_t FLILL; + struct { + uint32_t invalid_instr0; + uint32_t invalid_instr1; + uint32_t invalid_instr2; + uint32_t invalid_instr3; + }; + }; + union { /* 0x08 */ + uint32_t FLPB; + struct { + uint32_t FPBA :13; + uint32_t :19; + }; + }; +}; + +struct flash_region { + + union { + uint32_t FLREG0; /* Flash Descriptor */ + struct { + uint32_t reg0_base :13; + uint32_t :3; + uint32_t reg0_limit :13; + uint32_t :3; + }; + }; + union { + uint32_t FLREG1; /* BIOS */ + struct { + uint32_t reg1_base :13; + uint32_t :3; + uint32_t reg1_limit :13; + uint32_t :3; + }; + }; + union { + uint32_t FLREG2; /* ME */ + struct { + uint32_t reg2_base :13; + uint32_t :3; + uint32_t reg2_limit :13; + uint32_t :3; + }; + }; + union { + uint32_t FLREG3; /* GbE */ + struct { + uint32_t reg3_base :13; + uint32_t :3; + uint32_t reg3_limit :13; + uint32_t :3; + }; + }; +}; + +struct flash_master { + union { + uint32_t FLMSTR1; + struct { + uint32_t BIOS_req_ID :16; + uint32_t BIOS_descr_read :1; + uint32_t BIOS_BIOS_read :1; + uint32_t BIOS_ME_read :1; + uint32_t BIOS_GbE_read :1; + uint32_t BIOS_plat_read :1; + uint32_t :3; + uint32_t BIOS_descr_write :1; + uint32_t BIOS_BIOS_write :1; + uint32_t BIOS_ME_write :1; + uint32_t BIOS_GbE_write :1; + uint32_t BIOS_plat_write :1; + uint32_t :3; + }; + }; + union { + uint32_t FLMSTR2; + struct { + uint32_t ME_req_ID :16; + uint32_t ME_descr_read :1; + uint32_t ME_BIOS_read :1; + uint32_t ME_ME_read :1; + uint32_t ME_GbE_read :1; + uint32_t ME_plat_read :1; + uint32_t :3; + uint32_t ME_descr_write :1; + uint32_t ME_BIOS_write :1; + uint32_t ME_ME_write :1; + uint32_t ME_GbE_write :1; + uint32_t ME_plat_write :1; + uint32_t :3; + }; + }; + union { + uint32_t FLMSTR3; + struct { + uint32_t GbE_req_ID :16; + uint32_t GbE_descr_read :1; + uint32_t GbE_BIOS_read :1; + uint32_t GbE_ME_read :1; + uint32_t GbE_GbE_read :1; + uint32_t GbE_plat_read :1; + uint32_t :3; + uint32_t GbE_descr_write :1; + uint32_t GbE_BIOS_write :1; + uint32_t GbE_ME_write :1; + uint32_t GbE_GbE_write :1; + uint32_t GbE_plat_write :1; + uint32_t :3; + }; + }; +}; + +struct flash_descriptors { + struct flash_content content; + struct flash_component component; + struct flash_region region; + struct flash_master master; +}; + +void prettyprint_ich_descriptors(enum chipset, const struct flash_descriptors *desc); + +void prettyprint_ich_descriptor_content(const struct flash_content *content); +void prettyprint_ich_descriptor_component(const struct flash_descriptors *desc); +void prettyprint_ich_descriptor_region(const struct flash_region *region); +void prettyprint_ich_descriptor_master(const struct flash_master *master); + +void read_ich_descriptors_via_fdo(void *spibar, struct flash_descriptors *desc); + +#endif // __ICH_DESCRIPTORS_H__ +#endif // defined(__i386__) || defined(__x86_64__) diff --git a/ichspi.c b/ichspi.c index 2480fa5..edca654 100644 --- a/ichspi.c +++ b/ichspi.c @@ -30,6 +30,7 @@ #include "chipdrivers.h" #include "programmer.h" #include "spi.h" +#include "ich_descriptors.h" /* ICH9 controller register definition */ #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ @@ -120,6 +121,14 @@ #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ +#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */ +#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */ +/* The individual fields of the VSCC registers are defined in the file + * ich_descriptors.h. The reason is that the same fields are also used in the + * flash descriptors to define the properties of the different flash chips + * supported by the BIOS image. These descriptors are also the source for the + * registers above. */ + #define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ #define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ #define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) @@ -302,8 +311,6 @@ static void prettyprint_opcodes(OPCODES *ops) } } -#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) - static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) { msg_pdbg("HSFS: "); @@ -1191,6 +1198,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + int ichspi_desc = 0; switch (ich_generation) { case 7: @@ -1262,6 +1270,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + if (tmp2 & HSFS_FDV) + ichspi_desc = 1; tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); @@ -1312,9 +1322,26 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0xA0: 0x%08x (BBAR)\n", ichspi_bbar); + + tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); + msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); + msg_pdbg("LVSCC: "); + prettyprint_ich9_reg_vscc(tmp); + + tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); + msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); + msg_pdbg("UVSCC: "); + prettyprint_ich9_reg_vscc(tmp); + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + msg_pdbg("\n"); + if (ichspi_desc) { + struct flash_descriptors desc = {{ 0 }}; + read_ich_descriptors_via_fdo(ich_spibar, &desc); + prettyprint_ich_descriptors(CHIPSET_UNKNOWN, &desc); + } ich_init_opcodes(); break; default: -- 1.7.1

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[PATCH 1/4] ichspi.c: refactor filling and reading the fdata/spid registers
by Stefan Tauner 15 Jul '11

15 Jul '11

- add ich_fill_data to fill the chipset registers from an array - add ich_read_data to copy the data from the chipset register into an array - replace the existing code with calls to those functions - minor cosmetic changes Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> --- ichspi.c | 135 ++++++++++++++++++++++++++------------------------------------ 1 files changed, 57 insertions(+), 78 deletions(-) diff --git a/ichspi.c b/ichspi.c index 99c4613..2480fa5 100644 --- a/ichspi.c +++ b/ichspi.c @@ -6,6 +6,7 @@ * Copyright (C) 2008 Dominik Geyer <dominik.geyer(a)kontron.com> * Copyright (C) 2008 coresystems GmbH <info(a)coresystems.de> * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger + * Copyright (C) 2011 Stefan Tauner * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,18 +23,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* - * This module is designed for supporting the devices - * ST M25P40 - * ST M25P80 - * ST M25P16 - * ST M25P32 already tested - * ST M25P64 - * AT 25DF321 already tested - * ... and many more SPI flash devices - * - */ - #if defined(__i386__) || defined(__x86_64__) #include <string.h> @@ -293,7 +282,7 @@ static OPCODE POSSIBLE_OPCODES[] = { static OPCODES O_EXISTING = {}; /* pretty printing functions */ -static void pretty_print_opcodes(OPCODES *ops) +static void prettyprint_opcodes(OPCODES *ops) { if(ops == NULL) return; @@ -592,6 +581,51 @@ static void ich_set_bbar(uint32_t min_addr) msg_perr("Setting BBAR failed!\n"); } +/* Read len bytes from the fdata/spid register into the data array. + * + * Note that using len > spi_programmer->max_data_read will return garbage or + * may even crash. + */ + static void ich_read_data(uint8_t *data, int len, int reg0_off) + { + int i; + uint32_t temp32 = 0; + + for (i = 0; i < len; i++) { + if ((i % 4) == 0) + temp32 = REGREAD32(reg0_off + i); + + data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; + } +} + +/* Fill len bytes from the data array into the fdata/spid registers. + * + * Note that using len > spi_programmer->max_data_write will trash the registers + * following the data registers. + */ +static void ich_fill_data(const uint8_t *data, int len, int reg0_off) +{ + uint32_t temp32 = 0; + int i; + + if (len <= 0) + return; + + for (i = 0; i < len; i++) { + if ((i % 4) == 0) + temp32 = 0; + + temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); + + if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ + REGWRITE32(reg0_off + (i - (i % 4)), temp32); + } + i--; + if ((i % 4) != 3) /* Write remaining data to regs. */ + REGWRITE32(reg0_off + (i - (i % 4)), temp32); +} + /* This function generates OPCODES from or programs OPCODES to ICH according to * the chipset's SPI configuration lock. * @@ -627,7 +661,7 @@ static int ich_init_opcodes(void) } else { curopcodes = curopcodes_done; msg_pdbg("done\n"); - pretty_print_opcodes(curopcodes); + prettyprint_opcodes(curopcodes); msg_pdbg("\n"); return 0; } @@ -638,9 +672,8 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, { int write_cmd = 0; int timeout; - uint32_t temp32 = 0; + uint32_t temp32; uint16_t temp16; - uint32_t a; uint64_t opmenu; int opcode_index; @@ -664,26 +697,8 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32); /* Program data into SPID0 to N */ - if (write_cmd && (datalength != 0)) { - temp32 = 0; - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = 0; - } - - temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); - - if ((a % 4) == 3) { - REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)), - temp32); - } - } - if (((a - 1) % 4) != 3) { - REGWRITE32(ICH7_REG_SPID0 + - ((a - 1) - ((a - 1) % 4)), temp32); - } - - } + if (write_cmd && (datalength != 0)) + ich_fill_data(data, datalength, ICH7_REG_SPID0); /* Assemble SPIS */ temp16 = REGREAD16(ICH7_REG_SPIS); @@ -764,17 +779,8 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, return 1; } - if ((!write_cmd) && (datalength != 0)) { - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = REGREAD32(ICH7_REG_SPID0 + (a)); - } - - data[a] = - (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) - >> ((a % 4) * 8); - } - } + if ((!write_cmd) && (datalength != 0)) + ich_read_data(data, datalength, ICH7_REG_SPID0); return 0; } @@ -785,7 +791,6 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, int write_cmd = 0; int timeout; uint32_t temp32; - uint32_t a; uint64_t opmenu; int opcode_index; @@ -810,25 +815,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32); /* Program data into FDATA0 to N */ - if (write_cmd && (datalength != 0)) { - temp32 = 0; - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = 0; - } - - temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); - - if ((a % 4) == 3) { - REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)), - temp32); - } - } - if (((a - 1) % 4) != 3) { - REGWRITE32(ICH9_REG_FDATA0 + - ((a - 1) - ((a - 1) % 4)), temp32); - } - } + if (write_cmd && (datalength != 0)) + ich_fill_data(data, datalength, ICH9_REG_FDATA0); /* Assemble SSFS + SSFC */ temp32 = REGREAD32(ICH9_REG_SSFS); @@ -916,17 +904,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, return 1; } - if ((!write_cmd) && (datalength != 0)) { - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = REGREAD32(ICH9_REG_FDATA0 + (a)); - } - - data[a] = - (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) - >> ((a % 4) * 8); - } - } + if ((!write_cmd) && (datalength != 0)) + ich_read_data(data, datalength, ICH9_REG_FDATA0); return 0; } -- 1.7.1

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[PATCH 0/4] ichspi 7.0
by Stefan Tauner 15 Jul '11

15 Jul '11

the first one is already acked, but not committed yet, because i want it to be tested first (again :). i have worked a lot on the descriptor patch: - i have split the main part which integrates into flashrom directly (2/4) from the stand-alone utility (3/4). - the global variables are all gone. references to the memory holding the descriptors have to be passed as arguments instead. this is a problem for the hwseq patch, because ich_hwseq_probe no longer has access to the descriptors and can't know number of flashes or their densities without this. a workaround has been added while we are working on the generic opaque programmer framwork. - the structs for the ibex peak straps are now complete, but the big chunk of work - the decoding into human readable output - is not even started. - lots of cleanup done, lots of cleanup to come :) Stefan Tauner (4): ichspi.c: refactor filling and reading the fdata/spid registers add ICH/PCH flash descriptor decoding via FDOC/FDOD add ich_descriptor_tool to decode all flash descriptors stored in a flash dump file ichspi.c: add support for Intel Hardware Sequencing Makefile | 3 +- chipdrivers.h | 6 + flashchips.c | 23 +- flashchips.h | 2 + ich_descriptors.c | 471 ++++++++++++++++++++ ich_descriptors.h | 459 ++++++++++++++++++++ ichspi.c | 495 ++++++++++++++++++---- programmer.h | 1 + util/ich_descriptors_tool/Makefile | 42 ++ util/ich_descriptors_tool/TODO | 5 + util/ich_descriptors_tool/ich_descriptors_tool.c | 197 +++++++++ 11 files changed, 1612 insertions(+), 92 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c

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[PATCH] add known board MSI-7369 (K9N Neo V2) ... unsupported
by Melchior FRANZ 14 Jul '11

14 Jul '11

In case this board isn't missing for a particular reason, you may want to add it as unsupported. The problem is its usage of NVIDIA MCP65. I reported the output a while ago, but here again the short form: $ sudo ./flashrom flashrom v0.9.3-r1370 on Linux 2.6.39.3 (x86_64), built with libpci 3.1.7, \ GCC 4.5.1 20101208 [gcc-4_5-branch revision 167585], little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP65", enabling flash write... \ This chipset is not really supported yet. Guesswork... SPI on this chipset is WIP. Write is unsupported! Mapping NVIDIA MCP6x SPI at 0xfec80000, unaligned size 0x544. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Found chip "Winbond W25X80" (1024 kB, SPI) at physical address 0xfff00000. No operations were specified. m.

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MS-7369 (MSI K9N Neo V2): flashrom -V
by Melchior FRANZ 14 Jul '11

14 Jul '11

flashrom v0.9.3-r1370 on Linux 2.6.39.3 (x86_64) works: reading verifying untested: erasing writing m.

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Re: [flashrom] [PATCH 1/3] ichspi.c: refactor filling and reading the fdata/spid registers
by Carl-Daniel Hailfinger 13 Jul '11

13 Jul '11

Am 01.07.2011 05:38 schrieb Stefan Tauner: > - add ich_fill_data to fill the chipset registers from an array > - add ich_read_data to copy the data from the chipset register into an array > - replace the existing code with calls to those functions > > NB: this changes the semantic of the *run_opcode functions a bit: > previously they could trash the chipset registers following the data registers because there > was no (explicit) length check (it was and is checked by the dispatching run_opcode method). > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > I know you're just moving code, but this is a chance to clean up the code and improve readability. > diff --git a/ichspi.c b/ichspi.c > index 19e52d2..905ed70 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -592,6 +592,57 @@ static void ich_set_bbar(uint32_t min_addr) > msg_perr("Setting BBAR failed!\n"); > } > > +/* Reads up to len byte from the fdata/spid register into the data array. > + * The amount actually read is limited by the maximum read size of the > + * chipset. */ > Can you put the terminating */ on its own line like the multiline comments in other files? > + static void ich_read_data(uint8_t *data, int len, int reg0_off) > + { > + int a; > int i would be a nicer name... although you just moved that code, so it's not your fault. > + uint32_t temp32 = 0; > + > + if (len > spi_programmer->max_data_read) > + len = spi_programmer->max_data_read; > Can this really happen? If yes, does it depend on bugs elsewhere in the code? This needs at least a msg_perr("bug in blabla, please report to flashrom@"), we might even want to have the function return int to handle errors. > + > + for (a = 0; a < len; a++) { > + if ((a % 4) == 0) > + temp32 = REGREAD32(reg0_off + (a)); > Are the extra parentheses around a really needed? > + > + data[a] = (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) > + >> ((a % 4) * 8); > I think David had a suggestion on how to simplify this formula a bit. > + } > +} > + > +/* Fills up to len bytes from the data array into the fdata/spid registers. > + * The amount actually written is limited by the maximum write size of the > + * chipset and is returned by the function. */ > The result is discarded anyway, and we probably shouldn't call this function with a too big len in the first place, so a return type of void may be the best choice. That said, if you decide to care about the result of this function, please make sure that ich_fill_data and ich_read_data have identical return types and check that the comments above the functions match the prototypes. > +static uint8_t ich_fill_data(const uint8_t *data, int len, int reg0_off) > +{ > + uint32_t temp32 = 0; > + int a; > See ich_read_data. > + > + if (len > spi_programmer->max_data_write) > + len = spi_programmer->max_data_write; > See ich_read_data. > + > + if (len <= 0) > + return 0; > Superfluous check? len<0 should not happen, and len==0 won't execute the for loop below. > + > + for (a = 0; a < len; a++) { > + if ((a % 4) == 0) { > + temp32 = 0; > + } > Please kill superfluous {}. > + > + temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); > + > + if ((a % 4) == 3) { > + REGWRITE32(reg0_off + (a - (a % 4)), temp32); > + } > Please kill superfluous {}. > + } > + if (((a - 1) % 4) != 3) { > Yeargh! AFAIK modulo for negative integers is implementation-defined. So your len<=0 check a few lines above may have been a good idea. That said, it is a good idea to add a comment so others won't fall into that trap. And all this (a-1) stuff in the line above and below would be a lot more readable if you inserted a--; before the if. > + REGWRITE32(reg0_off + ((a - 1) - ((a - 1) % 4)), temp32); > + } > Please kill superfluous {}. > + return len; > +} > + > /* This function generates OPCODES from or programs OPCODES to ICH according to > * the chipset's SPI configuration lock. > * > @@ -638,9 +689,8 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, > { > int write_cmd = 0; > int timeout; > - uint32_t temp32 = 0; > + uint32_t temp32; > uint16_t temp16; > - uint32_t a; > uint64_t opmenu; > int opcode_index; > > @@ -664,26 +714,8 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, > REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32); > > /* Program data into SPID0 to N */ > - if (write_cmd && (datalength != 0)) { > - temp32 = 0; > - for (a = 0; a < datalength; a++) { > - if ((a % 4) == 0) { > - temp32 = 0; > - } > - > - temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); > - > - if ((a % 4) == 3) { > - REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)), > - temp32); > - } > - } > - if (((a - 1) % 4) != 3) { > - REGWRITE32(ICH7_REG_SPID0 + > - ((a - 1) - ((a - 1) % 4)), temp32); > - } > - > - } > + if (write_cmd && (datalength != 0)) > + ich_fill_data(data, datalength, ICH7_REG_SPID0); > Nice! Killed superfluous {}. > > /* Assemble SPIS */ > temp16 = REGREAD16(ICH7_REG_SPIS); > @@ -765,15 +797,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, > } > > if ((!write_cmd) && (datalength != 0)) { > - for (a = 0; a < datalength; a++) { > - if ((a % 4) == 0) { > - temp32 = REGREAD32(ICH7_REG_SPID0 + (a)); > - } > - > - data[a] = > - (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) > - >> ((a % 4) * 8); > - } > + ich_read_data(data, datalength, ICH7_REG_SPID0); > Can you kill {} here as well? > } > > return 0; > @@ -785,7 +809,6 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, > int write_cmd = 0; > int timeout; > uint32_t temp32; > - uint32_t a; > uint64_t opmenu; > int opcode_index; > > @@ -810,25 +833,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, > REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32); > > /* Program data into FDATA0 to N */ > - if (write_cmd && (datalength != 0)) { > - temp32 = 0; > - for (a = 0; a < datalength; a++) { > - if ((a % 4) == 0) { > - temp32 = 0; > - } > - > - temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); > - > - if ((a % 4) == 3) { > - REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)), > - temp32); > - } > - } > - if (((a - 1) % 4) != 3) { > - REGWRITE32(ICH9_REG_FDATA0 + > - ((a - 1) - ((a - 1) % 4)), temp32); > - } > - } > + if (write_cmd && (datalength != 0)) > + ich_fill_data(data, datalength, ICH9_REG_FDATA0); > > /* Assemble SSFS + SSFC */ > temp32 = REGREAD32(ICH9_REG_SSFS); > @@ -917,15 +923,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, > } > > if ((!write_cmd) && (datalength != 0)) { > - for (a = 0; a < datalength; a++) { > - if ((a % 4) == 0) { > - temp32 = REGREAD32(ICH9_REG_FDATA0 + (a)); > - } > - > - data[a] = > - (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) > - >> ((a % 4) * 8); > - } > + ich_read_data(data, datalength, ICH9_REG_FDATA0); > Kill superfluous {} > } > > return 0; > Regards, Carl-Daniel -- http://www.hailfinger.org/

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Desktop Summit 2011 in Berlin
by Paul Menzel 13 Jul '11

13 Jul '11

Dear coreboot folks, the Desktop Summit 2011 [1] will take place in Berlin from August 6th– 12th. The first three days will consist of keynotes and talks [2]. There seem to be some open slots on Monday and maybe on the weekend evening too. I am CCing Lennart Poettering as one of the organizers(?). Knowing that some coreboot or flashrom developers live in Berlin it would be awesome if one of them could present coreboot or flashrom. For coreboot a short introduction and demonstration of for example the ThinkPad X60/T60 and ASRock E350M1 would be a good idea. I know this is on short notice and the Desktop Summit is normally associated with GNOME and KDE and therefore coreboot seems out of place. But in my opinion – if accepted – coreboot could reach *developers* who might be interested in the possibilities of coreboot and do not know about this. flashrom could be interesting for the desktop developers to know that there are tools to upgrade the BIOS from the desktop and maybe someone is motivated to code up a GUI (graphical user interface) for flashrom. That is just a thought and I do not know how easy that would be and if flashrom provides these kinds of means to be hooked up to a GUI. I would do it, but I am only able to be there on Saturday and not being that knowledgeable with the internals I would rather not do it. Thanks, Paul [1] https://desktopsummit.org/ [2] https://desktopsummit.org/program

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[commit] r1372 - trunk
by repository service 13 Jul '11

13 Jul '11

Author: stefanct Date: Wed Jul 13 22:48:54 2011 New Revision: 1372 URL: http://flashrom.org/trac/flashrom/changeset/1372 Log: enable writing on mcp6x_7x this was deliberately disabled until now, but seems to work well enough. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Wed Jul 13 13:22:03 2011 (r1371) +++ trunk/chipset_enable.c Wed Jul 13 22:48:54 2011 (r1372) @@ -912,8 +912,9 @@ */ buses_supported = CHIP_BUSTYPE_NONE; msg_pdbg("Flash bus type is SPI\n"); - msg_perr("SPI on this chipset is WIP. Write is unsupported!\n"); - programmer_may_write = 0; + msg_pinfo("SPI on this chipset is WIP. Please report any " + "success or failure by mailing us the verbose " + "output to flashrom(a)flashrom.org, thanks!\n"); break; default: /* Should not happen. */

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[commit] r1371 - trunk
by repository service 13 Jul '11

13 Jul '11

Author: uwe Date: Wed Jul 13 13:22:03 2011 New Revision: 1371 URL: http://flashrom.org/trac/flashrom/changeset/1371 Log: Change "class" parameter name to "devclass" to avoid C++ issues. In C++ "class" is a reserved keyword, and as we'll want to use libflashrom from C++ code at some point, let's make sure it doesn't cause issues. Other places in the code already used "devclass" anyway, so it also increases consistency and readability a bit. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/internal.c trunk/programmer.h Modified: trunk/internal.c ============================================================================== --- trunk/internal.c Wed Jul 13 00:35:21 2011 (r1370) +++ trunk/internal.c Wed Jul 13 13:22:03 2011 (r1371) @@ -35,7 +35,7 @@ return NULL; } -struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class) +struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t devclass) { struct pci_dev *temp; struct pci_filter filter; @@ -48,7 +48,7 @@ if (pci_filter_match(&filter, temp)) { /* Read PCI class */ tmp2 = pci_read_word(temp, 0x0a); - if (tmp2 == class) + if (tmp2 == devclass) return temp; } Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Wed Jul 13 00:35:21 2011 (r1370) +++ trunk/programmer.h Wed Jul 13 13:22:03 2011 (r1371) @@ -289,7 +289,7 @@ #endif #if NEED_PCI == 1 struct pci_dev *pci_dev_find_filter(struct pci_filter filter); -struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class); +struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t devclass); struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device, uint16_t card_vendor, uint16_t card_device);

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Re: [flashrom] [PATCH] fix unchecked malloc calls
by Uwe Hermann 13 Jul '11

13 Jul '11

On Fri, Jul 01, 2011 at 06:05:07AM +0200, Stefan Tauner wrote: > compile tested only. > btw... why dont we wrap malloc to automatically include these checks? > there is probably a patch somewhere that adds totally awesome shutdown code in OOM cases, > but afaics we just print a warning and exit right now... it is just stupid to do the checks in the real > code then. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> It's definately better than what we have now (no error checking at all), so: Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> A few notes for later though: - We should call any shutdown function which may need to be called in the respective places (and any free()s which may be needed). - Later we should not exit(1) upon the error, but rather return an error code instead (e.g. FL_ERR_MALLOC or similar), at least in all public "API" functions which are meant to be in the upcoming libflashrom. - A small xmalloc() wrapper (or use another name) would indeed be nice, too, but once we really return error codes etc. it's not really useful anymore I think. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r1370 - trunk
by repository service 13 Jul '11

13 Jul '11

Author: stefanct Date: Wed Jul 13 00:35:21 2011 New Revision: 1370 URL: http://flashrom.org/trac/flashrom/changeset/1370 Log: fix unchecked malloc calls and casts of malloc return values in the long term the exit calls should be replaced by returns. until then this is the correct way to handle failures. the casts are not needed (in C) and we don't cast malloc return values anywhere else. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flashrom.c trunk/hwaccess.c trunk/pcidev.c trunk/serial.c Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Wed Jul 13 00:01:44 2011 (r1369) +++ trunk/flashrom.c Wed Jul 13 00:35:21 2011 (r1370) @@ -1513,7 +1513,11 @@ unsigned int usable_erasefunctions = count_usable_erasers(flash); msg_cinfo("Erasing and writing flash chip... "); - curcontents = (uint8_t *) malloc(size); + curcontents = malloc(size); + if (!curcontents) { + msg_gerr("Out of memory!\n"); + exit(1); + } /* Copy oldcontents to curcontents to avoid clobbering oldcontents. */ memcpy(curcontents, oldcontents, size); @@ -1880,10 +1884,18 @@ goto out_nofree; } - oldcontents = (uint8_t *) malloc(size); + oldcontents = malloc(size); + if (!oldcontents) { + msg_gerr("Out of memory!\n"); + exit(1); + } /* Assume worst case: All bits are 0. */ memset(oldcontents, 0x00, size); - newcontents = (uint8_t *) malloc(size); + newcontents = malloc(size); + if (!newcontents) { + msg_gerr("Out of memory!\n"); + exit(1); + } /* Assume best case: All bits should be 1. */ memset(newcontents, 0xff, size); /* Side effect of the assumptions above: Default write action is erase Modified: trunk/hwaccess.c ============================================================================== --- trunk/hwaccess.c Wed Jul 13 00:01:44 2011 (r1369) +++ trunk/hwaccess.c Wed Jul 13 00:35:21 2011 (r1370) @@ -226,6 +226,10 @@ { \ struct undo_mmio_write_data *undo_mmio_write_data; \ undo_mmio_write_data = malloc(sizeof(struct undo_mmio_write_data)); \ + if (!undo_mmio_write_data) { \ + msg_gerr("Out of memory!\n"); \ + exit(1); \ + } \ undo_mmio_write_data->addr = a; \ undo_mmio_write_data->type = mmio_write_type_##c; \ undo_mmio_write_data->c##data = mmio_read##c(a); \ Modified: trunk/pcidev.c ============================================================================== --- trunk/pcidev.c Wed Jul 13 00:01:44 2011 (r1369) +++ trunk/pcidev.c Wed Jul 13 00:35:21 2011 (r1370) @@ -295,6 +295,10 @@ { \ struct undo_pci_write_data *undo_pci_write_data; \ undo_pci_write_data = malloc(sizeof(struct undo_pci_write_data)); \ + if (!undo_pci_write_data) { \ + msg_gerr("Out of memory!\n"); \ + exit(1); \ + } \ undo_pci_write_data->dev = *a; \ undo_pci_write_data->reg = b; \ undo_pci_write_data->type = pci_write_type_##c; \ Modified: trunk/serial.c ============================================================================== --- trunk/serial.c Wed Jul 13 00:01:44 2011 (r1369) +++ trunk/serial.c Wed Jul 13 00:35:21 2011 (r1370) @@ -110,6 +110,8 @@ (tolower((unsigned char)dev[1]) == 'o') && (tolower((unsigned char)dev[2]) == 'm')) { dev2 = malloc(strlen(dev) + 5); + if (!dev2) + sp_die("Error: Out of memory"); strcpy(dev2, "\\\\.\\"); strcpy(dev2 + 4, dev); }

1 0

MSI K9A2 Platinum OK
by Sylvain BERTRAND 12 Jul '11

12 Jul '11

Hi, Successfully flashed BIOS v1.9 on this motherboard. Cheers, Sylvain BERTRAND

2 2

MSI "K8MM-V" (MS-7142) successful BIOS update
by Benjamin Bellec 12 Jul '11

12 Jul '11

Hello, I successfully flash this motherboard with a "Winbond W39V040A" (512 kB, LPC) chip which is currently tagged as UNTESTED for ERASE and WRITE. Flash from BIOS version 1.0 to 1.A (the last one). http://eu.msi.com/product/mb/K8MM-V.html Here are the logs. Benjamin

2 1

Re: [flashrom] Report scan flashrom v0.9.3-r1299 for Asus M2N-MX SE Plus
by Paul Menzel 12 Jul '11

12 Jul '11

Dear Alexabder, Am Montag, den 11.07.2011, 20:46 +0300 schrieb Senior College Krikoon Hilton Enterprise: > I Alexabder > I very hope and trust you > How many time you need do this? I am sorry I do not understand your question. What do we need to do? > [root@localhost flashrom]# flashrom -V > flashrom v0.9.3-r1299 on Linux 2.6.38.8-32.fc15.i686 (i686), built with > libpci 3.1.7, GCC 4.6.0 20110428 (Red Hat 4.6.0-6), little endian > flashrom is free software, get the source code at http://www.flashrom.org […] If you want to upgrade you BIOS you should try a newer version [1][2] and make sure you can recover from a failed flashing operation if your motherboard is not marked as supported. Thanks, Paul [1] http://flashrom.org/Flashrom [2] http://flashrom.org/Downloads

1 0

Report scan flashrom v0.9.3-r1299
by Senior College Krikoon Hilton Enterprise 11 Jul '11

11 Jul '11

I Alexabder I very hope and trust you How many time you need do this? [root@localhost flashrom]# flashrom -V flashrom v0.9.3-r1299 on Linux 2.6.38.8-32.fc15.i686 (i686), built with libpci 3.1.7, GCC 4.6.0 20110428 (Red Hat 4.6.0-6), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 3 usecs, 1029M loops per second, 10 myus = 10 us, 100 myus = 95 us, 1000 myus = 1033 us, 10000 myus = 9413 us, 12 myus = 12 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "M2N-MX SE Plus" DMI string baseboard-version: "Rev x.xx" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8712 on port 0x2e Found chipset "NVIDIA MCP61", enabling flash write... chipset PCI ID is 10de:03e0, This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Flash bus type is SPI SPI on this chipset is WIP. Write is unsupported! Found SMBus device 10de:03eb at 00:01:1 MCP SPI BAR is at 0xfec80000 Mapping NVIDIA MCP6x SPI at 0xfec80000, unaligned size 0x544. SPI control is 0x0002, req=0, gnt=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Super I/O ID 0x8712 is not on the list of flash capable controllers. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV001BB, 128 KB: skipped. Probing for AMD Am29LV001BT, 128 KB: skipped. Probing for AMD Am29LV002BB, 256 KB: skipped. Probing for AMD Am29LV002BT, 256 KB: skipped. Probing for AMD Am29LV004BB, 512 KB: skipped. Probing for AMD Am29LV004BT, 512 KB: skipped. Probing for AMD Am29LV008BB, 1024 KB: skipped. Probing for AMD Am29LV008BT, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for AMIC A25L05PT, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L05PU, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PT, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PU, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PT, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PU, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L80P, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PT, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PU, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L080, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L016, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25LQ032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DQ161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for Bright BM29F040, 512 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for EMST F25L008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN29F010, 128 KB: skipped. Probing for Eon EN29F002(A)(N)B, 256 KB: skipped. Probing for Eon EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Hyundai HY29F040A, 512 KB: skipped. Probing for Intel 28F001BN/BX-B, 128 KB: skipped. Probing for Intel 28F001BN/BX-T, 128 KB: skipped. Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: skipped. Probing for Intel 28F008S3/S5/SC, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address 0xfff00000. Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635E, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29F040, 512 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for MoselVitelic V29C51000B, 64 KB: skipped. Probing for MoselVitelic V29C51000T, 64 KB: skipped. Probing for MoselVitelic V29C51400B, 512 KB: skipped. Probing for MoselVitelic V29C51400T, 512 KB: skipped. Probing for MoselVitelic V29LC51000, 64 KB: skipped. Probing for MoselVitelic V29LC51001, 128 KB: skipped. Probing for MoselVitelic V29LC51002, 256 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: skipped. Probing for PMC Pm49FL004, 512 KB: skipped. Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL004A, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL032A, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL064A, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF010.REMS, 128 KB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF064C, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25LF040A.RES, 512 KB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BB, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: skipped. Probing for ST M50FLW040B, 512 KB: skipped. Probing for ST M50FLW080A, 1024 KB: skipped. Probing for ST M50FLW080B, 1024 KB: skipped. Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W29C020(C)/W29C022, 256 KB: skipped. Probing for Winbond W29C040/P, 512 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W39L040, 512 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040B, 512 KB: skipped. Probing for Winbond W39V040C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V040FB, 512 KB: skipped. Probing for Winbond W39V040FC, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U/N, 256 KB: skipped. Probing for Winbond W49F020, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for AMIC unknown AMIC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon unknown Eon SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix unknown Macronix SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (RDID), 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 0xc2, id2 0x13 === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! No operations were specified. [root@localhost flashrom]# A non-text attachment has been stripped: flash-rom-read It is available at http://paste.flashrom.org/view.php?id=691

1 0

Re: [flashrom] Additional voltages
by Stefan Tauner 11 Jul '11

11 Jul '11

On Sun, 10 Jul 2011 16:07:33 -0400 Steven Zakulec <spzakulec(a)gmail.com> wrote: > Index: flashchips.c > =================================================================== > --- flashchips.c (revision 1368) > +++ flashchips.c (working copy) > @@ -143,10 +143,11 @@ > .block_erase = erase_chip_block_jedec, > }, > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {4750, 5250}, /* -55 speed is +-5%, all others +-10% */ > }, > > { > .vendor = "AMD", > .name = "Am29F016D", > @@ -254,10 +255,11 @@ > .block_erase = erase_chip_block_jedec, > }, > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {3000, 3600}, /* -45R speed is 3.0-3.6V, others 2.7-3.6V */ > }, > > { > .vendor = "AMD", > .name = "Am29LV001BT", > @@ -284,10 +286,11 @@ > .block_erase = erase_chip_block_jedec, > }, > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {3000, 3600}, /* -45R speed is 3.0-3.6V, others 2.7-3.6V */ > }, > > { > .vendor = "AMD", > .name = "Am29LV002BB", > @@ -315,10 +318,11 @@ > .block_erase = erase_chip_block_jedec, > }, > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {3000, 3600}, /* -55 speed is 3.0-3.6V, others 2.7-3.6V */ > }, > > { > .vendor = "AMD", > .name = "Am29LV002BT", > @@ -346,10 +350,11 @@ > .block_erase = erase_chip_block_jedec, > }, > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {3000, 3600}, /* -55 speed is 3.0-3.6V, others 2.7-3.6V */ > }, > > { > .vendor = "AMD", > .name = "Am29LV004BB", > @@ -377,10 +382,11 @@ > .block_erase = erase_chip_block_jedec, > }, > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {2700, 3600}, > }, > > { > .vendor = "AMD", > .name = "Am29LV004BT", > @@ -408,10 +414,11 @@ > .block_erase = erase_chip_block_jedec, > }, > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {2700, 3600}, > }, > > { > .vendor = "AMD", > .name = "Am29LV008BB", > @@ -439,10 +446,11 @@ > .block_erase = erase_chip_block_jedec, > }, > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {3000, 3600} /* 3.0-3.6V (-70R), 2.7-3.6V for others */ > }, > > { > .vendor = "AMD", > .name = "Am29LV008BT", > @@ -470,10 +478,11 @@ > .block_erase = erase_chip_block_jedec, > }, > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {3000, 3600} /* 3.0-3.6V (-70R), 2.7-3.6V for others */ > }, > > { > .vendor = "AMD", > .name = "Am29LV040B", > @@ -496,11 +505,11 @@ > .block_erase = erase_chip_block_jedec, > }, > }, > .write = write_jedec_1, > .read = read_memmapped, > - .voltage = {2700, 3600}, > + .voltage = {3000, 3600}, /* 3.0-3.6V (-60R), 2.7-3.6V for others */ > }, > > { > .vendor = "AMD", > .name = "Am29LV081B", > @@ -523,11 +532,11 @@ > .block_erase = erase_chip_block_jedec, > }, > }, > .write = write_jedec_1, > .read = read_memmapped, > - .voltage = {2700, 3600}, > + .voltage = {3000, 3600}, /* regulated voltage range- full range is 2.7-3.6V */ probably a speed grade distinction again? > }, > > { > .vendor = "AMIC", > .name = "A25L05PT", > @@ -589,10 +598,11 @@ > }, > .printlock = spi_prettyprint_status_register_amic_a25l05p, > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_256, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { > .vendor = "AMIC", > .name = "A25L10PT", > @@ -1330,11 +1340,11 @@ > }, > .printlock = spi_prettyprint_status_register_at25df, > .unlock = spi_disable_blockprotect_at25df, > .write = spi_chip_write_256, > .read = spi_chip_read, > - .voltage = {2300, 3600}, /* Datasheet says 2.3-3.6V or 2.7-3.6V */ > + .voltage = {2700, 3600}, /* Datasheet says there's a 2.3-3.6V & 2.7-3.6V model */ > }, > > { > .vendor = "Atmel", > .name = "AT25DF041A", > @@ -1368,11 +1378,11 @@ > }, > .printlock = spi_prettyprint_status_register_at25df, > .unlock = spi_disable_blockprotect_at25df, > .write = spi_chip_write_256, > .read = spi_chip_read, > - .voltage = {2300, 3600}, /* Datasheet says 2.3-3.6V or 2.7-3.6V */ > + .voltage = {2700, 3600}, /* Datasheet says there's a 2.3-3.6V & 2.7-3.6V model */ > }, > > { > .vendor = "Atmel", > .name = "AT25DF081", > @@ -1444,10 +1454,11 @@ > }, > .printlock = spi_prettyprint_status_register_at25df_sec, > .unlock = spi_disable_blockprotect_at25df_sec, > .write = spi_chip_write_256, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { > .vendor = "Atmel", > .name = "AT25DF161", > @@ -1771,11 +1782,11 @@ > .block_erase = spi_block_erase_20, > } > }, > .write = NULL /* Incompatible Page write */, > .read = spi_chip_read, > - .voltage = {2700, 3600}, /* Datasheet says 3.0-3.6 V or 2.7-3.6 V */ > + .voltage = {2700, 3600}, /* Datasheet says 3.0-3.6 V or 2.7-3.6 V- either range is fine */ that comment is a bit vague... i like the one of the AT25DF041A above better. > }, > > { > .vendor = "Atmel", > .name = "AT26DF081A", > @@ -2112,11 +2123,11 @@ > .tested = TEST_BAD_READ, > .probe = probe_spi_rdid, > .probe_timing = TIMING_ZERO, > .write = NULL, > .read = NULL, > - .voltage = {2500, 3600}, /* Datasheet says 2.5-3.6 V or 2.7-3.6 V */ > + .voltage = {2700, 3600}, /* Datasheet says 2.5-3.6 V or 2.7-3.6 V */ > }, > > { > .vendor = "Atmel", > .name = "AT45DB161D", > @@ -2128,11 +2139,11 @@ > .tested = TEST_BAD_READ, > .probe = probe_spi_rdid, > .probe_timing = TIMING_ZERO, > .write = NULL, > .read = NULL, > - .voltage = {2500, 3600}, /* Datasheet says 2.5-3.6 V or 2.7-3.6 V */ > + .voltage = {2700, 3600}, /* Datasheet says 2.5-3.6 V or 2.7-3.6 V */ > }, > > { > .vendor = "Atmel", > .name = "AT45DB321C", > @@ -2315,10 +2326,11 @@ > .block_erase = erase_chip_block_jedec, > }, > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {4500, 5500}, > }, > > { > .vendor = "EMST", > .name = "F49B002UA", > @@ -3499,10 +3511,11 @@ > .block_erase = erase_chip_block_jedec, > }, > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {4500, 5500}, > }, > > { > .vendor = "Intel", > .name = "28F001BN/BX-B", > @@ -4050,10 +4063,11 @@ > } > }, > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_256, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { > .vendor = "Macronix", > .name = "MX25L3205", > @@ -4342,10 +4356,11 @@ > .block_erase = erase_chip_block_jedec, > }, > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {4500, 5500}, > }, > > { > .vendor = "Macronix", > .name = "MX29LV040", > @@ -4773,10 +4788,11 @@ > } > }, > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_256, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { > .vendor = "PMC", > .name = "Pm25LV020", > @@ -4898,10 +4914,11 @@ > } > }, > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_256, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { > .vendor = "PMC", > .name = "Pm29F002T", > @@ -5199,10 +5216,11 @@ > } > }, > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_256, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { > .vendor = "Spansion", > .name = "S25FL008A", > @@ -5279,10 +5297,11 @@ > } > }, > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_256, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { > .vendor = "Spansion", > .name = "S25FL064A", > @@ -5305,10 +5324,11 @@ > } > }, > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_256, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { > .vendor = "SST", > .name = "SST25VF010.REMS", > @@ -5334,10 +5354,11 @@ > }, > }, > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_1, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { > .vendor = "SST", > .name = "SST25VF016B", > @@ -5471,10 +5492,11 @@ > }, > }, > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_1, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { > .vendor = "SST", > .name = "SST25VF040B", > @@ -5536,10 +5558,11 @@ > }, > }, > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_1, > .read = spi_chip_read, > + .voltage = {3000, 3600}, > }, > > { > .vendor = "SST", > .name = "SST25VF040B.REMS", > @@ -5571,10 +5594,11 @@ > }, > }, > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_1, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { > .vendor = "SST", > .name = "SST25VF080B", > @@ -5769,11 +5793,11 @@ > .manufacture_id = SST_ID, > .model_id = SST_SST39SF010, > .total_size = 128, > .page_size = 4096, > .feature_bits = FEATURE_EITHER_RESET, > - .tested = TEST_OK_PREW, > + .tested = TEST_OK_PR, why? > .probe = probe_jedec, > .probe_timing = 1, /* 150 ns */ > .block_erasers = > { > { > @@ -6703,11 +6727,11 @@ > .bustype = CHIP_BUSTYPE_SPI, > .manufacture_id = ST_ID, > .model_id = ST_M25P128, > .total_size = 16384, > .page_size = 256, > - .tested = TEST_OK_PREW, > + .tested = TEST_UNTESTED, why? > .probe = probe_spi_rdid, > .probe_timing = TIMING_ZERO, > .block_erasers = > { > { > @@ -6778,10 +6802,11 @@ > } > }, > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_256, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { > .vendor = "ST", > .name = "M25PX64", > @@ -7774,11 +7799,11 @@ > .read = spi_chip_read, > }, > > { > .vendor = "Winbond", > - .name = "W25X10", > + .name = "W25x10", ah i think i see the pattern... you are reverting my last changes. you need to rebase your changes on top of mine/the ones in svn instead. > .bustype = CHIP_BUSTYPE_SPI, > .manufacture_id = WINBOND_NEX_ID, > .model_id = WINBOND_NEX_W25X10, > .total_size = 128, > .page_size = 256, > @@ -7805,11 +7830,11 @@ > .voltage = {2700, 3600}, > }, > > { > .vendor = "Winbond", > - .name = "W25X20", > + .name = "W25x20", > .bustype = CHIP_BUSTYPE_SPI, > .manufacture_id = WINBOND_NEX_ID, > .model_id = WINBOND_NEX_W25X20, > .total_size = 256, > .page_size = 256, > @@ -7836,11 +7861,11 @@ > .voltage = {2700, 3600}, > }, > > { > .vendor = "Winbond", > - .name = "W25X40", > + .name = "W25x40", > .bustype = CHIP_BUSTYPE_SPI, > .manufacture_id = WINBOND_NEX_ID, > .model_id = WINBOND_NEX_W25X40, > .total_size = 512, > .page_size = 256, > @@ -7867,11 +7892,11 @@ > .voltage = {2700, 3600}, > }, > > { > .vendor = "Winbond", > - .name = "W25X80", > + .name = "W25x80", > .bustype = CHIP_BUSTYPE_SPI, > .manufacture_id = WINBOND_NEX_ID, > .model_id = WINBOND_NEX_W25X80, > .total_size = 1024, > .page_size = 256, > @@ -7898,11 +7923,11 @@ > .voltage = {2700, 3600}, > }, > > { > .vendor = "Winbond", > - .name = "W25X16", > + .name = "W25x16", > .bustype = CHIP_BUSTYPE_SPI, > .manufacture_id = WINBOND_NEX_ID, > .model_id = WINBOND_NEX_W25X16, > .total_size = 2048, > .page_size = 256, > @@ -7935,11 +7960,11 @@ > .voltage = {2700, 3600}, > }, > > { > .vendor = "Winbond", > - .name = "W25X32", > + .name = "W25x32", > .bustype = CHIP_BUSTYPE_SPI, > .manufacture_id = WINBOND_NEX_ID, > .model_id = WINBOND_NEX_W25X32, > .total_size = 4096, > .page_size = 256, > @@ -7972,11 +7997,11 @@ > .voltage = {2700, 3600}, > }, > > { > .vendor = "Winbond", > - .name = "W25X64", > + .name = "W25x64", > .bustype = CHIP_BUSTYPE_SPI, > .manufacture_id = WINBOND_NEX_ID, > .model_id = WINBOND_NEX_W25X64, > .total_size = 8192, > .page_size = 256, > @@ -8039,13 +8064,13 @@ > .manufacture_id = WINBOND_ID, > .model_id = WINBOND_W29C020, > .total_size = 256, > .page_size = 128, > .feature_bits = FEATURE_LONG_RESET, > - .tested = TEST_OK_PREW, > + .tested = TEST_OK_PRE, > .probe = probe_jedec, > - .probe_timing = 10, > + .probe_timing = 10, > .block_erasers = > { > { > .eraseblocks = { {256 * 1024, 1} }, > .block_erase = erase_chip_block_jedec, > @@ -8129,10 +8154,11 @@ > } > }, > .printlock = printlock_w39l040, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {3000, 3600}, > }, > > { > .vendor = "Winbond", > .name = "W39V040A", > @@ -8273,10 +8299,11 @@ > }, > .printlock = printlock_w39v040fb, > .unlock = unlock_w39v040fb, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {3000, 3600}, /*Also offers a 12V fast program */ space after /* please > }, > > { > .vendor = "Winbond", > .name = "W39V040FC", > @@ -8300,10 +8327,11 @@ > } > }, > .printlock = printlock_w39v040fc, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {3000, 3600}, /*Also offers a 12V fast program */ again > }, > > { > .vendor = "Winbond", > .name = "W39V080A", > @@ -8395,13 +8423,13 @@ > .manufacture_id = WINBOND_ID, > .model_id = WINBOND_W49V002A, > .total_size = 256, > .page_size = 128, > .feature_bits = FEATURE_EITHER_RESET, > - .tested = TEST_OK_PREW, > + .tested = TEST_OK_PRE, > .probe = probe_jedec, > - .probe_timing = 10, > + .probe_timing = 10, > .block_erasers = > { > { > .eraseblocks = { > {64 * 1024, 3}, > @@ -8504,10 +8532,11 @@ > } > }, > .printlock = printlock_w39v080fa_dual, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {3000, 3600}, /* 12 V fast program mode */ > }, > > { > .vendor = "AMIC", > .name = "unknown AMIC SPI chip", i just skimmed through it, so i may have missed a few things. thanks for trying to provide more context in the patch. it is not enough though... the number of 5 i told you was just an example. this adds 5 lines above and 5 lines below every change in a patch. what i wanted to accomplish is that the model name of every chip that is changed is mentioned in the patch. so depending on the number of erasers in the affected chips a number as high as 20 or so is needed (another example number). > I believe I've addressed all of your issues. > What's the correct datasheet for M25PX16 ? There seem to be several of them > , by different companies. st created a joint venture with others forming numonyx. numonyx was acquired by micron later... http://www.micron.com/get-document/?documentId=5983 -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] ECS GeForce 8000 series, NVIDIA MCP78S: flashrom -V (v0.9.2-r1141)
by Paul Menzel 10 Jul '11

10 Jul '11

Dear Philipp, please always reply to the list too and use interleaved style [3]. Am Sonntag, den 10.07.2011, 22:08 +0200 schrieb Philipp Shah: > actually I wrote that message because it was written on the console by > your program. Understood. > So I just wanted to support the project and didn't check whether a new > version exist and could cover my "case" of bios; I just used the ubuntu > package and wasn't thinking of a newer version. Thank you for the follow up. It is good to know that there is no problem on your end. Thanks again for supporting flashrom, Paul [3] http://en.opensuse.org/openSUSE:Mailing_list_netiquette

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Re: [flashrom] Additional voltages
by Stefan Tauner 10 Jul '11

10 Jul '11

On Mon, 4 Jul 2011 22:27:59 -0400 Steven Zakulec <spzakulec(a)gmail.com> wrote: > Hello, I've attached some additional voltages for a number of the remaining > chips in flashchips.c. thanks for your continuous contributions :) > I have some questions about some of the remaining > chips: > > Should the voltage range always be the most restrictive one offered, with > others mentioned in the comments? that's most probably what we want for now, yes. i dont know what we are gonna do with the values, but a possible use case could be to tell an external programmer what voltage it should supply. we would have to choose a safe value from a number of choices that the programmer supports. since we are not able to differentiate between different speed grades (or whatever the distinction of chips with different voltage ranges are), we have to choose one of the most conservative range in our database. later this could be extended to allow the user to set a voltage outside of the safe range, but inside the extended ranges. > Where can I find the datasheet for the Sanyo LF25FW203A? good question, i cant find one either. the guy who has added this (Sean Nelson <audiohacked(a)gmail.com>) is currently unavailable afaik. > Can I ignore the .REMS/etc text after a chip name when looking for the > datasheet? Is it something I need to be aware of? yes. the suffix corresponds with the opcode used to identify the chip. some chips do support multiple such opcodes and are added multiple times (for now) in flashchips.c supply voltage is independent and so should be equal for such variations. > Is there a difference for M25P40 and P40-old? similar to above the old version seems to use a different probing method. i have not looked at the datasheet(s) so i can't say if the supply voltages are different. http://www.coreboot.org/pipermail/coreboot/2008-May/034640.html and the preceding discussion may shed some light on this. if i were you i would just leave it out for now. > For the W25Q64, it seems to be on the same datasheet as the Q80, Q16, and > Q32, but it's only referenced once in the sheet, and makes me wonder if this > is the correct sheet then. there are multiple versions of the W25Q64 (and maybe also of the other chips in the 25Q series, i have not looked into it). http://www.winbond.com/hq/enu/ProductAndSales/ProductSearch/?partno=w25q64 V: 3V (no datasheet, probably predecessor of BV. BV: 3V (deprecated) CV: 3V (successor of BV) DW: 1.8V (not supported by flashrom yet, has a different id (0x6017) the difference between BV and CV regarding the supply voltage is, that the BV specs a supply voltage of at least 3.0V for "Octal Word Read Quad I/O (E3h)" when used with a clock of 50MHz. this can be ignored for now, just use 2.7-3.3 imho. > Index: flashchips.c > =================================================================== > --- flashchips.c (revision 1364) > +++ flashchips.c (working copy) i have not looked into it in detail yet, just a few comments... > @@ -145,6 +145,7 @@ > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {4750, 5250}, /* -55 speed is +-5%, all others +-10% */ > }, > > { > @@ -256,6 +257,7 @@ > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {3000, 3600}, /* -45R speed is 3.0-3.6V regulated, others 2.7-3.6V */ > }, i think you can drop "regulated" in those entries. its use in the datasheet is already a bit odd imho, but in the comments it is even less clear without the context of the datasheet. > { > @@ -286,6 +288,7 @@ > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {3000, 3600}, /* -45R speed is 3.0-3.6V regulated, others 2.7-3.6V */ > }, > > { > @@ -317,6 +320,7 @@ > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {3000, 3600}, /* -55 speed is 3.0-3.6V regulated, others 2.7-3.6V */ > }, > > { > @@ -348,6 +352,7 @@ > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {3000, 3600}, /* -55 speed is 3.0-3.6V regulated, others 2.7-3.6V */ > }, > > { > @@ -379,6 +384,7 @@ > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {2700, 3600}, > }, > > { > @@ -410,6 +416,7 @@ > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {2700, 3600}, > }, > > { > @@ -441,6 +448,7 @@ > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {3000, 3600} /* 3.0-3.6V regulated(-70R), 2.7-3.6V for others */ > }, > > { > @@ -472,6 +480,7 @@ > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {3000, 3600} /* 3.0-3.6V regulated(-70R), 2.7-3.6V for others */ > }, > > { > @@ -498,7 +507,7 @@ > }, > .write = write_jedec_1, > .read = read_memmapped, > - .voltage = {2700, 3600}, > + .voltage = {3000, 3600}, /* regulated voltage range- full range is 2.7-3.6V */ > }, NB: that's the diff for Am29LV040B >3.0V for the -60R speedgrade only, so essentially the line should be similar to the ones above. when reading that datasheet i noticed the following paragraph: "The device requires only a single power supply (2.7 V–3.6V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations." this indicates to me that at least for these "regulated" means that they have an internal voltage regulator to guarantee stable supply for write/erase operations. such regulators need a minimum difference between input (vcc) and output (some internal voltage rail), hence the 0.3V higher vcc requirement. i am not sure if the other chips we have encountered also have internal regulators, but they may have. these are implementation-specific details which are not necessarily interesting to flashrom or its users. i think just naming the speed grades for the noted ranges is the best way to deal with such chips for now. > { > @@ -525,7 +534,7 @@ > }, > .write = write_jedec_1, > .read = read_memmapped, > - .voltage = {2700, 3600}, > + .voltage = {3000, 3600}, /* regulated voltage range- full range is 2.7-3.6V */ > }, > > { > @@ -591,6 +600,7 @@ > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_256, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { > @@ -1446,6 +1456,7 @@ > .unlock = spi_disable_blockprotect_at25df_sec, > .write = spi_chip_write_256, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { > @@ -2317,6 +2328,7 @@ > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {4500, 5500}, > }, > > { > @@ -3501,6 +3513,7 @@ > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {4500, 5500}, > }, > > { > @@ -4052,6 +4065,7 @@ > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_256, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { > @@ -4344,6 +4358,7 @@ > }, > .write = write_jedec_1, > .read = read_memmapped, > + .voltage = {4500, 5500}, > }, > > { > @@ -4775,6 +4790,7 @@ > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_256, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { > @@ -4900,6 +4916,7 @@ > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_256, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { > @@ -5201,6 +5218,7 @@ > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_256, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { > @@ -5281,6 +5299,7 @@ > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_256, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { > @@ -5307,6 +5326,7 @@ > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_256, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { > @@ -6780,6 +6800,7 @@ > .unlock = spi_disable_blockprotect, > .write = spi_chip_write_256, > .read = spi_chip_read, > + .voltage = {2700, 3600}, > }, > > { to ease review you could post diffs with more context so that the chip models are included in each hunk. i cant remember the correct svn diff parameters right now for this though. i personally don't need it, but if you can figure it out quickly it may be nice to have. :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Probe, Read, Erase, Write Success on Winbond W25Q16 with buspirate_spi
by Stefan Tauner 10 Jul '11

10 Jul '11

On Sat, 9 Jul 2011 21:28:42 -0400 Jon Szymaniak <jon.szymaniak(a)gmail.com> wrote: > Hi there, > > Per the "UNTESTED" message I received in v0.9.3-r1364, I just wanted to > report a couple successful PROBE, READ, WRITE and ERASE operations on a > Winbond W25Q16 with a BusPirate v2g0 (FW 4.1). I suppose this is expected > given that the W25X16 is supported, but thought someone might like to know > ;). > > I've attached the requested -V dumps for the aforementioned operations, as > well as 'time' output for each operation. With the BP v2g0 running FW v4.1, > I was seeing ~30 min on a 2MB read, and ~90 min on a 2MB write. I see that > somewhere above FW v5.7 and with some flashrom patches I should be able to > get some much quicker reads and writes. If I can get that going, I'd be > happy to do a bit more testing with this chip if you folks are interested. > > Thank you for providing a wonderful piece of software...cheers! > Jon Szymaniak hello jon and thanks for your (thorough) report! i have marked the chip as fully tested and will commit that later. PS: uncompressed logs are preferred (because they can be easier searched), no need to resend them though. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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flashrom -V
by Philipp Shah 10 Jul '11

10 Jul '11

flashrom v0.9.2-r1141 on Linux 2.6.38-8-generic (x86_64), built with libpci 3.1.7, GCC 4.5.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 767M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1001 us, 10000 myus = 10008 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "ECS" DMI string system-product-name: "GeForce 8000 series" DMI string system-version: "1.0 " DMI string baseboard-manufacturer: "ECS" DMI string baseboard-product-name: "GeForce 8000 series" DMI string baseboard-version: "1.0 " DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP78S", enabling flash write... chipset PCI ID is 10de:075c, This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Flash bus type is SPI Found SMBus device 10de:0752 at 00:01:1 MCP SPI BAR is at 0xf9f80000 SPI control is 0xc012, req=0, gnt=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for AMIC A25L05PT, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L05PU, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PT, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PU, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PT, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PU, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L80P, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PT, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PU, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L080, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L016, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25LQ032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for ASD AE49F2008, 256 KB: skipped. Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DQ161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for EMST F25L008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN29F010, 128 KB: skipped. Probing for Eon EN29F002(A)(N)B, 256 KB: skipped. Probing for Eon EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Intel 28F001BX-B, 128 KB: skipped. Probing for Intel 28F001BX-T, 128 KB: skipped. Probing for Intel 28F002BC-T, 256 KB: skipped. Probing for Intel 28F004S5, 512 KB: skipped. Probing for Intel 28F004BV/BE-B, 512 KB: skipped. Probing for Intel 28F004BV/BE-T, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-B, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address 0xfff00000. Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for MoselVitelic V29C51000B, 64 KB: skipped. Probing for MoselVitelic V29C51000T, 64 KB: skipped. Probing for MoselVitelic V29C51400B, 512 KB: skipped. Probing for MoselVitelic V29C51400T, 512 KB: skipped. Probing for MoselVitelic V29LC51000, 64 KB: skipped. Probing for MoselVitelic V29LC51001, 128 KB: skipped. Probing for MoselVitelic V29LC51002, 256 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: skipped. Probing for PMC Pm49FL004, 512 KB: skipped. Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF064C, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25LF040A.RES, 512 KB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BB, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: skipped. Probing for ST M50FLW040B, 512 KB: skipped. Probing for ST M50FLW080A, 1024 KB: skipped. Probing for ST M50FLW080B, 1024 KB: skipped. Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W29C011, 128 KB: skipped. Probing for Winbond W29C020C, 256 KB: skipped. Probing for Winbond W29C040P, 512 KB: skipped. Probing for Winbond W29EE011, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040B, 512 KB: skipped. Probing for Winbond W39V040C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U, 256 KB: skipped. Probing for Winbond W49F020, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for AMIC unknown AMIC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon unknown Eon SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix unknown Macronix SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (RDID), 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 0xc2, id2 0x13 No operations were specified.

2 1

[PATCH] remove unneeded inclusions of chipdrivers.h
by Stefan Tauner 10 Jul '11

10 Jul '11

this is related to the spi split patch as discussed in: http://www.flashrom.org/pipermail/flashrom/2010-February/thread.html#2364 the old commit (r914) log notes: "Some of the spi programmer drivers required chipdrivers.h, needs fixing later: it87spi.c ichspi.c sb600spi.c wbsio_spi.c buspirate_spi.c ft2232spi.c bitbang_spi.c dediprog.c" there still remain a few cases where chipdrivers.h is needed: dediprog.c it87spi.c wbsio_spi.c (spi_programmer registration only) besides that, there are also non-spi files that do not need it. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- bitbang_spi.c | 1 - buspirate_spi.c | 1 - ft2232_spi.c | 1 - ichspi.c | 1 - it85spi.c | 1 - jedec.c | 1 - pm49fl00x.c | 1 - sb600spi.c | 1 - sst_fwhub.c | 1 - w29ee011.c | 1 - w39.c | 1 - 11 files changed, 0 insertions(+), 11 deletions(-) diff --git a/bitbang_spi.c b/bitbang_spi.c index 3c718af..8e2f780 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -22,7 +22,6 @@ #include <stdlib.h> #include <ctype.h> #include "flash.h" -#include "chipdrivers.h" #include "programmer.h" #include "spi.h" diff --git a/buspirate_spi.c b/buspirate_spi.c index f872309..caa27c0 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -23,7 +23,6 @@ #include <ctype.h> #include <unistd.h> #include "flash.h" -#include "chipdrivers.h" #include "programmer.h" #include "spi.h" diff --git a/ft2232_spi.c b/ft2232_spi.c index 7416e5b..cf67ff5 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -25,7 +25,6 @@ #include <stdlib.h> #include <ctype.h> #include "flash.h" -#include "chipdrivers.h" #include "programmer.h" #include "spi.h" #include <ftdi.h> diff --git a/ichspi.c b/ichspi.c index 99c4613..d9c9b4b 100644 --- a/ichspi.c +++ b/ichspi.c @@ -38,7 +38,6 @@ #include <string.h> #include "flash.h" -#include "chipdrivers.h" #include "programmer.h" #include "spi.h" diff --git a/it85spi.c b/it85spi.c index d4ca13b..c82f975 100644 --- a/it85spi.c +++ b/it85spi.c @@ -30,7 +30,6 @@ #include <stdio.h> #include <stdlib.h> #include "flash.h" -#include "chipdrivers.h" #include "spi.h" #include "programmer.h" diff --git a/jedec.c b/jedec.c index b96f5fd..cf34bcd 100644 --- a/jedec.c +++ b/jedec.c @@ -23,7 +23,6 @@ */ #include "flash.h" -#include "chipdrivers.h" #define MAX_REFLASH_TRIES 0x10 #define MASK_FULL 0xffff diff --git a/pm49fl00x.c b/pm49fl00x.c index 4136b17..28052e5 100644 --- a/pm49fl00x.c +++ b/pm49fl00x.c @@ -21,7 +21,6 @@ */ #include "flash.h" -#include "chipdrivers.h" static void write_lockbits_49fl00x(chipaddr bios, int size, unsigned char bits, int block_size) diff --git a/sb600spi.c b/sb600spi.c index 37aac3b..5ad5782 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -24,7 +24,6 @@ #if defined(__i386__) || defined(__x86_64__) #include "flash.h" -#include "chipdrivers.h" #include "programmer.h" #include "spi.h" diff --git a/sst_fwhub.c b/sst_fwhub.c index 65bd2b3..a11cccb 100644 --- a/sst_fwhub.c +++ b/sst_fwhub.c @@ -23,7 +23,6 @@ /* Adapted from the Intel FW hub stuff for 82802ax parts. */ #include "flash.h" -#include "chipdrivers.h" static int check_sst_fwhub_block_lock(struct flashchip *flash, int offset) { diff --git a/w29ee011.c b/w29ee011.c index 4fc8853..de6b63c 100644 --- a/w29ee011.c +++ b/w29ee011.c @@ -20,7 +20,6 @@ #include <string.h> #include "flash.h" -#include "chipdrivers.h" int probe_w29ee011(struct flashchip *flash) { diff --git a/w39.c b/w39.c index 2635988..5e5d59e 100644 --- a/w39.c +++ b/w39.c @@ -20,7 +20,6 @@ */ #include "flash.h" -#include "chipdrivers.h" static int printlock_w39_fwh_block(struct flashchip *flash, int offset) { -- 1.7.1

1 0

Probe, Read, Erase, Write Success on Winbond W25Q16 with buspirate_spi
by Jon Szymaniak 10 Jul '11

10 Jul '11

Hi there, Per the "UNTESTED" message I received in v0.9.3-r1364, I just wanted to report a couple successful PROBE, READ, WRITE and ERASE operations on a Winbond W25Q16 with a BusPirate v2g0 (FW 4.1). I suppose this is expected given that the W25X16 is supported, but thought someone might like to know ;). I've attached the requested -V dumps for the aforementioned operations, as well as 'time' output for each operation. With the BP v2g0 running FW v4.1, I was seeing ~30 min on a 2MB read, and ~90 min on a 2MB write. I see that somewhere above FW v5.7 and with some flashrom patches I should be able to get some much quicker reads and writes. If I can get that going, I'd be happy to do a bit more testing with this chip if you folks are interested. Thank you for providing a wonderful piece of software...cheers! Jon Szymaniak

1 0

Re: [flashrom] [PATCH] warn the user if flashrom is x months old
by Stefan Tauner 09 Jul '11

09 Jul '11

On Fri, 8 Jul 2011 11:46:38 -0700 David Hendricks <dhendrix(a)google.com> wrote: > On Fri, Jul 8, 2011 at 4:35 AM, Stefan Tauner < > stefan.tauner(a)student.tuwien.ac.at> wrote: > > > i had the idea to implement an expiration date for flashrom binaries > > (i.e. a time bomb). in the case distributions ship ancient binaries > > (in the future) this may save a bunch of hardware. > > > > i noted two reactions back then when i proposed this idea on IRC in my > > todo.txt: > > <twice11> If I validated software to work on some system, I don't want > > it to suddenly break one year later. > > <agaran> twice11: but kind notify that version you use is %d days old > > (and repeated every multiple of time or 100days or so) could be nice > > > > Interesting idea, but I have to agree with twice11 here. I do not want a > version of flashrom that works fine on the systems I'm supporting to > suddenly start breaking scripts or throwing superfluous warnings to users > and testers. This will definitely cause headaches for ODMs/OEMs and > commercial Linux system vendors :-( sure. when i said "it is worth to think about something like this", i meant something like the current patch, that prints a warning only. OTOH, it may still be useful to provide an option to really bail out instead of warning only (which of course would be off by default). the question is if any maintainer or individual may ever use it... if there is interest for this, i could create an add-on patch for that so we can decide its inclusion independently from the warning patch. please say so, if you think i should do that. > IMHO it would be more useful to try and get generic distros to a) not > include a flashrom binary by default and b) when a user installs it > manually, fetch and compile sources from SVN. providing a script that tries to mimic what the wiki installation guide tells the user to do, might be worth then? checking the availability of different package managers is quite easy, checking for the correct names shouldnt be much harder? > As for the patch itself, if this idea moves forward then it would be nice to > isolate the code a bit more so it can be easily removed. Rather than placing > it in print_version(), I recommend creating another function which would be > called from cli_classic(). jup, certainly a good idea. "so it can be easily removed" -> do you think anyone would really want that? does it justify an option in the makefile? maybe we should "move" the OLD_MONTHS macro to the macro and add an #ifdef around the code? carldani: the xml "parsing" is not a problem... parsing the normal svn info output would be harder. do you see a problem in the way i do it? what do you think could "cause problems for users of live CDs and FreeDOS distributions" in the current implementation? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 2

Re: [flashrom] Help: trouble when flashing rom
by Idwer Vollering 09 Jul '11

09 Jul '11

Please use "reply to all" in the future. Thanks. 2011/4/19 Cyrille Bartholomée <cyrille(a)bartholomee.com>: > Dear Idwer, > > Just built checkout from svn. It outputs this result: Again: DO NOT REBOOT OR POWEROFF YOUR LAPTOP. > > flashrom v0.9.3-r1288 on Linux 2.6.35-28-generic (i686), built with libpci > 3.1.7, GCC 4.4.5, little endian > > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... delay loop is unreliable, trying to continue OK. > > Found chipset "Intel ICH4-M", enabling flash write... OK. > > This chipset supports the following protocols: FWH. > > Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. > > Flash image seems to be a legacy BIOS. Disabling checks. > > Erasing and writing flash chip... ERASE FAILED at 0x00016000! Expected=0xff, > Read=0xae, failed byte count from 0x00016000-0x00016fff: 0xfde > > ERASE FAILED! > > ERASE FAILED at 0x00010000! Expected=0xff, Read=0xca, failed byte count from > 0x00010000-0x0001ffff: 0xfeb2 > > ERASE FAILED! > > Segmentatiefout > > Segmentatiefout=segmentation error flashrom should NOT have segfaulted. Can you show the last lines of dmesg (dmesg | tail) ? > > Maybe this information can help you? > > Regards, > > Cyrille Bartholomée | De Damhouderestraat 20 | 2018 Antwerpen > > t. 0032 3 298 4244 | m. 0032 499 711 018 | e. cyrille(a)bartholomee.com > > Op dinsdag 19 april 2011 07:25:59 schreef Cyrille Bartholomée: > >> Dear Idwer, > >> > >> > >> First of all thank you for responding so fast and trying to help me! > >> > >> 1. Downloaded and built latest flashrom. Problem remains exactly the same >> as with previous version. > >> 2. I am using an Asus laptop model M6Ne, the exact type of board I don't >> know. > >> 3. I have run the commands you mentioned, the results are attached to this >> mail. > >> > >> If there is more information you need, please let me know. > >> > >> Again, thanks for your help. > >> > >> > >> Kind regards, > >> > >> Cyrille Bartholomée | De Damhouderestraat 20 | 2018 Antwerpen > >> t. 0032 3 298 4244 | m. 0032 499 711 018 | e. cyrille(a)bartholomee.com > >> > >> Op dinsdag 19 april 2011 00:21:28 schreef u: > >> > 2011/4/18 Cyrille Bartholomée <cyrille(a)bartholomee.com>: > >> > > Dear, > >> > > > >> > > I'm facing this problem when flashing my rom: > >> > > > >> > > flashrom v0.9.2-r1028 on Linux 2.6.35-28-generic (i686), built with >> > > libpci > >> > > 3.0.0, GCC 4.4.4, little endian > >> > > > >> > > flashrom is free software, get the source code at >> > > http://www.flashrom.org > >> > > > >> > > Calibrating delay loop... delay loop is unreliable, trying to continue >> > > OK. > >> > > > >> > > No coreboot table found. > >> > > > >> > > Found chipset "Intel ICH4-M", enabling flash write... OK. > >> > > > >> > > This chipset supports the following protocols: Non-SPI. > >> > > > >> > > Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address >> > > 0xfff80000. > >> > > > >> > > Flash image seems to be a legacy BIOS. Disabling checks. > >> > > > >> > > Writing flash chip... Erasing flash chip... ERASE FAILED at >> > > 0x00000008! > >> > > Expected=0xff, Read=0x00, failed byte count from >> > > 0x00000000-0x00000fff: > >> > > 0xfc5 > >> > > > >> > > ERASE FAILED! > >> > > > >> > > ERASE FAILED at 0x00000008! Expected=0xff, Read=0x00, failed byte >> > > count from > >> > > 0x00000000-0x0000ffff: 0xfadb > >> > > > >> > > ERASE FAILED! > >> > > > >> > > FAILED! > >> > > > >> > > ERASE FAILED! > >> > > > >> > > FAILED! > >> > > > >> > > Your flash chip is in an unknown state. > >> > > > >> > > Get help on IRC at irc.freenode.net (channel #flashrom) or > >> > > > >> > > mail flashrom(a)flashrom.org! > >> > > >> > Can you: > >> > - try a newer release (or build the latest developemt code yourself > >> > http://www.flashrom.org/Downloads#Installation_from_source) > >> > - mention the exact name of your board (including revision, if there > >> > are multiple revisions) > >> > - attach the output of 'flashrom -V', 'lspci -nnvvvxxx', 'superiotool > >> > -deV' (run all commands as root) > >> > > >> > > >> > Thanks in advance, > >> > Idwer > >> > > >> > > > >> > > >> > > ------------------------------------------------------------------------------- > >> > > > >> > > DO NOT REBOOT OR POWEROFF! > >> > > > >> > > Regards, > >> > > > >> > > Cyrille Bartholomée | De Damhouderestraat 20 | 2018 Antwerpen > >> > > > >> > > t. 0032 3 298 4244 | m. 0032 499 711 018 | e. cyrille(a)bartholomee.com > >> > > > >> > > _______________________________________________ > >> > > flashrom mailing list > >> > > flashrom(a)flashrom.org > >> > > http://www.flashrom.org/mailman/listinfo/flashrom > >> > > > >> > > >>

3 10

[commit] r1368 - trunk
by repository service 09 Jul '11

09 Jul '11

Author: stefanct Date: Sat Jul 9 21:46:53 2011 New Revision: 1368 URL: http://flashrom.org/trac/flashrom/changeset/1368 Log: add untested board enable for ASUS M6Ne http://patchwork.coreboot.org/patch/2893/ lspci: http://paste.flashrom.org/view.php?id=494 only writing a backup file was tested, so mark it as untested. Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Thu Jul 7 21:56:58 2011 (r1367) +++ trunk/board_enable.c Sat Jul 9 21:46:53 2011 (r1368) @@ -1521,6 +1521,15 @@ /* * Suited for: + * - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M + */ +static int intel_ich_gpio43_raise(void) +{ + return intel_ich_gpio_set(43, 1); +} + +/* + * Suited for: * - HP Vectra VL400: 815 + ICH + PC87360 */ static int board_hp_vl400(void) @@ -1996,6 +2005,7 @@ {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, P3, "ASUS", "A8N-VM CSM", 0, NT, w83627ehf_gpio24_raise_2e}, {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, P3, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, P3, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, + {0x8086, 0x24cc, 0, 0, 0x8086, 0x24c3, 0x1043, 0x1869, "^M6Ne$", NULL, NULL, P3, "ASUS", "M6Ne", 0, NT, intel_ich_gpio43_raise}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^P2B-N$", NULL, NULL, P3, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower}, {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, P3, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, P3, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Thu Jul 7 21:56:58 2011 (r1367) +++ trunk/print.c Sat Jul 9 21:46:53 2011 (r1368) @@ -451,6 +451,7 @@ B("ASUS", "M4A785TD-M EVO", 1, "http://www.asus.com/product.aspx?P_ID=QHbvGVB1mXmmD8qQ", NULL), B("ASUS", "M4A79T Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=lhJiLTN5huPfCVkW", NULL), B("ASUS", "M4A87TD/USB3", 1, "http://www.asus.com/product.aspx?P_ID=nlWYrI9wlNIYHAaa", NULL), + B("ASUS", "M6Ne", 0, "http://www.asus.com/Product.aspx?P_ID=IbqN4JCxeRiep4WN", "Untested board enable."), B("ASUS", "MEW-AM", 0, "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/", "No public report found. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>. May work now."), B("ASUS", "MEW-VM", 0, "http://www.elhvb.com/mboards/OEM/HP/manual/ASUS%20MEW-VM.htm", "No public report found. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>. May work now."), B("ASUS", "P2B", 1, "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b/", NULL),

1 0

Is the DVD burner LG GSA-4167B supported?
by Paul Menzel 09 Jul '11

09 Jul '11

Dear flashrom folks, listening to Carl-Daniel’s interview with RadioTux at LinuxTag [1] he mentions that flashrom also supports some DVD drives. Does flashrom support the DVD burner LG GSA-4167B? Searching the WWW I found a forum post [2] but contacting the author [3] was unsuccessful. Here is an excerpt from my message to the author. I want to flash my drive LG GSA-4167B currently running firmware version DL12 to DL13 [4][5]. $ dmesg [ 1.588392] ata4.00: ATAPI: HL-DT-ST DVDRAM GSA-4167B, DL12, max UDMA/33 [ 1.605261] ata4.00: configured for UDMA/33 [ 1.614030] scsi 3:0:0:0: CD-ROM HL-DT-ST DVDRAM GSA-4167B DL12 PQ: 0 ANSI: 5 It would be great if you could help me and provide me with the utility. What license do you use for your flasher? I guess the flashrom project [6] would be very much interested in your program. Thanks, Paul [1] http://blog.radiotux.de/2011/06/09/linuxtag-interview-mit-carl-daniel-von-f… [2] http://club.myce.com/f91/firmware-update-linux-304147/#post2465757 [3] http://devilsclaw.net/ [4] http://www.cdrinfo.com/Sections/Firmware/SingleModel.aspx?DriveId=1177 [5] http://lgodd.lge.com/fwdrv/DVD-WRITER/GSA4167DL13.exe [6] http://flashrom.org/

1 0

[PATCH] warn the user if flashrom is x months old
by Stefan Tauner 08 Jul '11

08 Jul '11

i had the idea to implement an expiration date for flashrom binaries (i.e. a time bomb). in the case distributions ship ancient binaries (in the future) this may save a bunch of hardware. i noted two reactions back then when i proposed this idea on IRC in my todo.txt: <twice11> If I validated software to work on some system, I don't want it to suddenly break one year later. <agaran> twice11: but kind notify that version you use is %d days old (and repeated every multiple of time or 100days or so) could be nice this proof of concept is probably not mergeable - especially the strptime() might be a problem (alternatives welcome), but i still think it is worth to think about something like this. comments? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

4 4

Re: [flashrom] [Patch] NVIDIA Tegra2 SPI controller support
by Carl-Daniel Hailfinger 08 Jul '11

08 Jul '11

Am 07.07.2011 02:32 schrieb David Hendricks: > On Tue, Jun 28, 2011 at 5:54 PM, Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2006(a)gmx.net> wrote: > >> 2-3-add_arm_isms.patch >> Have you checked with an architecture guru that sync_primitive() can >> really be empty, not only for that arch in general, but also for >> accesses to a mmapped region the way flashrom does it? >> > Nope. Scattered resources/forum posts about ARMv7 suggest that peripheral > memory is strongly ordered. Also, the U-Boot code doesn't have special > handling for sync primitives AFAICT. > > I'm pretty new to ARM... Any advice from experts on this list would be > appreciated. > I can't help you directly, but if you tell a Linux kernel developer with ARM experience how we access such regions, he/she might have some useful info for you: open("/dev/mem", O_RDWR | O_SYNC), then mmap, then reading/writing those regions with "normal" memory accessors. Opening /dev/mem with O_SYNC sometimes already has the right propertiess and no additional ordering helper is required. > I've updated this patch set on top of the other patches you've been working > on (autodetect target processor <http://patchwork.coreboot.org/patch/3256/> > and the libpci hack <http://patchwork.coreboot.org/patch/3255/>). > Thanks. > The difference between this patchset and the previous one is pretty minor. > We can now discard the first patch which #ifdef'd out PCI code for ARM > targets. The remaining differences are mostly centered around the Makefile > and arch.h > > New patches are: > Signed-off-by: David Hendricks <dhendrix(a)google.com> > > > 2-2-add_tegra2_spi_controller.patch: > Index: flashrom-tegra2/processor_enable.c > =================================================================== > --- flashrom-tegra2.orig/processor_enable.c > +++ flashrom-tegra2/processor_enable.c > @@ -81,6 +81,48 @@ static int is_loongson(void) > } > #endif > > +#if defined(__arm__) > +#include <stdio.h> > +#include <string.h> > +#include <ctype.h> > + > +/* Returns true if the /proc/cpuinfo contains a line: "CPU part *: *0xc09". > + * TODO: need to extend in future for same SPI controller in chip family. > + */ > +static int is_tegra2(void) > +{ > + FILE *cpuinfo; > + uint32_t impl = 0, architecture = 0, variant = 0, part = 0; > + const char *name = "CPU part"; > + const char *value = "0xc09"; > + int ret = 0; > + > + cpuinfo = fopen("/proc/cpuinfo", "rb"); > Hm. Would it be possible to share some code with the Loongson cpuinfo parser? > + if (!cpuinfo) > + return 0; > + while (!feof(cpuinfo)) { > + char line[512], *ptr; > + if (fgets(line, sizeof(line), cpuinfo) == NULL) > + break; > + ptr = line; > + while (*ptr && isspace((unsigned char)*ptr)) > + ptr++; > + if (strncmp(ptr, name, strlen(name)) == 0) > + ptr += strlen(name); > + while (*ptr && isspace((unsigned char)*ptr)) > + ptr++; > + if (*ptr != ':') > + continue; > + ptr++; > + while (*ptr && isspace((unsigned char)*ptr)) > + ptr++; > + ret = (strncmp(ptr, value, strlen(value)) == 0); > + } > I'm going to trust you on this code. It seems to work for you. > + fclose(cpuinfo); > + return ret; > +} > +#endif > + > int processor_flash_enable(void) > { > /* FIXME: detect loongson on FreeBSD and OpenBSD as well. */ > @@ -90,6 +132,13 @@ int processor_flash_enable(void) > return 0; > } > #endif > + > +#if defined (__arm__) > + if (is_tegra2()) { > + msg_pdbg("Detected NVIDIA Tegra 2.\n"); > + return tegra2_spi_init(); > + } > +#endif > /* Not implemented yet. Oh well. */ > return 1; > } > Index: flashrom-tegra2/programmer.h > =================================================================== > --- flashrom-tegra2.orig/programmer.h > +++ flashrom-tegra2/programmer.h > @@ -524,6 +524,9 @@ enum spi_controller { > SPI_CONTROLLER_VIA, > SPI_CONTROLLER_WBSIO, > #endif > +#if defined(__arm__) > + SPI_CONTROLLER_TEGRA2, > +#endif > #endif > #if CONFIG_FT2232_SPI == 1 > SPI_CONTROLLER_FT2232, > @@ -589,6 +592,13 @@ int mcp6x_spi_init(int want_spi); > /* sb600spi.c */ > int sb600_probe_spi(struct pci_dev *dev); > > +/* tegra2_spi.c */ > +int tegra2_spi_init(void); > +int tegra2_spi_send_command(unsigned int writecnt, unsigned int readcnt, > + const unsigned char *writearr, unsigned char *readarr); > +int tegra2_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > +int tegra2_spi_write(struct flashchip *flash, uint8_t *buf, int start, int len); > Can you kill the two lines above? > + > /* wbsio_spi.c */ > int wbsio_check_for_spi(void); > #endif > Index: flashrom-tegra2/tegra2_spi.c > =================================================================== > --- /dev/null > +++ flashrom-tegra2/tegra2_spi.c > @@ -0,0 +1,405 @@ > +/* > + * This file is part of the flashrom project. > + * > + * Copyright (C) 2010 NVIDIA Corporation > + * Copyright (C) 2011 Google Inc > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#if defined(__arm__) > +#include <assert.h> > +#include <stdio.h> > +#include <stdlib.h> > +#include <string.h> > + > +#include "flash.h" > +#include "programmer.h" > +#include "tegra2_spi.h" > + > +static void *gpio_base, *clkrst_base, *apbmisc_base, *spi_base; > + > +#define SPI_TIMEOUT 50000 /* 100ms = 50000 * 2us */ > + > +/* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */ > +#define UART_DISABLE_PORT 8 > +#define UART_DISABLE_BIT 3 > + > +/* Config port:bit as GPIO, not SFPIO (default) */ > +static void __set_config(unsigned port, unsigned bit, int type) > Rename type to val? Names starting with __ do not really make me happy. How about tegra2_spi_set_config? Or are there compelling cosmetic reasons? > +{ > + u32 u; > + > + msg_pdbg("%s: port = %d, bit = %d, %s\n", __func__, > + port, bit, type ? "GPIO" : "SFPIO"); > + > + u = mmio_readl(GPIO_CNF(port)); > + if (type) /* GPIO */ > + u |= 1 << bit; > + else > + u &= ~(1 << bit); > + rmmio_writel(u, GPIO_CNF(port)); > +} > + > +/* Config GPIO port:bit as input or output (OE) */ > +static void __set_direction(unsigned port, unsigned bit, int output) > Function rename, please (see above). > +{ > + u32 u; > + > + msg_pdbg("%s: port = %d, bit = %d, %s\n", __func__, > + port, bit, output ? "OUT" : "IN"); > + > + u = mmio_readl(GPIO_OE(port)); > + if (output) > + u |= 1 << bit; > + else > + u &= ~(1 << bit); > + rmmio_writel(u, GPIO_OE(port)); > +} > + > +/* set GPIO OUT port:bit as 0 or 1 */ > +static void __set_level(unsigned port, unsigned bit, int high) > Rename high to val? > +{ > + u32 u; > + > + msg_pdbg("%s: port = %d, bit %d == %d\n", __func__, > + port, bit, high); > + > + u = mmio_readl(GPIO_OUT(port)); > + if (high) > + u |= 1 << bit; > + else > + u &= ~(1 << bit); > + rmmio_writel(u, GPIO_OUT(port)); > +} > + > +/* set GPIO port:bit as an output, with polarity 'value' */ > +static int tg2_gpio_direction_output(unsigned port, unsigned bit, int value) > Rename value to val? Or rename val to value everywhere else in this patch? > +{ > + msg_pdbg("%s: port = %d, bit = %d, value = %d\n", > + __func__, port, bit, value); > + > + /* Configure as a GPIO */ > + __set_config(port, bit, 1); > + > + /* Configure GPIO output value. */ > + __set_level(port, bit, value); > + > + /* Configure GPIO direction as output. */ > + __set_direction(port, bit, 1); > + > + return 0; > +} > + > +static void spi_cs_activate(void) > +{ > + uint32_t *spi_cmd = (uint32_t *)spi_base; > + > + /* > + * CS is negated on Tegra, so drive a 1 to get a 0 > + */ > + mmio_writel(mmio_readl(spi_cmd) | SPI_CMD_CS_VAL, spi_cmd); > + msg_pspew("%s: CS driven %s\n", __func__, > + (mmio_readl(spi_cmd) & SPI_CMD_CS_VAL) ? "LOW" : "HIGH"); > +} > + > +static void spi_cs_deactivate(void) > +{ > + uint32_t *spi_cmd = (uint32_t *)spi_base; > + > + > + /* > + * CS is negated on Tegra, so drive a 0 to get a 1 > + */ > + mmio_writel(mmio_readl(spi_cmd) & ~SPI_CMD_CS_VAL, spi_cmd); > + msg_pspew("%s: CS driven %s\n", __func__, > + (mmio_readl(spi_cmd) & SPI_CMD_CS_VAL) ? "LOW" : "HIGH"); > +} > + > +/* Helper function to calculate the clock cycle in this round. > + * Also updates the byte count remaining to be used this round. > + * > + * For example, we want to write 6 bytes to SPI and then read 5 bytes back. > + * > + * +---+---+---+---+---+---+ > + * | W | W | W | W | W | W | > + * +---+---+---+---+---+---+---+---+---+---+---+ > + * | R | R | R | R | R | > + * +---+---+---+---+---+ > + * |<-- round 0 -->| > + * |<-- round 1 -->| > + * |<-- round 2 -->| > + * > + * So that the continuous calling this function would get: > + * > + * round| RET| writecnt readcnt bits to_write to_read > + * -----+----+--------------------------------------------- > + * INIT | | 6 5 > + * 0 | 1 | 2 5 32 4 0 > + * 1 | 1 | 0 3 32 2 2 > + * 2 | 1 | 0 0 24 0 3 > + * 3 | 0 | - - - - - > + * > + */ > +int next4Bytes(uint32_t *writecnt, uint32_t *readcnt, int *num_bits, > + uint32_t *to_write, uint32_t *to_read) { > + assert(writecnt); > Won't this explode in round 1+2? > + assert(readcnt); > Won't this explode in round 2? > + assert(num_bits); > + assert(to_write); > Explosions in round 2? > + assert(to_read); > Explosions in round 0? > + > + *to_write = min(*writecnt, 4); > + *to_read = min(*readcnt, 4 - *to_write); > + > + *writecnt -= *to_write; > + *readcnt -= *to_read; > + > + *num_bits = (*to_write + *to_read) * 8; > + > + if (*num_bits) > + return 1; /* need to be called again. */ > + else > + return 0; /* handled write and read requests. */ > +} > + > +/* > + * Tegra2 FIFO design is ... interesting. For example, you want to Tx 2 bytes: > + * > + * +---+---+ > + * writearr[]: | 0 | 1 | > + * +---+---+ > + * \ \ > + * \ \ > + * \ \ > + * \ \ > + * \ \ > + * 31 +---+---+---+---+ 0 > + * tmp(32-bits): | X | X | 0 | 1 | > + * +---+---+---+---+ LSB > + * > + * It is neither little or big endian. The first bit for SPI controller to > + * transfer is the bit 15 in FIFO, neither bit 31 or bit 0, because the transfer > + * length is 16 bits (2 bytes). > + * > + * Rx follows the similar rule. First bit comes at bit 0, and the whole FIFO > + * left-shifts 1 bit for every bit comes in. Hence, after reading 3 bytes, > + * the first coming bit will reside in bit 23. > + */ > +int tegra2_spi_send_command(unsigned int writecnt, > + unsigned int readcnt, > + const unsigned char *writearr, > + unsigned char *readarr) > +{ > + int retval = 0; > + uint8_t *delayed_msg = NULL; /* for UART is disabled. */ > + uint32_t *spi_cmd = (uint32_t *)spi_base; > + uint32_t *spi_sts = (uint32_t *)(spi_base + 0x04); > + uint32_t *tx_fifo = (uint32_t *)(spi_base + 0x10); > + uint32_t *rx_fifo = (uint32_t *)(spi_base + 0x20); > + uint32_t status; > + uint32_t to_write, to_read; /* byte counts to fill FIFO. */ > + uint32_t bits; /* bit count to tell SPI controller. */ > + > + mmio_writel(mmio_readl(spi_sts), spi_sts); > + mmio_writel(mmio_readl(spi_cmd) | SPI_CMD_TXEN | SPI_CMD_RXEN, spi_cmd); > + spi_cs_activate(); > + > + while (next4Bytes(&writecnt, &readcnt, &bits, &to_write, &to_read)) { > + int i; > + uint32_t tmp; > + uint32_t tm; /* timeout counter */ > + > + /* prepare Tx FIFO */ > + for (tmp = 0, i = 0; i < to_write; ++i) { > + tmp |= (*writearr++) << ((bits / 8 - 1 - i) * 8); > + } > + mmio_writel(tmp, tx_fifo); > + > + /* Kick the SCLK running: Shift out TX FIFO, and receive RX. */ > + mmio_writel(mmio_readl(spi_cmd) & ~SPI_CMD_BIT_LENGTH_MASK, > + spi_cmd); > + mmio_writel(mmio_readl(spi_cmd) | (bits - 1), > + spi_cmd); > + mmio_writel(mmio_readl(spi_cmd) | SPI_CMD_GO, spi_cmd); > + > + /* Wait for controller completes the task. */ > + for (tm = 0; tm < SPI_TIMEOUT; ++tm) { > + if (((status = mmio_readl(spi_sts)) & > + (SPI_STAT_BSY | SPI_STAT_RDY)) == SPI_STAT_RDY) > + break; > + /* We setup clock to 6MHz, so that we shall come back > + * after: 1 / (6MHz) * 8 bits = 1.333us > + */ > + programmer_delay(2); > + } > + mmio_writel(mmio_readl(spi_sts) | SPI_STAT_RDY, spi_sts); > + > + /* Since the UART is disabled here, we delay printing the > + * message until spi_cs_deactivate() is called. > + */ > + if (tm >= SPI_TIMEOUT) { > + static uint8_t err[256]; > + retval = -1; > + snprintf(err, sizeof(err), > + "%s():%d BSY&RDY timeout, status = 0x%08x\n", > + __func__, __LINE__, status); > + delayed_msg = err; > + break; > + } > + > + /* read RX FIFO */ > + tmp = mmio_readl(rx_fifo); > + for (i = 0; i < to_read; ++i) { > + *readarr++ = (tmp >> ((to_read - 1 - i) * 8)) & 0xFF; > + } > + } > + > + mmio_writel(status = mmio_readl(spi_sts), spi_sts); > + > + spi_cs_deactivate(); > + if (delayed_msg) { > + msg_perr("%s\n", delayed_msg); > + } > + > + return retval; > +} > + > +int tegra2_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +{ > + return spi_read_chunked(flash, buf, start, len, > + spi_programmer->max_data_read); > +} > The function above is not needed anymore. > + > +int tegra2_spi_write(struct flashchip *flash, uint8_t *buf, int start, int len) > +{ > + return spi_write_chunked(flash, buf, start, len, > + spi_programmer->max_data_write); > +} > The function above is not needed anymore. > + > +/* Unmap register spaces */ > +int tegra2_spi_shutdown(void *data) > +{ > + physunmap(gpio_base, 4096); > + physunmap(clkrst_base, 4096); > + physunmap(apbmisc_base, 4096); > + physunmap(spi_base - 0x380, 4096); > + return 0; > +} > + > +static const struct spi_programmer spi_programmer_tegra2 = { > + .type = SPI_CONTROLLER_TEGRA2, > + /* FIFO depth is 32, packets can be up to 32-bits in length. */ > + .max_data_read = 128, > + .max_data_write = 128, > + .command = tegra2_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = tegra2_spi_read, > + .write_256 = tegra2_spi_write, > Please change .read and .write_256 to use the generic functions if possible. > +}; > + > +/* Map register spaces */ > +int tegra2_spi_init(void) > +{ > + u32 val; > + uint32_t *spi_cmd; > + uint32_t *spi_sts; > + > + buses_supported = CHIP_BUSTYPE_SPI; > AFAICS setting buses_supported is handled by register_spi_programmer. That said, you may want to set it to CHIP_BUSTYPE_NONE here (the handling of buses_supported for internal is a bit weird for historic reasons). > + register_spi_programmer(&spi_programmer_tegra2); > Way too early, needs to be at the end of the init function. > + > + gpio_base = physmap("GPIO", TEGRA2_GPIO_BASE, 4096); > + clkrst_base = physmap("CLK/RST", NV_ADDRESS_MAP_PPSB_CLK_RST_BASE, > + 4096); > + apbmisc_base = physmap("APB MISC", NV_ADDRESS_MAP_APB_MISC_BASE, 4096); > + /* non-page offset */ > + spi_base = physmap("SPI", TEGRA2_SPI_BASE - 0x380, 4096) + 0x380; > + > + register_shutdown(tegra2_spi_shutdown, NULL); > + > + flashbase = 0; /* FIXME: to make sanity check happy. */ > + > + /* Init variables */ > + spi_cmd = (uint32_t *)spi_base; > + spi_sts = (uint32_t *)(spi_base + 0x04); > + > + /* > + * SPI reset/clocks init - reset SPI, set clocks, release from reset > + */ > + > + /* SWE_SPI1_RST: Hold SPI controller 1 in reset */ > + val = mmio_readl(clkrst_base + 0x08) | 0x800; > + rmmio_writel(val, (clkrst_base + 0x08)); > + msg_pdbg("%s: ClkRst = %08x\n", __func__, val); > + > + /* CLK_ENB_SPI1: Enable clock to SPI 1 Controller */ > + val = mmio_readl(clkrst_base + 0x14) | 0x800; > + rmmio_writel(val, (clkrst_base + 0x14)); > + msg_pdbg("%s: ClkEnable = %08x\n", __func__, val); > + > + /* Change default SPI clock from 12MHz to 6MHz, same as BootROM */ > + val = mmio_readl(clkrst_base + 0x114) | 0x2; > + rmmio_writel(val, (clkrst_base + 0x114)); > + msg_pdbg("%s: ClkSrc = %08x\n", __func__, val); > + > + /* SWE_SPI1_RST: Clear SPI1 reset bit (take it out of reset), > + * use regular mmio_writel (restore callback already registered) */ > + val = mmio_readl(clkrst_base + 0x08) & 0xFFFFF7FF; > + mmio_writel(val, (clkrst_base + 0x08)); > + msg_pdbg("%s: ClkRst final = %08x\n", __func__, val); > + > + /* Clear stale status here */ > + mmio_writel(SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | > + SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF, spi_sts); > + msg_pdbg("%s: STATUS = %08x\n", __func__, mmio_readl(spi_sts)); > + > + /* > + * Use sw-controlled CS, so we can clock in data after ReadID, etc. > + */ > + mmio_writel(mmio_readl(spi_cmd) | SPI_CMD_CS_SOFT, spi_cmd); > + msg_pdbg("%s: COMMAND = %08x\n", __func__, mmio_readl(spi_cmd)); > + > + /* > + * SPI pins on Tegra2 are muxed - change pinmux last due to UART issue > + */ > + val = mmio_readl(apbmisc_base + 0x88) | 0xC0000000; > + rmmio_writel(val, (apbmisc_base + 0x88)); > + msg_pdbg("%s: PinMuxRegC = %08x\n", __func__, val); > + > + /* Set Z_LSPI to non-tristate mode */ > + val = mmio_readl(apbmisc_base + 0x20) & 0xFFFFFFFE; > + rmmio_writel(val, (apbmisc_base + 0x20)); > + msg_pdbg("%s: TriStateReg = %08x\n", __func__, val); > + > + /* delay 100ms so that all chars in buffer (1KB) can be flushed. */ > + programmer_delay(100000); > + > + /* > + * We need to dynamically change the pinmux, shared w/UART RXD/CTS! > + */ > + val = mmio_readl(apbmisc_base + 0x84) | 0x0000000C; /* 3 = SFLASH */ > + rmmio_writel(val, (apbmisc_base + 0x84)); > + msg_pdbg("%s: PinMuxRegB = %08x\n", __func__, val); > + > + /* On Seaboard, MOSI/MISO are shared w/UART. > + * Use GPIO I3 (UART_DISABLE) to tristate UART during SPI activity. > + * Enable UART later (cs_deactivate) so we can use it for U-Boot comms. > + */ > + msg_pdbg("%s: DISABLING UART!\n", __func__); > + tg2_gpio_direction_output(UART_DISABLE_PORT, UART_DISABLE_BIT, 1); > Here is the right place for register_spi_programmer. > + > + return 0; > +} > +#endif > Index: flashrom-tegra2/tegra2_spi.h > =================================================================== > --- /dev/null > +++ flashrom-tegra2/tegra2_spi.h > @@ -0,0 +1,81 @@ > +/* > + * This file is part of the flashrom project. > + * > + * Copyright (C) 2010 NVIDIA Corporation > + * Copyright (C) 2011 Google Inc > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#ifndef __TEGRA2_SPI_H__ > +#define __TEGRA2_SPI_H__ > + > +// *************************************************************************** > +// Hardware BARs > + > +#define TEGRA2_GPIO_BASE 0x6000D000 > +#define TEGRA2_SPI_BASE 0x7000C380 > +#define NV_ADDRESS_MAP_PPSB_CLK_RST_BASE 0x60006000 > +#define NV_ADDRESS_MAP_APB_MISC_BASE 0x70000000 > + > +// *************************************************************************** > +// Clock/reset controller > +#define CLK_RST_ENB_H_0_OFFSET 0x14 > +#define CLK_RST_ENB_H_0_SPI1 (1 << 11) > + > +// *************************************************************************** > +// GPIO controller > + > +#define GPIO_OFF(port) (((port / 4) * 128) + ((port % 4) * 4)) > +#define GPIO_CNF(port) (gpio_base + GPIO_OFF(port) + 0x00) > +#define GPIO_OE(port) (gpio_base + GPIO_OFF(port) + 0x10) > +#define GPIO_OUT(port) (gpio_base + GPIO_OFF(port) + 0x20) > +#define GPIO_IN(port) (gpio_base + GPIO_OFF(port) + 0x30) > +#define GPIO_INT_STA(port) (gpio_base + GPIO_OFF(port) + 0x40) > +#define GPIO_INT_ENB(port) (gpio_base + GPIO_OFF(port) + 0x50) > +#define GPIO_INT_LVL(port) (gpio_base + GPIO_OFF(port) + 0x60) > +#define GPIO_INT_CLR(port) (gpio_base + GPIO_OFF(port) + 0x70) > + > +#define SPI_CMD_GO (1 << 30) > +#define SPI_CMD_ACTIVE_SCLK (1 << 26) > +#define SPI_CMD_CK_SDA (1 << 21) > +#define SPI_CMD_ACTIVE_SDA (1 << 18) > +#define SPI_CMD_CS_POL (1 << 16) > +#define SPI_CMD_TXEN (1 << 15) > +#define SPI_CMD_RXEN (1 << 14) > +#define SPI_CMD_CS_VAL (1 << 13) > +#define SPI_CMD_CS_SOFT (1 << 12) > +#define SPI_CMD_CS_DELAY (1 << 9) > +#define SPI_CMD_CS3_EN (1 << 8) > +#define SPI_CMD_CS2_EN (1 << 7) > +#define SPI_CMD_CS1_EN (1 << 6) > +#define SPI_CMD_CS0_EN (1 << 5) > +#define SPI_CMD_BIT_LENGTH (1 << 4) > +#define SPI_CMD_BIT_LENGTH_MASK 0x0000001F > + > +#define SPI_STAT_BSY (1 << 31) > +#define SPI_STAT_RDY (1 << 30) > +#define SPI_STAT_RXF_FLUSH (1 << 29) > +#define SPI_STAT_TXF_FLUSH (1 << 28) > +#define SPI_STAT_RXF_UNR (1 << 27) > +#define SPI_STAT_TXF_OVF (1 << 26) > +#define SPI_STAT_RXF_EMPTY (1 << 25) > +#define SPI_STAT_RXF_FULL (1 << 24) > +#define SPI_STAT_TXF_EMPTY (1 << 23) > +#define SPI_STAT_TXF_FULL (1 << 22) > +#define SPI_STAT_SEL_TXRX_N (1 << 16) > +#define SPI_STAT_CUR_BLKCNT (1 << 15) > + > +#endif /* __TEGRA2_SPI_H__ */ > Index: flashrom-tegra2/Makefile > =================================================================== > --- flashrom-tegra2.orig/Makefile > +++ flashrom-tegra2/Makefile > @@ -310,6 +310,10 @@ PROGRAMMER_OBJS += processor_enable.o ch > ifeq ($(ARCH),"x86") > PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o > else > +ifeq ($(ARCH),"arm") > +PROGRAMMER_OBJS += tegra2_spi.o > +else > +endif > endif > NEED_PCI := yes > endif > My overall impression of the Tegra2 SPI driver is that the hardware is some weird bitbanging/bytewise combination and nobody is sure how to deal with it. Please note that this is still not a complete review, but it will allow to get the patch closer to a mergeable state. Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

[commit] r1367 - trunk
by repository service 07 Jul '11

07 Jul '11

Author: stefanct Date: Thu Jul 7 21:56:58 2011 New Revision: 1367 URL: http://flashrom.org/trac/flashrom/changeset/1367 Log: add a bunch of new/tested stuff and various small changes 4 - add Asus E35M1-I DELUXE to boards_known http://www.flashrom.org/pipermail/flashrom/2011-June/006918.html - add Asus M3A to boards_known http://www.flashrom.org/pipermail/flashrom/2011-July/007085.html - add Freetech P6F91i to boards_known http://www.flashrom.org/pipermail/flashrom/2011-June/006800.html - add GA-M720-US3 to boards_known http://www.flashrom.org/pipermail/flashrom/2011-July/007096.html - add GA-MA770-UD3 (rev. 2.1) to boards_known http://www.flashrom.org/pipermail/flashrom/2011-June/006879.html - add GA-965GM-S2 to boards_known http://www.flashrom.org/pipermail/flashrom/2011-June/006746.html - add HP xw4400 (0A68h) to boards_known http://paste.flashrom.org/view.php?id=686 - add MSI MS-6566 (845 Ultra-C) to boards_known http://www.flashrom.org/pipermail/flashrom/2011-June/006908.html - add MSI MS-7698 (E350IA-E45) to boards_known http://www.flashrom.org/pipermail/flashrom/2011-June/007003.html - add PCCHIPS M863G (V5.1A) to boards_known http://www.flashrom.org/pipermail/flashrom/2011-July/007084.html - modify the X8SIE entry in boards_known with the information from "fuzzy" http://paste.flashrom.org/view.php?id=669 - mark W29C020(C)/W29C022 as fully tested http://www.flashrom.org/pipermail/flashrom/2011-June/006800.html - mark W49V002A as fully tested http://www.flashrom.org/pipermail/flashrom/2011-July/007084.html - mark M25P128 as fully tested http://www.flashrom.org/pipermail/flashrom/2011-June/006843.html - mark SST39SF010A as fully tested http://www.flashrom.org/pipermail/flashrom/2011-July/007115.html - correct entries for GA-K8NS Pro-939 (was ultra before. thanks uwe!) - another tiny fix for "a small fix"/r1321 Without this you will get broken bus names "Unknow" and "Non-SP". Note to self: don't self-ack even fairly trivial patches. - fix spew output of spi_rems in spi25.c - add URL to ASUS M3A76-CM - rename all Winbond W25x chips to W25X - fixes some common misspellings/typos in comments: lenght->length 2 ocassional->occasional 1 unsucessfull->unsuccessful 1 upto->up to 5 the patch for M25P128 is Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan(a)gmail.com> the typos are Signed-off-by: Peter Huewe <peterhuewe(a)gmx.de> everything else is Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/buspirate_spi.c trunk/dmi.c trunk/flashchips.c trunk/print.c trunk/serprog-protocol.txt trunk/serprog.c trunk/spi25.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Thu Jul 7 08:59:18 2011 (r1366) +++ trunk/board_enable.c Thu Jul 7 21:56:58 2011 (r1367) @@ -986,7 +986,7 @@ /* * Suited for: - * - Gigabyte GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8 + * - GIGABYTE GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8 */ static int nvidia_mcp_gpio0a_raise(void) { Modified: trunk/buspirate_spi.c ============================================================================== --- trunk/buspirate_spi.c Thu Jul 7 08:59:18 2011 (r1366) +++ trunk/buspirate_spi.c Thu Jul 7 21:56:58 2011 (r1367) @@ -203,7 +203,7 @@ * sufficient either. Use a 1.5 ms delay inside the loop to make * mostly sure that at least one USB frame had time to arrive. * Looping only 5 times is not sufficient and causes the - * ocassional failure. + * occasional failure. * Folding the delay into the loop above is not reliable either. */ for (i = 0; i < 10; i++) { Modified: trunk/dmi.c ============================================================================== --- trunk/dmi.c Thu Jul 7 08:59:18 2011 (r1366) +++ trunk/dmi.c Thu Jul 7 21:56:58 2011 (r1367) @@ -119,7 +119,7 @@ while (!feof(dmidecode_pipe)) getc(dmidecode_pipe); if (pclose(dmidecode_pipe) != 0) { - msg_pinfo("dmidecode execution unsucessfull - continuing " + msg_pinfo("dmidecode execution unsuccessful - continuing " "without DMI info\n"); return NULL; } Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Thu Jul 7 08:59:18 2011 (r1366) +++ trunk/flashchips.c Thu Jul 7 21:56:58 2011 (r1367) @@ -5771,7 +5771,7 @@ .total_size = 128, .page_size = 4096, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, /* 150 ns */ .block_erasers = @@ -6705,7 +6705,7 @@ .model_id = ST_M25P128, .total_size = 16384, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -7776,7 +7776,7 @@ { .vendor = "Winbond", - .name = "W25x10", + .name = "W25X10", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = WINBOND_NEX_ID, .model_id = WINBOND_NEX_W25X10, @@ -7807,7 +7807,7 @@ { .vendor = "Winbond", - .name = "W25x20", + .name = "W25X20", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = WINBOND_NEX_ID, .model_id = WINBOND_NEX_W25X20, @@ -7838,7 +7838,7 @@ { .vendor = "Winbond", - .name = "W25x40", + .name = "W25X40", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = WINBOND_NEX_ID, .model_id = WINBOND_NEX_W25X40, @@ -7869,7 +7869,7 @@ { .vendor = "Winbond", - .name = "W25x80", + .name = "W25X80", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = WINBOND_NEX_ID, .model_id = WINBOND_NEX_W25X80, @@ -7900,7 +7900,7 @@ { .vendor = "Winbond", - .name = "W25x16", + .name = "W25X16", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = WINBOND_NEX_ID, .model_id = WINBOND_NEX_W25X16, @@ -7937,7 +7937,7 @@ { .vendor = "Winbond", - .name = "W25x32", + .name = "W25X32", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = WINBOND_NEX_ID, .model_id = WINBOND_NEX_W25X32, @@ -7974,7 +7974,7 @@ { .vendor = "Winbond", - .name = "W25x64", + .name = "W25X64", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = WINBOND_NEX_ID, .model_id = WINBOND_NEX_W25X64, @@ -8041,9 +8041,9 @@ .total_size = 256, .page_size = 128, .feature_bits = FEATURE_LONG_RESET, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, - .probe_timing = 10, + .probe_timing = 10, .block_erasers = { { @@ -8397,9 +8397,9 @@ .total_size = 256, .page_size = 128, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, - .probe_timing = 10, + .probe_timing = 10, .block_erasers = { { Modified: trunk/print.c ============================================================================== --- trunk/print.c Thu Jul 7 08:59:18 2011 (r1366) +++ trunk/print.c Thu Jul 7 21:56:58 2011 (r1367) @@ -34,13 +34,13 @@ { char *ret = calloc(1, 1); if (bustype == CHIP_BUSTYPE_UNKNOWN) { - ret = strcat_realloc(ret, "Unknown,"); + ret = strcat_realloc(ret, "Unknown, "); /* * FIXME: Once all chipsets and flash chips have been updated, NONSPI * will cease to exist and should be eliminated here as well. */ } else if (bustype == CHIP_BUSTYPE_NONSPI) { - ret = strcat_realloc(ret, "Non-SPI,"); + ret = strcat_realloc(ret, "Non-SPI, "); } else { if (bustype & CHIP_BUSTYPE_PARALLEL) ret = strcat_realloc(ret, "Parallel, "); @@ -431,6 +431,7 @@ B("ASUS", "A8V Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=tvpdgPNCPaABZRVU", NULL), B("ASUS", "A8V-E Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=hQBPIJWEZnnGAZEh", NULL), B("ASUS", "A8V-E SE", 1, "http://www.asus.com/product.aspx?P_ID=VMfiJJRYTHM4gXIi", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html"), + B("ASUS", "E35M1-I DELUXE", 1, "http://www.asus.com/product.aspx?P_ID=9BmKhMwWCwqyl1lz", NULL), B("ASUS", "K8V", 1, "http://www.asus.com/product.aspx?P_ID=fG2KZOWF7v6MRFRm", NULL), B("ASUS", "K8V SE Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=65HeDI8XM1u6Uy6o", NULL), B("ASUS", "K8V-X SE", 1, "http://www.asus.com/product.aspx?P_ID=lzDXlbBVHkdckHVr", NULL), @@ -443,7 +444,8 @@ B("ASUS", "M2NPV-VM", 1, "http://www.asus.com/product.aspx?P_ID=HGTVnGv5nGahCYgK", NULL), B("ASUS", "M2V", 1, "http://www.asus.com/product.aspx?P_ID=OqYlEDFfF6ZqZGvp", NULL), B("ASUS", "M2V-MX", 1, "http://www.asus.com/product.aspx?P_ID=7grf8Ci4yxnqzt3z", NULL), - B("ASUS", "M3A76-CM", 1, NULL, NULL), + B("ASUS", "M3A", 1, "http://www.asus.com/product.aspx?P_ID=P48rppKk4jrc9pNd", NULL), + B("ASUS", "M3A76-CM", 1, "http://www.asus.com/product.aspx?P_ID=aU8effdifLvraVze", NULL), B("ASUS", "M3A78-EM", 1, "http://www.asus.com/product.aspx?P_ID=KjpYqzmAd9vsTM2D", NULL), B("ASUS", "M4A78-EM", 1, "http://www.asus.com/product.aspx?P_ID=0KyowHKUFAQqH2DO", NULL), B("ASUS", "M4A785TD-M EVO", 1, "http://www.asus.com/product.aspx?P_ID=QHbvGVB1mXmmD8qQ", NULL), @@ -514,6 +516,7 @@ B("FIC", "VA-502", 0, "ftp://ftp.fic.com.tw/motherboard/manual/socket7/va-502/", "No public report found. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>. Seems the PCI subsystem IDs are identical with the Tekram P6Pro-A5. May work now."), B("Foxconn", "6150K8MD-8EKRSH", 1, "http://www.foxconnchannel.com/product/motherboards/detail_overview.aspx?id=…", NULL), B("Foxconn", "A6VMX", 1, "http://www.foxconnchannel.com/product/motherboards/detail_overview.aspx?id=…", NULL), + B("Freetech", "P6F91i", 1, "http://web.archive.org/web/20010417035034/http://www.freetech.com/prod/P6F9…", NULL), B("Fujitsu-Siemens", "ESPRIMO P5915", 1, "http://uk.ts.fujitsu.com/rl/servicesupport/techsupport/professionalpc/ESPRI…", "Mainboard model is D2312-A2."), B("GIGABYTE", "GA-2761GXDK", 1, "http://www.computerbase.de/news/hardware/mainboards/amd-systeme/2007/mai/gi…", NULL), B("GIGABYTE", "GA-6BXC", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1445", NULL), @@ -529,17 +532,20 @@ B("GIGABYTE", "GA-8IP775", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1830", NULL), B("GIGABYTE", "GA-8IRML", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1343", NULL), B("GIGABYTE", "GA-8PE667 Ultra 2", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1607", NULL), + B("GIGABYTE", "GA-965GM-S2 (rev. 2.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2617", NULL), B("GIGABYTE", "GA-965P-DS4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2288", NULL), B("GIGABYTE", "GA-EP35-DS3L", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2778", NULL), B("GIGABYTE", "GA-EX58-UD4P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2986", NULL), B("GIGABYTE", "GA-K8N-SLI", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1928", NULL), B("GIGABYTE", "GA-K8N51GMF", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1950", NULL), B("GIGABYTE", "GA-K8N51GMF-9", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1939", NULL), - B("GIGABYTE", "GA-K8NS Ultra-939", 0, "http://www.gigabyte.com/products/product-page.aspx?pid=1839", "Untested board enable."), + B("GIGABYTE", "GA-K8NS Pro-939", 0, "http://www.gigabyte.com/products/product-page.aspx?pid=1875", "Untested board enable."), B("GIGABYTE", "GA-M57SLI-S4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2287", NULL), B("GIGABYTE", "GA-M61P-S3", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2434", NULL), + B("GIGABYTE", "GA-M720-US3", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3006", NULL), B("GIGABYTE", "GA-MA69VM-S2", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2500", NULL), B("GIGABYTE", "GA-MA74GM-S2H (rev. 3.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3152", NULL), + B("GIGABYTE", "GA-MA770-UD3 (rev. 2.1)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3302", NULL), B("GIGABYTE", "GA-MA770T-UD3P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3096", NULL), B("GIGABYTE", "GA-MA780G-UD3H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3004", NULL), B("GIGABYTE", "GA-MA78G-DS3H (rev. 1.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2800", NULL), @@ -555,7 +561,8 @@ B("HP", "Puffer2-UL8E", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00300023", NULL), B("HP", "Vectra VL400", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c000…", NULL), B("HP", "Vectra VL420 SFF", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c000…", NULL), - B("HP", "xw9400", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?lang=en&cc=us&pro…", "Boot block is write protected unless the solder points next to F2 are shorted." ), + B("HP", "xw4400 (0A68h)", 0, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c007…", "ICH7 with SPI lock down, BIOS lock, flash block detection (SST25VF080B); see http://paste.flashrom.org/view.php?id=686"), + B("HP", "xw9400", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?lang=en&cc=us&pro…", "Boot block is write protected unless the solder points next to F2 are shorted."), B("IBASE", "MB899", 1, "http://www.ibase-i.com.tw/2009/mb899.html", NULL), B("IBM", "x3455", 1, "http://www-03.ibm.com/systems/x/hardware/rack/x3455/index.html", NULL), B("IEI", "PICOe-9452", 1, "http://www.ieiworld.com/product_groups/industrial/content.aspx?keyword=WSB&…", NULL), @@ -578,6 +585,7 @@ B("MSI", "MS-6330 (K7T Turbo)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=327", NULL), B("MSI", "MS-6391 (845 Pro4)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=293", NULL), B("MSI", "MS-6561 (745 Ultra)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=274", NULL), + B("MSI", "MS-6566 (845 Ultra-C)",1, "http://www.msi.com/product/mb/845-Ultra-C.html", NULL), B("MSI", "MS-6570 (K7N2)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=519", NULL), B("MSI", "MS-6577 (Xenon)", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?product=90390&lc=en&cc=us&dlc=e…", "This is an OEM board from HP, the HP name is Xenon."), B("MSI", "MS-6590 (KT4 Ultra)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=502", NULL), @@ -607,8 +615,10 @@ B("MSI", "MS-7599 (870-C45)", 1, "http://www.msi.com/product/mb/870-C45.html", NULL), B("MSI", "MS-7640 (890FXA-GD70)",1, "http://www.msi.com/product/mb/890FXA-GD70.html", "Reported by \"Linux User #330250\" http://flashrom.org/pipermail/flashrom/2011-March/006072.html"), B("MSI", "MS-7642 (890GXM-G65)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=2012", NULL), + B("MSI", "MS-7698 (E350IA-E45)", 1, "http://www.msi.com/product/mb/E350IA-E45.html", NULL), B("NEC", "PowerMate 2000", 1, "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/", NULL), B("Nokia", "IP530", 1, NULL, NULL), + B("PCCHIPS ", "M863G (V5.1A)", 1, "http://www.pcchips.com.tw/PCCWebSite/Products/ProductsDetail.aspx?CategoryI…", NULL), B("PC Engines", "Alix.1c", 1, "http://pcengines.ch/alix1c.htm", NULL), B("PC Engines", "Alix.2c2", 1, "http://pcengines.ch/alix2c2.htm", NULL), B("PC Engines", "Alix.2c3", 1, "http://pcengines.ch/alix2c3.htm", NULL), @@ -639,7 +649,7 @@ B("Supermicro", "X8DTH-6F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTH-6F.cfm", NULL), B("Supermicro", "X8DTT-F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTT-F.cfm", NULL), B("Supermicro", "X8DTU-F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTU-F.cfm", NULL), - B("Supermicro", "X8SIE", 0, "http://www.supermicro.com/products/motherboard/Xeon3000/3400/X8SIE.cfm?IPMI…", "Does not work with 0.9.2; see http://www.flashrom.org/pipermail/flashrom/2011-May/006554.html May work now, but please consult us before trying."), + B("Supermicro", "X8SIE(-F)", 0, "http://www.supermicro.com/products/motherboard/Xeon3000/3400/X8SIE.cfm?IPMI…", "Requires unlocking the ME although the registers are set up correctly by the descriptor/BIOS already (tested with swseq and hwseq)."), B("Supermicro", "X8STi", 1, "http://www.supermicro.com/products/motherboard/Xeon3000/X58/X8STi.cfm", NULL), B("T-Online", "S-100", 1, "http://wiki.freifunk-hannover.de/T-Online_S_100", NULL), B("Tekram", "P6Pro-A5", 1, "http://www.motherboard.cz/mb/tekram/P6Pro-A5.htm", NULL), Modified: trunk/serprog-protocol.txt ============================================================================== --- trunk/serprog-protocol.txt Thu Jul 7 08:59:18 2011 (r1366) +++ trunk/serprog-protocol.txt Thu Jul 7 21:56:58 2011 (r1367) @@ -88,7 +88,7 @@ #define S_CMD_Q_BUSTYPE 0x05 /* Query supported bustypes */ #define S_CMD_Q_CHIPSIZE 0x06 /* Query supported chipsize (2^n format) */ #define S_CMD_Q_OPBUF 0x07 /* Query operation buffer size */ -#define S_CMD_Q_WRNMAXLEN 0x08 /* Query Write to opbuf: Write-N maximum lenght */ +#define S_CMD_Q_WRNMAXLEN 0x08 /* Query Write to opbuf: Write-N maximum length */ #define S_CMD_R_BYTE 0x09 /* Read a single byte */ #define S_CMD_R_NBYTES 0x0A /* Read n bytes */ #define S_CMD_O_INIT 0x0B /* Initialize operation buffer */ Modified: trunk/serprog.c ============================================================================== --- trunk/serprog.c Thu Jul 7 08:59:18 2011 (r1366) +++ trunk/serprog.c Thu Jul 7 21:56:58 2011 (r1367) @@ -56,7 +56,7 @@ #define S_CMD_Q_BUSTYPE 0x05 /* Query supported bustypes */ #define S_CMD_Q_CHIPSIZE 0x06 /* Query supported chipsize (2^n format) */ #define S_CMD_Q_OPBUF 0x07 /* Query operation buffer size */ -#define S_CMD_Q_WRNMAXLEN 0x08 /* Query opbuf-write-N maximum lenght */ +#define S_CMD_Q_WRNMAXLEN 0x08 /* Query opbuf-write-N maximum length */ #define S_CMD_R_BYTE 0x09 /* Read a single byte */ #define S_CMD_R_NBYTES 0x0A /* Read n bytes */ #define S_CMD_O_INIT 0x0B /* Initialize operation buffer */ @@ -168,10 +168,10 @@ usleep(1000 * 1000); sp_flush_incoming(); - /* Then try upto 8 times to send syncnop and get the correct special * - * return of NAK+ACK. Timing note: upto 10 characters, 10*50ms = * - * upto 500ms per try, 8*0.5s = 4s; +1s (above) = upto 5s sync * - * attempt, ~1s if immediate success. */ + /* Then try up to 8 times to send syncnop and get the correct special * + * return of NAK+ACK. Timing note: up to 10 characters, 10*50ms = * + * up to 500ms per try, 8*0.5s = 4s; +1s (above) = up to 5s sync * + * attempt, ~1s if immediate success. */ for (i = 0; i < 8; i++) { int n; unsigned char c = S_CMD_SYNCNOP; @@ -180,7 +180,7 @@ msg_pdbg("."); fflush(stdout); for (n = 0; n < 10; n++) { - c = sp_sync_read_timeout(5); /* wait upto 50ms */ + c = sp_sync_read_timeout(5); /* wait up to 50ms */ if (c != S_NAK) continue; c = sp_sync_read_timeout(2); Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Thu Jul 7 08:59:18 2011 (r1366) +++ trunk/spi25.c Thu Jul 7 21:56:58 2011 (r1367) @@ -62,7 +62,7 @@ } if (ret) return ret; - msg_cspew("REMS returned %02x %02x. ", readarr[0], readarr[1]); + msg_cspew("REMS returned 0x%02x 0x%02x. ", readarr[0], readarr[1]); return 0; }

1 0

selective probing?
by Bernd Blaauw 07 Jul '11

07 Jul '11

Whenever I read the verbose logs I see *all* chips being probed, which is pretty fast already. Is there any point to "optimise"(?) this amount to "per size" ? Possibly followed by per-method? For example if I'd want to write a 8Mbit BIOS file, only scan for 1024KB eeproms (determine (uncompressed) BIOS file's filesize). Reading/erasing is more difficult ofcourse, or not worthwile, requiring you be able to enter a size parameter. So from: * alphabetical name for EEPROM * various sizes * various scan methods To: * filesize * scan method 1 * results in some EEPROMS * scan method 2 * results in other EEPROMS -- etc (this assumes 1 EEPROM only found through 1 method, or 1st method used, whatever). Probably not worthwile, though it would reduce the verbose log by 75% Maybe also mirror the user's entered commandline in the log (minus the prompt/directory) to allow more eyes to check user's input

3 2

Re: [flashrom] [PATCH] Autodetect target processor architecture
by Carl-Daniel Hailfinger 07 Jul '11

07 Jul '11

Am 07.07.2011 02:05 schrieb David Hendricks: > The latest revision fixed the issue seen on IRC where the ARCH string might > get duplicated. > > I tested it on both x86 and ARM (using the tegra2 patches) and it worked, > so: > Acked-by: David Hendricks <dhendrix(a)google.com> > Thanks for the review and the tests. Committed in r1366. Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

[commit] r1366 - trunk
by repository service 07 Jul '11

07 Jul '11

Author: hailfinger Date: Thu Jul 7 08:59:18 2011 New Revision: 1366 URL: http://flashrom.org/trac/flashrom/changeset/1366 Log: Autodetect target processor architecture. Enable architecture dependent compilation of individual sub-drivers for the internal programmer. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: David Hendricks <dhendrix(a)google.com> Added: trunk/arch.h Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Thu Jul 7 06:10:57 2011 (r1365) +++ trunk/Makefile Thu Jul 7 08:59:18 2011 (r1366) @@ -37,7 +37,10 @@ CFLAGS += -Werror endif -# FIXME We have to differentiate between host and target arch. +# Determine the destination processor architecture +override ARCH = $(strip $(shell LC_ALL=C $(CC) -E arch.h|grep -v '^\#')) + +# FIXME We have to differentiate between host and target OS architecture. OS_ARCH ?= $(shell uname) ifneq ($(OS_ARCH), SunOS) STRIP_ARGS = -s @@ -304,8 +307,10 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o -# FIXME: The PROGRAMMER_OBJS below should only be included on x86. +ifeq ($(ARCH),"x86") PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +else +endif NEED_PCI := yes endif @@ -500,6 +505,11 @@ echo "found." || ( echo "not found."; \ rm -f .test.c .test$(EXEC_SUFFIX); exit 1) @rm -f .test.c .test$(EXEC_SUFFIX) + @printf "ARCH is " + @# FreeBSD wc will output extraneous whitespace. + @echo $(ARCH)|wc -l|grep -q '^[[:blank:]]*1[[:blank:]]*$$' || \ + ( echo "unknown. Aborting."; exit 1) + @printf "%s\n" '$(ARCH)' ifeq ($(CHECK_LIBPCI), yes) pciutils: compiler Added: trunk/arch.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/arch.h Thu Jul 7 08:59:18 2011 (r1366) @@ -0,0 +1,31 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2011 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Header file for CPU architecture checking. + */ + +#if defined (__i386__) || defined (__x86_64__) +#define __FLASHROM_ARCH__ "x86" +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) +#define __FLASHROM_ARCH__ "mips" +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) +#define __FLASHROM_ARCH__ "ppc" +#endif +__FLASHROM_ARCH__

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Success erasing and writing a SST39SF010A with a Silicon Image 3124 card
by Tim Small 07 Jul '11

07 Jul '11

Erase: flashrom v0.9.3-r1364 on Linux 2.6.39-2-amd64 (x86_64), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 2496M loops per second, 10 myus = 10 us, 100 myus = 110 us, 1000 myus = 1011 us, 10000 myus = 10015 us, 4 myus = 6 us, OK. Initializing satasii programmer Found "Silicon Image SiI 3124 PCI-X SATA Ctrl" (1095:3124, BDF 05:00.0). Requested BAR is MEM, 64bit, not prefetchable Mapping SATA SIL registers at 0xf7fff000, unaligned size 0x100. Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BB, 1024 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BT, 1024 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002B, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C512, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT29C010A, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT29C020, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT29C040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT49BV512, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT49F020, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT49F002(N), 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT49F002(N)T, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Bright BM29F040, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for EMST F49B002UA, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Eon EN29F010, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 kB: probe_m29f400bt: id1 0x55, id2 0x78 Probing for Fujitsu MBM29F400TC, 512 kB: probe_m29f400bt: id1 0x55, id2 0x78 Probing for Hyundai HY29F002T, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Hyundai HY29F002B, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Hyundai HY29F040A, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Intel 28F001BN/BX-T, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: probe_82802ab: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 kB: probe_82802ab: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: probe_82802ab: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: probe_82802ab: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: probe_82802ab: id1 0x55, id2 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: probe_82802ab: id1 0x55, id2 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001B, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002B, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002T, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29C51000T, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29C51400B, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29C51400T, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29LC51000, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29LC51001, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29LC51002, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for PMC Pm29F002T, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST28SF040A, 512 kB: probe_82802ab: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST29LE010, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST29EE020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST29LE020, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39SF512, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39SF010A, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Found chip "SST SST39SF010A" (128 kB, Parallel) on satasii. Probing for SST SST39SF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39SF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39VF512, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39VF010, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39VF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39VF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39VF080, 1024 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for ST M29F002B, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 kB: probe_m29f400bt: id1 0x55, id2 0x78 Probing for ST M29F400BT, 512 kB: probe_m29f400bt: id1 0x55, id2 0x78 Probing for ST M29W010B, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for TI TMS29F002RB, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Winbond W29C040/P, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39L040, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Winbond W49F002U/N, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Winbond W49F020, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 === This flash part has status UNTESTED for operations: ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Erasing and writing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x000fff:E, 0x001000-0x001fff:E, 0x002000-0x002fff:E, 0x003000-0x003fff:E, 0x004000-0x004fff:E, 0x005000-0x005fff:E, 0x006000-0x006fff:E, 0x007000-0x007fff:E, 0x008000-0x008fff:E, 0x009000-0x009fff:E, 0x00a000-0x00afff:E, 0x00b000-0x00bfff:E, 0x00c000-0x00cfff:E, 0x00d000-0x00dfff:E, 0x00e000-0x00efff:E, 0x00f000-0x00ffff:E, 0x010000-0x010fff:E, 0x011000-0x011fff:E, 0x012000-0x012fff:E, 0x013000-0x013fff:E, 0x014000-0x014fff:E, 0x015000-0x015fff:E, 0x016000-0x016fff:E, 0x017000-0x017fff:E, 0x018000-0x018fff:E, 0x019000-0x019fff:E, 0x01a000-0x01afff:E, 0x01b000-0x01bfff:E, 0x01c000-0x01cfff:E, 0x01d000-0x01dfff:E, 0x01e000-0x01efff:E, 0x01f000-0x01ffff:E Done. Write: flashrom v0.9.3-r1364 on Linux 2.6.39-2-amd64 (x86_64), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 2496M loops per second, 10 myus = 10 us, 100 myus = 116 us, 1000 myus = 1012 us, 10000 myus = 10018 us, 4 myus = 5 us, OK. Initializing satasii programmer Found "Silicon Image SiI 3124 PCI-X SATA Ctrl" (1095:3124, BDF 05:00.0). Requested BAR is MEM, 64bit, not prefetchable Mapping SATA SIL registers at 0xf7fff000, unaligned size 0x100. Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BB, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BT, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C512, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT29C010A, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT29C020, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT29C040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT49BV512, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT49F020, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT49F002(N), 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT49F002(N)T, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Bright BM29F040, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for EMST F49B002UA, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Eon EN29F010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Fujitsu MBM29F400TC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Hyundai HY29F002T, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Hyundai HY29F002B, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Hyundai HY29F040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Intel 28F001BN/BX-T, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29C51000T, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29C51400B, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29C51400T, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29LC51000, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29LC51001, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29LC51002, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for PMC Pm29F002T, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST28SF040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST29LE010, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST29EE020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST29LE020, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39SF512, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39SF010A, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Found chip "SST SST39SF010A" (128 kB, Parallel) on satasii. Probing for SST SST39SF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39SF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39VF512, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39VF010, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39VF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39VF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39VF080, 1024 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for ST M29F002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29F400BT, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29W010B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for TI TMS29F002RB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Winbond W29C040/P, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39L040, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Winbond W49F002U/N, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Winbond W49F020, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 === This flash part has status UNTESTED for operations: ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Reading old flash chip contents... done. Erasing and writing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x000fff:W, 0x001000-0x001fff:W, 0x002000-0x002fff:W, 0x003000-0x003fff:W, 0x004000-0x004fff:W, 0x005000-0x005fff:W, 0x006000-0x006fff:W, 0x007000-0x007fff:W, 0x008000-0x008fff:W, 0x009000-0x009fff:W, 0x00a000-0x00afff:W, 0x00b000-0x00bfff:W, 0x00c000-0x00cfff:W, 0x00d000-0x00dfff:W, 0x00e000-0x00efff:W, 0x00f000-0x00ffff:W, 0x010000-0x010fff:S, 0x011000-0x011fff:S, 0x012000-0x012fff:S, 0x013000-0x013fff:S, 0x014000-0x014fff:S, 0x015000-0x015fff:S, 0x016000-0x016fff:S, 0x017000-0x017fff:S, 0x018000-0x018fff:S, 0x019000-0x019fff:S, 0x01a000-0x01afff:S, 0x01b000-0x01bfff:S, 0x01c000-0x01cfff:S, 0x01d000-0x01dfff:S, 0x01e000-0x01efff:S, 0x01f000-0x01ffff:W Done. Verifying flash... VERIFIED.

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Re: [flashrom] [PATCH 4/8] ichspi.c: preserve reserved bits in address registers
by Stefan Tauner 07 Jul '11

07 Jul '11

On Wed, 6 Jul 2011 20:51:06 -0700 David Hendricks <dhendrix(a)google.com> wrote: > On Thu, Jun 30, 2011 at 5:52 PM, Stefan Tauner < > stefan.tauner(a)student.tuwien.ac.at> wrote: > > > On Fri, 01 Jul 2011 01:21:33 +0200 > > Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> wrote: > > > > > Am 28.06.2011 05:33 schrieb Stefan Tauner: > > > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > > > > > > > > > > Makes sense, but I worry that this might eventually break something. Do > > > we (want to) report the inital address setting during programmer init, > > > especially the reserved bits? > > > > we do the usual register dumping for SPIA on ICH7 and VIA, but > > we dont print the equivalent FADDR in the ICH9 branch. patch appended. > > > Acked-by: David Hendricks <dhendrix(a)google.com> > thanks, r1365 -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1365 - trunk
by repository service 07 Jul '11

07 Jul '11

Author: stefanct Date: Thu Jul 7 06:10:57 2011 New Revision: 1365 URL: http://flashrom.org/trac/flashrom/changeset/1365 Log: ichspi.c: print FADDR in ich_init_spi We print the address registers for ICH7 and VIA at init. We should do so for ICH9 too. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: David Hendricks <dhendrix(a)google.com> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Mon Jul 4 09:27:17 2011 (r1364) +++ trunk/ichspi.c Thu Jul 7 06:10:57 2011 (r1365) @@ -1288,6 +1288,8 @@ msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); prettyprint_ich9_reg_hsfc(tmp2); + tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR); + msg_pdbg("0x08: 0x%08x (FADDR)\n", tmp); tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp));

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Re: [flashrom] [PATCH 4/8] ichspi.c: preserve reserved bits in address registers
by Carl-Daniel Hailfinger 07 Jul '11

07 Jul '11

Am 28.06.2011 05:33 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Makes sense, but I worry that this might eventually break something. Do we (want to) report the inital address setting during programmer init, especially the reserved bits? Anyway, this is Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [Patch] NVIDIA Tegra2 SPI controller support
by Carl-Daniel Hailfinger 07 Jul '11

07 Jul '11

Am 28.06.2011 01:52 schrieb David Hendricks: > This patch set makes Flashrom a bit more ARM-friendly and adds raw Tegra2 > SPI controller support. It isolates a few PCI-isms, adds some low-level > hardware access stubs, adds Tegra2 processor detection, and adds Tegra2 raw > SPI controller code. > Nice! > I've attached some logfiles for read/erase/write operations. This particular > patch set was tested using a board based off NVIDIA's Tegra2 reference board > ("Seaboard"). Earlier revisions were tested on a Seaboard. > > All three attached patches are: > Signed-off-by: David Hendricks <dhendrix(a)google.com> > > Much of the original U-Boot --> Flashrom porting work was done by Stefan > Reinauer <reinauer(a)google.com>, and the FIFO code updated / fixed up by > Louis Lo <yjlou(a)google.com>. > > A few notes: > 1. A few programmers must be disabled due to reliance on PCI. You can hack > up your Makefile or compile with "CONFIG_RAYER_SPI=no CONFIG_NIC3COM=no > CONFIG_NICREALTEK=no CONFIG_SATAMV=no". > Actually, it is a requirement for PCI port I/O space (well, the non-memmapped space specified in the PCI standard, usually accesses with in[bwl]/out[bwl] functions). We ought to detect unavailability of that at compile time, preferably in the Makefile. > 2. Due to issues with libpci, you can't use the same binary on machines with > PCI and without PCI. So for example, you can't program a SPI ROM onboard a > PCI card that is connected to your ARM SoC. > Could you explain more? IIRC some people were using flashrom on ARM (independent patch) with PCI support. Not calling any PCI functions should be enough to avoid any and all interactions between libpci and the hardware. > 4. The tegra2_spi code was originally contributed by NVIDIA to the Chromium > OS U-Boot<http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=blob;…> > branch > and was later grafted into Flashrom so we could more easily perform SPI ROM > updates from userspace. Please excuse minor style inconsistencies as we are > trying to stay reasonably close to the code checked into the U-Boot tree ;-) > Ah, that explains some of the quirks I saw. Could you explain the Tegra2 hardware a bit more? The code suggests that it is more or less a slightly intelligent bitbanging controller with a "special" programing interface. At a first glance, the following issues stick out: 1-3-isolate_pci_isms.patch This essentially declares ARM a no-PCI zone. That's OK for testing, but not for merge. What exactly is the problem with PCI probing here? Does it return errors? Does it crash or terminate the application? Does it mess with the machine in ways which might cause breakage? 2-3-add_arm_isms.patch Have you checked with an architecture guru that sync_primitive() can really be empty, not only for that arch in general, but also for accesses to a mmapped region the way flashrom does it? 3-3-add_tegra2_spi_controller.patch Not your fault, but we really need a way to detect the target architecture in the Makefile. The issues of which SPI masters to include for internal exists on all architectures. Any ideas? I experimented with uname calls in the past, but that checks the host arch, not the target arch. Grepping the preprocessor output for the compiler might be an option. echo|gcc -dM -E -|grep "whatever\|arch\|defines" Or you try this pretty straightforward solution: Create a file arch.h with these contents: #if defined (__i386__) #define __FLASHROM_ARCH__ "x86" #elif defined (__x86_64__) #define __FLASHROM_ARCH__ "x86_64" #elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) #define __FLASHROM_ARCH__ "mips" #elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) #define __FLASHROM_ARCH__ "ppc" #endif __FLASHROM_ARCH__ Then run gcc -E arch.h|grep -v ^# The result on my machine will be "x86" Side note: Such an arch.h file (with some extensions) might save us from having to check every possible arch define everywhere we need to differentiate between architectures. I will comment on the Tegra2 SPI driver later, we should get the infrastructure questions addressed first. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH] Autodetect target processor architecture
by Carl-Daniel Hailfinger 07 Jul '11

07 Jul '11

Thanks for the reviews! New version. Autodetect target processor architecture. Enable architecture dependent compilation of individual sub-drivers for the internal programmer. With this patch, you no longer have to edit the Makefile to compile the internal driver on MIPS/ARM/... Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-target_arch/Makefile =================================================================== --- flashrom-target_arch/Makefile (Revision 1364) +++ flashrom-target_arch/Makefile (Arbeitskopie) @@ -37,7 +37,10 @@ CFLAGS += -Werror endif -# FIXME We have to differentiate between host and target arch. +# Determine the destination processor architecture +ARCH = $(strip $(shell LC_ALL=C $(CC) -E arch.h|grep -v '^\#')) + +# FIXME We have to differentiate between host and target OS architecture. OS_ARCH ?= $(shell uname) ifneq ($(OS_ARCH), SunOS) STRIP_ARGS = -s @@ -304,8 +307,10 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o -# FIXME: The PROGRAMMER_OBJS below should only be included on x86. +ifeq ($(ARCH),"x86") PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +else +endif NEED_PCI := yes endif @@ -500,6 +505,11 @@ echo "found." || ( echo "not found."; \ rm -f .test.c .test$(EXEC_SUFFIX); exit 1) @rm -f .test.c .test$(EXEC_SUFFIX) + @printf "ARCH is " + @# FreeBSD wc will output extraneous whitespace. + @echo $(ARCH)|wc -l|grep -q '^[[:blank:]]*1[[:blank:]]*$$' || \ + ( echo "unknown. Aborting."; exit 1) + @printf "%s\n" '$(ARCH)' ifeq ($(CHECK_LIBPCI), yes) pciutils: compiler Index: flashrom-target_arch/arch.h =================================================================== --- flashrom-target_arch/arch.h (Revision 0) +++ flashrom-target_arch/arch.h (Revision 0) @@ -0,0 +1,31 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2011 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Header file for CPU architecture checking. + */ + +#if defined (__i386__) || defined (__x86_64__) +#define __FLASHROM_ARCH__ "x86" +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) +#define __FLASHROM_ARCH__ "mips" +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) +#define __FLASHROM_ARCH__ "ppc" +#endif +__FLASHROM_ARCH__ -- http://www.hailfinger.org/

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Re: [flashrom] PCCHIPS M863G V5.1A + Winbond W49V002AP - Write OK
by Stefan Tauner 06 Jul '11

06 Jul '11

On Sun, 3 Jul 2011 11:11:16 -0300 Marcos Felipe Rasia de Mello <marcosfrm(a)gmail.com> wrote: > 2011/7/3 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > > > > hello and thanks for your report! > > i have added the board to our supported hw list and marked the W49V002A > > as fully tested and will commit that later. > > > > You are welcome. > When should I send "lspci -nnvvxxx" output? Is only "flashrom -V" > output sufficient? > well, i would say for all reports that do not involve board enables (i.e. if there is no ""Disabling flash write protection for board" in the output), then flashrom -V is enough. but having the associated lspci data does not hurt (us) at all... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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AT26F004 support [PATCH]
by Tim Small 06 Jul '11

06 Jul '11

Hi, Back from holiday now - was wondering if there were any thoughts regarding the AT26F004 support patch? http://marc.info/?l=flashrom&m=130861563117389&w=2 <http://marc.info/?l=flashrom&m=130861563117389&w=2> Anything else needed to get it merged? Cheers! Tim.

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Re: [flashrom] SPI Controller ICH9 Flash driver
by Stefan Tauner 06 Jul '11

06 Jul '11

On Tue, 5 Jul 2011 23:27:31 +0000 "Branham, Paul" <paul.branham(a)hp.com> wrote: > Hello, > > We are using your open source flashrom driver for Intel PCH Ibex Peak. (SPI_Controller_ICH9 in the source code with generation>8 => ie. SPIBAR = 0x3800). > > The flash ROM driver works well using CS0 by design. > > What we are looking for is information on how to use the other chip select -CS1- for some other SPI device. All Intel documentation we have found for this SPI Controller only specifies how to use the Flash capabilities of CS0, but no information whatsoever on how to use CS1 for any other SPI device. > > Would you have any source code or other information that may be of help? > hello paul, most of the public documentation from Intel does not help a lot as you already have found out... :) as far as i understand it, using multiple chips is only supported with hardware sequencing. you can read about that in detail here: http://blogs.coreboot.org/blog/2011/06/11/gsoc-2011-flashrom-part-1/ we are working on that and you can look at the following patches for preliminary support: http://patchwork.coreboot.org/patch/3242/ http://patchwork.coreboot.org/patch/3243/ http://patchwork.coreboot.org/patch/3244/ http://patchwork.coreboot.org/patch/3253/ they should be applied to the current source files, see http://flashrom.org/Downloads#Installation_from_source for details if your flash descriptors are correct and indicate two attached devices it should already work with the above patches unless the ME or the FREG registers prohibits flashrom to access some regions (which is likely on ibex peak platforms). in that case flashrom is not an option yet. i am working on that too, but it is not ready yet. in any case, sending us verbose logs of running flashrom with the patches above applied would be much appreciated. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 3/3] ichspi.c: add support for Intel Hardware Sequencing
by Stefan Tauner 06 Jul '11

06 Jul '11

"fuzzy" on irc has tested the 6.1 patch set. the attached patch fixes the address checking. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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SPI Controller ICH9 Flash driver
by Branham, Paul 06 Jul '11

06 Jul '11

Hello, We are using your open source flashrom driver for Intel PCH Ibex Peak. (SPI_Controller_ICH9 in the source code with generation>8 => ie. SPIBAR = 0x3800). The flash ROM driver works well using CS0 by design. What we are looking for is information on how to use the other chip select -CS1- for some other SPI device. All Intel documentation we have found for this SPI Controller only specifies how to use the Flash capabilities of CS0, but no information whatsoever on how to use CS1 for any other SPI device. Would you have any source code or other information that may be of help? Thanks, - Paul Paul Branham Software Engineer, EB ESSN HPN Security Hewlett-Packard Company 512-681-8511

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Additional voltages
by Steven Zakulec 05 Jul '11

05 Jul '11

Hello, I've attached some additional voltages for a number of the remaining chips in flashchips.c. I have some questions about some of the remaining chips: Should the voltage range always be the most restrictive one offered, with others mentioned in the comments? Where can I find the datasheet for the Sanyo LF25FW203A ? Can I ignore the .REMS/etc text after a chip name when looking for the datasheet? Is it something I need to be aware of? Is there a difference for M25P40 and P40-old? For the W25Q64, it seems to be on the same datasheet as the Q80, Q16, and Q32, but it's only referenced once in the sheet, and makes me wonder if this is the correct sheet then. For other chips, I'm mostly still working on them. Signed-off-by: Steven Zakulec <spzakulec(a)gmail.com>

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