- flashrom - mail.coreboot.org

Re: [flashrom] Shuttle SN78S flash info
by Stefan Tauner 07 Feb '12

07 Feb '12

On Mon, 6 Feb 2012 21:42:56 -0500 Dan Stoner <danstoner(a)gmail.com> wrote: > flashrom v0.9.1-r946 Hi Dan! Please upgrade! Your version of flashrom is 2,5 years old. Nvidia support is still not complete, but it should work way better than with 0.9.1. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Hello, flashrom problem
by Carl-Daniel Hailfinger 07 Feb '12

07 Feb '12

Hi Elena, Am 06.02.2012 23:54 schrieb Elena Gusanu: > Good morning, > My name is Elena Gusanu and i have a big problem with my laptop. I > flashrom my laptop and I didn't know what was this and i turned off, > unfortunately. Is there a solution to solve my problem and to get back bios? Please remove the power cable and battery from your laptop, wait 1 hour, then plug in battery and power cable and switch on your laptop again. That should work. Regards, Carl-Daniel

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Shuttle SN78S flash info
by Dan Stoner 07 Feb '12

07 Feb '12

from flashrom -V output

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Hello, flashrom problem
by Elena Gusanu 06 Feb '12

06 Feb '12

Good morning, My name is Elena Gusanu and i have a big problem with my laptop. I flashrom my laptop and I didn't know what was this and i turned off, unfortunately. Is there a solution to solve my problem and to get back bios? Thank you

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Re: [flashrom] NetBSD ARM static version
by Jonathan A. Kollasch 05 Feb '12

05 Feb '12

On Fri, Feb 03, 2012 at 09:58:24AM +0400, Donnie Lee wrote: > Hello! > > I have Marvell ARM SoC board with NetBSD 4 inside. I can't compile > flashrom natively on it, can only copy binaries. Please help with > instruction how to cross-compile it from NetBSD 4 i386 or Mac OS > x86_64. Or, if someone can upload static flashrom binary for NetBSD4 > ARM, it will be even better. Thanks in advance. Flashrom's ARM support isn't there yet. I compiled a NetBSD-4 flashrom binary, but I had to rip various parts out to make it compile, and once it did compile, I was unable to mmap /dev/mem properly (on NetBSD-current on Marvell Orion w/ NOR flash). I'd recommend using UBoot's built-in flash commands at this point. Jonathan Kollasch

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successful flashing of a bios rom HP Microserver N40L
by Jeremi Pałka Zawadzki 03 Feb '12

03 Feb '12

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 as requested by stefanct on the #flashrom irc channel and with many thanks for your work! debian wheezy (fully updated) flashrom from svn Checked out revision 1487. ############################# root@microserver:/usr/src/flashrom/romstore/# flashrom -Vw O41072911.ROM flashrom v0.9.4-r1487 on Linux 3.1.0-1-686-pae (i686), built with libpci 3.1.8, GCC 4.6.2, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 746M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1021 us, 10000 myus = 10024 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "HP" DMI string system-product-name: "ProLiant MicroServer" DMI string system-version: " " DMI string baseboard-manufacturer: "" DMI string baseboard-product-name: "" DMI string baseboard-version: "" DMI string chassis-type: "Tower" Found chipset "AMD SB700/SB710/SB750/SB850" with PCI ID 1002:439d. Enabling flash write... SPI base address is at 0xfec10000 AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0 PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1 SpiArbEnable=1, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, ArbWaitCount=7, SpiBridgeDisable=1, DropOneClkOnRd=0 NormSpeed is 33 MHz GPIO11 used for SPI_DO GPIO12 used for SPI_DI GPIO31 used for SPI_HOLD GPIO32 used for SPI_CS GPIO47 used for SPI_CLK SB700 IMC is not active. ROM strap override is not active OK. The following protocols are supported: LPC, FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for SST SST25LF040A, 512 kB: probe_spi_res2: id1 0xbf, id2 0x41 Probing for SST SST25LF080A, 1024 kB: probe_spi_res2: id1 0xbf, id2 0x41 Probing for SST SST25VF010, 128 kB: probe_spi_rems: id1 0xbf, id2 0x41 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Chip status register is 00 Chip status register: Block Protect Write Disable (BPL) is not set Chip status register: Auto Address Increment Programming (AAI) is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Resulting block protection : none Found SST flash chip "SST25VF016B" (2048 kB, SPI) at physical address 0xffe00000. Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0xbf, id2 0x41 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xbf, id2 0x41 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xbf, id2 0x41 Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xe0, id2 0x94, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x0c, id2 0xe4, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xe0, id2 0x94, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x0c, id2 0xe4, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xe0, id2 0x94, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x0c, id2 0xe4, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x24, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xe0, id2 0x94, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xe0, id2 0x94, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0x0c, id2 0xe4, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0x0c, id2 0xe4, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xe0, id2 0x94, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xe0, id2 0x94, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xe0, id2 0x94, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xe0, id2 0x94, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x0c, id2 0xe4, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xe0, id2 0x94, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xe0, id2 0x94, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xe0, id2 0x94, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xe0, id2 0x94, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xe0, id2 0x94, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xe0, id2 0x94, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xe0, id2 0x94, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0x0c, id2 0xe4, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x0c, id2 0xe4, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xe0, id2 0x94, id1 is normal flash content, id2 is normal flash content Found SST flash chip "SST25VF016B" (2048 kB, SPI). Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:S, 0x001000-0x001fff:S, 0x002000-0x002fff:S, 0x003000-0x003fff:S, 0x004000-0x004fff:S, 0x005000-0x005fff:S, 0x006000-0x006fff:S, 0x007000-0x007fff:S, 0x008000-0x008fff:S, 0x009000-0x009fff:S, 0x00a000-0x00afff:S, 0x00b000-0x00bfff:S, 0x00c000-0x00cfff:S, 0x00d000-0x00dfff:S, 0x00e000-0x00efff:S, 0x00f000-0x00ffff:S, 0x010000-0x010fff:S, 0x011000-0x011fff:S, 0x012000-0x012fff:S, 0x013000-0x013fff:S, 0x014000-0x014fff:S, 0x015000-0x015fff:S, 0x016000-0x016fff:S, 0x017000-0x017fff:S, 0x018000-0x018fff:S, 0x019000-0x019fff:S, 0x01a000-0x01afff:S, 0x01b000-0x01bfff:S, 0x01c000-0x01cfff:S, 0x01d000-0x01dfff:S, 0x01e000-0x01efff:S, 0x01f000-0x01ffff:S, 0x020000-0x020fff:S, 0x021000-0x021fff:S, 0x022000-0x022fff:S, 0x023000-0x023fff:S, 0x024000-0x024fff:S, 0x025000-0x025fff:S, 0x026000-0x026fff:S, 0x027000-0x027fff:S, 0x028000-0x028fff:S, 0x029000-0x029fff:S, 0x02a000-0x02afff:S, 0x02b000-0x02bfff:S, 0x02c000-0x02cfff:S, 0x02d000-0x02dfff:S, 0x02e000-0x02efff:S, 0x02f000-0x02ffff:S, 0x030000-0x030fff:S, 0x031000-0x031fff:S, 0x032000-0x032fff:S, 0x033000-0x033fff:S, 0x034000-0x034fff:S, 0x035000-0x035fff:S, 0x036000-0x036fff:S, 0x037000-0x037fff:S, 0x038000-0x038fff:S, 0x039000-0x039fff:S, 0x03a000-0x03afff:S, 0x03b000-0x03bfff:S, 0x03c000-0x03cfff:S, 0x03d000-0x03dfff:S, 0x03e000-0x03efff:S, 0x03f000-0x03ffff:S, 0x040000-0x040fff:S, 0x041000-0x041fff:S, 0x042000-0x042fff:S, 0x043000-0x043fff:S, 0x044000-0x044fff:S, 0x045000-0x045fff:S, 0x046000-0x046fff:S, 0x047000-0x047fff:S, 0x048000-0x048fff:S, 0x049000-0x049fff:S, 0x04a000-0x04afff:S, 0x04b000-0x04bfff:S, 0x04c000-0x04cfff:S, 0x04d000-0x04dfff:S, 0x04e000-0x04efff:S, 0x04f000-0x04ffff:S, 0x050000-0x050fff:S, 0x051000-0x051fff:S, 0x052000-0x052fff:S, 0x053000-0x053fff:S, 0x054000-0x054fff:S, 0x055000-0x055fff:S, 0x056000-0x056fff:S, 0x057000-0x057fff:S, 0x058000-0x058fff:S, 0x059000-0x059fff:S, 0x05a000-0x05afff:S, 0x05b000-0x05bfff:S, 0x05c000-0x05cfff:S, 0x05d000-0x05dfff:S, 0x05e000-0x05efff:S, 0x05f000-0x05ffff:S, 0x060000-0x060fff:S, 0x061000-0x061fff:S, 0x062000-0x062fff:S, 0x063000-0x063fff:S, 0x064000-0x064fff:S, 0x065000-0x065fff:S, 0x066000-0x066fff:S, 0x067000-0x067fff:S, 0x068000-0x068fff:S, 0x069000-0x069fff:S, 0x06a000-0x06afff:S, 0x06b000-0x06bfff:S, 0x06c000-0x06cfff:S, 0x06d000-0x06dfff:S, 0x06e000-0x06efff:S, 0x06f000-0x06ffff:S, 0x070000-0x070fff:S, 0x071000-0x071fff:S, 0x072000-0x072fff:S, 0x073000-0x073fff:S, 0x074000-0x074fff:S, 0x075000-0x075fff:S, 0x076000-0x076fff:S, 0x077000-0x077fff:S, 0x078000-0x078fff:S, 0x079000-0x079fff:S, 0x07a000-0x07afff:S, 0x07b000-0x07bfff:S, 0x07c000-0x07cfff:S, 0x07d000-0x07dfff:S, 0x07e000-0x07efff:S, 0x07f000-0x07ffff:S, 0x080000-0x080fff:S, 0x081000-0x081fff:S, 0x082000-0x082fff:S, 0x083000-0x083fff:S, 0x084000-0x084fff:S, 0x085000-0x085fff:S, 0x086000-0x086fff:S, 0x087000-0x087fff:S, 0x088000-0x088fff:S, 0x089000-0x089fff:S, 0x08a000-0x08afff:S, 0x08b000-0x08bfff:S, 0x08c000-0x08cfff:S, 0x08d000-0x08dfff:S, 0x08e000-0x08efff:S, 0x08f000-0x08ffff:S, 0x090000-0x090fff:S, 0x091000-0x091fff:S, 0x092000-0x092fff:S, 0x093000-0x093fff:S, 0x094000-0x094fff:S, 0x095000-0x095fff:S, 0x096000-0x096fff:S, 0x097000-0x097fff:S, 0x098000-0x098fff:S, 0x099000-0x099fff:S, 0x09a000-0x09afff:S, 0x09b000-0x09bfff:S, 0x09c000-0x09cfff:S, 0x09d000-0x09dfff:S, 0x09e000-0x09efff:S, 0x09f000-0x09ffff:S, 0x0a0000-0x0a0fff:S, 0x0a1000-0x0a1fff:S, 0x0a2000-0x0a2fff:S, 0x0a3000-0x0a3fff:S, 0x0a4000-0x0a4fff:S, 0x0a5000-0x0a5fff:S, 0x0a6000-0x0a6fff:S, 0x0a7000-0x0a7fff:S, 0x0a8000-0x0a8fff:S, 0x0a9000-0x0a9fff:S, 0x0aa000-0x0aafff:S, 0x0ab000-0x0abfff:S, 0x0ac000-0x0acfff:S, 0x0ad000-0x0adfff:S, 0x0ae000-0x0aefff:S, 0x0af000-0x0affff:S, 0x0b0000-0x0b0fff:S, 0x0b1000-0x0b1fff:S, 0x0b2000-0x0b2fff:S, 0x0b3000-0x0b3fff:S, 0x0b4000-0x0b4fff:S, 0x0b5000-0x0b5fff:S, 0x0b6000-0x0b6fff:S, 0x0b7000-0x0b7fff:S, 0x0b8000-0x0b8fff:S, 0x0b9000-0x0b9fff:S, 0x0ba000-0x0bafff:S, 0x0bb000-0x0bbfff:S, 0x0bc000-0x0bcfff:S, 0x0bd000-0x0bdfff:S, 0x0be000-0x0befff:S, 0x0bf000-0x0bffff:S, 0x0c0000-0x0c0fff:S, 0x0c1000-0x0c1fff:S, 0x0c2000-0x0c2fff:S, 0x0c3000-0x0c3fff:S, 0x0c4000-0x0c4fff:S, 0x0c5000-0x0c5fff:S, 0x0c6000-0x0c6fff:S, 0x0c7000-0x0c7fff:S, 0x0c8000-0x0c8fff:S, 0x0c9000-0x0c9fff:S, 0x0ca000-0x0cafff:S, 0x0cb000-0x0cbfff:S, 0x0cc000-0x0ccfff:S, 0x0cd000-0x0cdfff:S, 0x0ce000-0x0cefff:S, 0x0cf000-0x0cffff:S, 0x0d0000-0x0d0fff:S, 0x0d1000-0x0d1fff:S, 0x0d2000-0x0d2fff:S, 0x0d3000-0x0d3fff:S, 0x0d4000-0x0d4fff:S, 0x0d5000-0x0d5fff:S, 0x0d6000-0x0d6fff:S, 0x0d7000-0x0d7fff:S, 0x0d8000-0x0d8fff:S, 0x0d9000-0x0d9fff:S, 0x0da000-0x0dafff:S, 0x0db000-0x0dbfff:S, 0x0dc000-0x0dcfff:S, 0x0dd000-0x0ddfff:S, 0x0de000-0x0defff:S, 0x0df000-0x0dffff:S, 0x0e0000-0x0e0fff:S, 0x0e1000-0x0e1fff:S, 0x0e2000-0x0e2fff:S, 0x0e3000-0x0e3fff:S, 0x0e4000-0x0e4fff:S, 0x0e5000-0x0e5fff:S, 0x0e6000-0x0e6fff:S, 0x0e7000-0x0e7fff:S, 0x0e8000-0x0e8fff:S, 0x0e9000-0x0e9fff:S, 0x0ea000-0x0eafff:S, 0x0eb000-0x0ebfff:S, 0x0ec000-0x0ecfff:S, 0x0ed000-0x0edfff:S, 0x0ee000-0x0eefff:S, 0x0ef000-0x0effff:S, 0x0f0000-0x0f0fff:S, 0x0f1000-0x0f1fff:S, 0x0f2000-0x0f2fff:S, 0x0f3000-0x0f3fff:S, 0x0f4000-0x0f4fff:S, 0x0f5000-0x0f5fff:S, 0x0f6000-0x0f6fff:S, 0x0f7000-0x0f7fff:S, 0x0f8000-0x0f8fff:S, 0x0f9000-0x0f9fff:S, 0x0fa000-0x0fafff:S, 0x0fb000-0x0fbfff:S, 0x0fc000-0x0fcfff:S, 0x0fd000-0x0fdfff:S, 0x0fe000-0x0fefff:S, 0x0ff000-0x0fffff:S, 0x100000-0x100fff:S, 0x101000-0x101fff:S, 0x102000-0x102fff:S, 0x103000-0x103fff:S, 0x104000-0x104fff:S, 0x105000-0x105fff:S, 0x106000-0x106fff:S, 0x107000-0x107fff:S, 0x108000-0x108fff:S, 0x109000-0x109fff:S, 0x10a000-0x10afff:S, 0x10b000-0x10bfff:S, 0x10c000-0x10cfff:S, 0x10d000-0x10dfff:S, 0x10e000-0x10efff:S, 0x10f000-0x10ffff:S, 0x110000-0x110fff:S, 0x111000-0x111fff:S, 0x112000-0x112fff:S, 0x113000-0x113fff:S, 0x114000-0x114fff:S, 0x115000-0x115fff:S, 0x116000-0x116fff:S, 0x117000-0x117fff:S, 0x118000-0x118fff:S, 0x119000-0x119fff:S, 0x11a000-0x11afff:S, 0x11b000-0x11bfff:S, 0x11c000-0x11cfff:S, 0x11d000-0x11dfff:S, 0x11e000-0x11efff:S, 0x11f000-0x11ffff:S, 0x120000-0x120fff:S, 0x121000-0x121fff:S, 0x122000-0x122fff:S, 0x123000-0x123fff:S, 0x124000-0x124fff:S, 0x125000-0x125fff:S, 0x126000-0x126fff:S, 0x127000-0x127fff:S, 0x128000-0x128fff:S, 0x129000-0x129fff:S, 0x12a000-0x12afff:S, 0x12b000-0x12bfff:S, 0x12c000-0x12cfff:S, 0x12d000-0x12dfff:S, 0x12e000-0x12efff:S, 0x12f000-0x12ffff:S, 0x130000-0x130fff:S, 0x131000-0x131fff:S, 0x132000-0x132fff:S, 0x133000-0x133fff:S, 0x134000-0x134fff:S, 0x135000-0x135fff:S, 0x136000-0x136fff:S, 0x137000-0x137fff:S, 0x138000-0x138fff:S, 0x139000-0x139fff:S, 0x13a000-0x13afff:S, 0x13b000-0x13bfff:S, 0x13c000-0x13cfff:S, 0x13d000-0x13dfff:S, 0x13e000-0x13efff:S, 0x13f000-0x13ffff:S, 0x140000-0x140fff:S, 0x141000-0x141fff:S, 0x142000-0x142fff:S, 0x143000-0x143fff:S, 0x144000-0x144fff:S, 0x145000-0x145fff:S, 0x146000-0x146fff:S, 0x147000-0x147fff:S, 0x148000-0x148fff:S, 0x149000-0x149fff:S, 0x14a000-0x14afff:S, 0x14b000-0x14bfff:S, 0x14c000-0x14cfff:S, 0x14d000-0x14dfff:S, 0x14e000-0x14efff:S, 0x14f000-0x14ffff:S, 0x150000-0x150fff:S, 0x151000-0x151fff:S, 0x152000-0x152fff:S, 0x153000-0x153fff:S, 0x154000-0x154fff:S, 0x155000-0x155fff:S, 0x156000-0x156fff:S, 0x157000-0x157fff:S, 0x158000-0x158fff:S, 0x159000-0x159fff:S, 0x15a000-0x15afff:S, 0x15b000-0x15bfff:S, 0x15c000-0x15cfff:S, 0x15d000-0x15dfff:S, 0x15e000-0x15efff:S, 0x15f000-0x15ffff:S, 0x160000-0x160fff:S, 0x161000-0x161fff:S, 0x162000-0x162fff:S, 0x163000-0x163fff:S, 0x164000-0x164fff:S, 0x165000-0x165fff:S, 0x166000-0x166fff:S, 0x167000-0x167fff:S, 0x168000-0x168fff:S, 0x169000-0x169fff:S, 0x16a000-0x16afff:S, 0x16b000-0x16bfff:S, 0x16c000-0x16cfff:S, 0x16d000-0x16dfff:S, 0x16e000-0x16efff:S, 0x16f000-0x16ffff:S, 0x170000-0x170fff:S, 0x171000-0x171fff:S, 0x172000-0x172fff:S, 0x173000-0x173fff:S, 0x174000-0x174fff:S, 0x175000-0x175fff:S, 0x176000-0x176fff:S, 0x177000-0x177fff:S, 0x178000-0x178fff:S, 0x179000-0x179fff:S, 0x17a000-0x17afff:S, 0x17b000-0x17bfff:S, 0x17c000-0x17cfff:S, 0x17d000-0x17dfff:S, 0x17e000-0x17efff:S, 0x17f000-0x17ffff:S, 0x180000-0x180fff:S, 0x181000-0x181fff:S, 0x182000-0x182fff:S, 0x183000-0x183fff:S, 0x184000-0x184fff:S, 0x185000-0x185fff:S, 0x186000-0x186fff:S, 0x187000-0x187fff:S, 0x188000-0x188fff:S, 0x189000-0x189fff:S, 0x18a000-0x18afff:S, 0x18b000-0x18bfff:S, 0x18c000-0x18cfff:S, 0x18d000-0x18dfff:S, 0x18e000-0x18efff:S, 0x18f000-0x18ffff:S, 0x190000-0x190fff:S, 0x191000-0x191fff:S, 0x192000-0x192fff:S, 0x193000-0x193fff:S, 0x194000-0x194fff:S, 0x195000-0x195fff:S, 0x196000-0x196fff:S, 0x197000-0x197fff:S, 0x198000-0x198fff:S, 0x199000-0x199fff:S, 0x19a000-0x19afff:S, 0x19b000-0x19bfff:S, 0x19c000-0x19cfff:S, 0x19d000-0x19dfff:S, 0x19e000-0x19efff:S, 0x19f000-0x19ffff:S, 0x1a0000-0x1a0fff:S, 0x1a1000-0x1a1fff:S, 0x1a2000-0x1a2fff:S, 0x1a3000-0x1a3fff:S, 0x1a4000-0x1a4fff:S, 0x1a5000-0x1a5fff:S, 0x1a6000-0x1a6fff:S, 0x1a7000-0x1a7fff:S, 0x1a8000-0x1a8fff:S, 0x1a9000-0x1a9fff:S, 0x1aa000-0x1aafff:S, 0x1ab000-0x1abfff:S, 0x1ac000-0x1acfff:S, 0x1ad000-0x1adfff:S, 0x1ae000-0x1aefff:S, 0x1af000-0x1affff:S, 0x1b0000-0x1b0fff:S, 0x1b1000-0x1b1fff:S, 0x1b2000-0x1b2fff:S, 0x1b3000-0x1b3fff:S, 0x1b4000-0x1b4fff:S, 0x1b5000-0x1b5fff:S, 0x1b6000-0x1b6fff:S, 0x1b7000-0x1b7fff:S, 0x1b8000-0x1b8fff:S, 0x1b9000-0x1b9fff:S, 0x1ba000-0x1bafff:S, 0x1bb000-0x1bbfff:S, 0x1bc000-0x1bcfff:S, 0x1bd000-0x1bdfff:S, 0x1be000-0x1befff:S, 0x1bf000-0x1bffff:S, 0x1c0000-0x1c0fff:S, 0x1c1000-0x1c1fff:S, 0x1c2000-0x1c2fff:S, 0x1c3000-0x1c3fff:S, 0x1c4000-0x1c4fff:S, 0x1c5000-0x1c5fff:S, 0x1c6000-0x1c6fff:S, 0x1c7000-0x1c7fff:S, 0x1c8000-0x1c8fff:S, 0x1c9000-0x1c9fff:S, 0x1ca000-0x1cafff:S, 0x1cb000-0x1cbfff:S, 0x1cc000-0x1ccfff:S, 0x1cd000-0x1cdfff:S, 0x1ce000-0x1cefff:S, 0x1cf000-0x1cffff:S, 0x1d0000-0x1d0fff:S, 0x1d1000-0x1d1fff:S, 0x1d2000-0x1d2fff:S, 0x1d3000-0x1d3fff:S, 0x1d4000-0x1d4fff:S, 0x1d5000-0x1d5fff:S, 0x1d6000-0x1d6fff:S, 0x1d7000-0x1d7fff:S, 0x1d8000-0x1d8fff:S, 0x1d9000-0x1d9fff:S, 0x1da000-0x1dafff:S, 0x1db000-0x1dbfff:S, 0x1dc000-0x1dcfff:S, 0x1dd000-0x1ddfff:S, 0x1de000-0x1defff:S, 0x1df000-0x1dffff:S, 0x1e0000-0x1e0fff:S, 0x1e1000-0x1e1fff:S, 0x1e2000-0x1e2fff:S, 0x1e3000-0x1e3fff:S, 0x1e4000-0x1e4fff:S, 0x1e5000-0x1e5fff:S, 0x1e6000-0x1e6fff:S, 0x1e7000-0x1e7fff:S, 0x1e8000-0x1e8fff:S, 0x1e9000-0x1e9fff:S, 0x1ea000-0x1eafff:S, 0x1eb000-0x1ebfff:S, 0x1ec000-0x1ecfff:E, 0x1ed000-0x1edfff:E, 0x1ee000-0x1eefff:S, 0x1ef000-0x1effff:S, 0x1f0000-0x1f0fff:S, 0x1f1000-0x1f1fff:S, 0x1f2000-0x1f2fff:S, 0x1f3000-0x1f3fff:S, 0x1f4000-0x1f4fff:S, 0x1f5000-0x1f5fff:S, 0x1f6000-0x1f6fff:S, 0x1f7000-0x1f7fff:S, 0x1f8000-0x1f8fff:S, 0x1f9000-0x1f9fff:S, 0x1fa000-0x1fafff:S, 0x1fb000-0x1fbfff:S, 0x1fc000-0x1fcfff:S, 0x1fd000-0x1fdfff:S, 0x1fe000-0x1fefff:S, 0x1ff000-0x1fffff:S Erase/write done. Verifying flash... VERIFIED. - -- Jeremi Pałka Zawadzki OpenPGP Key ID: 0x5ED74710 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (Darwin) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAk8rrSYACgkQeowHhV7XRxC1TwCgh+70Dvqvl/GQIlHA1qMwfRbi cUcAn0SMKD/paofhCyVMiQqBDgKkGMk5 =JT7H -----END PGP SIGNATURE-----

2 1

M95128 compatibility
by Raffaele Maietta 03 Feb '12

03 Feb '12

Hi, I need to program an EEPROM M95128, but flashrom reports that the software is not compatible with my device. Is there a way to proceed with a read / write EEPROM from this? Thanks -- Raffaele Maietta Cell 3289547251 Software Developer TME s.r.l.

2 1

Re: [flashrom] [PATCH] print*.c: Refine the do not count nor print generic flash chip entries.
by Carl-Daniel Hailfinger 03 Feb '12

03 Feb '12

Am 31.01.2012 06:51 schrieb Stefan Tauner: > Previously only the generic "unknown XXXX SPI chips" were ignored (because their > name started with "unknown". > This patch adds also all chips whose vendor starts with "Unknown" (none so far). > Change the vendor of the entry for the opaque programmer framework to > "Unknown" to ignore it. Could you undo the "Programmer"->"unknown" conversion and just ignore chips with vendor name "Programmer" as well? "Unknown" conveys some insecurity, but for opaque programmers that insecurity is not what we want. > Another patch will add the SFDP chip template also with an "Unknown" vendor field. > > Rationale: these entries do not contain any useful information when shown in -L > or wiki output. It would be better to add them to a general feature section or similar. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > diff --git a/flashchips.c b/flashchips.c > index ca1c57f..0c8257b 100644 > --- a/flashchips.c > +++ b/flashchips.c > @@ -8874,7 +8874,7 @@ const struct flashchip flashchips[] = { > }, > > { > - .vendor = "Programmer", > + .vendor = "Unknown", > .name = "Opaque flash chip", > .bustype = BUS_PROG, > .manufacture_id = PROGMANUF_ID, > diff --git a/print.c b/print.c > index 0e152a6..ba86ebb 100644 > --- a/print.c > +++ b/print.c > @@ -74,8 +74,9 @@ static void print_supported_chips(void) > > /* calculate maximum column widths and by iterating over all chips */ > for (f = flashchips; f->name != NULL; f++) { > - /* Ignore "unknown XXXX SPI chip" entries. */ > - if (!strncmp(f->name, "unknown", 7)) > + /* Ignore generic entries. */ > + if (!strncmp(f->vendor, "Unknown", 7) || > + !strncmp(f->name, "unknown", 7)) > continue; > chipcount++; > > @@ -161,8 +162,9 @@ static void print_supported_chips(void) > msg_ginfo("(P = PROBE, R = READ, E = ERASE, W = WRITE)\n\n"); > > for (f = flashchips; f->name != NULL; f++) { > - /* Don't print "unknown XXXX SPI chip" entries. */ > - if (!strncmp(f->name, "unknown", 7)) > + /* Don't print generic entries. */ > + if (!strncmp(f->vendor, "Unknown", 7) || > + !strncmp(f->name, "unknown", 7)) > continue; > > /* support for multiline vendor names: > diff --git a/print_wiki.c b/print_wiki.c > index 1c9241e..70f4427 100644 > --- a/print_wiki.c > +++ b/print_wiki.c > @@ -216,9 +216,9 @@ static void print_supported_chips_wiki(int cols) > char vmin[6]; > > for (f = flashchips; f->name != NULL; f++) { > - /* Don't count "unknown XXXX SPI chip" entries. */ > - if (!strncmp(f->name, "unknown", 7)) > - continue; > + /* Don't count generic entries. */ > + if (!strncmp(f->vendor, "Unknown", 7) || > + !strncmp(f->name, "unknown", 7)) > chipcount++; > } > > @@ -227,8 +227,9 @@ static void print_supported_chips_wiki(int cols) > "| valign=\"top\"|\n\n%s", chipcount, chip_th); > > for (f = flashchips; f->name != NULL; f++, i++) { > - /* Don't print "unknown XXXX SPI chip" entries. */ > - if (!strncmp(f->name, "unknown", 7)) > + /* Don't print generic entries. */ > + if (!strncmp(f->vendor, "Unknown", 7) || > + !strncmp(f->name, "unknown", 7)) > continue; > > /* Alternate colors if the vendor changes. */ Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[commit] r1488 - trunk
by repository service 03 Feb '12

03 Feb '12

Author: stefanct Date: Fri Feb 3 23:32:09 2012 New Revision: 1488 URL: http://flashrom.org/trac/flashrom/changeset/1488 Log: print*.c: Refine the do not count nor print generic flash chip entries conditions. Previously only the generic "unknown XXXX SPI chips" were ignored (because their name started with "unknown". This patch adds also all chips whose vendor starts with "Unknown" (none so far) and "Programmer" (currently used by the opaque flash chip framework) . A patch will add the SFDP chip template with an "Unknown" vendor field later. Rationale: these entries do not contain any useful information when shown in -L or wiki output. It would be better to add them to a general feature section or similar. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/print.c trunk/print_wiki.c Modified: trunk/print.c ============================================================================== --- trunk/print.c Tue Jan 31 07:51:56 2012 (r1487) +++ trunk/print.c Fri Feb 3 23:32:09 2012 (r1488) @@ -74,8 +74,10 @@ /* calculate maximum column widths and by iterating over all chips */ for (f = flashchips; f->name != NULL; f++) { - /* Ignore "unknown XXXX SPI chip" entries. */ - if (!strncmp(f->name, "unknown", 7)) + /* Ignore generic entries. */ + if (!strncmp(f->vendor, "Unknown", 7) || + !strncmp(f->vendor, "Programmer", 10) || + !strncmp(f->name, "unknown", 7)) continue; chipcount++; @@ -161,8 +163,10 @@ msg_ginfo("(P = PROBE, R = READ, E = ERASE, W = WRITE)\n\n"); for (f = flashchips; f->name != NULL; f++) { - /* Don't print "unknown XXXX SPI chip" entries. */ - if (!strncmp(f->name, "unknown", 7)) + /* Don't print generic entries. */ + if (!strncmp(f->vendor, "Unknown", 7) || + !strncmp(f->vendor, "Programmer", 10) || + !strncmp(f->name, "unknown", 7)) continue; /* support for multiline vendor names: Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Tue Jan 31 07:51:56 2012 (r1487) +++ trunk/print_wiki.c Fri Feb 3 23:32:09 2012 (r1488) @@ -216,9 +216,10 @@ char vmin[6]; for (f = flashchips; f->name != NULL; f++) { - /* Don't count "unknown XXXX SPI chip" entries. */ - if (!strncmp(f->name, "unknown", 7)) - continue; + /* Don't count generic entries. */ + if (!strncmp(f->vendor, "Unknown", 7) || + !strncmp(f->vendor, "Programmer", 10) || + !strncmp(f->name, "unknown", 7)) chipcount++; } @@ -227,8 +228,10 @@ "| valign=\"top\"|\n\n%s", chipcount, chip_th); for (f = flashchips; f->name != NULL; f++, i++) { - /* Don't print "unknown XXXX SPI chip" entries. */ - if (!strncmp(f->name, "unknown", 7)) + /* Don't print generic entries. */ + if (!strncmp(f->vendor, "Unknown", 7) || + !strncmp(f->vendor, "Programmer", 10) || + !strncmp(f->name, "unknown", 7)) continue; /* Alternate colors if the vendor changes. */

1 0

Re: [flashrom] [PATCH 3/3] serprog: add support for setting the SPI frequency
by Uwe Hermann 03 Feb '12

03 Feb '12

On Thu, Sep 08, 2011 at 12:56:23AM +0200, Stefan Tauner wrote: > +0x14 Set SPI clock frequency 16-bit requested frequency ACK + 16-bit set frequency / NAK ^ "Set SPI clock frequency (in Hz)" > + 0x14 (S_SPI_SCK): Please rename to S_SPI_FREQ (also all other places with 'SCK'). SCK is often used to name a clock pin, this is unnecessarily confusing here. > + Set the SPI clock frequency. ^ in Hz > + f_spi = extract_programmer_param("sck"); sck -> freq > + if (f_spi && strlen(f_spi)) { > + uint8_t buf[2]; > + uint16_t tmp = atoi(f_spi); Hm, maybe use strtol() later and check for errors, atoi() is not so good for that. > + if (sp_check_commandavail(S_CMD_S_SPI_SCK) == 0) > + msg_pdbg(MSGHEADER "Setting SPI clock rate is " > + "not supported!\n"); > + else if (sp_docommand(S_CMD_S_SPI_SCK, 2, buf, 2, buf) > + == 0) { > + tmp = buf[0] | (buf[1]<<8); ^^ Missing spaces. > + msg_pdbg(MSGHEADER "Requested to set SPI clock " > + "frequency to %s kHz. It was actually " > + "set to %d kHz\n", f_spi, tmp); kHz -> Hz I would highly recommend to use Hz as the unit for setting the frequency (in the API). The frontend (flashrom) can easily allow freq=1000, or freq=1khz, or freq=1mhz etc. for user friendlyness, but the API should maintain max. flexibility IMHO. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

2 2

NetBSD ARM static version
by Donnie Lee 03 Feb '12

03 Feb '12

Hello! I have Marvell ARM SoC board with NetBSD 4 inside. I can't compile flashrom natively on it, can only copy binaries. Please help with instruction how to cross-compile it from NetBSD 4 i386 or Mac OS x86_64. Or, if someone can upload static flashrom binary for NetBSD4 ARM, it will be even better. Thanks in advance. Donnie.

1 0

Re: [flashrom] Help: unable to upgrade bios
by Raghuramchary Jallipalli 02 Feb '12

02 Feb '12

Hi David, Sorry for the late reply. I have done the changes as suggested and don’t see either 1 or 2 for op.atomic after issuing the “flashrom –V –p internal:this_is_not_a_laptop –r foo.bin” command. Please see attached log. Will this now confirm that the flashrom utility cannot be used for BIOS upgrade on my board? NOTE: The log is collected for AT25DF641A(8MB) flash as opposed to AT25DF321A(4MB) flash before. Thanks for the help, Raghu From: David Hendricks [mailto:dhendrix@google.com] Sent: Wednesday, January 11, 2012 3:32 AM To: Raghuramchary Jallipalli Cc: flashrom(a)flashrom.org; V Balaji; Vishnuvardhan Reddy Subject: Re: [flashrom] Help: unable to upgrade bios On Mon, Jan 9, 2012 at 3:20 AM, Raghuramchary Jallipalli <Raghuramchary.Jallipalli(a)lntinfotech.com<mailto:Raghuramchary.Jallipalli@lntinfotech.com>> wrote: Thanks David. As you said, the reason for not programming is due to wrong op.atomic configuration. Is there any way to set these properly? It should be set automatically. Carl-Daniel clarified on IRC that the "atomic" cycle flag will always be 0 at the stage they are printed. Sorry for the confusion! I recommend adding a debug print to ich9_run_opcode() to see what the "atomic" flag ends up being: Index: ichspi.c =================================================================== --- ichspi.c (revision 1483) +++ ichspi.c (working copy) @@ -908,6 +908,7 @@ This means the timeout must be sufficient for chip erase of slow high-capacity chips. */ + msg_pdbg("opcode: 0x%02x, spi_type: %u, atomic: %u\n", op.opcode, op.spi_type, op.atomic); switch (op.atomic) { case 2: /* Select second preop. */ Then run "flashrom -V -p internal:this_is_not_a_laptop -r foo.bin" and make sure that the sector erase opcode (0x20) and byte program opcode (0x02) show either "1" or "2" for op.atomic. This will help us to prove whether or not this is the problem you are encountering. Yes jumper selects the ROM at a time. Okay. I do not think Flashrom is confused about the flash part, then. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. ________________________________ The contents of this e-mail and any attachment(s) may contain confidential or privileged information for the intended recipient(s). Unintended recipients are prohibited from taking action on the basis of information in this e-mail and using or disseminating the information, and must notify the sender and delete it from their system. L&T Infotech will not accept responsibility or liability for the accuracy or completeness of, or the presence of any virus or disabling code in this e-mail" ************************************************************************* This email and attachments have been scanned for potential proprietary or sensitive information leakage. Websense Data Security, Protecting Your Information from the Inside Out. www.websense.com *************************************************************************

1 0

Re: [flashrom] Board identification patch for the MSC Q7 Tunnel Creek board
by Feldschmid, Ingo 01 Feb '12

01 Feb '12

Hi, thanks for all the input. I have created a new patch file, which addresses the problems mentioned in the last few replies: - print.c: added entry in boards_known array- board_enable.c: phase 2 function name changed to "p2_not_a_laptop" - board_enable.c: new entry in board_matches array sorted by vendor name - board_enable.c: board detection mechanism changed to use first pci identifier for tunnel creek and second pci identifier for EG20T and dmi information for vendor name The detection mechanism should now work for all boards with Tunnel Creek CPU with EG20T southbridge from vendor "MSC Vertriebs GmbH". I tried to narrow it down with the CPU/chipset/DMI combination, since we don't have any company-specific pci devices on this board. Signed-off-by: Ingo Feldschmid <ifel(a)msc-ge.com> Best regards, Ingo Es gelten unsere Allgemeinen Leistungsbedingungen die unter http://www.msc-ge.com/alb abrufbar sind. Our standard terms and conditions apply which are available under http://www.msc-ge.com/alb . MSC Vertriebs GmbH Sitz der Gesellschaft: Industriestrasse 16, 76297 Stutensee Handelsregister: Mannheim, HRB Nr. 10 3631 Geschaftsfuhrung: Manfred Schwarztrauber, Lothar Kummerlin, Rudiger Kuhn, Silvano Geissler Umsatzsteuer ID Nr.: DE 143 585 507 WEEE Reg. Nr. : DE 31011852 Gleichmann & Co. Electronics GmbH Sitz der Gesellschaft: Schraderstrasse 44, 67227 Frankenthal Handelsregister: Ludwigshafen, HRB Nr. 21305 Geschaftsfuhrung: Manfred Schwarztrauber, Thomas Klein Umsatzsteuer ID Nr. : DE 148 421 329 WEEE Reg. Nr.: DE 72277043 Diese E-Mail enthalt vertrauliche und/ oder rechtlich geschutzte Informationen. Wenn Sie nicht der beabsichtigte Empfanger sind, informieren Sie bitte sofort den Absender und loschen Sie diese E-Mail. The information contained in this message is confidential and/ or protected by law. If you are not the intended recipient, please contact the sender and delete this message.

3 2

[RFC] Does code implementing support for non-flash EEPROMs belong to 'flashrom'?
by Andrey Smirnov 31 Jan '12

31 Jan '12

Hell everybody, I'm working with a board that has a ST M95320-R(http://www.st.com/internet/mcu/product/113067.jsp) EEPROM chip that works as a NVM for a Gigabit Ethernet card. This chip supports very basic subset of instructions (read/write, write enable/disable, read/write status word). Right now, in order to write the firmware to the chip I use custom tool that does only this task. And I think it would be much more convenient not to reinvent the wheel and just implement support of the said microchip in more generic open source tool such as 'flashrom'. But as far as I can tell, 'flashrom' is the tool built with flash memory solely in mind (24bit address assumption, erase +write cycle, etc.). So what I would like to know if 'flashrom' ever aimed to implement its functionality for aforementioned kind of chips? Is there any point for me to try to implement said functionality in the code-base? Andrey Smirnov P.S. I'm not subscribed to the mailing list, please CC me in your responses.

2 1

[commit] r1487 - trunk
by repository service 31 Jan '12

31 Jan '12

Author: stefanct Date: Tue Jan 31 07:51:56 2012 New Revision: 1487 URL: http://flashrom.org/trac/flashrom/changeset/1487 Log: Add board enable for the MSC Q7 Tunnel Creek board This patch adds a generic phase 2 board enable that does nothing but set is_laptop to 0 to circumvent an erroneous laptop detection due to ambigous DMI chassis information. Signed-off-by: Ingo Feldschmid <ifel(a)msc-ge.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Thu Jan 19 18:50:32 2012 (r1486) +++ trunk/board_enable.c Tue Jan 31 07:51:56 2012 (r1487) @@ -2045,6 +2045,19 @@ return it87_gpio_set(63, 1); } +/* + * Suited for all boards with ambiguous DMI chassis information, which should be + * whitelisted because they are known to work: + * - MSC Q7 Tunnel Creek Module (Q7-TCTC) + */ +static int p2_not_a_laptop(void) +{ + /* label this board as not a laptop */ + is_laptop = 0; + msg_pdbg("Laptop detection overridden by P2 board enable.\n"); + return 0; +} + #endif /* @@ -2191,6 +2204,7 @@ {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, + {0x8086, 0x8186, 0x8086, 0x8186, 0x8086, 0x8800, 0x0000, 0x0000, "^MSC Vertriebs GmbH$", NULL, NULL, P2, "MSC", "Q7-TCTC", 0, OK, p2_not_a_laptop}, {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, P3, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, /* TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html. */ {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, P3, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise}, {0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, P3, "MSI", "MS-6561 (745 Ultra)", 0, OK, w836xx_memw_enable_2e}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Thu Jan 19 18:50:32 2012 (r1486) +++ trunk/print.c Tue Jan 31 07:51:56 2012 (r1487) @@ -791,6 +791,7 @@ B("Lanner", "EM-8510C", 1, NULL, NULL), B("Lex", "CV700A", 1, "http://www.lex.com.tw/product/CV700A-spec.htm", NULL), B("Mitac", "6513WU", 1, "http://web.archive.org/web/20050313054828/http://www.mitac.com/micweb/produ…", NULL), + B("MSC", "Q7-TCTC", 1, "http://www.msc-ge.com/en/produkte/com/moduls/overview/5779-www.html", NULL), B("MSI", "MS-6153", 1, "http://www.msi.com/product/mb/MS-6153.html", NULL), B("MSI", "MS-6156", 1, "http://uk.ts.fujitsu.com/rl/servicesupport/techsupport/boards/Motherboards/…", NULL), B("MSI", "MS-6163 (MS-6163 Pro)",1, "http://www.msi.com/product/mb/MS-6163-Pro.html", NULL),

1 0

[PATCH] Add support for SFDP (JESD216).
by Stefan Tauner 31 Jan '12

31 Jan '12

Similar to modules using the opaque programmer framework (e.g. ICH Hardware Sequencing) this uses a template struct flashchip element in flashchips.c with a special probe function that fills the obtained values into that struct. This allows yet unknown SPI chips to be supported (read, erase, write) almost as if it was already added to flashchips.c. Documentation used: http://www.jedec.org/standards-documents/docs/jesd216 (2011-04) W25Q32BV data sheet Revision F (2011-04-01) EN25QH16 data sheet Revision F (2011-06-01) todo: - handle programmers which have a problem with the dummy bytes needed - move sfdp_add_uniform_eraser to spi25.c for further use like spi_get_erasefn_from_opcode? - is setting the generic SPI unlock method safe? - what page_size should be set? Tested-by: David Hendricks <dhendrix(a)google.com> on W25Q64CV Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 2 +- chipdrivers.h | 4 + flash.h | 2 + flashchips.c | 23 ++++ flashchips.h | 1 + flashrom.c | 28 +++++- sfdp.c | 355 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ spi.h | 5 + spi25.c | 31 +++++ 9 files changed, 449 insertions(+), 2 deletions(-) create mode 100644 sfdp.c diff --git a/Makefile b/Makefile index 83aa038..b890d8a 100644 --- a/Makefile +++ b/Makefile @@ -252,7 +252,7 @@ endif CHIP_OBJS = jedec.o stm50flw0x0x.o w39.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o sharplhf00l04.o \ - a25.o at25.o opaque.o + a25.o at25.o opaque.o sfdp.o LIB_OBJS = layout.o diff --git a/chipdrivers.h b/chipdrivers.h index a1d0cd9..bd81098 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -41,6 +41,7 @@ int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, unsigned int b int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_60(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode); int spi_chip_write_1(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int spi_chip_write_256(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start, int unsigned len); @@ -58,6 +59,9 @@ int spi_read_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, u int spi_write_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); int spi_aai_write(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); +/* sfdp.c */ +int probe_spi_sfdp(struct flashctx *flash); + /* opaque.c */ int probe_opaque(struct flashctx *flash); int read_opaque(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); diff --git a/flash.h b/flash.h index e51b6d4..6bcae71 100644 --- a/flash.h +++ b/flash.h @@ -174,6 +174,8 @@ struct flashctx { struct registered_programmer *pgm; }; +typedef int (erasefunc_t)(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + #define TEST_UNTESTED 0 #define TEST_OK_PROBE (1 << 0) diff --git a/flashchips.c b/flashchips.c index 0c8257b..b22e709 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8872,6 +8872,29 @@ const struct flashchip flashchips[] = { .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program */ }, + + { + .vendor = "Unknown", + .name = "SFDP device", + .bustype = BUS_SPI, + .manufacture_id = GENERIC_MANUF_ID, + .model_id = SFDP_DEVICE_ID, + /* We present our own "report this" text hence we do not + * want the default "This flash part has status UNTESTED..." + * text to be printed. */ + .tested = TEST_OK_PREW, + .probe = probe_spi_sfdp, + .unlock = spi_disable_blockprotect, /* is this safe? */ + .read = spi_chip_read, + .page_size = 256, /* ? */ + /* FIXME: some vendor extensions define this */ + .voltage = {}, + /* Everything below will be set by the probing function. */ + .write = NULL, + .total_size = 0, + .feature_bits = 0, + .block_erasers = {}, + }, { .vendor = "Unknown", diff --git a/flashchips.h b/flashchips.h index 03efb86..1f2a8ca 100644 --- a/flashchips.h +++ b/flashchips.h @@ -36,6 +36,7 @@ #define GENERIC_MANUF_ID 0xffff /* Check if there is a vendor ID */ #define GENERIC_DEVICE_ID 0xffff /* Only match the vendor ID */ +#define SFDP_DEVICE_ID 0xfffe #define ALLIANCE_ID 0x52 /* Alliance Semiconductor */ #define ALLIANCE_AS29F002B 0x34 diff --git a/flashrom.c b/flashrom.c index ee68344..84fb3fc 100644 --- a/flashrom.c +++ b/flashrom.c @@ -986,7 +986,33 @@ int probe_flash(struct registered_programmer *pgm, int startchip, * probe_flash() is the first one and thus no chip has been * found before. */ - if (startchip == 0 || fill_flash->model_id != GENERIC_DEVICE_ID) + if (startchip == 0 && fill_flash->model_id == SFDP_DEVICE_ID) { + msg_cinfo("===\n" + "SFDP has autodetected a flash chip which is " + "not natively supported by flashrom yet.\n"); + if (count_usable_erasers(fill_flash) == 0) + msg_cinfo("The standard operations read and " + "verify should work, but to support " + "erase, write and all other " + "possible features"); + else + msg_cinfo("All standard operations (read, " + "verify, erase and write) should " + "work, but to support all possible " + "features"); + + msg_cinfo(" we need to add them manually.\nYou " + "can help us by mailing us the output of " + "the following command to flashrom@flashrom." + "org: \n'flashrom -VV [plus the " + "-p/--programmer parameter (if needed)]" + "'\nThanks for your help!\n" + "===\n"); + } + + if (startchip == 0 || + ((fill_flash->model_id != GENERIC_DEVICE_ID) && + (fill_flash->model_id != SFDP_DEVICE_ID))) break; notfound: diff --git a/sfdp.c b/sfdp.c new file mode 100644 index 0000000..7c00ff5 --- /dev/null +++ b/sfdp.c @@ -0,0 +1,355 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2011-2012 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include "flash.h" +#include "spi.h" +#include "chipdrivers.h" + +static int spi_sfdp_wrapper(struct flashctx *flash, uint32_t address, uint8_t *buf, int len) +{ + int i, ret; + const unsigned char cmd[JEDEC_SFDP_OUTSIZE] = { + JEDEC_SFDP, + (address >> 16) & 0xff, + (address >> 8) & 0xff, + (address >> 0) & 0xff, + 0 + }; + msg_cspew("spi_sfdp_wrapper: addr=0x%x, len=%d, data:\n", address, len); + ret = spi_send_command(flash, sizeof(cmd), len, cmd, buf); + for (i = 0; i < len; i++) + msg_cspew(" 0x%02x", buf[i]); + msg_cspew("\n"); + return ret; +} + +/* FIXME: eventually something similar like this but more generic should be + * available to split up spi commands. use that then instead */ +static int spi_sfdp(struct flashctx *flash, uint32_t address, uint8_t *buf, int len) +{ + /* FIXME: this is wrong. */ + int maxstep = 8; + int ret = 0; + while (len > 0) { + int step = min(len, maxstep); + ret = spi_sfdp_wrapper(flash, address, buf, step); + if (ret) + return ret; + address += step; + buf += step; + len -= step; + } + return ret; +} + +struct sfdp_tbl_hdr { + uint8_t id; + uint8_t v_minor; + uint8_t v_major; + uint8_t len; + uint32_t ptp; /* 24b pointer */ +}; + +static int sfdp_add_uniform_eraser(struct flashctx *f, uint8_t opcode, uint32_t bsize) +{ + uint32_t total_size = f->total_size * 1024; + int i; + erasefunc_t *erasefn = spi_get_erasefn_from_opcode(opcode); + if (erasefn == NULL) + return 1; + for (i = 0; i < NUM_ERASEFUNCTIONS; i++) { + struct block_eraser *eraser = &f->block_erasers[i]; + if (eraser->eraseblocks[0].size != 0 || !eraser->block_erase) + continue; + eraser->block_erase = erasefn; + eraser->eraseblocks[0].size = bsize; + eraser->eraseblocks[0].count = total_size/bsize; + msg_cdbg2(" Block eraser %d: %d x %d B with opcode " + "0x%02x\n", i, total_size/bsize, bsize, + opcode); + return 0; + } + msg_cinfo("%s: Not enough space to store another eraser (i=%d)." + " Please report this at flashrom(a)flashrom.org\n", + __func__, i); + return 1; +} + +static int sfdp_fill_flash(struct flashctx *f, uint8_t *buf, uint16_t len) +{ + uint32_t tmp32; + uint8_t tmp8; + uint32_t total_size; /* in bytes */ + uint32_t bsize; + uint8_t opcode_4k = 0xFF; + int dw, j; + + msg_cdbg("Parsing JEDEC SFDP parameter table... "); + if (len != 9 * 4 && len != 4 * 4) { + msg_cerr("%s: len out of spec\n", __func__); + return 1; + } + msg_cdbg2("\n"); + + /* 1. double word */ + dw = 0; + tmp32 = buf[(4 * dw) + 0]; + tmp32 |= ((unsigned int)buf[(4 * dw) + 1]) << 8; + tmp32 |= ((unsigned int)buf[(4 * dw) + 2]) << 16; + tmp32 |= ((unsigned int)buf[(4 * dw) + 3]) << 24; + + tmp8 = (tmp32 >> 17) & 0x3; + switch (tmp8) { + case 0x0: + msg_cdbg2(" 3-Byte only addressing.\n"); + break; + case 0x1: + msg_cdbg2(" 3-Byte (and optionally 4-Byte) addressing.\n"); + break; + case 0x2: + msg_cdbg(" 4-Byte only addressing not supported.\n"); + return 1; + default: + msg_cdbg(" Required addressing mode (0x%x) not supported.\n", + tmp8); + return 1; + } + + msg_cdbg2(" Writes to the status register have "); + if (tmp32 & (1 << 3)) { + msg_cdbg2("to be enabled with "); + if (tmp32 & (1 << 4)) { + f->feature_bits = FEATURE_WRSR_WREN; + msg_cdbg2("WREN (0x06).\n"); + } else { + f->feature_bits = FEATURE_WRSR_EWSR; + msg_cdbg2("EWSR (0x50).\n"); + } + } else + msg_cdbg2("not to be especially enabled.\n"); + + msg_cdbg2(" Write granularity is "); + if (tmp32 & (1 << 2)) { + msg_cdbg2("at least 64 B.\n"); + f->write = spi_chip_write_256; + } else { + msg_cdbg2("1 B only.\n"); + f->write = spi_chip_write_1; + } + + if ((tmp32 & 0x3) == 0x1) { + opcode_4k = (tmp32 >> 8) & 0xFF; /* will be dealt with later */ + } + + /* 2. double word */ + dw = 1; + tmp32 = buf[(4 * dw) + 0]; + tmp32 |= ((unsigned int)buf[(4 * dw) + 1]) << 8; + tmp32 |= ((unsigned int)buf[(4 * dw) + 2]) << 16; + tmp32 |= ((unsigned int)buf[(4 * dw) + 3]) << 24; + + if (tmp32 & (1 << 31)) { + msg_cerr("Flash chip size >= 4 Gb/512 MB not supported.\n"); + return 1; + } + total_size = ((tmp32 & 0x7FFFFFFF) + 1) / 8; + f->total_size = total_size / 1024; + msg_cdbg2(" Flash chip size is %d kB.\n", f->total_size); + + /* FIXME: double words 3-7 contain unused fast read information */ + + if (len == 4 * 4) { + msg_cdbg("It seems like this chip supports the preliminary " + "Intel version of SFDP, skipping processing of double " + "words 3-9.\n"); + goto proc_4k; + } + + dw = 8; + for (j = 0; j < 4; j++) { + /* 8 double words from the start + 2 words for every eraser */ + tmp32 = buf[(4 * dw) + (2 * j)]; + if (tmp32 == 0) { + msg_cdbg2(" Block eraser %d is unused.\n", j); + continue; + } + if (tmp32 >= 31) { + msg_cdbg2(" Block size of eraser %d (2^%d) is too big." + "\n", j, tmp32); + continue; + } + bsize = 1 << (tmp32); /* bsize = 2 ^ field */ + + tmp8 = buf[(4 * dw) + (2 * j) + 1]; + if(sfdp_add_uniform_eraser(f, tmp8, bsize)) + continue; + /* If there is a valid 4k value in the last double words, + * we want to override the value from double word 1, hence force + * skipping its processing: */ + if (bsize == 4 * 1024) + opcode_4k = 0xFF; + } + +proc_4k: + if (opcode_4k != 0xFF) { + sfdp_add_uniform_eraser(f, opcode_4k, 4 * 1024); + } + msg_cdbg("done.\n"); + return 0; +} + +static int sfdp_fetch_pt(struct flashctx *flash, uint32_t addr, uint8_t *buf, uint16_t len) +{ + uint16_t i; + if (spi_sfdp(flash, addr, buf, len)) { + msg_cerr("Receiving SFDP parameter table failed.\n"); + return 1; + } + msg_cspew(" Parameter table contents:\n"); + for(i = 0; i < len; i++) { + if ((i % 8) == 0) { + msg_cspew(" 0x%03x: ", i); + } + msg_cspew(" 0x%02x", buf[i]); + if ((i % 8) == 7) { + msg_cspew("\n"); + continue; + } + if ((i % 8) == 3) { + msg_cspew(" "); + continue; + } + } + msg_cspew("\n"); + return 0; +} + +int probe_spi_sfdp(struct flashctx *flash) +{ + int ret = 0; + uint8_t buf[8]; + uint32_t tmp32; + uint8_t nph; + /* need to limit the table loop by comparing i to uint8_t nph hence: */ + uint16_t i; + struct sfdp_tbl_hdr *hdrs; + uint8_t *hbuf; + uint8_t *tbuf; + + if (spi_sfdp(flash, 0x00, buf, 4)) { + msg_cerr("Receiving SFDP signature failed.\n"); + return 0; + } + tmp32 = buf[0]; + tmp32 |= ((unsigned int)buf[1]) << 8; + tmp32 |= ((unsigned int)buf[2]) << 16; + tmp32 |= ((unsigned int)buf[3]) << 24; + + msg_cdbg2("SFDP signature = 0x%08x (should be 0x50444653)\n", tmp32); + if (tmp32 != 0x50444653) { + msg_cdbg("No SFDP signature found.\n"); + return 0; + } + if (spi_sfdp(flash, 0x04, buf, 3)) { + msg_cerr("Receiving SFDP revision and number of parameter " + "headers (NPH) failed. "); + return 0; + } + msg_cdbg2("SFDP revision = %d.%d\n", buf[1], buf[0]); + nph = buf[2]; + msg_cdbg2("SFDP number of parameter headers (NPH) = %d (+ 1 mandatory)" + "\n", nph); + + /* Fetch all parameter headers, even if we don't use them all (yet). */ + hbuf = malloc(sizeof(struct sfdp_tbl_hdr) * (nph + 1)); + hdrs = malloc((nph + 1) * 8); + if (hbuf == NULL || hdrs == NULL ) { + msg_gerr("Out of memory!\n"); + exit(1); /* FIXME: shutdown gracefully */ + } + if (spi_sfdp(flash, 0x08, hbuf, (nph + 1) * 8)) { + msg_cerr("Receiving SFDP parameter table headers failed.\n"); + goto cleanup_hdrs; + } + + i = 0; + do { + uint16_t len; + hdrs[i].id = hbuf[(8 * i) + 0]; + hdrs[i].v_minor = hbuf[(8 * i) + 1]; + hdrs[i].v_major = hbuf[(8 * i) + 2]; + hdrs[i].len = hbuf[(8 * i) + 3]; + hdrs[i].ptp = hbuf[(8 * i) + 4]; + hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 5]) << 8; + hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 6]) << 16; + msg_cdbg2("SFDP parameter table header %d/%d:\n", i, nph); + msg_cdbg2(" ID 0x%02x, version %d.%d\n", hdrs[i].id, + hdrs[i].v_major, hdrs[i].v_minor); + len = hdrs[i].len * 4; + tmp32 = hdrs[i].ptp; + msg_cdbg2(" Length %d B, Parameter Table Pointer 0x%06x\n", + len, tmp32); + + if (len + tmp32 > UINT16_MAX) { + msg_cerr("SFDP Parameter Table %d supposedly " + "overflows addressable SFDP area. This most\n" + "probably indicates a corrupt SFDP parameter " + "table header. Aborting SFDP probe!\n", i); + ret = 0; + goto cleanup_hdrs; + } + + tbuf = malloc(len); + if (tbuf == NULL) { + msg_gerr("Out of memory!\n"); + exit(1); /* FIXME: shutdown gracefully */ + } + if (sfdp_fetch_pt(flash, tmp32, tbuf, len)){ + msg_cerr("Fetching SFDP parameter table %d failed.\n", + i); + free(tbuf); + break; + } + if (i == 0) { /* Mandatory JEDEC SFDP parameter table */ + if (hdrs[i].id != 0) + msg_cdbg("ID of the mandatory JEDEC SFDP " + "parameter table is not 0 as demanded " + "by JESD216 (warning only).\n"); + + if (len != 9 * 4 && len != 4 * 4) { + msg_cdbg("Length of the mandatory JEDEC SFDP " + "parameter table is %d B instead of " + "36 B (i.e. 9 double words) as " + "demanded by JESD216, skipping " + "parsing.\n", len); + } else if (sfdp_fill_flash(flash, tbuf, len) == 0) + ret = 1; + } + + free(tbuf); + i++; + } while(i <= nph); + +cleanup_hdrs: + free(hdrs); + free(hbuf); + return ret; +} diff --git a/spi.h b/spi.h index b908603..5f07eae 100644 --- a/spi.h +++ b/spi.h @@ -40,6 +40,11 @@ #define JEDEC_REMS_OUTSIZE 0x04 #define JEDEC_REMS_INSIZE 0x02 +/* Read Serial Flash Discoverable Parameters (SFDP) */ +#define JEDEC_SFDP 0x5a +#define JEDEC_SFDP_OUTSIZE 0x05 /* 8b op, 24b addr, 8b dummy */ +/* JEDEC_SFDP_INSIZE : any length */ + /* Read Electronic Signature */ #define JEDEC_RES 0xab #define JEDEC_RES_OUTSIZE 0x04 diff --git a/spi25.c b/spi25.c index d81616c..8b3887e 100644 --- a/spi25.c +++ b/spi25.c @@ -720,6 +720,37 @@ int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, return spi_chip_erase_c7(flash); } +erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode) +{ + switch(opcode){ + case 0xff: + case 0x00: + /* Not specified, assuming "not supported". */ + return NULL; + case 0x20: + return &spi_block_erase_20; + break; + case 0x52: + return &spi_block_erase_52; + break; + case 0x60: + return &spi_block_erase_60; + break; + case 0xc7: + return &spi_block_erase_c7; + break; + case 0xd7: + return &spi_block_erase_d7; + break; + case 0xd8: + return &spi_block_erase_d8; + default: + msg_cinfo("%s: unknown erase opcode (0x%02x). Please report " + "this at flashrom(a)flashrom.org\n", __func__, opcode); + return NULL; + } +} + static int spi_write_status_register_flag(struct flashctx *flash, int status, const unsigned char opcode) { int result; -- 1.7.1

1 0

[PATCH] SFDP 3.2
by Stefan Tauner 31 Jan '12

31 Jan '12

just a few minor changes. this should be reviewed now. the only show stopper is the hacky workaround for programmer which dont allow arbitrary writearr sizes and dummy bytes. i may add some vendor-specific tables later, but this will be in a patch of its own of course. Stefan Tauner (1): Add support for SFDP (JESD216). Makefile | 2 +- chipdrivers.h | 4 + flash.h | 2 + flashchips.c | 23 ++++ flashchips.h | 1 + flashrom.c | 28 +++++- sfdp.c | 355 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ spi.h | 5 + spi25.c | 31 +++++ 9 files changed, 449 insertions(+), 2 deletions(-) create mode 100644 sfdp.c

1 0

[PATCH] print*.c: Refine the do not count nor print generic flash chip entries.
by Stefan Tauner 31 Jan '12

31 Jan '12

Previously only the generic "unknown XXXX SPI chips" were ignored (because their name started with "unknown". This patch adds also all chips whose vendor starts with "Unknown" (none so far). Change the vendor of the entry for the opaque programmer framework to "Unknown" to ignore it. Another patch will add the SFDP chip template also with an "Unknown" vendor field. Rationale: these entries do not contain any useful information when shown in -L or wiki output. It would be better to add them to a general feature section or similar. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashchips.c | 2 +- print.c | 10 ++++++---- print_wiki.c | 11 ++++++----- 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/flashchips.c b/flashchips.c index ca1c57f..0c8257b 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8874,7 +8874,7 @@ const struct flashchip flashchips[] = { }, { - .vendor = "Programmer", + .vendor = "Unknown", .name = "Opaque flash chip", .bustype = BUS_PROG, .manufacture_id = PROGMANUF_ID, diff --git a/print.c b/print.c index 0e152a6..ba86ebb 100644 --- a/print.c +++ b/print.c @@ -74,8 +74,9 @@ static void print_supported_chips(void) /* calculate maximum column widths and by iterating over all chips */ for (f = flashchips; f->name != NULL; f++) { - /* Ignore "unknown XXXX SPI chip" entries. */ - if (!strncmp(f->name, "unknown", 7)) + /* Ignore generic entries. */ + if (!strncmp(f->vendor, "Unknown", 7) || + !strncmp(f->name, "unknown", 7)) continue; chipcount++; @@ -161,8 +162,9 @@ static void print_supported_chips(void) msg_ginfo("(P = PROBE, R = READ, E = ERASE, W = WRITE)\n\n"); for (f = flashchips; f->name != NULL; f++) { - /* Don't print "unknown XXXX SPI chip" entries. */ - if (!strncmp(f->name, "unknown", 7)) + /* Don't print generic entries. */ + if (!strncmp(f->vendor, "Unknown", 7) || + !strncmp(f->name, "unknown", 7)) continue; /* support for multiline vendor names: diff --git a/print_wiki.c b/print_wiki.c index 1c9241e..70f4427 100644 --- a/print_wiki.c +++ b/print_wiki.c @@ -216,9 +216,9 @@ static void print_supported_chips_wiki(int cols) char vmin[6]; for (f = flashchips; f->name != NULL; f++) { - /* Don't count "unknown XXXX SPI chip" entries. */ - if (!strncmp(f->name, "unknown", 7)) - continue; + /* Don't count generic entries. */ + if (!strncmp(f->vendor, "Unknown", 7) || + !strncmp(f->name, "unknown", 7)) chipcount++; } @@ -227,8 +227,9 @@ static void print_supported_chips_wiki(int cols) "| valign=\"top\"|\n\n%s", chipcount, chip_th); for (f = flashchips; f->name != NULL; f++, i++) { - /* Don't print "unknown XXXX SPI chip" entries. */ - if (!strncmp(f->name, "unknown", 7)) + /* Don't print generic entries. */ + if (!strncmp(f->vendor, "Unknown", 7) || + !strncmp(f->name, "unknown", 7)) continue; /* Alternate colors if the vendor changes. */ -- 1.7.1

1 0

[PATCH] dummyflasher: Add a status register to SPI chips.
by Stefan Tauner 31 Jan '12

31 Jan '12

This is just a quick hack, that could be expanded. What do you think? Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- dummyflasher.c | 34 +++++++++++++++++++++++++++++++--- 1 files changed, 31 insertions(+), 3 deletions(-) diff --git a/dummyflasher.c b/dummyflasher.c index 99f81f5..4ccfd9c 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -55,6 +55,7 @@ static unsigned int emu_jedec_be_52_size = 0; static unsigned int emu_jedec_be_d8_size = 0; static unsigned int emu_jedec_ce_60_size = 0; static unsigned int emu_jedec_ce_c7_size = 0; +static uint8_t emu_status = 0; #endif #endif @@ -126,6 +127,9 @@ int dummy_init(void) { char *bustext = NULL; char *tmp = NULL; +#if EMULATE_SPI_CHIP + char *status = NULL; +#endif #if EMULATE_CHIP struct stat image_stat; #endif @@ -178,6 +182,14 @@ int dummy_init(void) goto dummy_init_out; } #if EMULATE_SPI_CHIP + status = extract_programmer_param("status"); + if (status) { + emu_status = atoi(status); + msg_pdbg("Initial status register is set to 0x%02x.\n", + emu_status); + free(status); + } + if (!strcmp(tmp, "M25P10.RES")) { emu_chip = EMULATE_ST_M25P10_RES; emu_chip_size = 128 * 1024; @@ -385,10 +397,26 @@ static int emulate_spi_chip_response(unsigned int writecnt, if (readcnt > 2) readarr[2] = 0x4a; break; - case JEDEC_RDSR: - memset(readarr, 0, readcnt); + case JEDEC_RDSR: { + uint8_t tmp_status = emu_status; if (aai_active) - memset(readarr, 1 << 6, readcnt); + tmp_status |= 1 << 6; + memset(readarr, tmp_status, readcnt); + break; + } + case JEDEC_WREN: + emu_status |= (1 << 1); + break; + case JEDEC_WRSR: + if (!(emu_status & (1 << 1))) { + msg_perr("WRSR attempted, but WEL is 0!\n"); + return 1; + } + if (aai_active) { + msg_perr("WRSR attempted during AAI sequence!\n"); + return 1; + } + emu_status = writearr[1] & 0xFC; /* resets WEL and WIP */ break; case JEDEC_READ: offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; -- 1.7.1

1 0

[PATCH] spi25.c: Refactor spi_write_status_register helpers.
by Stefan Tauner 31 Jan '12

31 Jan '12

In r1115 "Write protection handling for Atmel AT25*" the old spi_write_status_register function was duplicated to send WREN and EWSR commands respectively controlled by a new common wrapper function spi_write_status_register without a reason. Both functions' resulting code is equal apart from the opcode used. The code itself does also differ in the macros used, but their value (apart from the opcode) is equal. This patch adds a new parameter for the opcode to the helper function which allows removal of the other one. This relies on the fact that EWSR and WREN have the same INSIZE and OUTSIZE though. If that is really seen as an issue, the sizes could be made parameters too. This patch also changes the wrapper so that it no longer sets the feature bits of the struct flash(ctx) argument. This may result in changed output, because it no longer implicitly disables the debug message in following executions. Also, spi_write_status_enable has been dead code since r658 or so. Remove it. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- spi25.c | 90 ++++++++++----------------------------------------------------- 1 files changed, 14 insertions(+), 76 deletions(-) diff --git a/spi25.c b/spi25.c index 3ce7f08..d81616c 100644 --- a/spi25.c +++ b/spi25.c @@ -720,81 +720,19 @@ int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, return spi_chip_erase_c7(flash); } -int spi_write_status_enable(struct flashctx *flash) -{ - static const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR }; - int result; - - /* Send EWSR (Enable Write Status Register). */ - result = spi_send_command(flash, sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); - - if (result) - msg_cerr("%s failed\n", __func__); - - return result; -} - -/* - * This is according the SST25VF016 datasheet, who knows it is more - * generic that this... - */ -static int spi_write_status_register_ewsr(struct flashctx *flash, int status) +static int spi_write_status_register_flag(struct flashctx *flash, int status, const unsigned char opcode) { int result; int i = 0; - struct spi_command cmds[] = { - { - /* WRSR requires either EWSR or WREN depending on chip type. */ - .writecnt = JEDEC_EWSR_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_EWSR }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_WRSR_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution\n", - __func__); - /* No point in waiting for the command to complete if execution - * failed. - */ - return result; - } - /* WRSR performs a self-timed erase before the changes take effect. - * This may take 50-85 ms in most cases, and some chips apparently - * allow running RDSR only once. Therefore pick an initial delay of - * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed. + /* + * WRSR requires either EWSR or WREN depending on chip type. + * The code below relies on the fact hat EWSR and WREN have the same + * INSIZE and OUTSIZE. */ - programmer_delay(100 * 1000); - while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP) { - if (++i > 490) { - msg_cerr("Error: WIP bit after WRSR never cleared\n"); - return TIMEOUT_ERROR; - } - programmer_delay(10 * 1000); - } - return 0; -} - -static int spi_write_status_register_wren(struct flashctx *flash, int status) -{ - int result; - int i = 0; struct spi_command cmds[] = { { - /* WRSR requires either EWSR or WREN depending on chip type. */ .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, + .writearr = (const unsigned char[]){ opcode }, .readcnt = 0, .readarr = NULL, }, { @@ -811,8 +749,7 @@ static int spi_write_status_register_wren(struct flashctx *flash, int status) result = spi_send_multicommand(flash, cmds); if (result) { - msg_cerr("%s failed during command execution\n", - __func__); + msg_cerr("%s failed during command execution\n", __func__); /* No point in waiting for the command to complete if execution * failed. */ @@ -836,17 +773,18 @@ static int spi_write_status_register_wren(struct flashctx *flash, int status) int spi_write_status_register(struct flashctx *flash, int status) { + int feature_bits = flash->feature_bits; int ret = 1; - if (!(flash->feature_bits & (FEATURE_WRSR_WREN | FEATURE_WRSR_EWSR))) { + if (!(feature_bits & (FEATURE_WRSR_WREN | FEATURE_WRSR_EWSR))) { msg_cdbg("Missing status register write definition, assuming " "EWSR is needed\n"); - flash->feature_bits |= FEATURE_WRSR_EWSR; + feature_bits |= FEATURE_WRSR_EWSR; } - if (flash->feature_bits & FEATURE_WRSR_WREN) - ret = spi_write_status_register_wren(flash, status); - if (ret && (flash->feature_bits & FEATURE_WRSR_EWSR)) - ret = spi_write_status_register_ewsr(flash, status); + if (feature_bits & FEATURE_WRSR_WREN) + ret = spi_write_status_register_flag(flash, status, JEDEC_WREN); + if (ret && (feature_bits & FEATURE_WRSR_EWSR)) + ret = spi_write_status_register_flag(flash, status, JEDEC_EWSR); return ret; } -- 1.7.1

1 0

[PATCH] add support for SFDP (JESD216)
by Stefan Tauner 30 Jan '12

30 Jan '12

Similar to modules using the opaque programmer framework (e.g. ICH Hardware Sequencing) this uses a generic struct flashchip element in flashchips.c with dummy values and a special probe function that fills the obtained values into that generic struct. Documentation used: http://www.jedec.org/standards-documents/docs/jesd216 (2011-04) W25Q32BV data sheet Revision F (2011-04-01) EN25QH16 data sheet Revision F (2011-06-01) todo: - handle programmers which have a problem with the dummy bytes needed - move sfdp_add_uniform_eraser to flashchips.c? Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 2 +- chipdrivers.h | 4 + flash.h | 2 + flashchips.c | 24 ++++ flashchips.h | 1 + flashrom.c | 28 +++++- sfdp.c | 356 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ spi.h | 5 + spi25.c | 31 +++++ 9 files changed, 451 insertions(+), 2 deletions(-) create mode 100644 sfdp.c diff --git a/Makefile b/Makefile index 83aa038..b890d8a 100644 --- a/Makefile +++ b/Makefile @@ -252,7 +252,7 @@ endif CHIP_OBJS = jedec.o stm50flw0x0x.o w39.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o sharplhf00l04.o \ - a25.o at25.o opaque.o + a25.o at25.o opaque.o sfdp.o LIB_OBJS = layout.o diff --git a/chipdrivers.h b/chipdrivers.h index a1d0cd9..bd81098 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -41,6 +41,7 @@ int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, unsigned int b int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_60(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode); int spi_chip_write_1(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int spi_chip_write_256(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start, int unsigned len); @@ -58,6 +59,9 @@ int spi_read_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, u int spi_write_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); int spi_aai_write(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); +/* sfdp.c */ +int probe_spi_sfdp(struct flashctx *flash); + /* opaque.c */ int probe_opaque(struct flashctx *flash); int read_opaque(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); diff --git a/flash.h b/flash.h index e51b6d4..6bcae71 100644 --- a/flash.h +++ b/flash.h @@ -174,6 +174,8 @@ struct flashctx { struct registered_programmer *pgm; }; +typedef int (erasefunc_t)(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + #define TEST_UNTESTED 0 #define TEST_OK_PROBE (1 << 0) diff --git a/flashchips.c b/flashchips.c index ca1c57f..f0fde20 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8872,6 +8872,30 @@ const struct flashchip flashchips[] = { .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program */ }, + + { + .vendor = "Unknown", + .name = "SFDP device", + .bustype = BUS_SPI, + .manufacture_id = GENERIC_MANUF_ID, + .model_id = SFDP_DEVICE_ID, + /* We present our own "report this" text hence we do not + * want the default "This flash part has status UNTESTED..." + * text to be printed. */ + .tested = TEST_OK_PREW, + .probe = probe_spi_sfdp, + .read = spi_chip_read, + /* FIXME: some vendor extensions define this */ + .voltage = {}, + /* Everything below will be set by the probing function. */ + .page_size = 0, + .write = NULL, + .total_size = 0, + .feature_bits = 0, + .block_erasers = {}, + .unlock = NULL, + .printlock = NULL, + }, { .vendor = "Programmer", diff --git a/flashchips.h b/flashchips.h index 03efb86..1f2a8ca 100644 --- a/flashchips.h +++ b/flashchips.h @@ -36,6 +36,7 @@ #define GENERIC_MANUF_ID 0xffff /* Check if there is a vendor ID */ #define GENERIC_DEVICE_ID 0xffff /* Only match the vendor ID */ +#define SFDP_DEVICE_ID 0xfffe #define ALLIANCE_ID 0x52 /* Alliance Semiconductor */ #define ALLIANCE_AS29F002B 0x34 diff --git a/flashrom.c b/flashrom.c index ee68344..84fb3fc 100644 --- a/flashrom.c +++ b/flashrom.c @@ -986,7 +986,33 @@ int probe_flash(struct registered_programmer *pgm, int startchip, * probe_flash() is the first one and thus no chip has been * found before. */ - if (startchip == 0 || fill_flash->model_id != GENERIC_DEVICE_ID) + if (startchip == 0 && fill_flash->model_id == SFDP_DEVICE_ID) { + msg_cinfo("===\n" + "SFDP has autodetected a flash chip which is " + "not natively supported by flashrom yet.\n"); + if (count_usable_erasers(fill_flash) == 0) + msg_cinfo("The standard operations read and " + "verify should work, but to support " + "erase, write and all other " + "possible features"); + else + msg_cinfo("All standard operations (read, " + "verify, erase and write) should " + "work, but to support all possible " + "features"); + + msg_cinfo(" we need to add them manually.\nYou " + "can help us by mailing us the output of " + "the following command to flashrom@flashrom." + "org: \n'flashrom -VV [plus the " + "-p/--programmer parameter (if needed)]" + "'\nThanks for your help!\n" + "===\n"); + } + + if (startchip == 0 || + ((fill_flash->model_id != GENERIC_DEVICE_ID) && + (fill_flash->model_id != SFDP_DEVICE_ID))) break; notfound: diff --git a/sfdp.c b/sfdp.c new file mode 100644 index 0000000..6ede009 --- /dev/null +++ b/sfdp.c @@ -0,0 +1,356 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2011-2012 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include "flash.h" +#include "spi.h" +#include "chipdrivers.h" + +static int spi_sfdp_wrapper(struct flashctx *flash, uint32_t address, uint8_t *buf, int len) +{ + int i, ret; + const unsigned char cmd[JEDEC_SFDP_OUTSIZE] = { + JEDEC_SFDP, + (address >> 16) & 0xff, + (address >> 8) & 0xff, + (address >> 0) & 0xff, + 0 + }; + msg_cspew("spi_sfdp_wrapper: addr=0x%x, len=%d, data:\n", address, len); + ret = spi_send_command(flash, sizeof(cmd), len, cmd, buf); + for (i = 0; i < len; i++) + msg_cspew(" 0x%02x", buf[i]); + msg_cspew("\n"); + return ret; +} + +/* FIXME: eventually something similar like this but more generic should be + * available to split up spi commands. use that then instead */ +static int spi_sfdp(struct flashctx *flash, uint32_t address, uint8_t *buf, int len) +{ + /* FIXME: this is wrong. */ + int maxstep = 8; + int ret = 0; + while (len > 0) { + int step = min(len, maxstep); + ret = spi_sfdp_wrapper(flash, address, buf, step); + if (ret) + return ret; + address += step; + buf += step; + len -= step; + } + return ret; +} + +struct sfdp_tbl_hdr { + uint8_t id; + uint8_t v_minor; + uint8_t v_major; + uint8_t len; + uint32_t ptp; /* 24b pointer */ +}; + +static int sfdp_add_uniform_eraser(struct flashctx *f, uint8_t opcode, uint32_t bsize) +{ + uint32_t total_size = f->total_size * 1024; + int i; + erasefunc_t *erasefn = spi_get_erasefn_from_opcode(opcode); + if (erasefn == NULL) + return 1; + for (i = 0; i < NUM_ERASEFUNCTIONS; i++) { + struct block_eraser *eraser = &f->block_erasers[i]; + if (eraser->eraseblocks[0].size != 0) + continue; + eraser->block_erase = erasefn; + eraser->eraseblocks[0].size = bsize; + eraser->eraseblocks[0].count = total_size/bsize; + msg_cdbg2(" Block eraser %d: %d x %d B with opcode " + "0x%02x\n", i, total_size/bsize, bsize, + opcode); + return 0; + } + msg_cinfo("%s: Not enough space to store another eraser (i=%d)." + " Please report this at flashrom(a)flashrom.org\n", + __func__, i); + return 1; +} + +static int sfdp_fill_flash(struct flashctx *f, uint8_t *buf, uint16_t len) +{ + uint32_t tmp32; + uint8_t tmp8; + uint32_t total_size; /* in bytes */ + uint32_t bsize; + uint8_t opcode_4k = 0xFF; + int dw, j; + + msg_cdbg2("Parsing JEDEC SFDP parameter table...\n"); + if (len != 9 * 4 && len != 4 * 4) { + msg_cerr("%s: len out of spec\n", __func__); + return 1; + } + + /* 1. double word */ + dw = 0; + tmp32 = buf[(4 * dw) + 0]; + tmp32 |= ((unsigned int)buf[(4 * dw) + 1]) << 8; + tmp32 |= ((unsigned int)buf[(4 * dw) + 2]) << 16; + tmp32 |= ((unsigned int)buf[(4 * dw) + 3]) << 24; + + tmp8 = (tmp32 >> 17) & 0x3; + switch (tmp8) { + case 0x0: + msg_cdbg2(" 3-Byte only addressing.\n"); + break; + case 0x1: + msg_cdbg2(" 3-Byte (and optionally 4-Byte) addressing.\n"); + break; + case 0x2: + msg_cdbg(" 4-Byte only addressing not supported.\n"); + return 1; + default: + msg_cdbg(" Required addressing mode (0x%x) not supported.\n", + tmp8); + return 1; + } + + msg_cdbg2(" Writes to the status register have "); + if (tmp32 & (1 << 3)) { + f->unlock = spi_disable_blockprotect; + msg_cdbg2("to be enabled with "); + if (tmp32 & (1 << 4)) { + f->feature_bits = FEATURE_WRSR_WREN; + msg_cdbg2("WREN (0x06).\n"); + } else { + f->feature_bits = FEATURE_WRSR_EWSR; + msg_cdbg2("EWSR (0x50).\n"); + } + } else + msg_cdbg2("not to be especially enabled.\n"); + + msg_cdbg2(" Write granularity is "); + if (tmp32 & (1 << 2)) { + msg_cdbg2("at least 64 B.\n"); + f->page_size = 64; + f->write = spi_chip_write_256; + } else { + msg_cdbg2("1 B only.\n"); + f->page_size = 256; /* ? */ + f->write = spi_chip_write_1; + } + + if ((tmp32 & 0x3) == 0x1) { + opcode_4k = (tmp32 >> 8) & 0xFF; /* will be dealt with later */ + } + + /* 2. double word */ + dw = 1; + tmp32 = buf[(4 * dw) + 0]; + tmp32 |= ((unsigned int)buf[(4 * dw) + 1]) << 8; + tmp32 |= ((unsigned int)buf[(4 * dw) + 2]) << 16; + tmp32 |= ((unsigned int)buf[(4 * dw) + 3]) << 24; + + if (tmp32 & (1 << 31)) { + msg_cerr(" Flash chip size >= 4 Gb/512 MB not supported.\n"); + return 1; + } + total_size = ((tmp32 & 0x7FFFFFFF) + 1) / 8; + f->total_size = total_size / 1024; + msg_cdbg2(" Flash chip size is %d kB.\n", f->total_size); + + /* FIXME: double words 3-7 contain unused fast read information */ + + if (len == 4 * 4) { + msg_cdbg("It seems like this chip supports the preliminary " + "Intel version of SFDP, skipping processing of double " + "words 3-9.\n"); + goto proc_4k; + } + + dw = 8; + for (j = 0; j < 4; j++) { + /* 8 double words from the start + 2 words for every eraser */ + tmp32 = buf[(4 * dw) + (2 * j)]; + if (tmp32 == 0) { + msg_cdbg2(" Block eraser %d is unused.\n", j); + continue; + } + if (tmp32 >= 31) { + msg_cdbg2(" Block size of eraser %d (2^%d) is too big." + "\n", j, tmp32); + continue; + } + bsize = 1 << (tmp32); /* bsize = 2 ^ field */ + + tmp8 = buf[(4 * dw) + (2 * j) + 1]; + if(sfdp_add_uniform_eraser(f, tmp8, bsize)) + continue; + /* If there is a valid 4k value in the last double words, + * we want to override the value from double word 1, hence force + * skipping its processing: */ + if (bsize == 4 * 1024) + opcode_4k = 0xFF; + } + +proc_4k: + if (opcode_4k != 0xFF) { + sfdp_add_uniform_eraser(f, opcode_4k, 4 * 1024); + } + return 0; +} + +static int sfdp_fetch_pt(struct flashctx *flash, uint32_t addr, uint8_t *buf, uint16_t len) +{ + uint16_t i; + if (spi_sfdp(flash, addr, buf, len)) { + msg_cerr("Receiving SFDP parameter table failed.\n"); + return 1; + } + msg_cspew(" Parameter table contents:\n"); + for(i = 0; i < len; i++) { + if ((i % 8) == 0) { + msg_cspew(" 0x%03x: ", i); + } + msg_cspew(" 0x%02x", buf[i]); + if ((i % 8) == 7) { + msg_cspew("\n"); + continue; + } + if ((i % 8) == 3) { + msg_cspew(" "); + continue; + } + } + msg_cspew("\n"); + return 0; +} + +int probe_spi_sfdp(struct flashctx *flash) +{ + int ret = 0; + uint8_t buf[8]; + uint32_t tmp32; + uint8_t nph; + /* need to limit the table loop by comparing i to uint8_t nph hence: */ + uint16_t i; + struct sfdp_tbl_hdr *hdrs; + uint8_t *hbuf; + uint8_t *tbuf; + + if (spi_sfdp(flash, 0x00, buf, 4)) { + msg_cerr("Receiving SFDP signature failed.\n"); + return 0; + } + tmp32 = buf[0]; + tmp32 |= ((unsigned int)buf[1]) << 8; + tmp32 |= ((unsigned int)buf[2]) << 16; + tmp32 |= ((unsigned int)buf[3]) << 24; + + msg_cdbg2("SFDP signature = 0x%08x (should be 0x50444653)\n", tmp32); + if (tmp32 != 0x50444653) { + msg_cdbg("No SFDP signature found.\n"); + return 0; + } + if (spi_sfdp(flash, 0x04, buf, 3)) { + msg_cerr("Receiving SFDP revision and number of parameter " + "headers (NPH) failed. "); + return 0; + } + msg_cdbg2("SFDP revision = %d.%d\n", buf[1], buf[0]); + nph = buf[2]; + msg_cdbg2("SFDP number of parameter headers (NPH) = %d (+ 1 mandatory)" + "\n", nph); + + /* Fetch all parameter headers, even if we don't use them all (yet). */ + hbuf = malloc(sizeof(struct sfdp_tbl_hdr) * (nph + 1)); + hdrs = malloc((nph + 1) * 8); + if (hbuf == NULL || hdrs == NULL ) { + msg_gerr("Out of memory!\n"); + exit(1); /* FIXME: shutdown gracefully */ + } + if (spi_sfdp(flash, 0x08, hbuf, (nph + 1) * 8)) { + msg_cerr("Receiving SFDP parameter table headers failed.\n"); + goto cleanup_hdrs; + } + + i = 0; + do { + uint16_t len; + hdrs[i].id = hbuf[(8 * i) + 0]; + hdrs[i].v_minor = hbuf[(8 * i) + 1]; + hdrs[i].v_major = hbuf[(8 * i) + 2]; + hdrs[i].len = hbuf[(8 * i) + 3]; + hdrs[i].ptp = hbuf[(8 * i) + 4]; + hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 5]) << 8; + hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 6]) << 16; + msg_cdbg2("SFDP parameter table header %d/%d:\n", i, nph); + msg_cdbg2(" ID 0x%02x, version %d.%d\n", hdrs[i].id, + hdrs[i].v_major, hdrs[i].v_minor); + len = hdrs[i].len * 4; + tmp32 = hdrs[i].ptp; + msg_cdbg2(" Length %d B, Parameter Table Pointer 0x%06x\n", + len, tmp32); + + if (len + tmp32 > UINT16_MAX) { + msg_cerr("SFDP Parameter Table %d supposedly " + "overflows addressable SFDP area. This most\n" + "probably indicates a corrupt SFDP parameter " + "table header. Aborting SFDP probe!\n", i); + ret = 0; + goto cleanup_hdrs; + } + + tbuf = malloc(len); + if (tbuf == NULL) { + msg_gerr("Out of memory!\n"); + exit(1); /* FIXME: shutdown gracefully */ + } + if (sfdp_fetch_pt(flash, tmp32, tbuf, len)){ + msg_cerr("Fetching SFDP parameter table %d failed.\n", + i); + free(tbuf); + break; + } + if (i == 0) { /* Mandatory JEDEC SFDP parameter table */ + if (hdrs[i].id != 0) + msg_cdbg("ID of the mandatory JEDEC SFDP " + "parameter table is not 0 as demanded " + "by JESD216 (warning only).\n"); + + if (len != 9 * 4 && len != 4 * 4) { + msg_cdbg("Length of the mandatory JEDEC SFDP " + "parameter table is %d B instead of " + "36 B (i.e. 9 double words) as " + "demanded by JESD216, skipping " + "parsing.\n", len); + } else if (sfdp_fill_flash(flash, tbuf, len) == 0) + ret = 1; + } + + free(tbuf); + i++; + } while(i <= nph); + +cleanup_hdrs: + free(hdrs); + free(hbuf); + return ret; +} diff --git a/spi.h b/spi.h index b908603..5f07eae 100644 --- a/spi.h +++ b/spi.h @@ -40,6 +40,11 @@ #define JEDEC_REMS_OUTSIZE 0x04 #define JEDEC_REMS_INSIZE 0x02 +/* Read Serial Flash Discoverable Parameters (SFDP) */ +#define JEDEC_SFDP 0x5a +#define JEDEC_SFDP_OUTSIZE 0x05 /* 8b op, 24b addr, 8b dummy */ +/* JEDEC_SFDP_INSIZE : any length */ + /* Read Electronic Signature */ #define JEDEC_RES 0xab #define JEDEC_RES_OUTSIZE 0x04 diff --git a/spi25.c b/spi25.c index 3ce7f08..15ec300 100644 --- a/spi25.c +++ b/spi25.c @@ -720,6 +720,37 @@ int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, return spi_chip_erase_c7(flash); } +erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode) +{ + switch(opcode){ + case 0x00: + case 0xff: + /* Not specified, assuming "not supported". */ + return NULL; + case 0x20: + return &spi_block_erase_20; + break; + case 0x52: + return &spi_block_erase_52; + break; + case 0x60: + return &spi_block_erase_60; + break; + case 0xc7: + return &spi_block_erase_c7; + break; + case 0xd7: + return &spi_block_erase_d7; + break; + case 0xd8: + return &spi_block_erase_d8; + default: + msg_cinfo("%s: unknown erase opcode (0x%02x). Please report " + "this at flashrom(a)flashrom.org\n", __func__, opcode); + return NULL; + } +} + int spi_write_status_enable(struct flashctx *flash) { static const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR }; -- 1.7.1

1 0

[PATCH] SFDP 3.1
by Stefan Tauner 30 Jan '12

30 Jan '12

thanks to david's testing a few other STUPID bugs are taken out... we might be getting there eventually :) Stefan Tauner (1): add support for SFDP (JESD216) Makefile | 2 +- chipdrivers.h | 4 + flash.h | 2 + flashchips.c | 24 ++++ flashchips.h | 1 + flashrom.c | 28 +++++- sfdp.c | 356 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ spi.h | 5 + spi25.c | 31 +++++ 9 files changed, 451 insertions(+), 2 deletions(-) create mode 100644 sfdp.c

1 0

[PATCH] add support for SFDP (JESD216)
by Stefan Tauner 29 Jan '12

29 Jan '12

Similar to modules using the opaque programmer framework (e.g. ICH Hardware Sequencing) this uses a generic struct flashchip element in flashchips.c with dummy values and a special probe function that fills the obtained values into that generic struct. Documentation used: http://www.jedec.org/standards-documents/docs/jesd216 (2011-04) W25Q32BV data sheet Revision F (2011-04-01) EN25QH16 data sheet Revision F (2011-06-01) todo: - handle programmers which have a problem with the dummy bytes needed - move sfdp_add_uniform_eraser to flashchips.c? Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 2 +- chipdrivers.h | 4 + flash.h | 2 + flashchips.c | 24 ++++ flashchips.h | 1 + flashrom.c | 28 +++++- sfdp.c | 356 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ spi.h | 5 + spi25.c | 31 +++++ 9 files changed, 451 insertions(+), 2 deletions(-) create mode 100644 sfdp.c diff --git a/Makefile b/Makefile index 83aa038..b890d8a 100644 --- a/Makefile +++ b/Makefile @@ -252,7 +252,7 @@ endif CHIP_OBJS = jedec.o stm50flw0x0x.o w39.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o sharplhf00l04.o \ - a25.o at25.o opaque.o + a25.o at25.o opaque.o sfdp.o LIB_OBJS = layout.o diff --git a/chipdrivers.h b/chipdrivers.h index a1d0cd9..bd81098 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -41,6 +41,7 @@ int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, unsigned int b int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_60(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode); int spi_chip_write_1(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int spi_chip_write_256(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start, int unsigned len); @@ -58,6 +59,9 @@ int spi_read_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, u int spi_write_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); int spi_aai_write(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); +/* sfdp.c */ +int probe_spi_sfdp(struct flashctx *flash); + /* opaque.c */ int probe_opaque(struct flashctx *flash); int read_opaque(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); diff --git a/flash.h b/flash.h index e51b6d4..6bcae71 100644 --- a/flash.h +++ b/flash.h @@ -174,6 +174,8 @@ struct flashctx { struct registered_programmer *pgm; }; +typedef int (erasefunc_t)(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + #define TEST_UNTESTED 0 #define TEST_OK_PROBE (1 << 0) diff --git a/flashchips.c b/flashchips.c index ca1c57f..f0fde20 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8872,6 +8872,30 @@ const struct flashchip flashchips[] = { .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program */ }, + + { + .vendor = "Unknown", + .name = "SFDP device", + .bustype = BUS_SPI, + .manufacture_id = GENERIC_MANUF_ID, + .model_id = SFDP_DEVICE_ID, + /* We present our own "report this" text hence we do not + * want the default "This flash part has status UNTESTED..." + * text to be printed. */ + .tested = TEST_OK_PREW, + .probe = probe_spi_sfdp, + .read = spi_chip_read, + /* FIXME: some vendor extensions define this */ + .voltage = {}, + /* Everything below will be set by the probing function. */ + .page_size = 0, + .write = NULL, + .total_size = 0, + .feature_bits = 0, + .block_erasers = {}, + .unlock = NULL, + .printlock = NULL, + }, { .vendor = "Programmer", diff --git a/flashchips.h b/flashchips.h index 03efb86..1f2a8ca 100644 --- a/flashchips.h +++ b/flashchips.h @@ -36,6 +36,7 @@ #define GENERIC_MANUF_ID 0xffff /* Check if there is a vendor ID */ #define GENERIC_DEVICE_ID 0xffff /* Only match the vendor ID */ +#define SFDP_DEVICE_ID 0xfffe #define ALLIANCE_ID 0x52 /* Alliance Semiconductor */ #define ALLIANCE_AS29F002B 0x34 diff --git a/flashrom.c b/flashrom.c index ee68344..84fb3fc 100644 --- a/flashrom.c +++ b/flashrom.c @@ -986,7 +986,33 @@ int probe_flash(struct registered_programmer *pgm, int startchip, * probe_flash() is the first one and thus no chip has been * found before. */ - if (startchip == 0 || fill_flash->model_id != GENERIC_DEVICE_ID) + if (startchip == 0 && fill_flash->model_id == SFDP_DEVICE_ID) { + msg_cinfo("===\n" + "SFDP has autodetected a flash chip which is " + "not natively supported by flashrom yet.\n"); + if (count_usable_erasers(fill_flash) == 0) + msg_cinfo("The standard operations read and " + "verify should work, but to support " + "erase, write and all other " + "possible features"); + else + msg_cinfo("All standard operations (read, " + "verify, erase and write) should " + "work, but to support all possible " + "features"); + + msg_cinfo(" we need to add them manually.\nYou " + "can help us by mailing us the output of " + "the following command to flashrom@flashrom." + "org: \n'flashrom -VV [plus the " + "-p/--programmer parameter (if needed)]" + "'\nThanks for your help!\n" + "===\n"); + } + + if (startchip == 0 || + ((fill_flash->model_id != GENERIC_DEVICE_ID) && + (fill_flash->model_id != SFDP_DEVICE_ID))) break; notfound: diff --git a/sfdp.c b/sfdp.c new file mode 100644 index 0000000..4687737 --- /dev/null +++ b/sfdp.c @@ -0,0 +1,356 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2011-2012 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include "flash.h" +#include "spi.h" +#include "chipdrivers.h" + +static int spi_sfdp_wrapper(struct flashctx *flash, uint32_t address, uint8_t *buf, int len) +{ + int i, ret; + const unsigned char cmd[JEDEC_SFDP_OUTSIZE] = { + JEDEC_SFDP, + (address >> 16) & 0xff, + (address >> 8) & 0xff, + (address >> 0) & 0xff, + 0 + }; + msg_cspew("spi_sfdp_wrapper: addr=0x%x, len=%d, data:\n", address, len); + ret = spi_send_command(flash, sizeof(cmd), len, cmd, buf); + for (i = 0; i < len; i++) + msg_cspew(" 0x%02x", buf[i]); + msg_cspew("\n"); + return ret; +} + +/* FIXME: eventually something similar like this but more generic should be + * available to split up spi commands. use that then instead */ +static int spi_sfdp(struct flashctx *flash, uint32_t address, uint8_t *buf, int len) +{ + /* FIXME: this is wrong. */ + int maxstep = 8; + int ret = 0; + while (len > 0) { + int step = min(len, maxstep); + ret = spi_sfdp_wrapper(flash, address, buf, step); + if (ret) + return ret; + address += step; + buf += step; + len -= step; + } + return ret; +} + +struct sfdp_tbl_hdr { + uint8_t id; + uint8_t v_minor; + uint8_t v_major; + uint8_t len; + uint32_t ptp; /* 24b pointer */ +}; + +static int sfdp_add_uniform_eraser(struct flashctx *f, uint8_t opcode, uint32_t bsize) +{ + uint32_t total_size = f->total_size * 1024; + int i; + erasefunc_t *erasefn = spi_get_erasefn_from_opcode(opcode); + if (erasefn == NULL) + return 1; + for (i = 0; i < NUM_ERASEFUNCTIONS; i++) { + struct block_eraser eraser = f->block_erasers[i]; + if (eraser.eraseblocks[0].size != 0) + continue; + eraser.block_erase = erasefn; + eraser.eraseblocks[0].size = bsize; + eraser.eraseblocks[0].count = total_size/bsize; + msg_cdbg2(" Block eraser %d: %d x %d B with opcode " + "0x%02x\n", i, total_size/bsize, bsize, + opcode); + return 0; + } + msg_cinfo("%s: Not enough space to store another eraser (i=%d)." + " Please report this at flashrom(a)flashrom.org\n", + __func__, i); + return 1; +} + +static int sfdp_fill_flash(struct flashctx *f, uint8_t *buf, uint16_t len) +{ + uint32_t tmp32; + uint8_t tmp8; + uint32_t total_size; /* in bytes */ + uint32_t bsize; + uint8_t opcode_4k = 0xFF; + int dw, j; + + msg_cdbg2("Parsing JEDEC SFDP parameter table...\n"); + if (len != 9 * 4 && len != 4 * 4) { + msg_cerr("%s: len out of spec\n", __func__); + return 1; + } + + /* 1. double word */ + dw = 0; + tmp32 = buf[(4 * dw) + 0]; + tmp32 |= ((unsigned int)buf[(4 * dw) + 1]) << 8; + tmp32 |= ((unsigned int)buf[(4 * dw) + 2]) << 16; + tmp32 |= ((unsigned int)buf[(4 * dw) + 3]) << 24; + + tmp8 = (tmp32 >> 17) & 0x3; + switch (tmp8) { + case 0x0: + msg_cdbg2(" 3-Byte only addressing.\n"); + break; + case 0x1: + msg_cdbg2(" 3-Byte (and optionally 4-Byte) addressing.\n"); + break; + case 0x2: + msg_cdbg(" 4-Byte only addressing not supported.\n"); + return 1; + default: + msg_cdbg(" Required addressing mode (0x%x) not supported.\n", + tmp8); + return 1; + } + + msg_cdbg2(" Writes to the status register have "); + if (tmp32 & (1 << 3)) { + f->unlock = spi_disable_blockprotect; + msg_cdbg2("to be enabled with "); + if (tmp32 & (1 << 4)) { + f->feature_bits = FEATURE_WRSR_WREN; + msg_cdbg2("WREN (0x06).\n"); + } else { + f->feature_bits = FEATURE_WRSR_EWSR; + msg_cdbg2("EWSR (0x50).\n"); + } + } else + msg_cdbg2("not to be especially enabled.\n"); + + msg_cdbg2(" Write granularity is "); + if (tmp32 & (1 << 2)) { + msg_cdbg2(" at least 64 B.\n"); + f->page_size = 64; + f->write = spi_chip_write_256; + } else { + msg_cdbg2(" 1 B only.\n"); + f->page_size = 256; /* ? */ + f->write = spi_chip_write_1; + } + + if ((tmp32 & 0x3) == 0x1) { + opcode_4k = (tmp32 >> 8) & 0xFF; /* will be dealt with later */ + } + + /* 2. double word */ + dw = 1; + tmp32 = buf[(4 * dw) + 0]; + tmp32 |= ((unsigned int)buf[(4 * dw) + 1]) << 8; + tmp32 |= ((unsigned int)buf[(4 * dw) + 2]) << 16; + tmp32 |= ((unsigned int)buf[(4 * dw) + 3]) << 24; + + if (tmp32 & (1 << 31)) { + msg_cerr(" Flash chip size >= 4 Gb/500 MB not supported.\n"); + return 1; + } + total_size = (tmp32 & 0x7FFFFFFF) / 8; + f->total_size = total_size / 1024; + msg_cdbg2(" Flash chip size is %d kB.\n", f->total_size); + + /* FIXME: double words 3-7 contain unused fast read information */ + + if (len == 4 * 4) { + msg_cdbg("It seems like this chip supports the preliminary " + "Intel version of SFDP, skipping processing of double " + "words 3-9.\n"); + goto proc_4k; + } + + dw = 8; + for (j = 0; j < 4; j++) { + /* 8 double words from the start + 2 words for every eraser */ + tmp32 = buf[(4 * dw) + (2 * j)]; + if (tmp32 == 0) { + msg_cdbg2(" Block eraser %d is unused.\n", j); + continue; + } + if (tmp32 >= 31) { + msg_cdbg2(" Block size of eraser %d (2^%d) is too big." + "\n", j, tmp32); + continue; + } + bsize = 1 << (tmp32); /* bsize = 2 ^ field */ + + tmp8 = buf[(4 * dw) + (2 * j) + 1]; + if(sfdp_add_uniform_eraser(f, tmp8, bsize)) + continue; + /* If there is a valid 4k value in the last double words, + * we want to override the value from double word 1, hence force + * skipping its processing: */ + if (bsize == 4 * 1024) + opcode_4k = 0xFF; + } + +proc_4k: + if (opcode_4k != 0xFF) { + sfdp_add_uniform_eraser(f, opcode_4k, 4 * 1024); + } + return 0; +} + +static int sfdp_fetch_pt(struct flashctx *flash, uint32_t addr, uint8_t *buf, uint16_t len) +{ + uint16_t i; + if (spi_sfdp(flash, addr, buf, len)) { + msg_cerr("Receiving SFDP parameter table failed.\n"); + return 1; + } + msg_cspew(" Parameter table contents:\n"); + for(i = 0; i < len; i++) { + if ((i % 8) == 0) { + msg_cspew(" 0x%03x: ", i); + } + msg_cspew(" 0x%02x", buf[i]); + if ((i % 8) == 7) { + msg_cspew("\n"); + continue; + } + if ((i % 8) == 3) { + msg_cspew(" "); + continue; + } + } + msg_cspew("\n"); + return 0; +} + +int probe_spi_sfdp(struct flashctx *flash) +{ + int ret = 0; + uint8_t buf[8]; + uint32_t tmp32; + uint8_t nph; + /* need to limit the table loop by comparing i to uint8_t nph hence: */ + uint16_t i; + struct sfdp_tbl_hdr *hdrs; + uint8_t *hbuf; + uint8_t *tbuf; + + if (spi_sfdp(flash, 0x00, buf, 4)) { + msg_cerr("Receiving SFDP signature failed.\n"); + return 0; + } + tmp32 = buf[0]; + tmp32 |= ((unsigned int)buf[1]) << 8; + tmp32 |= ((unsigned int)buf[2]) << 16; + tmp32 |= ((unsigned int)buf[3]) << 24; + + msg_cdbg2("SFDP signature = 0x%08x (should be 0x50444653)\n", tmp32); + if (tmp32 != 0x50444653) { + msg_cdbg("No SFDP signature found.\n"); + return 0; + } + if (spi_sfdp(flash, 0x04, buf, 3)) { + msg_cerr("Receiving SFDP revision and number of parameter " + "headers (NPH) failed. "); + return 0; + } + msg_cdbg2("SFDP revision = %d.%d\n", buf[1], buf[0]); + nph = buf[2]; + msg_cdbg2("SFDP number of parameter headers (NPH) = %d (+ 1 mandatory)" + "\n", nph); + + /* Fetch all parameter headers, even if we don't use them all (yet). */ + hbuf = malloc(sizeof(struct sfdp_tbl_hdr) * (nph + 1)); + hdrs = malloc((nph + 1) * 8); + if (hbuf == NULL || hdrs == NULL ) { + msg_gerr("Out of memory!\n"); + exit(1); /* FIXME: shutdown gracefully */ + } + if (spi_sfdp(flash, 0x08, hbuf, (nph + 1) * 8)) { + msg_cerr("Receiving SFDP parameter table headers failed.\n"); + goto cleanup_hdrs; + } + + i = 0; + do { + uint16_t len; + hdrs[i].id = hbuf[(8 * i) + 0]; + hdrs[i].v_minor = hbuf[(8 * i) + 1]; + hdrs[i].v_major = hbuf[(8 * i) + 2]; + hdrs[i].len = hbuf[(8 * i) + 3]; + hdrs[i].ptp = hbuf[(8 * i) + 4]; + hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 5]) << 8; + hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 6]) << 16; + msg_cdbg2("SFDP parameter table header %d/%d:\n", i, nph); + msg_cdbg2(" ID 0x%02x, version %d.%d\n", hdrs[i].id, + hdrs[i].v_major, hdrs[i].v_minor); + len = hdrs[i].len * 4; + tmp32 = hdrs[i].ptp; + msg_cdbg2(" Length %d B, Parameter Table Pointer 0x%06x\n", + len, tmp32); + + if (len + tmp32 > UINT16_MAX) { + msg_cerr("SFDP Parameter Table %d supposedly " + "overflows addressable SFDP area. This most\n" + "probably indicates a corrupt SFDP parameter " + "table header. Aborting SFDP probe!\n", i); + ret = 0; + goto cleanup_hdrs; + } + + tbuf = malloc(len); + if (tbuf == NULL) { + msg_gerr("Out of memory!\n"); + exit(1); /* FIXME: shutdown gracefully */ + } + if (sfdp_fetch_pt(flash, tmp32, tbuf, len)){ + msg_cerr("Fetching SFDP parameter table %d failed.\n", + i); + free(tbuf); + break; + } + if (i == 0) { /* Mandatory JEDEC SFDP parameter table */ + if (hdrs[i].id != 0) + msg_cdbg("ID of the mandatory JEDEC SFDP " + "parameter table is not 0 as demanded " + "by JESD216 (warning only).\n"); + + if (len != 9 * 4 && len != 4 * 4) { + msg_cdbg("Length of the mandatory JEDEC SFDP " + "parameter table is %d B instead of " + "36 B (i.e. 9 double words) as " + "demanded by JESD216, skipping " + "parsing.\n", len); + } else if (sfdp_fill_flash(flash, tbuf, len) == 0) + ret = 1; + } + + free(tbuf); + i++; + } while(i <= nph); + +cleanup_hdrs: + free(hdrs); + free(hbuf); + return ret; +} diff --git a/spi.h b/spi.h index b908603..5f07eae 100644 --- a/spi.h +++ b/spi.h @@ -40,6 +40,11 @@ #define JEDEC_REMS_OUTSIZE 0x04 #define JEDEC_REMS_INSIZE 0x02 +/* Read Serial Flash Discoverable Parameters (SFDP) */ +#define JEDEC_SFDP 0x5a +#define JEDEC_SFDP_OUTSIZE 0x05 /* 8b op, 24b addr, 8b dummy */ +/* JEDEC_SFDP_INSIZE : any length */ + /* Read Electronic Signature */ #define JEDEC_RES 0xab #define JEDEC_RES_OUTSIZE 0x04 diff --git a/spi25.c b/spi25.c index 3ce7f08..15ec300 100644 --- a/spi25.c +++ b/spi25.c @@ -720,6 +720,37 @@ int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, return spi_chip_erase_c7(flash); } +erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode) +{ + switch(opcode){ + case 0x00: + case 0xff: + /* Not specified, assuming "not supported". */ + return NULL; + case 0x20: + return &spi_block_erase_20; + break; + case 0x52: + return &spi_block_erase_52; + break; + case 0x60: + return &spi_block_erase_60; + break; + case 0xc7: + return &spi_block_erase_c7; + break; + case 0xd7: + return &spi_block_erase_d7; + break; + case 0xd8: + return &spi_block_erase_d8; + default: + msg_cinfo("%s: unknown erase opcode (0x%02x). Please report " + "this at flashrom(a)flashrom.org\n", __func__, opcode); + return NULL; + } +} + int spi_write_status_enable(struct flashctx *flash) { static const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR }; -- 1.7.1

1 0

[PATCH] SFDP 3.0
by Stefan Tauner 29 Jan '12

29 Jan '12

after fixing an embarrassing off-by-one error and a few other mistakes, i refactored the setting of erasers and (hopefully) added support for the preliminary SFDP version by intel. Stefan Tauner (1): add support for SFDP (JESD216) Makefile | 2 +- chipdrivers.h | 4 + flash.h | 2 + flashchips.c | 24 ++++ flashchips.h | 1 + flashrom.c | 28 +++++- sfdp.c | 356 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ spi.h | 5 + spi25.c | 31 +++++ 9 files changed, 451 insertions(+), 2 deletions(-) create mode 100644 sfdp.c

1 0

Re: [flashrom] Board identification patch for the MSC Q7 Tunnel Creek board
by Carl-Daniel Hailfinger 29 Jan '12

29 Jan '12

Hi, thanks for this patch. Am 27.01.2012 18:11 schrieb Idwer Vollering: > From: "Feldschmid, Ingo" <ifel(a)msc-ge.com> > Date: Fri, 27 Jan 2012 15:05:22 +0100 > > When trying to flash the bios chip on our Tunnel Creek module, there always > is the “you may be running flashrom on an unsupported laptop” warning. > Since our board is neither unsupported nor a laptop, I would love to patch > that. > > Basically, I added identification for our module to the board_matches list > for phase P2, which is just before the laptop / laptop ok check. In the > board function that is called from this list, I just set the global > variable “is_laptop” to zero. This will prevent the laptop warning for > tunnel creek boards which have the dmi string “Q7-TCTC”. > > I am not sure if this mechanism is the correct way to do this, since > entries in this lists are normally used to execute board-specific > flash-chip-enable functions. This is exactly what phase 2 board enables are designed for. I'm happy it works as designed. > Of course, an easier path would be to just set the chassis information to > something like “Desktop”, but we are not building complete boards, just a > COM (Computer-On-Module). Therefore, the module could be used in all > different kinds of chassis, but the flash chip update mechanism would > always work, since everything relevant is on the module. Is there a chassis type which is called Computer-On-Module or something like that? Then again, the situation here is complicated because even if such a chassis type can be encoded in DMI data, flashrom can't really know if flashing can be done safely. > The attached patch has been built against flashrom trunk version 1486. > > I have also included two flashrom logs, just to prove that we can > flawlessly read and write the bios flash chip on our module. > > Signed-off-by: Ingo Feldschmid <ifel(a)msc-ge.com> > > Index: board_enable.c > =================================================================== > --- board_enable.c (revision 1486) > +++ board_enable.c (working copy) > @@ -2045,6 +2045,17 @@ > return it87_gpio_set(63, 1); > } > > +/* > + * Suited for: > + * - MSC Q7 Tunnel Creek Module, phase 2 detection patch > + */ > +static int msc_q7tctc_p2(void) > +{ > + /* we are a computer-on-module, not a laptop */ > + is_laptop = 0; > + return 1; > +} > + > #endif > > /* > @@ -2220,6 +2231,7 @@ > {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, P3, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise}, > {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, P3, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, > {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, P3, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, > + {0x8086, 0x8186, 0x8086, 0x8186, 0x0000, 0x0000, 0x0000, 0x0000, "^Q7-TCTC", NULL, NULL, P2, "MSC", "Q7-TCTC", 0, OK, msc_q7tctc_p2}, > #endif > { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, P3, NULL, NULL, 0, NT, NULL}, /* end marker */ > }; The only question I have is whether we can make the match more specific: - Second set of PCI IDs, preferably one which has a vendor ID of MSC-GE - Use "^Q7-TCTC$" instead Otherwise it looks good. Once the question above is answered, this patch is Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 2

FOSDEM 2012
by Carl-Daniel Hailfinger 29 Jan '12

29 Jan '12

Hey, it seems we forgot to apply for a devroom (well, at least I didn't see anything on the mailing list). Should we submit talks to the individual devrooms? Should we ask for a coreboot/flashrom booth/table? Regards, Carl-Daniel

1 2

board inspection results
by Nick O'Neill 29 Jan '12

29 Jan '12

Hi, I'm trying to write to a Macronix MX25L3205 on a Samsung Series 5 laptop, I backed up the original contents and attempted to flash a new one which always fails at the same spot. Erasing fails at that spot, but succeeds up to then. I'm happy to do some work to get this working, here's the requested information: bin (http://paste.flashrom.org/view.php?id=1032) for unknown by nickoneill superio (http://paste.flashrom.org/view.php?id=1031) for unknown by nickoneill lspci (http://paste.flashrom.org/view.php?id=1030) for unknown by nickoneill flash (http://paste.flashrom.org/view.php?id=1029) for unknown by nickoneill Thanks, Nick

2 1

Board identification patch for the MSC Q7 Tunnel Creek board
by Idwer Vollering 27 Jan '12

27 Jan '12

I have stripped the "embedded world 2012" banner. -- From: "Feldschmid, Ingo" <ifel(a)msc-ge.com> To: <flashrom(a)flashrom.org> Cc: Date: Fri, 27 Jan 2012 15:05:22 +0100 Subject: [flashrom] Board identification patch for the MSC Q7 Tunnel Creek board Hi, **** ** ** When trying to flash the bios chip on our Tunnel Creek module, there always is the “you may be running flashrom on an unsupported laptop” warning. Since our board is neither unsupported nor a laptop, I would love to patch that. **** ** ** Basically, I added identification for our module to the board_matches list for phase P2, which is just before the laptop / laptop ok check. In the board function that is called from this list, I just set the global variable “is_laptop” to zero. This will prevent the laptop warning for tunnel creek boards which have the dmi string “Q7-TCTC”. **** ** ** I am not sure if this mechanism is the correct way to do this, since entries in this lists are normally used to execute board-specific flash-chip-enable functions. **** ** ** Of course, an easier path would be to just set the chassis information to something like “Desktop”, but we are not building complete boards, just a COM (Computer-On-Module). Therefore, the module could be used in all different kinds of chassis, but the flash chip update mechanism would always work, since everything relevant is on the module. **** ** ** The attached patch has been built against flashrom trunk version 1486. **** I have also included two flashrom logs, just to prove that we can flawlessly read and write the bios flash chip on our module. **** ** ** Signed-off-by: Ingo Feldschmid <ifel(a)msc-ge.com>**** ** ** Best regards,**** Ingo**** ** ** Es gelten unsere Allgemeinen Leistungsbedingungen die unter http://www.msc-ge.com/alb abrufbar sind. Our standard terms and conditions apply which are available under http://www.msc-ge.com/alb. MSC Vertriebs GmbH Sitz der Gesellschaft: Industriestrasse 16, 76297 Stutensee Handelsregister: Mannheim, Germany, HRB No. 10 3631 Geschaftsfuhrung: Manfred Schwarztrauber, Lothar Kummerlin, Rudiger Kuhn, Silvano Geissler Umsatzsteuer ID Nr.: DE 143 585 507 WEEE Reg. Nr.: DE 31011852 Gleichmann & Co. Electronics GmbH Sitz der Gesellschaft: Schraderstrasse 44, 67227 Frankenthal Handelsregister: Ludwigshafen, Germany, HRB No. 21305 Geschaftsfuhrung: Manfred Schwarztrauber, Thomas Klein Umsatzsteuer ID Nr.: DE 148 421 329 WEEE Reg. Nr.: DE 72277043 ------------------------------ Diese E-Mail enthalt vertrauliche und/ oder rechtlich geschutzte Informationen. Wenn Sie nicht der beabsichtigte Empfanger sind, informieren Sie bitte sofort den Absender und loschen Sie diese E-Mail. The information contained in this message is confidential and/ or protected by law. If you are not the intended recipient, please contact the sender and delete this message.

1 0

[PATCH] TunnelCreek uses ICH7 SPI instead of poulsbo
by Markus Pietrek 27 Jan '12

27 Jan '12

While LPC/FHW is not supported on TunnelCreek, SPI is (see TunnelCreek's HW ref manual 2.13) The SPI controller is compatible to ICH7 Reading has been tested on Q7_TCTC using the command "flashrom -p internal:laptop=force_I_want_a_brick -r /tmp/test.bin" Writing has not been verified! --- chipset_enable.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 21990f6..dc97703 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1217,7 +1217,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4}, {0x8086, 0x8119, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo}, - {0x8086, 0x8186, NT, "Intel", "Atom E6xx(T)/Tunnel Creek", enable_flash_poulsbo}, + {0x8086, 0x8186, NT, "Intel", "Atom E6xx(T)/Tunnel Creek", enable_flash_ich7}, #endif {}, }; -- 1.7.4.1 Es gelten unsere Allgemeinen Leistungsbedingungen die unter http://www.msc-ge.com/alb abrufbar sind. Our standard terms and conditions apply which are available under http://www.msc-ge.com/alb . MSC Vertriebs GmbH Sitz der Gesellschaft: Industriestrasse 16, 76297 Stutensee Handelsregister: Mannheim, HRB Nr. 10 3631 Geschäftsführung: Manfred Schwarztrauber, Lothar Kümmerlin, Rüdiger Kuhn, Silvano Geissler Umsatzsteuer ID Nr.: DE 143 585 507 WEEE Reg. Nr. : DE 31011852 Gleichmann & Co. Electronics GmbH Sitz der Gesellschaft: Schraderstrasse 44, 67227 Frankenthal Handelsregister: Ludwigshafen, HRB Nr. 21305 Geschäftsführung: Manfred Schwarztrauber, Thomas Klein Umsatzsteuer ID Nr. : DE 148 421 329 WEEE Reg. Nr.: DE 72277043 Diese E-Mail enthält vertrauliche und/ oder rechtlich geschützte Informationen. Wenn Sie nicht der beabsichtigte Empfänger sind, informieren Sie bitte sofort den Absender und löschen Sie diese E-Mail. The information contained in this message is confidential and/ or protected by law. If you are not the intended recipient, please contact the sender and delete this message.

4 3

Intel D425KT write not working
by Marek Zakrzewski 27 Jan '12

27 Jan '12

Write is not working, module is 1024kB, ROM is 2048kB. flashrom flashrom v0.9.4-r1486 on Linux 2.6.38.2-xxxx-std-ipv6-64 (x86_64), built with libpci 3.1.7, GCC 4.1.2 20080704 (Red Hat 4.1.2-51), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... delay loop is unreliable, trying to continue OK. -s: No such file or directory dmidecode execution unsuccessful - continuing without DMI info Found chipset "Intel NM10". Enabling flash write... WARNING: Setting 0xdc from 0xa to 0xb on NM10 failed. New value is 0xa. WARNING: SPI Configuration Lockdown activated. PROBLEMS, continuing anyway Found Winbond flash chip "W25Q80" (1024 kB, SPI) at physical address 0xfff00000. No operations were specified. flashrom -Vw flashrom v0.9.4-r1486 on Linux 2.6.38.2-xxxx-std-ipv6-64 (x86_64), built with libpci 3.1.7, GCC 4.1.2 20080704 (Red Hat 4.1.2-51), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 372M loops per second, delay more than 10% too short (got 82% of expected delay), recalculating... 363M loops per second, delay more than 10% too short (got 80% of expected delay), recalculating... 373M loops per second, delay more than 10% too short (got 83% of expected delay), recalculating... 364M loops per second, delay more than 10% too short (got 82% of expected delay), recalculating... 359M loops per second, 10 myus = 8 us, 100 myus = 80 us, 1000 myus = 798 us, 10000 myus = 9481 us, 4 myus = 3 us, OK. Initializing internal programmer No coreboot table found. dmidecode execution unsuccessful - continuing without DMI info Found chipset "Intel NM10" with PCI ID 8086:27bc. Enabling flash write... 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x4 0x7fffffff/0x7fffffff FWH IDSEL: 0x5 0x7fffffff/0x7fffffff FWH IDSEL: 0x6 0x7fffffff/0x7fffffff FWH IDSEL: 0x7 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0xa WARNING: Setting 0xdc from 0xa to 0xb on NM10 failed. New value is 0xa. Root Complex Register Block address = 0xfed1c000 GCS = 0x200465: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3020 0x00: 0x8004 (SPIS) 0x02: 0x4130 (SPIC) 0x04: 0x00000000 (SPIA) 0x08: 0x00140000 (SPID0) 0x0c: 0x00000000 (SPID0+4) 0x10: 0x00000000 (SPID1) 0x14: 0x00000000 (SPID1+4) 0x18: 0xeb4150bf (SPID2) 0x1c: 0x0000001d (SPID2+4) 0x20: 0x00000000 (SPID3) 0x24: 0x00000000 (SPID3+4) 0x28: 0xffff0434 (SPID4) 0x2c: 0xffffff50 (SPID4+4) 0x30: 0x00000000 (SPID5) 0x34: 0x00000000 (SPID5+4) 0x38: 0x8be9090f (SPID6) 0x3c: 0x000000f8 (SPID6+4) 0x40: 0x00000000 (SPID7) 0x44: 0xffff0000 (SPID7+4) 0x50: 0x00000000 (BBAR) 0x54: 0x0006 (PREOP) 0x56: 0x103b (OPTYPE) 0x58: 0x05200302 (OPMENU) 0x5c: 0x0001009f (OPMENU+4) 0x60: 0x00000000 (PBR0) 0x64: 0x00000000 (PBR1) 0x68: 0x00000000 (PBR2) WARNING: SPI Configuration Lockdown activated. Reading OPCODES... done SPI Read Configuration: prefetching enabled, caching enabled, PROBLEMS, continuing anyway The following protocols are supported: SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25LF080A, 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25VF010, 128 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25VF040, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST SST25VF040B.REMS, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Chip status register is 00 Found Winbond flash chip "W25Q80" (1024 kB, SPI) at physical address 0xfff00000. Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4014 Probing for Generic unknown SPI chip (REMS), 0 kB: Invalid OPCODE 0x90, will not execute. Found Winbond flash chip "W25Q80" (1024 kB, SPI). Restoring MMIO space at 0x7fb1c2a0a070 Restoring PCI config space for 00:1f:0 reg 0xdc Found chipset "Intel NM10". Enabling flash write... WARNING: Setting 0xdc from 0xa to 0xb on NM10 failed. New value is 0xa. WARNING: SPI Configuration Lockdown activated. PROBLEMS, continuing anyway Found Winbond flash chip "W25Q80" (1024 kB, SPI) at physical address 0xfff00000. Error: Image size doesn't match

2 4

Support MB Gigabyte GA-EP31-DS3L
by Vít Škaban 27 Jan '12

27 Jan '12

Chips: W28X80 and SST25VF080B Vendor: Gigabyte Mainboard: GA-EP31-DS3L Required option: none Status: OK Thank you for this program. It was very helful for me in reparing laptop BIOS via this mainboard. Vit Skraban Czech Republic EU

2 3

ASUS M4N78 PRO -- flashrom -V
by Pavel Stehlík 24 Jan '12

24 Jan '12

Bios written and read sueccessfully. (On Xubuntu 11.10 Oneiric) Thanks for your work on this utility, Pavel Stehlik. P.S. : Possibility to rewrite Macronix_MX25L8005 status register (user value, 00->FF or something like that) would be welcome. I wont to write-protect my BIOS and besides connecting pin 3(!WP) to gnd, setting of some bits of SR is neccessary.

2 1

Re: [flashrom] Chip SST25VF040 @ flashrom v0.9.4-r1486
by Stefan Tauner 24 Jan '12

24 Jan '12

On Sun, 22 Jan 2012 11:33:52 +0100 Marc Kolly <marc.kolly(a)googlemail.com> wrote: > flashrom v0.9.4-r1486 on Linux 2.6.32-37-generic-pae (i686), built with > […] > Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0xbf, id2 0x44 > Chip status register is 00 > Chip status register: Block Protect Write Disable (BPL) is not set > Chip status register: Auto Address Increment Programming (AAI) is not set > Chip status register: Bit 5 / Block Protect 3 (BP3) is not set > Chip status register: Bit 4 / Block Protect 2 (BP2) is not set > Chip status register: Bit 3 / Block Protect 1 (BP1) is not set > Chip status register: Bit 2 / Block Protect 0 (BP0) is not set > Chip status register: Write Enable Latch (WEL) is not set > Chip status register: Write In Progress (WIP/BUSY) is not set > […] > This flash part has status UNTESTED for operations: ERASE WRITE […] > Reading flash... done. Hello Marc, thanks for your report! Your log does only show a successful read, but this was already tested for this chip. Did you also try erase and write? If you have not and plan to, please store the backup you made with -r safely. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

abit A-S78H: flashrom -V
by Prakash Punnoor 24 Jan '12

24 Jan '12

Hi, after some intial confusion I can confirm that flashrom works nicely on my motherboard. Cheers, Prakash Dumps: flashrom -V flashrom v0.9.4-r1395 on Linux 3.3.0-rc1+ (x86_64), built with libpci 3.1.7, GCC 4.5.2, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1596M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 999 us, 10000 myus = 10000 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "." DMI string system-product-name: "." DMI string system-version: "." DMI string baseboard-manufacturer: "http://www.abit.com.tw/" DMI string baseboard-product-name: "A-S78H(RS780+SB700)" DMI string baseboard-version: "1.x " DMI string chassis-type: "Desktop" Found chipset "AMD SB700/SB710/SB750/SB850" with PCI ID 1002:439d. Enabling flash write... SPI base address is at 0xfec10000 AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0 PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1 SpiArbEnable=0, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, ArbWaitCount=0, SpiBridgeDisable=0, DropOneClkOnRd=0 NormSpeed is 33 MHz GPIO11 used for SPI_DO GPIO12 used for SPI_DI GPIO31 used for SPI_HOLD GPIO32 used for SPI_CS GPIO47 used for SPI_CLK SB700 IMC is not active. ROM strap override is not active OK. This chipset supports the following protocols: LPC, FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0x67, id2 0x6c, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x67, id2 0x6c, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x4d, id2 0x49, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found Macronix flash chip "MX25L8005" (1024 kB, SPI) at physical address 0xfff00000. Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x67, id2 0x6c, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x4d, id2 0x49, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25LF040A.RES, 512 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x8a, id2 0xba, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x67, id2 0x6c, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x67, id2 0x6c, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x4d, id2 0x49, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x4d, id2 0x49, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0x4d, id2 0x49, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0x67, id2 0x6c, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0x67, id2 0x6c, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4d, id2 0x49, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0x4d, id2 0x49, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x67, id2 0x6c, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x67, id2 0x6c, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x4d, id2 0x49, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x4d, id2 0x49, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0x4d, id2 0x49, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x67, id2 0x6c, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x4d, id2 0x49, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0x4d, id2 0x49, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0x67, id2 0x6c, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0x67, id2 0x6c, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0x67, id2 0x6c, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x67, id2 0x6c, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x67, id2 0x6c, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x67, id2 0x6c, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0x4d, id2 0x49, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x4d, id2 0x49, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x67, id2 0x6c, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xc2, id2 0x13 No operations were specified. lspci -nnvvxxx 00:00.0 Host bridge [0600]: Advanced Micro Devices [AMD] RS780 Host Bridge [1022:9600] Subsystem: ABIT Computer Corp. Device [147b:a705] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 64 Region 3: Memory at <ignored> (64-bit, non-prefetchable) Capabilities: [c4] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=12 MastHost- DefDir- DUL- Link Control 0: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 3.00 Link Frequency 0: [b] Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE- OFlE- PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [54] HyperTransport: UnitID Clumping Capabilities: [40] HyperTransport: Retry Mode Capabilities: [9c] HyperTransport: #1a Capabilities: [f8] HyperTransport: #1c 00: 22 10 00 96 06 00 30 22 00 00 00 06 00 40 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 e0 20: 00 00 00 00 00 00 00 00 00 00 00 00 7b 14 05 a7 30: 00 00 00 00 c4 00 00 00 00 00 00 00 00 00 00 00 40: 08 9c 00 c0 c1 00 00 00 00 00 00 00 42 20 05 00 50: 7b 14 05 a7 08 40 00 90 08 10 05 00 08 00 cc 51 60: 7f 00 00 00 00 00 00 00 00 02 20 00 09 80 8e 81 70: 00 00 00 00 00 00 00 00 70 23 0f 00 00 00 00 20 80: 00 00 00 00 10 00 00 03 20 01 00 00 33 26 00 00 90: 00 00 00 d8 7f 00 00 00 00 00 00 00 08 f8 7c d0 a0: 26 00 74 00 00 00 00 80 00 00 00 00 79 01 40 05 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 80 08 54 80 01 20 00 11 11 d0 00 00 00 d0: 60 0b 75 1c 02 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 0c 02 00 00 00 00 00 0f f0: 00 00 00 00 00 80 80 00 08 00 00 e0 00 00 00 00 00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780/RS880 PCI to PCI bridge (int gfx) [1022:9602] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 99 Bus: primary=00, secondary=01, subordinate=01, sec-latency=68 I/O behind bridge: 0000e000-0000efff Memory behind bridge: fdc00000-fddfffff Prefetchable memory behind bridge: 00000000d8000000-00000000dfffffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [44] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] RS780/RS880 PCI to PCI bridge (int gfx) [1022:9602] 00: 22 10 02 96 07 00 30 02 00 00 04 06 00 63 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 44 e1 e1 20 02 20: c0 fd d0 fd 01 d8 f1 df 00 00 00 00 00 00 00 00 30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 08 00 40: 00 00 00 00 08 b0 03 a8 00 00 00 00 22 10 02 96 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 0d 00 00 00 22 10 02 96 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:09.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780/RS880 PCI to PCI bridge (PCIE port 4) [1022:9608] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 0000d000-0000dfff Memory behind bridge: fdb00000-fdbfffff Prefetchable memory behind bridge: 00000000fda00000-00000000fdafffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #9, PowerLimit 25.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Not Supported, TimeoutDis- ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0f00c Data: 4151 Capabilities: [b0] Subsystem: ABIT Computer Corp. Device [147b:a705] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [110 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport 00: 22 10 08 96 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 d1 d1 00 00 20: b0 fd b0 fd a1 fd a1 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 03 c8 00 00 00 00 10 a0 42 01 20 80 00 00 60: 10 08 00 00 12 0c 30 00 40 00 11 70 80 0c 4c 00 70: 00 00 48 01 00 00 01 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 b0 01 00 0c f0 e0 fe 51 41 00 00 00 00 00 00 b0: 0d b8 00 00 7b 14 05 a7 08 00 03 a8 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0a.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780/RS880 PCI to PCI bridge (PCIE port 5) [1022:9609] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: 0000c000-0000cfff Memory behind bridge: fdf00000-fdffffff Prefetchable memory behind bridge: 00000000fde00000-00000000fdefffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #10, PowerLimit 25.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Not Supported, TimeoutDis- ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0f00c Data: 4159 Capabilities: [b0] Subsystem: ABIT Computer Corp. Device [147b:a705] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [110 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport 00: 22 10 09 96 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 03 03 00 c1 c1 00 00 20: f0 fd f0 fd e1 fd e1 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 05 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 03 c8 00 00 00 00 10 a0 42 01 20 80 00 00 60: 10 08 00 00 12 0c 30 01 40 00 11 70 80 0c 54 00 70: 00 00 48 01 00 00 01 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 b0 01 00 0c f0 e0 fe 59 41 00 00 00 00 00 00 b0: 0d b8 00 00 7b 14 05 a7 08 00 03 a8 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:11.0 SATA controller [0106]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] [1002:4391] (prog-if 01 [AHCI 1.0]) Subsystem: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] [1002:4391] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 96, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 43 Region 0: I/O ports at ff00 [size=8] Region 1: I/O ports at fe00 [size=4] Region 2: I/O ports at fd00 [size=8] Region 3: I/O ports at fc00 [size=4] Region 4: I/O ports at fb00 [size=16] Region 5: Memory at fe02f000 (32-bit, non-prefetchable) [size=1K] Capabilities: [60] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable+ Count=1/4 Maskable- 64bit+ Address: 00000000fee0f00c Data: 4169 Capabilities: [70] SATA HBA v1.0 InCfgSpace Kernel driver in use: ahci 00: 02 10 91 43 07 00 30 02 00 01 06 01 10 60 00 00 10: 01 ff 00 00 01 fe 00 00 01 fd 00 00 01 fc 00 00 20: 01 fb 00 00 00 f0 02 fe 00 00 00 00 02 10 91 43 30: 00 00 00 00 60 00 00 00 00 00 00 00 0b 01 00 00 40: 10 00 00 20 01 00 10 00 00 00 20 01 00 00 00 00 50: 05 70 85 00 0c f0 e0 fe 00 00 00 00 69 41 00 00 60: 01 50 22 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 12 00 10 00 0f 00 00 00 10 03 00 00 00 00 00 00 80: 00 00 00 00 06 00 00 2c 1a 80 b4 01 1a 80 b4 01 90: 1a 80 b4 01 1a 80 b4 01 1a 80 b4 01 1a 80 b4 01 a0: ef a0 ef a0 ef a0 ef a0 ef a0 ef a0 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 20 00 00 e0: 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:12.0 USB controller [0c03]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] (prog-if 10 [OHCI]) Subsystem: ABIT Computer Corp. Device [147b:a705] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 49 Region 0: Memory at fe02e000 (32-bit, non-prefetchable) [size=4K] Capabilities: [d0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0f00c Data: 41a9 Kernel driver in use: ohci_hcd 00: 02 10 97 43 06 00 b0 02 00 10 03 0c 10 40 80 00 10: 00 e0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 7b 14 05 a7 30: 00 00 00 00 d0 00 00 00 00 00 00 00 07 01 00 00 40: 80 00 00 00 11 00 00 00 00 00 00 00 00 00 00 00 50: 40 13 01 f0 00 00 00 00 ff ff ff ff 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 05 00 01 00 0c f0 e0 fe a9 41 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:12.1 USB controller [0c03]: Advanced Micro Devices [AMD] nee ATI SB7x0 USB OHCI1 Controller [1002:4398] (prog-if 10 [OHCI]) Subsystem: ABIT Computer Corp. Device [147b:a705] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 50 Region 0: Memory at fe02d000 (32-bit, non-prefetchable) [size=4K] Capabilities: [d0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0f00c Data: 41b1 Kernel driver in use: ohci_hcd 00: 02 10 98 43 06 00 b0 02 00 10 03 0c 10 40 00 00 10: 00 d0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 7b 14 05 a7 30: 00 00 00 00 d0 00 00 00 00 00 00 00 07 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 05 00 01 00 0c f0 e0 fe b1 41 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:12.2 USB controller [0c03]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] (prog-if 20 [EHCI]) Subsystem: ABIT Computer Corp. Device [147b:a705] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 47 Region 0: Memory at fe02c000 (32-bit, non-prefetchable) [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Bridge: PM- B3+ Capabilities: [d0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0f00c Data: 4189 Capabilities: [e4] Debug port: BAR=1 offset=00e0 Kernel driver in use: ehci_hcd 00: 02 10 96 43 16 00 b0 02 00 20 03 0c 10 40 00 00 10: 00 c0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 7b 14 05 a7 30: 00 00 00 00 c0 00 00 00 00 00 00 00 0a 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 1e 98 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 00 00 01 00 00 08 e0 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 d0 02 7e 00 00 40 00 00 00 00 00 00 00 00 00 d0: 05 e4 01 00 0c f0 e0 fe 89 41 00 00 00 00 00 00 e0: 00 00 00 00 0a 00 e0 20 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:13.0 USB controller [0c03]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] (prog-if 10 [OHCI]) Subsystem: ABIT Computer Corp. Device [147b:a705] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 51 Region 0: Memory at fe02b000 (32-bit, non-prefetchable) [size=4K] Capabilities: [d0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0f00c Data: 41b9 Kernel driver in use: ohci_hcd 00: 02 10 97 43 06 00 b0 02 00 10 03 0c 10 40 80 00 10: 00 b0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 7b 14 05 a7 30: 00 00 00 00 d0 00 00 00 00 00 00 00 05 01 00 00 40: 80 00 00 00 11 00 00 00 00 00 00 00 00 00 00 00 50: 40 13 01 f0 00 00 00 00 ff ff ff ff 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 05 00 01 00 0c f0 e0 fe b9 41 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:13.1 USB controller [0c03]: Advanced Micro Devices [AMD] nee ATI SB7x0 USB OHCI1 Controller [1002:4398] (prog-if 10 [OHCI]) Subsystem: ABIT Computer Corp. Device [147b:a705] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 52 Region 0: Memory at fe02a000 (32-bit, non-prefetchable) [size=4K] Capabilities: [d0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0f00c Data: 41c1 Kernel driver in use: ohci_hcd 00: 02 10 98 43 06 00 b0 02 00 10 03 0c 10 40 00 00 10: 00 a0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 7b 14 05 a7 30: 00 00 00 00 d0 00 00 00 00 00 00 00 05 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 05 00 01 00 0c f0 e0 fe c1 41 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:13.2 USB controller [0c03]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] (prog-if 20 [EHCI]) Subsystem: ABIT Computer Corp. Device [147b:a705] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 48 Region 0: Memory at fe029000 (32-bit, non-prefetchable) [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Bridge: PM- B3+ Capabilities: [d0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0f00c Data: 4199 Capabilities: [e4] Debug port: BAR=1 offset=00e0 Kernel driver in use: ehci_hcd 00: 02 10 96 43 16 00 b0 02 00 20 03 0c 10 40 00 00 10: 00 90 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 7b 14 05 a7 30: 00 00 00 00 c0 00 00 00 00 00 00 00 03 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 1e 98 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 00 00 01 00 00 08 e0 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 d0 02 7e 00 00 40 00 00 00 00 00 00 00 00 00 d0: 05 e4 01 00 0c f0 e0 fe 99 41 00 00 00 00 00 00 e0: 00 00 00 00 0a 00 e0 20 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.0 SMBus [0c05]: Advanced Micro Devices [AMD] nee ATI SBx00 SMBus Controller [1002:4385] (rev 3a) Subsystem: ABIT Computer Corp. Device [147b:a705] Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [b0] HyperTransport: MSI Mapping Enable- Fixed+ 00: 02 10 85 43 03 04 30 02 3a 00 05 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 7b 14 05 a7 30: 00 00 00 00 b0 00 00 00 00 00 00 00 00 00 00 00 40: 44 7b 00 fc 00 00 00 00 0f ff 00 00 00 00 00 80 50: f0 01 f0 00 f0 00 f0 00 21 0b 78 8f 00 00 00 00 60: 01 00 24 20 bf fc de 02 7f 90 00 00 20 00 00 00 70: 00 00 00 00 08 00 c0 fe ff 6e 00 00 00 00 f0 0f 80: f0 0a f0 0f 00 00 00 00 00 00 00 00 00 00 00 00 90: 01 0b 00 00 f9 ce ff 00 00 00 00 00 00 00 00 00 a0: 00 00 ff ff 7f ff f0 09 00 ff 22 02 16 71 20 18 b0: 08 00 02 a8 00 00 d0 fe 00 00 00 00 f0 0f 08 1a c0: 09 60 e0 df 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 20 b9 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: d8 0c 00 00 00 00 44 00 00 00 00 00 fe 00 30 00 00:14.1 IDE interface [0101]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 IDE Controller [1002:439c] (prog-if 8f [Master SecP SecO PriP PriO]) Subsystem: ABIT Computer Corp. Device [147b:a705] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 44 Region 0: I/O ports at 1000 [size=8] Region 1: I/O ports at 1010 [size=4] Region 2: I/O ports at 1008 [size=8] Region 3: I/O ports at 1014 [size=4] Region 4: I/O ports at fa00 [size=16] Capabilities: [70] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0f00c Data: 4171 Kernel driver in use: pata_atiixp 00: 02 10 9c 43 05 00 30 02 00 8f 01 01 10 40 00 00 10: 01 10 00 00 11 10 00 00 09 10 00 00 15 10 00 00 20: 01 fa 00 00 00 00 00 00 00 00 00 00 7b 14 05 a7 30: 00 00 00 00 70 00 00 00 00 00 00 00 ff 01 00 00 40: 5d 20 5d 5d ff 20 ff ff 00 00 04 00 00 00 00 00 50: 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 60: 00 00 40 24 10 2c 01 07 01 00 00 00 ff ff 0f 00 70: 05 00 01 00 0c f0 e0 fe 71 41 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.2 Audio device [0403]: Advanced Micro Devices [AMD] nee ATI SBx00 Azalia (Intel HDA) [1002:4383] Subsystem: ABIT Computer Corp. Device [147b:a705] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 53 Region 0: Memory at fe024000 (64-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [60] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0f00c Data: 41c9 Kernel driver in use: snd_hda_intel 00: 02 10 83 43 06 04 10 04 00 00 03 04 10 40 00 00 10: 04 40 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 7b 14 05 a7 30: 00 00 00 00 50 00 00 00 00 00 00 00 07 01 00 00 40: 00 00 02 00 01 01 00 00 00 00 00 00 01 00 00 00 50: 01 60 42 c8 00 00 00 00 00 00 00 00 00 00 00 00 60: 05 00 81 00 0c f0 e0 fe 00 00 00 00 c9 41 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.3 ISA bridge [0601]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 LPC host controller [1002:439d] Subsystem: ABIT Computer Corp. Device [147b:a705] Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 00: 02 10 9d 43 0f 00 20 02 00 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 7b 14 05 a7 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 04 00 00 00 d5 ff 03 ff 3f ff 40 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 02 00 00 00 00 0f 00 b8 ff ff ff 70: 67 45 23 00 00 00 00 00 1d 00 00 00 05 0b 00 00 80: 08 00 03 a8 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00 00 a0: 02 00 c1 fe 2f 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 e9 f2 ff 00 00 c0: 00 00 00 00 00 00 08 00 f7 ff ff ff 00 00 00 78 d0: 00 ff ff 00 00 00 00 ff ff ff ff 00 00 00 00 0c e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.4 PCI bridge [0604]: Advanced Micro Devices [AMD] nee ATI SBx00 PCI to PCI Bridge [1002:4384] (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop+ ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Bus: primary=00, secondary=04, subordinate=04, sec-latency=64 I/O behind bridge: 0000b000-0000bfff Memory behind bridge: fd900000-fd9fffff Prefetchable memory behind bridge: fd800000-fd8fffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [54] HyperTransport: MSI Mapping Enable+ Fixed+ 00: 02 10 84 43 27 00 b0 02 00 01 04 06 00 40 81 00 10: 00 00 00 00 00 00 00 00 00 04 04 40 b0 b0 80 22 20: 90 fd 90 fd 80 fd 80 fd 00 00 00 00 00 00 00 00 30: 00 00 00 00 54 00 00 00 00 00 00 00 00 00 00 00 40: 2e 00 0c ff 00 00 00 00 0c 0f 3c d1 00 01 00 00 50: 01 00 00 00 08 00 03 a8 00 00 00 00 85 00 ff ff 60: ca 0e 17 00 ba d8 10 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 02 06 e0: 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration [1022:1200] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn+ ExtCTL- 64b- Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Revision ID: 3.00 Link Frequency: [b] Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz+ 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA+ UIDRD- ExtRS- UCnfE- 00: 22 10 00 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 02 04 00 01 02 04 00 01 02 04 00 01 02 04 00 50: 01 02 04 00 01 02 04 00 01 02 04 00 01 02 04 00 60: 00 00 03 00 e0 00 00 00 20 a8 2e 01 00 f8 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 00 01 21 20 20 11 11 60 0b f5 8f 13 00 00 00 90: d0 02 85 80 00 00 00 00 07 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor Address Map [1022:1201] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 01 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 27 01 00 00 00 00 01 00 00 00 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 03 0a 00 00 00 0b 00 00 00 00 00 00 00 00 00 00 90: 03 00 d8 00 00 ff df 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 03 00 f0 00 00 02 fe 00 b0: 03 00 e0 00 80 4f e0 00 00 00 00 00 00 00 00 00 c0: 13 b0 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 f0: 03 28 00 d8 00 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller [1022:1202] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 02 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 00 00 00 01 01 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: e0 3e 78 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 06 00 48 0f 00 00 00 00 80: 05 00 00 00 00 00 00 00 24 fa 7c 5d 45 03 22 00 90: 10 04 01 00 0b 80 58 7f 07 42 00 8d 00 00 00 00 a0: 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: eb 6d 32 a6 4e 00 00 00 2e 3a 32 0a d6 88 24 93 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 22 fb c8 52 79 53 ac 89 06 c7 96 0c a2 7d 64 01 e0: 6c c1 d9 13 56 71 d0 e6 71 3f eb 80 6d 5f 48 54 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control [1022:1203] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [f0] Secure device <?> Kernel driver in use: k10temp 00: 22 10 03 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 40: 00 01 00 00 5c 00 b0 4a 00 00 00 00 00 00 00 00 50: ee 1d 40 9a 93 4c 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 04 00 24 34 00 00 00 30 51 80 01 60 70: 51 11 32 60 01 01 98 00 14 0c 20 00 0d 08 07 00 80: 81 e6 00 e6 e6 41 e6 01 08 00 00 00 00 40 40 00 90: 43 00 00 00 66 00 00 00 00 77 1b 01 00 00 00 00 a0: 00 08 1c a0 80 18 88 10 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 39 c5 04 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 26 0f 81 c8 16 18 00 03 28 63 47 01 e0: 00 00 00 00 30 1a 40 1c 59 7f 07 00 00 00 00 00 f0: 0f 00 10 00 00 00 00 00 00 00 00 00 53 0f 10 00 00:18.4 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor Link Control [1022:1204] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 04 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:05.0 VGA compatible controller [0300]: Advanced Micro Devices [AMD] nee ATI RS780 [Radeon HD 3200] [1002:9610] (prog-if 00 [VGA controller]) Subsystem: ABIT Computer Corp. Device [147b:a705] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at d8000000 (32-bit, prefetchable) [size=128M] Region 1: I/O ports at ee00 [size=256] Region 2: Memory at fddf0000 (32-bit, non-prefetchable) [size=64K] Region 5: Memory at fdc00000 (32-bit, non-prefetchable) [size=1M] Expansion ROM at <unassigned> [disabled] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Kernel driver in use: radeon Kernel modules: radeon 00: 02 10 10 96 07 00 10 00 00 00 00 03 10 00 80 00 10: 08 00 00 d8 01 ee 00 00 00 00 df fd 00 00 00 00 20: 00 00 00 00 00 00 c0 fd 00 00 00 00 7b 14 05 a7 30: 00 00 00 00 50 00 00 00 00 00 00 00 05 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 7b 14 05 a7 50: 01 a0 03 06 00 00 00 00 10 a0 12 00 a0 8f 00 00 60: 10 08 0a 00 01 0d 00 00 00 00 01 11 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 1f 00 00 00 80: 00 00 00 00 00 00 00 00 01 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] (rev 01) Subsystem: Realtek Semiconductor Co., Ltd. TEG-ECTX Gigabit PCI-E Adapter [Trendnet] [10ec:8168] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 46 Region 0: I/O ports at de00 [size=256] Region 2: Memory at fdbff000 (64-bit, non-prefetchable) [size=4K] [virtual] Expansion ROM at fda00000 [disabled] [size=128K] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] Vital Product Data Unknown small resource type 05, will not decode more. Capabilities: [50] MSI: Enable+ Count=1/2 Maskable- 64bit+ Address: 00000000fee0f00c Data: 4181 Capabilities: [60] Express (v1) Endpoint, MSI 00 DevCap: MaxPayload 1024 bytes, PhantFunc 0, Latency L0s <1us, L1 unlimited ExtTag+ AttnBtn+ AttnInd+ PwrInd+ RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 4096 bytes DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s, Latency L0 unlimited, L1 unlimited ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [84] Vendor Specific Information: Len=4c <?> Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- AERCap: First Error Pointer: 14, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [12c v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Capabilities: [148 v1] Device Serial Number 45-12-00-00-10-ec-81-68 Capabilities: [154 v1] Power Budgeting <?> Kernel driver in use: r8169 00: ec 10 68 81 07 04 10 00 01 00 00 02 10 00 00 00 10: 01 de 00 00 00 00 00 00 04 f0 bf fd 00 00 00 00 20: 00 00 00 00 00 00 00 00 02 01 00 00 ec 10 68 81 30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 01 00 00 40: 01 48 c2 f7 00 00 00 00 03 50 00 00 29 81 ec 10 50: 05 60 83 00 0c f0 e0 fe 00 00 00 00 81 41 00 00 60: 10 84 01 00 23 7f 00 00 10 58 1a 00 41 f4 03 00 70: 40 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 09 00 4c 01 01 1c 02 00 fb ff ff 11 90: 08 30 00 00 7f e2 0f 00 8f a0 03 00 c3 00 00 00 a0: 02 28 ff 01 00 00 00 00 00 08 00 00 03 00 03 00 b0: 00 00 00 00 ff 3f ff 3f ff ff 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03:00.0 Ethernet controller [0200]: Marvell Technology Group Ltd. 88E8056 PCI- E Gigabit Ethernet Controller [11ab:4364] (rev 14) Subsystem: ABIT Computer Corp. Device [147b:a705] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 45 Region 0: Memory at fdffc000 (64-bit, non-prefetchable) [size=16K] Region 2: I/O ports at ce00 [size=256] [virtual] Expansion ROM at fde00000 [disabled] [size=128K] Capabilities: [48] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data Product Name: Marvell Yukon 88E8056 Gigabit Ethernet Controller Read-only fields: [PN] Part number: Yukon 88E8056 [EC] Engineering changes: Rev. 1.4 [MN] Manufacture ID: 4d 61 72 76 65 6c 6c [SN] Serial number: AbCdEfG0439C2 [CP] Extended capability: 01 10 cc 03 [RV] Reserved: checksum good, 9 byte(s) reserved Read/write fields: [RW] Read-write area: 121 byte(s) free End Capabilities: [5c] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0f00c Data: 4179 Capabilities: [e0] Express (v1) Legacy Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 unlimited ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 1f, GenCap- CGenEn- ChkCap- ChkEn- Kernel driver in use: sky2 00: ab 11 64 43 07 04 10 00 14 00 00 02 10 00 00 00 10: 04 c0 ff fd 00 00 00 00 01 ce 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 7b 14 05 a7 30: 00 00 00 00 48 00 00 00 00 00 00 00 05 01 00 00 40: 00 00 f0 01 00 80 a0 01 01 50 03 fe 00 20 00 13 50: 03 5c fc 80 00 00 00 78 00 00 34 01 05 e0 81 00 60: 0c f0 e0 fe 00 00 00 00 79 41 00 00 00 00 00 00 70: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 70 00 00 00 00 00 00 82 a8 e8 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 10 00 11 00 c0 8f 64 00 00 20 19 00 11 ac 07 01 f0: 48 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00 superiotool -deV superiotool r Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xc000, id=0x23a0 Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xa023, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0xa023 Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0xa023, rev=0x00 Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Found Winbond W83627DHG (id=0xa0, rev=0x23) at 0x2e Register dump: idx 02 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f val ff a0 23 ff 00 c0 00 00 ff 50 00 7c 00 ea 00 00 ff def 00 a0 NA ff 00 MM 00 MM RR 50 00 00 RR e2 21 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val 00 00 00 00 04 0e 00 ff 00 00 def 01 03 f0 06 02 8e 00 ff 00 00 LDN 0x01 (Parallel port) idx 30 60 61 70 74 f0 val 00 00 00 00 04 3f def 01 03 78 07 04 3f LDN 0x02 (COM1) idx 30 60 61 70 f0 val 00 00 00 00 00 def 01 03 f8 04 00 LDN 0x03 (COM2) idx 30 60 61 70 f0 f1 val 00 00 00 00 00 00 def 01 02 f8 03 00 00 LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 72 f0 val 01 00 60 00 64 01 0c 83 def 01 00 60 00 64 01 0c 83 LDN 0x06 (Serial peripheral interface) idx 30 62 63 val 00 ff ff def 00 00 00 LDN 0x07 (GPIO 6) idx 30 f4 f5 f6 f7 val 06 ff ff ff ff def 00 ff 00 00 00 LDN 0x08 (WDTO#, PLED) idx 30 f5 f6 f7 val 01 00 00 00 def 00 00 00 00 LDN 0x09 (GPIO 2, GPIO 3, GPIO 4, GPIO 5) idx 30 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f0 f1 f2 f3 f4 f5 f6 f7 fe val 07 ff ff ff ff 0c 00 00 e3 ff ff 9c 80 63 00 20 a4 db 00 00 def 00 ff 00 00 ff 00 00 00 00 00 00 ff 00 00 00 ff 00 00 00 00 LDN 0x0a (ACPI) idx 30 70 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f2 f3 f4 f6 f7 fe val 00 00 00 00 12 24 00 00 0c 00 09 00 7d 00 00 00 08 00 def 00 00 01 00 ff 08 00 RR 1c 00 RR RR 7c 00 00 00 00 00 LDN 0x0b (Hardware monitor) idx 30 60 61 70 f0 f1 f2 val 01 02 90 02 81 ff 81 def 00 00 00 00 81 00 00 LDN 0x0c (PECI, SST) idx e0 e1 e2 e3 e4 e5 e8 f1 fe ff val 00 48 48 48 48 00 00 48 ff ff def 00 48 48 48 48 00 00 48 00 00 Hardware monitor (0x0295) Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. Probing for AMD EC Super I/O at 0xaa... Probing for Server Engines Super I/O at 0x2e... Failed. Returned data: id=0xffff, rev=0xff Probing for Infineon Super I/O at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for Infineon Super I/O at 0x4e... Failed. Returned data: id=0xff, rev=0xff

2 1

Re: [flashrom] Difference of factory bios and dumped image
by Prakash Punnoor 23 Jan '12

23 Jan '12

On Saturday 31 December 2011 13:55:45 Idwer Vollering wrote: > 2011/12/31 Prakash Punnoor <prakashp(a)arcor.de>: > > On 31.12.2011 11:39, Paul Menzel wrote: > >> Am Samstag, den 31.12.2011, 10:55 +0100 schrieb Prakash Punnoor: > >>> flashrom kind of works on my system, but not with the factory > >>> images. If I read it out with flashrom and write it back with > >>> flashrom (also to a different chip) it works. The sizes of factory > >>> and dumped image are same but they are somewhat binary different. > >>> Any idea? The motherboard is Abit A-S78H. As I am playing around > >>> with coreboot - so far unsuccessfully - I want to know whether > >>> flashrom is writing the generated image correctly... I can upload > >>> both images somewhere if interested. This is flashrom output on my > >>> system: > >>> > >>> > >>> flashrom v0.9.4-r1395 on Linux 3.2.0-rc7+ (x86_64), built with > >>> libpci 3.1.7, GCC 4.5.2, little endian > >>> flashrom is free software, get the source code at > >>> http://www.flashrom.org > >>> > >>> Calibrating delay loop... OK. > >>> Found chipset "AMD SB700/SB710/SB750/SB850". Enabling flash write... > >>> OK. This chipset supports the following protocols: LPC, FWH, SPI. > >>> Found Macronix flash chip "MX25L8005" (1024 kB, SPI) at physical > >>> address 0xfff00000. > >>> No operations were specified. > >> > >> Unfortunately this question seems not be listed in the FAQ. Most of > >> the > >> time some areas differ because the MAC address and other configuration > >> data of the downloaded images differs [2]. I hope you mean the > >> downloaded image by factory/vendor image. > > > > To clarify: > > - Image I got from vendor web page: Flashed with flashrom won't work > > (machine doesn't POST). Flashed with awdflash works. > > Is the bootblock in the downloaded image intact/present? You can use > bios_extract: http://cgit.freedesktop.org/~libv/bios_extract > > What happens when you reset the CMOS/ESCD data after flashing with > flashrom? awdflash does that with the /cp parameter, see > http://www.plasma-online.de/textual/howto/flash_award.html For what is worth, I tried flashing dumped file and then factory bios on top. this worked, so I guess everythign is alright. I'l send a separate mail for inclusion in wiki. Regards, Prakash

1 0

Chip SST25VF040 @ flashrom v0.9.4-r1486
by Marc Kolly 22 Jan '12

22 Jan '12

flashrom v0.9.4-r1486 on Linux 2.6.32-37-generic-pae (i686), built with libpci 3.0.0, GCC 4.4.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1823M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 982 us, 10000 myus = 10131 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "LENOVO" DMI string system-product-name: "898573G" DMI string system-version: "ThinkCentre M55E" DMI string baseboard-manufacturer: "LENOVO" DMI string baseboard-product-name: "LENOVO" DMI string baseboard-version: "Not Specified" DMI string chassis-type: "Mini Tower" Found ITE Super I/O, ID 0x8718 on port 0x2e Found chipset "Intel ICH7/ICH7R" with PCI ID 8086:27b8. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 Root Complex Register Block address = 0xfed1c000 GCS = 0x464: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3020 0x00: 0x0004 (SPIS) 0x02: 0x7f10 (SPIC) 0x04: 0x0007ffc0 (SPIA) 0x08: 0x27c88086 (SPID0) 0x0c: 0x0000ffff (SPID0+4) 0x10: 0xd5b00000 (SPID1) 0x14: 0x27c98086 (SPID1+4) 0x18: 0x0000ffff (SPID2) 0x1c: 0xd5ba0000 (SPID2+4) 0x20: 0x27ca8086 (SPID3) 0x24: 0x0000ffff (SPID3+4) 0x28: 0xd5c40000 (SPID4) 0x2c: 0x27cb8086 (SPID4+4) 0x30: 0x0000ffff (SPID5) 0x34: 0xd5ce0000 (SPID5+4) 0x38: 0x00e1f5e9 (SPID6) 0x3c: 0x00000000 (SPID6+4) 0x40: 0x00e260ea (SPID7) 0x44: 0x000000f0 (SPID7+4) 0x50: 0x00000000 (BBAR) 0x54: 0x5006 (PREOP) 0x56: 0x463b (OPTYPE) 0x58: 0x05d80302 (OPMENU) 0x5c: 0xc79f0190 (OPMENU+4) 0x60: 0x00000000 (PBR0) 0x64: 0x00000000 (PBR1) 0x68: 0x00000000 (PBR2) Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done SPI Read Configuration: prefetching disabled, caching enabled, OK. No IT87* serial flash segment enabled. The following protocols are supported: SPI. Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0xbf, id2 0x44 Chip status register is 00 Chip status register: Block Protect Write Disable (BPL) is not set Chip status register: Auto Address Increment Programming (AAI) is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found SST flash chip "SST25VF040" (512 kB, SPI) at physical address 0xfff80000. === This flash part has status UNTESTED for operations: ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -VE, -Vw), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Reading flash... done. Restoring MMIO space at 0xb7787070 Restoring MMIO space at 0xb778707c Restoring MMIO space at 0xb7787078 Restoring MMIO space at 0xb7787076 Restoring MMIO space at 0xb7787074

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Re: [flashrom] Mainboard no tested
by Stefan Tauner 21 Jan '12

21 Jan '12

hello again this looks like it needs way more work than i thought in the beginning. the flash chip is probably behind the super i/o chip (fintek F71882) which flashrom does not yet support. there has been a patch in the works for a long time, but i think there was not much demand/testers to finish it. could you please apply the following patch to r1455 of flashrom, recompile, run flashrom -V and send us the log? http://patchwork.coreboot.org/patch/3440/ this will *not* enable you to use flashrom as a programmer, but it might induce further development. i think it is safe to test (no flash access is done). i will inform the author of the patch that a new victim^Wtester arrived ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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successfull Flash log [was Re: [PATCH] Add board enable for AOpen D2544-B1 (used in FCS ESPRIMO Q5010)]
by Oliver Rath 19 Jan '12

19 Jan '12

Hi stefan, Ive added a verbose log of flash the esprimo machine. The flashing with the modified bios runs, but the additional functionality seems hidden. Regards, Oliver

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[commit] r1486 - trunk
by repository service 19 Jan '12

19 Jan '12

Author: stefanct Date: Thu Jan 19 18:50:32 2012 New Revision: 1486 URL: http://flashrom.org/trac/flashrom/changeset/1486 Log: Add board enable for AOpen i945GMx-VFX (used in FCS ESPRIMO Q5010) Typical AWARD enable structure with an ICH GPIO board enable. This board seems also to be known as D2544-B1. Success report: http://www.flashrom.org/pipermail/flashrom/2012-January/008590.html Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Tested-by: Oliver Rath <rath(a)mglug.de> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Thu Jan 12 14:58:43 2012 (r1485) +++ trunk/board_enable.c Thu Jan 19 18:50:32 2012 (r1486) @@ -1560,6 +1560,16 @@ /* * Suited for: + * - AOpen i945GMx-VFX: Intel 945GM + ICH7-M used in ... + * - FCS ESPRIMO Q5010 (SMBIOS: D2544-B1) + */ +static int intel_ich_gpio38_raise(void) +{ + return intel_ich_gpio_set(38, 1); +} + +/* + * Suited for: * - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M */ static int intel_ich_gpio43_raise(void) @@ -2098,6 +2108,7 @@ {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, P3, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", P3, "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", P3, "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, + {0x8086, 0x27b9, 0xa0a0, 0x0632, 0x8086, 0x27da, 0xa0a0, 0x0632, NULL, NULL, NULL, P3, "AOpen", "i945GMx-VFX", 0, OK, intel_ich_gpio38_raise}, {0x8086, 0x277c, 0xa0a0, 0x060b, 0x8086, 0x27da, 0xa0a0, 0x060b, NULL, NULL, NULL, P3, "AOpen", "i975Xa-YDG", 0, OK, board_aopen_i975xa_ydg}, {0x8086, 0x27b8, 0x1849, 0x27b8, 0x8086, 0x27da, 0x1849, 0x27da, "^ConRoeXFire-eSATA2", NULL, NULL, P3, "ASRock", "ConRoeXFire-eSATA2", 0, OK, intel_ich_gpio16_raise}, {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Thu Jan 12 14:58:43 2012 (r1485) +++ trunk/print.c Thu Jan 19 18:50:32 2012 (r1486) @@ -556,6 +556,7 @@ B("Advantech", "PCM-5820", 1, "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm", NULL), B("agami", "Aruma", 1, "http://web.archive.org/web/20080212111524/http://www.agami.com/site/ais-600…", NULL), B("Albatron", "PM266A Pro", 1, "http://www.albatron.com.tw/English/Product/MB/pro_detail.asp?rlink=Overview…", NULL), /* FIXME */ + B("AOpen", "i945GMx-VFX", 1, NULL, "This is (also?) an OEM board from FCS (used in e.g. ESPRIMO Q5010 with designation D2544-B1)."), B("AOpen", "vKM400Am-S", 1, "http://usa.aopen.com/products_detail.aspx?Auno=824", NULL), B("Artec Group","DBE61", 1, "http://wiki.thincan.org/DBE61", NULL), B("Artec Group","DBE62", 1, "http://wiki.thincan.org/DBE62", NULL),

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ASRock 775i65g, Flashrom r1485: log files (`flashrom -V`, …)
by Paul Menzel 18 Jan '12

18 Jan '12

Dear Flashrom folks, this board [1] is already listed as supported [2], but having captured the output of the successful read, erase and write operations I send it to the list anyway. I also sent some more log files to the coreboot list [3]. Thanks, Paul [1] http://www.asrock.com/MB/overview.asp?Model=775i65G [2] http://flashrom.org/Supported_hardware#Supported_mainboards [3] http://www.coreboot.org/pipermail/coreboot/2012-January/067990.html

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flashrom report for NVIDIA MCP51
by Jérôme 17 Jan '12

17 Jan '12

Hi. flashrom asked me to send you this report (see attached). Hope it helps. DMI string system-manufacturer: "Dell Inc" DMI string system-product-name: "XPS 630i" DMI string system-version: "Unknow" DMI string baseboard-manufacturer: "Dell Inc" DMI string baseboard-product-name: "0C113J" DMI string baseboard-version: "A00" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8718 on port 0x2e Found chipset "NVIDIA MCP51" with PCI ID 10de:0260. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! I was looking for something to flash a firmware on my DVD drive, but it looks like flashrom does not do that. I'll try with Intelliboot in DOS mode. Have a nice day. -- Jérôme

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Re: [flashrom] Problems flashing bios
by Stefan Tauner 17 Jan '12

17 Jan '12

hello axel i tried to reverse engineer what your bios does to disable the flash write protection. i was not very successfully yet though... if you still have access to the board, it would be great if you could compile/install superiotool and send us the output of "superiotool -deV". -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Mainboard no tested
by Stefan Tauner 16 Jan '12

16 Jan '12

On Sun, 15 Jan 2012 19:04:25 -0500 hector j <c1b3rh4ck(a)gmail.com> wrote: > 2012/1/15 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > > > > > from my very limited experience i think the chipset usually works just > > fine. in this case flashrom does not detect the flash chip. this can > > mean two things: > > - either we have to toggle an IO pin of the chipset (dependent on the > > mainboard) to enable the chip at all, or > > - the chip is not supported yet. > > > > most probably you just need a board enable > > (http://flashrom.org/Board_Enable) due to the first option. > > > > can you please confirm that this is you board > > http://www.msi.com/product/mb/K9N6PGM2-V.html#/?div=BIOS > > please also provide the output of lspci -xxxnnvv (run as root). > > creating the board enable can take days to months dependent on the > > motivation of our volunteers. > > Hi, > Is affirmative that's my board,but it not works,now i have two of the same > boards and testing in the first didn't work,and the second is awaiting > for,so im providing you the output,i'll read the link. > > thanks for your support. the output of just "lspci" is not enough, we need the additional information given by "lspci -xxxnnvv". -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[PATCH] Add board enable for AOpen D2544-B1 (used in FCS ESPRIMO Q5010)
by Stefan Tauner 16 Jan '12

16 Jan '12

Typical AWARD enable structure with an ICH GPIO board enable. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- The chip status register shows #TBL and #WP as active, so this code may not be everything we need. Check probe output for both *not* active before trying to write! board_enable.c | 11 +++++++++++ print.c | 1 + 2 files changed, 12 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 2229f8b..05ac1d9 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1560,6 +1560,16 @@ static int intel_ich_gpio34_raise(void) /* * Suited for: + * - AOpen D2544-B1: Intel 945GM + ICH7-M used in ... + * - FCS (e.g. ESPRIMO Q5010) + */ +static int intel_ich_gpio38_raise(void) +{ + return intel_ich_gpio_set(38, 1); +} + +/* + * Suited for: * - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M */ static int intel_ich_gpio43_raise(void) @@ -2098,6 +2108,7 @@ const struct board_match board_matches[] = { {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, P3, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", P3, "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", P3, "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, + {0x8086, 0x27b9, 0xa0a0, 0x0632, 0x8086, 0x27da, 0xa0a0, 0x0632, "^D2544-B1", NULL, NULL, P3, "AOpen", "D2544-B1", 0, OK, intel_ich_gpio38_raise}, {0x8086, 0x277c, 0xa0a0, 0x060b, 0x8086, 0x27da, 0xa0a0, 0x060b, NULL, NULL, NULL, P3, "AOpen", "i975Xa-YDG", 0, OK, board_aopen_i975xa_ydg}, {0x8086, 0x27b8, 0x1849, 0x27b8, 0x8086, 0x27da, 0x1849, 0x27da, "^ConRoeXFire-eSATA2", NULL, NULL, P3, "ASRock", "ConRoeXFire-eSATA2", 0, OK, intel_ich_gpio16_raise}, {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e}, diff --git a/print.c b/print.c index db7ed65..5804bcb 100644 --- a/print.c +++ b/print.c @@ -556,6 +556,7 @@ const struct board_info boards_known[] = { B("Advantech", "PCM-5820", 1, "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm", NULL), B("agami", "Aruma", 1, "http://web.archive.org/web/20080212111524/http://www.agami.com/site/ais-600…", NULL), B("Albatron", "PM266A Pro", 1, "http://www.albatron.com.tw/English/Product/MB/pro_detail.asp?rlink=Overview…", NULL), /* FIXME */ + B("AOpen", "D2544-B1", 1, "http://uk.ts.fujitsu.com/rl/servicesupport/techsupport/professionalpc/ESPRI…", "This is an OEM board from FCS (e.g. ESPRIMO Q5010)."), B("AOpen", "vKM400Am-S", 1, "http://usa.aopen.com/products_detail.aspx?Auno=824", NULL), B("Artec Group","DBE61", 1, "http://wiki.thincan.org/DBE61", NULL), B("Artec Group","DBE62", 1, "http://wiki.thincan.org/DBE62", NULL), -- 1.7.1

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Re: [flashrom] HP Viola-GL8E Pegatron ASUS M2N78-LA
by Stefan Tauner 16 Jan '12

16 Jan '12

On Wed, 11 Jan 2012 22:41:04 -0600 Zach Stuart <linuxjunkie999(a)gmail.com> wrote: hi zach and thanks for your report! > ** > http://h10025.www1.hp.com/ewfrf/wc/document?docname=c01421635&cc=us&dlc=en&… > straight from HP. This board is an oem rebrand slight > modification of an ASUS mobo (cannot find an exact asus mobo). there might not be a matching one, but it may have been produced solely for HP to use. > > linux-uphg:/usr/sbin # flashrom -V > flashrom v0.9.3-r1246 on Linux 2.6.37.6-0.5-desktop (x86_64), built with > libpci 3.1.7, GCC 4.5.1 20101208 [gcc-4_5-branch revision 167585], little > endian iirc we have enabled writing for this chipset in 0.9.4, which does not mean it will work on all boards, but that we do not forbid it unconditionally. please update and report any success or failure. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Mainboard no tested
by Stefan Tauner 16 Jan '12

16 Jan '12

On Thu, 12 Jan 2012 01:12:58 -0500 hector j <c1b3rh4ck(a)gmail.com> wrote: > Hi recently i'm using flashrom for update a new mainboard,a friend of mine > giving me this week,i've used flashrom sometimes but > unfortunately i've been checking and the chipset,i try flashrom and it show > me this message : > > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom(a)flashrom.org including a > > *Enabling flash write... This chipset is not really supported yet. > Guesswork... > Please send the output of "flashrom -V" to flashrom(a)flashrom.org with > your board name: flashrom -V as the subject to help us finish support for > your > chipset. Thanks. > OK. > > so i'm attaching two file one the verbose exit,and two my mainboard > information using dmidecode,and if you receive this email please send me a > confirmation or if you need more information just send me a mail . hi from my very limited experience i think the chipset usually works just fine. in this case flashrom does not detect the flash chip. this can mean two things: - either we have to toggle an IO pin of the chipset (dependent on the mainboard) to enable the chip at all, or - the chip is not supported yet. most probably you just need a board enable (http://flashrom.org/Board_Enable) due to the first option. can you please confirm that this is you board http://www.msi.com/product/mb/K9N6PGM2-V.html#/?div=BIOS please also provide the output of lspci -xxxnnvv (run as root). creating the board enable can take days to months dependent on the motivation of our volunteers. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Flashing GA-X48A-UDR3 sucessful !
by jerome 15 Jan '12

15 Jan '12

Hi Just some word to say I have flash sucessfully my GA-X48A-UDR3 rev 2. (Gigabyte). For now, all work just fine. Thanks to dev team. ~ # flashrom -V flashrom v0.9.4-r1394 on Linux 2.6.39-bpo.2-amd64 (x86_64), built with libpci 3.1.7, GCC 4.6.1 20110616 (prerelease), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1664M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 999 us, 10000 myus = 10003 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Gigabyte Technology Co., Ltd." DMI string system-product-name: "X58A-UD3R" DMI string system-version: " " DMI string baseboard-manufacturer: "Gigabyte Technology Co., Ltd." DMI string baseboard-product-name: "X58A-UD3R" DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8720 on port 0x2e Found chipset "Intel ICH10R" with PCI ID 8086:3a16. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 Root Complex Register Block address = 0xfed1c000 GCS = 0x464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x0000 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=0, SCIP=0, FDOPSS=0, FDV=0, FLOCKDN=0 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00001fff (FREG0: Flash Descriptor) Flash Descriptor region is unused. 0x58: 0x00001fff (FREG1: BIOS) BIOS region is unused. 0x5C: 0x00001fff (FREG2: Management Engine) Management Engine region is unused. 0x60: 0x00001fff (FREG3: Gigabit Ethernet) Gigabit Ethernet region is unused. 0x64: 0x00001fff (FREG4: Platform Data) Platform Data region is unused. 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0x04 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0x004140 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=1, SME=0, SCF=0 0x94: 0x5006 (PREOP) 0x96: 0x0bb4 (OPTYPE) 0x98: 0x9f200105 (OPMENU) 0x9C: 0x00000302 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xD0: 0x00000000 (FPB) Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done preop0=0x06, preop1=0x50 op[0]=0x02, 3, 0 op[1]=0x03, 2, 0 op[2]=0xd8, 3, 0 op[3]=0x05, 0, 0 op[4]=0x90, 2, 0 op[5]=0x01, 1, 0 op[6]=0x9f, 0, 0 op[7]=0xc7, 1, 0 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. No IT87* serial flash segment enabled. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x94, id2 0x9d, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x0f, id2 0x57, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found Macronix flash chip "MX25L1605" (2048 kB, SPI) at physical address 0xffe00000. Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x94, id2 0x9d, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x0f, id2 0x57, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xc2, id2 0x14 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x14 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for SST SST25LF040A.RES, 512 kB: program_opcodes: preop=5006 optype=462b opmenu=05ab0302c79f0190 on-the-fly OPCODE (0xAB) re-programmed, op-pos=2 probe_spi_res2: id1 0x14, id2 0x14 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x14 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x6f, id2 0xf4, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x94, id2 0x9d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x94, id2 0x9d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x0f, id2 0x57, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x0f, id2 0x57, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x94, id2 0x9d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x94, id2 0x9d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x0f, id2 0x57, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x0f, id2 0x57, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x94, id2 0x9d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x0f, id2 0x57, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x94, id2 0x9d, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x94, id2 0x9d, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x94, id2 0x9d, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x0f, id2 0x57, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x94, id2 0x9d, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xc2, id2 0x14 No operations were specified. Restoring MMIO space at 0x7fc30fa6d8a0 Restoring MMIO space at 0x7fc30fa6d89c Restoring MMIO space at 0x7fc30fa6d898 Restoring MMIO space at 0x7fc30fa6d896 Restoring MMIO space at 0x7fc30fa6d894 Restoring PCI config space for 00:1f:0 reg 0xdc -- Jérôme FAU

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Report on Flashing Board with Intel H67
by Peter A. Braun 15 Jan '12

15 Jan '12

Hi, last night I flashed my MSI H67MA-ED55(B3) with E7676IMS170. As the name says Intel H67 is the built in chipset. Flash chip is W25Q64. The flash process worked fine for me. Two things are a bit strange. Currently I try to investigate the reasons for. Perhaps you have any suggestions. 1. Sys fans cannot longer be controlled, because according BIOS parameters are not longer accessible. Currently I don't know how to get them back. 2. After cold booting the disabled "Full Screen Logo Display" is enabled again. It seems to be the default. But other boot parameter are not changed back to default. I attached the result of "flashrom -V" (result.txt). I hope results are detailed enough to switch entry H67 in your hardware list onto tested. Best regards, Peter

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Gigabyte M61SME-S2/Nvidia MCP61
by Adam Butler 15 Jan '12

15 Jan '12

1 0

Re: [flashrom] [PATCH] flashrom.c: Reorder list of options to test
by Stefan Tauner 13 Jan '12

13 Jan '12

On Fri, 13 Jan 2012 17:01:06 +0100 Idwer Vollering <vidwer(a)gmail.com> wrote: > + "operations you tested (verbose, verbose read,\n" first one should be "verbose probe" > "Please mention your board in the subject line. " can be removed. almost no reporter cares for this :/ and those few that do would choose an appropriate subject anyway imho. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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