- flashrom - mail.coreboot.org

Re: [coreboot] Re: [LinuxBoot] FOSDEM 2019 deadline today
by Carl-Daniel Hailfinger 01 Feb '19

01 Feb '19

On 01.02.2019 08:48, Martin Kepplinger wrote: > On 24.01.19 01:05, Carl-Daniel Hailfinger wrote: >> Hey everyone, >> >> just 9 days until FOSDEM in Brussels (2+3 February)! >> There are a couple of talks about coreboot and LinuxBoot and we have a >> coreboot/LinuxBoot/flashrom stand (building AW). Plus, there is a >> hardware enablement devroom. >> >> - Who's coming? >> - Are you volunteering for a shift at the stand? >> - What demo hardware can you bring? (We have only 1 table, so smaller >> hardware is preferred.) >> - What merchandise/giveaways can you bring? >> - Do we have 1-page flyers about each of coreboot, LinuxBoot and >> flashrom? (PDF is sufficient, I can print in black+white if needed.) >> - Do we have a large coreboot/LinuxBoot/flashrom banner which helps >> others find our stand? >> > hi, > > how're you doing with organisation? It's a bit chaotic, but I think we can manage. > I'm doing a 10min lightning talk about my little x230 coreboot project > tomorrow and obviously have that with me. > > There are talks I'll definitely attend, but in case you urgently need > somebody at the stand for a short shift, please just ask. > > I only have my X230 and some flashing hardware with me. It would be nice if you could stop by at our booth. We don't have a plan yet for the shifts at the booth, but I hope we can get something organized either tonight or tomorrow in the morning. Thanks, Carl-Daniel

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flashrom, and 4-byte addressing SPI (example: MX25L25635E)
by Евгений 29 Jan '19

29 Jan '19

Good day. MacOS+Homebrew+flashrom. Flashrom does not understand 4 byte addressing (chips > 16MB). With 3 byte addressing work perfectly (chips <= 16MB). May you add 4 byte addressing for SPI flash? Example MX25L25635E - 32MB uses in different new routers. CH341 in Windows work with 4 byte and read/write flash and registers from this SPI flash: JEDEC ID(9F) = 0xC22019 RES ID(AB) = 0x001818 REMS ID(90) = 0x00C218 Sreg: 00000000(0x00), 11111111(0xFF), 00000111(0x07) but on MacOS not software that can do it.

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flash chips not supported - modify config file?
by Hugo.Bitard 28 Jan '19

28 Jan '19

Hello, First of all, i would tell you that you do an amazing work with flashrom. It is really awsome!! I would like to dump the firmware of an Atmel 24C01A, but this flash chips is not a supported one. I found 2 files, that could be of interest: flashchips.c and flashchips.h, but i do not know how to modify it in order to support the Atmel 24C01A chips. If you could give me some advice about the procedure, it could be very helpful. Thank in advance Best regards Hugo message envoyé depuis ProtonMail

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Re: [flashrom] [coreboot] [LinuxBoot] FOSDEM 2019 deadline today
by Carl-Daniel Hailfinger 26 Jan '19

26 Jan '19

In that case, I'd also like to point you to the deadline for submitting main track talks which is tomorrow(!). https://fosdem.org/2019/news/2018-08-10-call-for-participation/ Having a coreboot/LinuxBoot talk there would be awesome. Ron/David, could you submit something or do you have someone in mind who can do that? There's also lightning talks, deadline is a bit later. OK, I'm submitting a request for a stand. I need a backup contact for the stand. Who is willing to do that? AFAICS we can still change the backup contact later if life happens. Regards, Carl-Daniel On 02.11.2018 20:48, David Hendricks wrote: > > > On Fri, Nov 2, 2018 at 9:15 AM 'Ron Minnich' via linuxboot > <linuxboot(a)googlegroups.com <mailto:linuxboot@googlegroups.com>> wrote: > > I"m leaning to yes, by which I mean if you do it, I'll show up. > > I can't believe I said that. > On Fri, Nov 2, 2018 at 7:20 AM Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2006(a)gmx.net > <mailto:c-d.hailfinger.devel.2006@gmx.net>> wrote: > > > > Hi! > > > > FOSDEM next year will be on 2 & 3 February 2019. > > The deadline for applying for a stand is today. > > Do we want a coreboot/flashrom/LinuxBoot stand/booth? > > > Same as what Ron said. I think someone from FB can be there to talk > about coreboot/LinuxBoot stuff and perhaps bring some hardware to demo. > >

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Google Coral ChromeBook issue
by Bank Wu 25 Jan '19

25 Jan '19

Hi There, I have an issue that cannot disable write protection mode on a dell chomebook which FW is Google_Coral_10068.63.0. Both BIOS and EC flash ROM were reprogrammed with brand new chips before we installed the RMA shim R69. 1. flashrom -p host -wp-disable (AC only, Battery is disconnected) coreboot table found at 0x7ab36000. FAILED [cid:image002.png@01D4B497.AC197D40] 2. fmap_decode readbios.bin fmap_signature="0x5f5f464d41505f5f" fmap_ver_major="1" fmap_ver_minor="1" fmap_base="0x0000000000000000" fmap_size="0x1000000" fmap_name="FLASH" fmap_nareas="35" area_offset="0x00000000" area_size="0x00400000" area_name="WP_RO" area_flags_raw="0x00" area_flags="" area_offset="0x00000000" area_size="0x00001000" area_name="SI_DESC" area_flags_raw="0x00" area_flags="" area_offset="0x00001000" area_size="0x001ff000" area_name="IFWI" area_flags_raw="0x00" area_flags="" area_offset="0x00200000" area_size="0x00004000" area_name="RO_VPD" area_flags_raw="0x00" area_flags="" area_offset="0x00204000" area_size="0x001fc000" area_name="RO_SECTION" area_flags_raw="0x00" area_flags="" area_offset="0x00204000" area_size="0x00000800" area_name="FMAP" area_flags_raw="0x00" area_flags="" area_offset="0x00204800" area_size="0x00000040" area_name="RO_FRID" area_flags_raw="0x00" area_flags="" area_offset="0x00204840" area_size="0x000007c0" area_name="RO_FRID_PAD" area_flags_raw="0x00" area_flags="" area_offset="0x00205000" area_size="0x0017b000" area_name="COREBOOT" area_flags_raw="0x00" area_flags="" area_offset="0x00380000" area_size="0x00040000" area_name="GBB" area_flags_raw="0x00" area_flags="" area_offset="0x003c0000" area_size="0x00040000" area_name="RO_UNUSED" area_flags_raw="0x00" area_flags="" area_offset="0x00400000" area_size="0x00030000" area_name="MISC_RW" area_flags_raw="0x00" area_flags="" area_offset="0x00400000" area_size="0x00021000" area_name="UNIFIED_MRC_CACHE" area_flags_raw="0x00" area_flags="" area_offset="0x00400000" area_size="0x00010000" area_name="RECOVERY_MRC_CACHE" area_flags_raw="0x00" area_flags="" area_offset="0x00410000" area_size="0x00010000" area_name="RW_MRC_CACHE" area_flags_raw="0x00" area_flags="" area_offset="0x00420000" area_size="0x00001000" area_name="RW_VAR_MRC_CACHE" area_flags_raw="0x00" area_flags="" area_offset="0x00421000" area_size="0x00003000" area_name="RW_ELOG" area_flags_raw="0x00" area_flags="" area_offset="0x00424000" area_size="0x00004000" area_name="RW_SHARED" area_flags_raw="0x00" area_flags="" area_offset="0x00424000" area_size="0x00002000" area_name="SHARED_DATA" area_flags_raw="0x00" area_flags="" area_offset="0x00426000" area_size="0x00002000" area_name="VBLOCK_DEV" area_flags_raw="0x00" area_flags="" area_offset="0x00428000" area_size="0x00002000" area_name="RW_VPD" area_flags_raw="0x00" area_flags="" area_offset="0x0042a000" area_size="0x00005000" area_name="RW_NVRAM" area_flags_raw="0x00" area_flags="" area_offset="0x0042f000" area_size="0x00001000" area_name="FPF_STATUS" area_flags_raw="0x00" area_flags="" area_offset="0x00430000" area_size="0x00480000" area_name="RW_SECTION_A" area_flags_raw="0x00" area_flags="" area_offset="0x00430000" area_size="0x00010000" area_name="VBLOCK_A" area_flags_raw="0x00" area_flags="" area_offset="0x00440000" area_size="0x0046ffc0" area_name="FW_MAIN_A" area_flags_raw="0x00" area_flags="" area_offset="0x008affc0" area_size="0x00000040" area_name="RW_FWID_A" area_flags_raw="0x00" area_flags="" area_offset="0x008b0000" area_size="0x00480000" area_name="RW_SECTION_B" area_flags_raw="0x00" area_flags="" area_offset="0x008b0000" area_size="0x00010000" area_name="VBLOCK_B" area_flags_raw="0x00" area_flags="" area_offset="0x008c0000" area_size="0x0046ffc0" area_name="FW_MAIN_B" area_flags_raw="0x00" area_flags="" area_offset="0x00d2ffc0" area_size="0x00000040" area_name="RW_FWID_B" area_flags_raw="0x00" area_flags="" area_offset="0x00d30000" area_size="0x00200000" area_name="RW_LEGACY" area_flags_raw="0x00" area_flags="" area_offset="0x00f30000" area_size="0x0004f000" area_name="BIOS_UNUSABLE" area_flags_raw="0x00" area_flags="" area_offset="0x00f7f000" area_size="0x00080000" area_name="DEVICE_EXTENSION" area_flags_raw="0x00" area_flags="" area_offset="0x00fff000" area_size="0x00001000" area_name="UNUSED_HOLE" area_flags_raw="0x00" area_flags="" 3. flashrom -p host -w bios.bin Calibrating delay loop... OK. coreboot table found at 0x7ab36000. Erasing and writing flash chip... Good. It seems nothing was changed. FAILED [cid:image003.png@01D4B497.AC197D40] Yuehui(Bank) Wu Testing Engineer MLB Engineering CSAT Solutions LP Work: +1 (713) 934-5200 Mobile: +1 (832) 729-1686 www.csat-solutions.com<http://www.csat-solutions.com/> Bank.Wu(a)csat-solutions.com<mailto:bank.wu@csat-solutions.com> [cid:image001.png@01D16F22.E9FCB900]

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flashrom v1.0 on Linux 4.20.3-gentoo (x86_64) with ch341a and GigaDevice GD25Q40(B)
by Néstor A. Marchesini 23 Jan '19

23 Jan '19

-------------------------------------------------------------------------------- Read 1 original memory. $ time flashrom --programmer ch341a_spi --chip "GD25Q40(B)" --read SAMSUNG-LS23C350H-00-original-GD25Q40B.bin -V flashrom v1.0 on Linux 4.20.3-gentoo (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.6.2, GCC 8.2.0, little endian Command line (7 args): flashrom --programmer ch341a_spi --chip GD25Q40(B) --read SAMSUNG-LS23C350H-00-original-GD25Q40B.bin -V Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Initializing ch341a_spi programmer Device revision is 3.0.4 The following protocols are supported: SPI. Probing for GigaDevice GD25Q40(B), 512 kB: probe_spi_rdid_generic: id1 0xc8, id2 0x4013 Found GigaDevice flash chip "GD25Q40(B)" (512 kB, SPI) on ch341a_spi. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set Chip status register: Block Protect 4 (BP4) is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. Thanks for your help! Reading flash... done. real 0m4,524s user 0m0,191s sys 0m0,006s -------------------------------------------------------------------------------- Read 2 original memory. $ time flashrom --programmer ch341a_spi --chip "GD25Q40(B)" --read SAMSUNG-LS23C350H-01-original-GD25Q40B.bin -V flashrom v1.0 on Linux 4.20.3-gentoo (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.6.2, GCC 8.2.0, little endian Command line (7 args): flashrom --programmer ch341a_spi --chip GD25Q40(B) --read SAMSUNG-LS23C350H-01-original-GD25Q40B.bin -V Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Initializing ch341a_spi programmer Device revision is 3.0.4 The following protocols are supported: SPI. Probing for GigaDevice GD25Q40(B), 512 kB: probe_spi_rdid_generic: id1 0xc8, id2 0x4013 Found GigaDevice flash chip "GD25Q40(B)" (512 kB, SPI) on ch341a_spi. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set Chip status register: Block Protect 4 (BP4) is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. Thanks for your help! Reading flash... done. real 0m4,542s user 0m0,187s sys 0m0,006s -------------------------------------------------------------------------------- List and compare the two reads. $ ls -l SAMSUNG-LS23C350H-0?-original-GD25Q40B.bin -rw-r--r-- 1 nestor nestor 524288 ene 23 03:38 SAMSUNG-LS23C350H-00-original-GD25Q40B.bin -rw-r--r-- 1 nestor nestor 524288 ene 23 03:40 SAMSUNG-LS23C350H-01-original-GD25Q40B.bin $ ls -lh SAMSUNG-LS23C350H-0?-original-GD25Q40B.bin -rw-r--r-- 1 nestor nestor 512K ene 23 03:38 SAMSUNG-LS23C350H-00-original-GD25Q40B.bin -rw-r--r-- 1 nestor nestor 512K ene 23 03:40 SAMSUNG-LS23C350H-01-original-GD25Q40B.bin $ cmp SAMSUNG-LS23C350H-00-original-GD25Q40B.bin SAMSUNG-LS23C350H-01-original-GD25Q40B.bin -b All ok, the compare are equals. $ eix -I flashrom [I] sys-apps/flashrom Available versions: 0.9.6.1 0.9.7 0.9.8 (~)0.9.9 (~)1.0 **9999 {atahpt +atapromise +atavia +bitbang_spi +buspirate_spi +ch341a_spi (+)dediprog +developerbox_spi +digilent_spi doc +drkaiser +dummy (+)ft2232_spi +gfxnvidia +internal +internal_dmi +it8212 +linux_mtd +linux_spi mstarddc_spi +nic3com +nicintel +nicintel_eeprom +nicintel_spi nicnatsemi (+)nicrealtek +ogp_spi +pickit2_spi +pony_spi (+)rayer_spi (+)satamv +satasii +serprog static tools usbblaster +usbblaster_spi +wiki} Installed versions: 1.0(03:41:50 07/11/18)(buspirate_spi ch341a_spi dummy ft2232_spi internal internal_dmi linux_spi pickit2_spi pony_spi serprog tools wiki -atahpt -atapromise -atavia -dediprog -drkaiser -gfxnvidia -it8212 -mstarddc_spi -nic3com -nicintel -nicintel_eeprom -nicintel_spi -nicnatsemi -nicrealtek -ogp_spi -rayer_spi -satamv -satasii -static -usbblaster_spi) Homepage: https://flashrom.org/ Description: Utility for reading, writing, erasing and verifying flash ROM chips I'am gentoo testing branck ~amd64 and I have ch341a and buspirate 3.5c, my motherboard is Gigabyte GA-990FXA-UD7 r1.00 with AMD FX8350 processor. Regards and thaks for make flashrom great!

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ENE KB9012QF A3 reflash help needed
by Nyúlós Lónyál 20 Jan '19

20 Jan '19

Hi! I'm trying to flash an ENE KB9012QF A3 KBC on LA-8241P motherboard. The problem is flashrom can't detect the internal SPI of it, fails with error. flashrom p1.0-141-g9cecc7e on Linux 4.15.0-20-generic (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.5.2, GCC 7.3.0, little endian Command line (5 args): ./flashrom -p rayer_spi -c KB9012 (EDI) -V Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Initializing rayer_spi programmer Using address 0x378 as I/O base for parallel port access. Using RayeR SPIPGM pinout. The following protocols are supported: SPI. Probing for ENE KB9012 (EDI), 128 kB: edi_chip_probe: reading hwversion failed No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. How to get it working? Thanks a lot for help!

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Found chipset "VIA VT82C597" with PCI ID 1106:0597. Works
by William Smart 18 Jan '19

18 Jan '19

Greetings Flashrom Crew! Found chipset "VIA VT82C597" with PCI ID 1106:0597. I was able to flash a bios on this chipset, using an EPOX EP-MVM3G2 mainboard, verbose log attached. Thanks!!! Bill

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Thomas-Krenn-Award 2019 - Win server hardware for Open Source Projects
by Thomas Niedermeier 18 Jan '19

18 Jan '19

Dear Ladies and Gentlemen, I hope you had a good start into the new year. Since you have already successfully applied for the Thomas-Krenn-Award with your project Flashrom, I would like to draw your attention to this year's award. Open source projects can again win server hardware with a total value of 6,500 Euros. The submission of a project is very easy - you select three configurations (1500 €, 2000 € and 3000 € net value of goods) and send an e-mail to award(a)thomas-krenn.com with a description for what purpose the server would be used in the project. All details can be found below: https://www.thomas-krenn.com/en/companies/about-us/thomas-krenn-award.html We at Thomas-Krenn would be delighted if you and your project could participate in our award again. You can also forward the information to other developers in the open source community (one submission per project is possible. There is also no registered association required to submit the project.) The registration deadline is 27.01.2019. Best regards, Thomas Niedermeier Thomas Niedermeier Knowledge Transfer E-Mail: tniedermeier(a)thomas-krenn.com Tel: +49 8551 91 50 264 [Lassen Sie sich zu Windows Server 2019 beraten]<https://www.thomas-krenn.com/de/produkte/software/microsoft-software/window…> Thomas-Krenn.AG; Speltenbach-Steinäcker 1; 94078 Freyung; Sitz der Gesellschaft: Freyung | HRB 6790; Vorstand: Ralf Hohmann, Christoph Maier; AR-Vorsitzender: Guido Bollue [Xing]<https://www.xing.com/companies/thomas-krenn.ag> [Facebook] <https://www.facebook.com/thomaskrenn.ag> [Twitter] <https://twitter.com/thomaskrennag> [LinkedIn] <https://de.linkedin.com/company/thomas-krenn.ag>

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AsRock Z370 Extreme4 not supported
by flashrom＠prvy.eu 18 Jan '19

18 Jan '19

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patch for allowing the use of the SOCKET target of the SF600
by Florian Kaiser 15 Jan '19

15 Jan '19

Hello, I am using this patch for a while now and I did not encounter any problems. I am not sure if this was/is not supported. Is there any reason why this is not supported? Thank you very much, Florian Kaiser

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patch: add support for the MCP2210
by Máté Kukri 12 Jan '19

12 Jan '19

Hello, This patch adds support for the MCP2210 USB to SPI bridge as a programmer. Since the MCP2210 is an HID device I have a working version using both libusb and hidraw + udev for finding the device. I have already made a github pull request with more details: https://github.com/flashrom/flashrom/pull/68. But I am posting it here as well. Máté Kukri

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Atmel AT49F002(N)T erase and write (was:asus p2b - successful erase and write)
by Branden Waldner 12 Jan '19

12 Jan '19

I realized I mixed up the flash part status with the motherboard, so figured I'd better make that clear. Sorry about that. On 1/4/19, Branden Waldner <scruffy99(a)gmail.com> wrote: > I got an asus p2b to go with my asus p2-99 for coreboot testing and it > works with flashrom. > > Erase and write are reported as untested, so attached are logs of > flashing from the award bios and from coreboot. It reports failure > when trying erase function 0, but tries erase function 1 and works. It > also requires the this_is_not_a_laptop option to work with the award > bios. > > I can do any further testing or supply logs if required. >

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Is it possible to change only DMI data using flashrom ?
by Марк Коренберг 08 Jan '19

08 Jan '19

I want to change, say, serial number of motherboard. -- Segmentation fault

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Help with a Winbond W25Q16
by iafdan 08 Jan '19

08 Jan '19

Hi to the cool guys from Flashrom! I'm trying to dump the contents of a Winbond W25Q16 using the command: ./flashrom -p ft2232_spi:type=232H,port=A -c W25Q16 -r dump.rom I'm getting an error that: This flash part has status NOT WORKING for operations... However, when I do "flashrom -L" the W25Q16 chip, with the exact same ID appears on the list. Here's a verbose output: https://paste.flashrom.org/view.php?id=3163 I also tried reading the chip without specifying the exact chip. Many thanks!!

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asus p2b - successful erase and write
by Branden Waldner 05 Jan '19

05 Jan '19

I got an asus p2b to go with my asus p2-99 for coreboot testing and it works with flashrom. Erase and write are reported as untested, so attached are logs of flashing from the award bios and from coreboot. It reports failure when trying erase function 0, but tries erase function 1 and works. It also requires the this_is_not_a_laptop option to work with the award bios. I can do any further testing or supply logs if required.

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new hardware
by Kajus Kevevari 03 Jan '19

03 Jan '19

Hello, I noticed that "winbond" flash W25Q256.V is marked as UNTESTED. I tested read and write functions and they work correct. I was able to fire up board after re flashing with Amontech JTAGkey2 programmer. Attaching some prove. Good day! [image: image.png] [image: image.png] [image: image.png]

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Flashrom for DOS?
by Woockash O 02 Jan '19

02 Jan '19

Hi, I am trying to flash my BIOS chip in Wyse SX30 thin client with Coreboot image. According to various articles, flashrom should be able to do that. However SX30 doesn't like most linux distributions (due to problems with BIOS that should be fixed after flashing the chip). I would like to try flashing it with flashrom release for DOS (freedos seems to work with no issues). However for some reason I am not able to access your buildbot website (tried on several browsers and networks). I have found only an old release (0.9.4) on another website. If there are any issues with buildbot site, could you please point me to the location where I can get some newer releases for DOS (at least 0.9.8)? Thanks Luc

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Re: [flashrom] Cleanup patches for flashrom
by Nico Huber 02 Jan '19

02 Jan '19

Hi Richard, On 20.12.18 11:11, Richard Hughes wrote: > We're slowly moving towards using libflashrom in fwupd, rather than > exec'ing the flashrom binary and screen scraping. So that it can be > consumed by users easily, I'm tempted to use flashrom as a subproject > to the fwupd project rather than waiting for distros to ship any new > bleeding edge version of flashrom to users. To make some of that > possible, I've fixed up a few of the CI failures we would see in > fwupd, which I've filed as a PR here: > https://github.com/flashrom/flashrom/pull/67 thanks. > > If a GitHub PR isn't how you want these kind of general patches please > let me know. One person already told me that I needed to use Gerrit, When we switched to Gerrit, we decided to still allow patches per email and also on GitHub. Though, all patches have to go through Gerrit in the end as that's where the official repository is. I've never been active on GitHub (my account is only few months old). And the developers that set the flashrom mirror up there obviously had the best intentions (pull requests are mentioned in the project des- cription) but aren't actively reviewing atm. I also can't say anymore that everything on Gerrit gets a review, though smaller changes do. If you'd use Gerrit, you'd hit the remaining active reviewers right in their everyday workflow. > but I'm not overly keen on learning a new process if I can avoid it. > Feedback welcome, thanks. I just tried, it was horrible ;) I just can't find a way to comment on individual commits of your PR (beside commenting inline in the code). I'll leave some comments their and pull those commits that seem ready to go. Nico

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Hardware support
by Waltteri Koskinen 02 Jan '19

02 Jan '19

Hello! I wanted to report that I have successfully probed, read, erased and wrote in this chip https://www.mouser.fi/datasheet/2/308/LE25U40CMD-D-972803.pdf I used raspberry pi 1.gen and linux_spi. Thank you for this fantastic software it saved my pc display. BR. Waltteri Koskinen

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FAILED: Asus Chromebox 3 / CN65 (TEEMO)
by Markku Viholainen 02 Jan '19

02 Jan '19

Hi, do you have any idea what to do with folowing error? ChromeOS Firmware Utility Script [2018-12-30] (c) Mr Chromebox <mrchromebox(a)gmail.com> ********************************************************* ** Device: Asus Chromebox 3 / CN65 (TEEMO) ** CPU Type: Intel KabyLake ** Fw Type: Stock ChromeOS ** Fw WP: Disabled ********************************************************* ** 1) Install/Update RW_LEGACY Firmware ** 2) Install/Update BOOT_STUB Firmware ** [WP] 3) Install/Update Full ROM Firmware ** [WP] 4) Set Boot Options (GBB flags) ** [WP] 5) Set Hardware ID (HWID) ** 6) Remove ChromeOS Bitmaps ** 7) Restore ChromeOS Bitmaps ** 8) Restore Stock BOOT_STUB ** 9) Restore Stock Firmware (full) ********************************************************* Select a menu option or R to reboot P to poweroff Q to quit 3 Install/Update UEFI Full ROM Firmware Standard disclaimer: flashing the firmware has the potential to brick your device, requiring relatively inexpensive hardware and some technical knowledge to recover. You have been warned. Also, flashing Full ROM firmware will remove your ability to run ChromeOS. Do you wish to continue? [y/N] y NOTE: After flashing UEFI firmware, you will need to install a UEFI-compatible OS; ChromeOS will no longer be bootable. UEFI firmware supports Windows and Linux on all devices. Debian/Ubuntu-based distros require a small fix to boot after install -- see https://mrchromebox.tech/#faq for more info. Press Y to continue or any other key to abort. y Create a backup copy of your stock firmware? This is highly recommended in case you wish to return your device to stock configuration/run ChromeOS, or in the (unlikely) event that things go south and you need to recover using an external EEPROM programmer. [Y/n] n Downloading Full ROM firmware (coreboot_tiano-fizz-mrchromebox_20181230.rom) Disabling software write-protect and clearing the WP range Installing Full ROM firmware (may take up to 90s) flashrom v0.9.9 : 266087c : Nov 20 2018 01:07:48 UTC on Linux 4.4.159-15346-gc5e629939ae0 (x86_64) Calibrating delay loop... OK. coreboot table found at 0x7aac2000. WARNING: SPI Configuration Lockdown activated. Erasing and writing flash chip... Verifying flash... VERIFY FAILED at 0x00000086! Expected=0x40, Read=0xc0, failed byte count from 0x00000000-0x00ffffff: 0x2 Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with FAILED: your board name in the subject line! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! FAILED An error occurred flashing the Full ROM firmware. DO NOT REBOOT! Press [Enter] to return to the main menu.^C +Markku+

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Flashing Asus KGPE-D16 Chip
by Joshua Aspinall 02 Jan '19

02 Jan '19

Hi, I am attempting to write a Libreboot ROM to my BIOS chip. The chip reports as follows: sudo flashrom -p linux_spi:dev=/dev/spidev0.0 'Found Winbond flash chip "W25Q16.V" (2048 kB, SPI) on linux_spi.' All of the online guides show reading the chip before attempting to flash, and confirming that the checksums match. However, when reading the contents of the flash chip, the checksums vary wildly. When attempting to flash the chip with a Libreboot ROM for the board, the erase function fails on all attempts as follows: sudo flashrom --programmer linux_spi:dev=/dev/spidev0.0 --write kgpe-d16_ukqwerty_txtmode.rom flashrom p1.0-141-g9cecc7e on Linux 4.14.79+ (armv6l) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Using default 2000kHz clock. Use 'spispeed' parameter to override. Found Winbond flash chip "W25Q16.V" (2048 kB, SPI) on linux_spi. Reading old flash chip contents... done. Erasing and writing flash chip... FAILED at 0x00000000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x00000fff: 0x1000 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. FAILED at 0x000007fd! Expected=0xff, Found=0xfe, failed byte count from 0x00000000-0x00007fff: 0x6218 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. FAILED at 0x000001bb! Expected=0xff, Found=0xfc, failed byte count from 0x00000000-0x0000ffff: 0xbde4 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. FAILED at 0x00000000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x001fffff: 0x18a7c0 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. FAILED at 0x00000111! Expected=0xff, Found=0xc0, failed byte count from 0x00000000-0x001fffff: 0x18af13 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. Looking for another erase function. Looking for another erase function. No usable erase functions left. FAILED! Uh oh. Erase/write failed. Checking if anything has changed. Reading current flash chip contents... done. Apparently at least some data has changed. Your flash chip is in an unknown state. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks! I am trying to determine whether I am doing something incorrectly, or whether the chip is unserviceable and needs to be replaced. Any help/hints would be greatly appreciated! Best Regards, Joshua Aspinall.

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Re: FAILED MARS
by Ivan Ivanov 31 Dec '18

31 Dec '18

Dear Tom, very happy to see your success :) Although I hope that you are installing Win7 not Win10 aka "spyware edition" ;) Happy New Year ! ;) BR, Ivan пн, 31 дек. 2018 г. в 21:44, Tom Santos <tom.81748418(a)gmail.com>: > > Good news!!! > > i just close and open google chrome and run the script again and done!! > > sorry for bad english, thanks for your support!! > > happy new year!!! > > Em segunda-feira, 31 de dezembro de 2018, Ivan Ivanov <qmastery16(a)gmail.com> escreveu: >> >> You may try to flash this image directly using flashrom, not using >> someone else's scripts because they might be faulty... >> >> пн, 31 дек. 2018 г. в 19:36, Tom Santos <tom.81748418(a)gmail.com>: >> > >> > Help pleas !!!! >> > >> > -- >> > Att, >> > >> > >> > Tom Santos. >> > >> > >> > >> > >> > A mente cria, o desejo atrai e a fé realiza. >> > _______________________________________________ >> > flashrom mailing list -- flashrom(a)flashrom.org >> > To unsubscribe send an email to flashrom-leave(a)flashrom.org > > > > -- > Att, > > > Tom Santos. > > > > > A mente cria, o desejo atrai e a fé realiza. >

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FAILED MARS
by Tom Santos 31 Dec '18

31 Dec '18

Help pleas !!!! -- Att, Tom Santos. A mente cria, o desejo atrai e a fé realiza.

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Successful flash of ASRock soldered BIOS via BIOS_PH header
by David Bartley 30 Dec '18

30 Dec '18

I have an ASRock Z390M-ITX/ac motherboard with a soldered/non-removable BIOS chip (this is apparently not uncommon on ASRock motherboards). I initially tried using test clips, but I wasn't able to get a good connection. Fortunately, the motherboard features a BIOS_PH header that is wired to the BIOS chip. Despite existing on multiple motherboards, its pinout is seemingly only documented in the J3355M manual ( http://asrock.pc.cdn.bitgravity.com/Manual/J3355M.pdf). Using this pinout, I was able to connect some jumpers from the BIOS_PH header to a CH341A programmer and successfully read from and write to the chip (a W25Q128JVSIQ in my case). For reference, the BIOS_PH pinout (corresponding to a 25xx chip) is: DI | GND CLK | no connection no pin | DO VCC | CS HOLD | WP

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