- flashrom - mail.coreboot.org

Re: [flashrom] Probe, Read, Erase, Write Success on Winbond W25Q16 with buspirate_spi
by Stefan Tauner 10 Jul '11

10 Jul '11

On Sat, 9 Jul 2011 21:28:42 -0400 Jon Szymaniak <jon.szymaniak(a)gmail.com> wrote: > Hi there, > > Per the "UNTESTED" message I received in v0.9.3-r1364, I just wanted to > report a couple successful PROBE, READ, WRITE and ERASE operations on a > Winbond W25Q16 with a BusPirate v2g0 (FW 4.1). I suppose this is expected > given that the W25X16 is supported, but thought someone might like to know > ;). > > I've attached the requested -V dumps for the aforementioned operations, as > well as 'time' output for each operation. With the BP v2g0 running FW v4.1, > I was seeing ~30 min on a 2MB read, and ~90 min on a 2MB write. I see that > somewhere above FW v5.7 and with some flashrom patches I should be able to > get some much quicker reads and writes. If I can get that going, I'd be > happy to do a bit more testing with this chip if you folks are interested. > > Thank you for providing a wonderful piece of software...cheers! > Jon Szymaniak hello jon and thanks for your (thorough) report! i have marked the chip as fully tested and will commit that later. PS: uncompressed logs are preferred (because they can be easier searched), no need to resend them though. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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flashrom -V
by Philipp Shah 10 Jul '11

10 Jul '11

flashrom v0.9.2-r1141 on Linux 2.6.38-8-generic (x86_64), built with libpci 3.1.7, GCC 4.5.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 767M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1001 us, 10000 myus = 10008 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "ECS" DMI string system-product-name: "GeForce 8000 series" DMI string system-version: "1.0 " DMI string baseboard-manufacturer: "ECS" DMI string baseboard-product-name: "GeForce 8000 series" DMI string baseboard-version: "1.0 " DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP78S", enabling flash write... chipset PCI ID is 10de:075c, This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Flash bus type is SPI Found SMBus device 10de:0752 at 00:01:1 MCP SPI BAR is at 0xf9f80000 SPI control is 0xc012, req=0, gnt=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for AMIC A25L05PT, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L05PU, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PT, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PU, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PT, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PU, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L80P, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PT, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PU, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L080, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L016, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25LQ032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for ASD AE49F2008, 256 KB: skipped. Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DQ161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for EMST F25L008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN29F010, 128 KB: skipped. Probing for Eon EN29F002(A)(N)B, 256 KB: skipped. Probing for Eon EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Intel 28F001BX-B, 128 KB: skipped. Probing for Intel 28F001BX-T, 128 KB: skipped. Probing for Intel 28F002BC-T, 256 KB: skipped. Probing for Intel 28F004S5, 512 KB: skipped. Probing for Intel 28F004BV/BE-B, 512 KB: skipped. Probing for Intel 28F004BV/BE-T, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-B, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address 0xfff00000. Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for MoselVitelic V29C51000B, 64 KB: skipped. Probing for MoselVitelic V29C51000T, 64 KB: skipped. Probing for MoselVitelic V29C51400B, 512 KB: skipped. Probing for MoselVitelic V29C51400T, 512 KB: skipped. Probing for MoselVitelic V29LC51000, 64 KB: skipped. Probing for MoselVitelic V29LC51001, 128 KB: skipped. Probing for MoselVitelic V29LC51002, 256 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: skipped. Probing for PMC Pm49FL004, 512 KB: skipped. Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF064C, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25LF040A.RES, 512 KB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BB, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: skipped. Probing for ST M50FLW040B, 512 KB: skipped. Probing for ST M50FLW080A, 1024 KB: skipped. Probing for ST M50FLW080B, 1024 KB: skipped. Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W29C011, 128 KB: skipped. Probing for Winbond W29C020C, 256 KB: skipped. Probing for Winbond W29C040P, 512 KB: skipped. Probing for Winbond W29EE011, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040B, 512 KB: skipped. Probing for Winbond W39V040C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U, 256 KB: skipped. Probing for Winbond W49F020, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for AMIC unknown AMIC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon unknown Eon SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix unknown Macronix SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (RDID), 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 0xc2, id2 0x13 No operations were specified.

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[PATCH] remove unneeded inclusions of chipdrivers.h
by Stefan Tauner 10 Jul '11

10 Jul '11

this is related to the spi split patch as discussed in: http://www.flashrom.org/pipermail/flashrom/2010-February/thread.html#2364 the old commit (r914) log notes: "Some of the spi programmer drivers required chipdrivers.h, needs fixing later: it87spi.c ichspi.c sb600spi.c wbsio_spi.c buspirate_spi.c ft2232spi.c bitbang_spi.c dediprog.c" there still remain a few cases where chipdrivers.h is needed: dediprog.c it87spi.c wbsio_spi.c (spi_programmer registration only) besides that, there are also non-spi files that do not need it. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- bitbang_spi.c | 1 - buspirate_spi.c | 1 - ft2232_spi.c | 1 - ichspi.c | 1 - it85spi.c | 1 - jedec.c | 1 - pm49fl00x.c | 1 - sb600spi.c | 1 - sst_fwhub.c | 1 - w29ee011.c | 1 - w39.c | 1 - 11 files changed, 0 insertions(+), 11 deletions(-) diff --git a/bitbang_spi.c b/bitbang_spi.c index 3c718af..8e2f780 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -22,7 +22,6 @@ #include <stdlib.h> #include <ctype.h> #include "flash.h" -#include "chipdrivers.h" #include "programmer.h" #include "spi.h" diff --git a/buspirate_spi.c b/buspirate_spi.c index f872309..caa27c0 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -23,7 +23,6 @@ #include <ctype.h> #include <unistd.h> #include "flash.h" -#include "chipdrivers.h" #include "programmer.h" #include "spi.h" diff --git a/ft2232_spi.c b/ft2232_spi.c index 7416e5b..cf67ff5 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -25,7 +25,6 @@ #include <stdlib.h> #include <ctype.h> #include "flash.h" -#include "chipdrivers.h" #include "programmer.h" #include "spi.h" #include <ftdi.h> diff --git a/ichspi.c b/ichspi.c index 99c4613..d9c9b4b 100644 --- a/ichspi.c +++ b/ichspi.c @@ -38,7 +38,6 @@ #include <string.h> #include "flash.h" -#include "chipdrivers.h" #include "programmer.h" #include "spi.h" diff --git a/it85spi.c b/it85spi.c index d4ca13b..c82f975 100644 --- a/it85spi.c +++ b/it85spi.c @@ -30,7 +30,6 @@ #include <stdio.h> #include <stdlib.h> #include "flash.h" -#include "chipdrivers.h" #include "spi.h" #include "programmer.h" diff --git a/jedec.c b/jedec.c index b96f5fd..cf34bcd 100644 --- a/jedec.c +++ b/jedec.c @@ -23,7 +23,6 @@ */ #include "flash.h" -#include "chipdrivers.h" #define MAX_REFLASH_TRIES 0x10 #define MASK_FULL 0xffff diff --git a/pm49fl00x.c b/pm49fl00x.c index 4136b17..28052e5 100644 --- a/pm49fl00x.c +++ b/pm49fl00x.c @@ -21,7 +21,6 @@ */ #include "flash.h" -#include "chipdrivers.h" static void write_lockbits_49fl00x(chipaddr bios, int size, unsigned char bits, int block_size) diff --git a/sb600spi.c b/sb600spi.c index 37aac3b..5ad5782 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -24,7 +24,6 @@ #if defined(__i386__) || defined(__x86_64__) #include "flash.h" -#include "chipdrivers.h" #include "programmer.h" #include "spi.h" diff --git a/sst_fwhub.c b/sst_fwhub.c index 65bd2b3..a11cccb 100644 --- a/sst_fwhub.c +++ b/sst_fwhub.c @@ -23,7 +23,6 @@ /* Adapted from the Intel FW hub stuff for 82802ax parts. */ #include "flash.h" -#include "chipdrivers.h" static int check_sst_fwhub_block_lock(struct flashchip *flash, int offset) { diff --git a/w29ee011.c b/w29ee011.c index 4fc8853..de6b63c 100644 --- a/w29ee011.c +++ b/w29ee011.c @@ -20,7 +20,6 @@ #include <string.h> #include "flash.h" -#include "chipdrivers.h" int probe_w29ee011(struct flashchip *flash) { diff --git a/w39.c b/w39.c index 2635988..5e5d59e 100644 --- a/w39.c +++ b/w39.c @@ -20,7 +20,6 @@ */ #include "flash.h" -#include "chipdrivers.h" static int printlock_w39_fwh_block(struct flashchip *flash, int offset) { -- 1.7.1

1 0

Probe, Read, Erase, Write Success on Winbond W25Q16 with buspirate_spi
by Jon Szymaniak 09 Jul '11

09 Jul '11

Hi there, Per the "UNTESTED" message I received in v0.9.3-r1364, I just wanted to report a couple successful PROBE, READ, WRITE and ERASE operations on a Winbond W25Q16 with a BusPirate v2g0 (FW 4.1). I suppose this is expected given that the W25X16 is supported, but thought someone might like to know ;). I've attached the requested -V dumps for the aforementioned operations, as well as 'time' output for each operation. With the BP v2g0 running FW v4.1, I was seeing ~30 min on a 2MB read, and ~90 min on a 2MB write. I see that somewhere above FW v5.7 and with some flashrom patches I should be able to get some much quicker reads and writes. If I can get that going, I'd be happy to do a bit more testing with this chip if you folks are interested. Thank you for providing a wonderful piece of software...cheers! Jon Szymaniak

1 0

Re: [flashrom] [PATCH] warn the user if flashrom is x months old
by Stefan Tauner 09 Jul '11

09 Jul '11

On Fri, 8 Jul 2011 11:46:38 -0700 David Hendricks <dhendrix(a)google.com> wrote: > On Fri, Jul 8, 2011 at 4:35 AM, Stefan Tauner < > stefan.tauner(a)student.tuwien.ac.at> wrote: > > > i had the idea to implement an expiration date for flashrom binaries > > (i.e. a time bomb). in the case distributions ship ancient binaries > > (in the future) this may save a bunch of hardware. > > > > i noted two reactions back then when i proposed this idea on IRC in my > > todo.txt: > > <twice11> If I validated software to work on some system, I don't want > > it to suddenly break one year later. > > <agaran> twice11: but kind notify that version you use is %d days old > > (and repeated every multiple of time or 100days or so) could be nice > > > > Interesting idea, but I have to agree with twice11 here. I do not want a > version of flashrom that works fine on the systems I'm supporting to > suddenly start breaking scripts or throwing superfluous warnings to users > and testers. This will definitely cause headaches for ODMs/OEMs and > commercial Linux system vendors :-( sure. when i said "it is worth to think about something like this", i meant something like the current patch, that prints a warning only. OTOH, it may still be useful to provide an option to really bail out instead of warning only (which of course would be off by default). the question is if any maintainer or individual may ever use it... if there is interest for this, i could create an add-on patch for that so we can decide its inclusion independently from the warning patch. please say so, if you think i should do that. > IMHO it would be more useful to try and get generic distros to a) not > include a flashrom binary by default and b) when a user installs it > manually, fetch and compile sources from SVN. providing a script that tries to mimic what the wiki installation guide tells the user to do, might be worth then? checking the availability of different package managers is quite easy, checking for the correct names shouldnt be much harder? > As for the patch itself, if this idea moves forward then it would be nice to > isolate the code a bit more so it can be easily removed. Rather than placing > it in print_version(), I recommend creating another function which would be > called from cli_classic(). jup, certainly a good idea. "so it can be easily removed" -> do you think anyone would really want that? does it justify an option in the makefile? maybe we should "move" the OLD_MONTHS macro to the macro and add an #ifdef around the code? carldani: the xml "parsing" is not a problem... parsing the normal svn info output would be harder. do you see a problem in the way i do it? what do you think could "cause problems for users of live CDs and FreeDOS distributions" in the current implementation? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 2

Re: [flashrom] Help: trouble when flashing rom
by Idwer Vollering 09 Jul '11

09 Jul '11

Please use "reply to all" in the future. Thanks. 2011/4/19 Cyrille Bartholomée <cyrille(a)bartholomee.com>: > Dear Idwer, > > Just built checkout from svn. It outputs this result: Again: DO NOT REBOOT OR POWEROFF YOUR LAPTOP. > > flashrom v0.9.3-r1288 on Linux 2.6.35-28-generic (i686), built with libpci > 3.1.7, GCC 4.4.5, little endian > > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... delay loop is unreliable, trying to continue OK. > > Found chipset "Intel ICH4-M", enabling flash write... OK. > > This chipset supports the following protocols: FWH. > > Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. > > Flash image seems to be a legacy BIOS. Disabling checks. > > Erasing and writing flash chip... ERASE FAILED at 0x00016000! Expected=0xff, > Read=0xae, failed byte count from 0x00016000-0x00016fff: 0xfde > > ERASE FAILED! > > ERASE FAILED at 0x00010000! Expected=0xff, Read=0xca, failed byte count from > 0x00010000-0x0001ffff: 0xfeb2 > > ERASE FAILED! > > Segmentatiefout > > Segmentatiefout=segmentation error flashrom should NOT have segfaulted. Can you show the last lines of dmesg (dmesg | tail) ? > > Maybe this information can help you? > > Regards, > > Cyrille Bartholomée | De Damhouderestraat 20 | 2018 Antwerpen > > t. 0032 3 298 4244 | m. 0032 499 711 018 | e. cyrille(a)bartholomee.com > > Op dinsdag 19 april 2011 07:25:59 schreef Cyrille Bartholomée: > >> Dear Idwer, > >> > >> > >> First of all thank you for responding so fast and trying to help me! > >> > >> 1. Downloaded and built latest flashrom. Problem remains exactly the same >> as with previous version. > >> 2. I am using an Asus laptop model M6Ne, the exact type of board I don't >> know. > >> 3. I have run the commands you mentioned, the results are attached to this >> mail. > >> > >> If there is more information you need, please let me know. > >> > >> Again, thanks for your help. > >> > >> > >> Kind regards, > >> > >> Cyrille Bartholomée | De Damhouderestraat 20 | 2018 Antwerpen > >> t. 0032 3 298 4244 | m. 0032 499 711 018 | e. cyrille(a)bartholomee.com > >> > >> Op dinsdag 19 april 2011 00:21:28 schreef u: > >> > 2011/4/18 Cyrille Bartholomée <cyrille(a)bartholomee.com>: > >> > > Dear, > >> > > > >> > > I'm facing this problem when flashing my rom: > >> > > > >> > > flashrom v0.9.2-r1028 on Linux 2.6.35-28-generic (i686), built with >> > > libpci > >> > > 3.0.0, GCC 4.4.4, little endian > >> > > > >> > > flashrom is free software, get the source code at >> > > http://www.flashrom.org > >> > > > >> > > Calibrating delay loop... delay loop is unreliable, trying to continue >> > > OK. > >> > > > >> > > No coreboot table found. > >> > > > >> > > Found chipset "Intel ICH4-M", enabling flash write... OK. > >> > > > >> > > This chipset supports the following protocols: Non-SPI. > >> > > > >> > > Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address >> > > 0xfff80000. > >> > > > >> > > Flash image seems to be a legacy BIOS. Disabling checks. > >> > > > >> > > Writing flash chip... Erasing flash chip... ERASE FAILED at >> > > 0x00000008! > >> > > Expected=0xff, Read=0x00, failed byte count from >> > > 0x00000000-0x00000fff: > >> > > 0xfc5 > >> > > > >> > > ERASE FAILED! > >> > > > >> > > ERASE FAILED at 0x00000008! Expected=0xff, Read=0x00, failed byte >> > > count from > >> > > 0x00000000-0x0000ffff: 0xfadb > >> > > > >> > > ERASE FAILED! > >> > > > >> > > FAILED! > >> > > > >> > > ERASE FAILED! > >> > > > >> > > FAILED! > >> > > > >> > > Your flash chip is in an unknown state. > >> > > > >> > > Get help on IRC at irc.freenode.net (channel #flashrom) or > >> > > > >> > > mail flashrom(a)flashrom.org! > >> > > >> > Can you: > >> > - try a newer release (or build the latest developemt code yourself > >> > http://www.flashrom.org/Downloads#Installation_from_source) > >> > - mention the exact name of your board (including revision, if there > >> > are multiple revisions) > >> > - attach the output of 'flashrom -V', 'lspci -nnvvvxxx', 'superiotool > >> > -deV' (run all commands as root) > >> > > >> > > >> > Thanks in advance, > >> > Idwer > >> > > >> > > > >> > > >> > > ------------------------------------------------------------------------------- > >> > > > >> > > DO NOT REBOOT OR POWEROFF! > >> > > > >> > > Regards, > >> > > > >> > > Cyrille Bartholomée | De Damhouderestraat 20 | 2018 Antwerpen > >> > > > >> > > t. 0032 3 298 4244 | m. 0032 499 711 018 | e. cyrille(a)bartholomee.com > >> > > > >> > > _______________________________________________ > >> > > flashrom mailing list > >> > > flashrom(a)flashrom.org > >> > > http://www.flashrom.org/mailman/listinfo/flashrom > >> > > > >> > > >>

3 10

[commit] r1368 - trunk
by repository service 09 Jul '11

09 Jul '11

Author: stefanct Date: Sat Jul 9 21:46:53 2011 New Revision: 1368 URL: http://flashrom.org/trac/flashrom/changeset/1368 Log: add untested board enable for ASUS M6Ne http://patchwork.coreboot.org/patch/2893/ lspci: http://paste.flashrom.org/view.php?id=494 only writing a backup file was tested, so mark it as untested. Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Thu Jul 7 21:56:58 2011 (r1367) +++ trunk/board_enable.c Sat Jul 9 21:46:53 2011 (r1368) @@ -1521,6 +1521,15 @@ /* * Suited for: + * - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M + */ +static int intel_ich_gpio43_raise(void) +{ + return intel_ich_gpio_set(43, 1); +} + +/* + * Suited for: * - HP Vectra VL400: 815 + ICH + PC87360 */ static int board_hp_vl400(void) @@ -1996,6 +2005,7 @@ {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, P3, "ASUS", "A8N-VM CSM", 0, NT, w83627ehf_gpio24_raise_2e}, {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, P3, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, P3, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, + {0x8086, 0x24cc, 0, 0, 0x8086, 0x24c3, 0x1043, 0x1869, "^M6Ne$", NULL, NULL, P3, "ASUS", "M6Ne", 0, NT, intel_ich_gpio43_raise}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^P2B-N$", NULL, NULL, P3, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower}, {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, P3, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, P3, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Thu Jul 7 21:56:58 2011 (r1367) +++ trunk/print.c Sat Jul 9 21:46:53 2011 (r1368) @@ -451,6 +451,7 @@ B("ASUS", "M4A785TD-M EVO", 1, "http://www.asus.com/product.aspx?P_ID=QHbvGVB1mXmmD8qQ", NULL), B("ASUS", "M4A79T Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=lhJiLTN5huPfCVkW", NULL), B("ASUS", "M4A87TD/USB3", 1, "http://www.asus.com/product.aspx?P_ID=nlWYrI9wlNIYHAaa", NULL), + B("ASUS", "M6Ne", 0, "http://www.asus.com/Product.aspx?P_ID=IbqN4JCxeRiep4WN", "Untested board enable."), B("ASUS", "MEW-AM", 0, "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/", "No public report found. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>. May work now."), B("ASUS", "MEW-VM", 0, "http://www.elhvb.com/mboards/OEM/HP/manual/ASUS%20MEW-VM.htm", "No public report found. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>. May work now."), B("ASUS", "P2B", 1, "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b/", NULL),

1 0

Is the DVD burner LG GSA-4167B supported?
by Paul Menzel 09 Jul '11

09 Jul '11

Dear flashrom folks, listening to Carl-Daniel’s interview with RadioTux at LinuxTag [1] he mentions that flashrom also supports some DVD drives. Does flashrom support the DVD burner LG GSA-4167B? Searching the WWW I found a forum post [2] but contacting the author [3] was unsuccessful. Here is an excerpt from my message to the author. I want to flash my drive LG GSA-4167B currently running firmware version DL12 to DL13 [4][5]. $ dmesg [ 1.588392] ata4.00: ATAPI: HL-DT-ST DVDRAM GSA-4167B, DL12, max UDMA/33 [ 1.605261] ata4.00: configured for UDMA/33 [ 1.614030] scsi 3:0:0:0: CD-ROM HL-DT-ST DVDRAM GSA-4167B DL12 PQ: 0 ANSI: 5 It would be great if you could help me and provide me with the utility. What license do you use for your flasher? I guess the flashrom project [6] would be very much interested in your program. Thanks, Paul [1] http://blog.radiotux.de/2011/06/09/linuxtag-interview-mit-carl-daniel-von-f… [2] http://club.myce.com/f91/firmware-update-linux-304147/#post2465757 [3] http://devilsclaw.net/ [4] http://www.cdrinfo.com/Sections/Firmware/SingleModel.aspx?DriveId=1177 [5] http://lgodd.lge.com/fwdrv/DVD-WRITER/GSA4167DL13.exe [6] http://flashrom.org/

1 0

[PATCH] warn the user if flashrom is x months old
by Stefan Tauner 08 Jul '11

08 Jul '11

i had the idea to implement an expiration date for flashrom binaries (i.e. a time bomb). in the case distributions ship ancient binaries (in the future) this may save a bunch of hardware. i noted two reactions back then when i proposed this idea on IRC in my todo.txt: <twice11> If I validated software to work on some system, I don't want it to suddenly break one year later. <agaran> twice11: but kind notify that version you use is %d days old (and repeated every multiple of time or 100days or so) could be nice this proof of concept is probably not mergeable - especially the strptime() might be a problem (alternatives welcome), but i still think it is worth to think about something like this. comments? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

4 4

Re: [flashrom] [Patch] NVIDIA Tegra2 SPI controller support
by Carl-Daniel Hailfinger 07 Jul '11

07 Jul '11

Am 07.07.2011 02:32 schrieb David Hendricks: > On Tue, Jun 28, 2011 at 5:54 PM, Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2006(a)gmx.net> wrote: > >> 2-3-add_arm_isms.patch >> Have you checked with an architecture guru that sync_primitive() can >> really be empty, not only for that arch in general, but also for >> accesses to a mmapped region the way flashrom does it? >> > Nope. Scattered resources/forum posts about ARMv7 suggest that peripheral > memory is strongly ordered. Also, the U-Boot code doesn't have special > handling for sync primitives AFAICT. > > I'm pretty new to ARM... Any advice from experts on this list would be > appreciated. > I can't help you directly, but if you tell a Linux kernel developer with ARM experience how we access such regions, he/she might have some useful info for you: open("/dev/mem", O_RDWR | O_SYNC), then mmap, then reading/writing those regions with "normal" memory accessors. Opening /dev/mem with O_SYNC sometimes already has the right propertiess and no additional ordering helper is required. > I've updated this patch set on top of the other patches you've been working > on (autodetect target processor <http://patchwork.coreboot.org/patch/3256/> > and the libpci hack <http://patchwork.coreboot.org/patch/3255/>). > Thanks. > The difference between this patchset and the previous one is pretty minor. > We can now discard the first patch which #ifdef'd out PCI code for ARM > targets. The remaining differences are mostly centered around the Makefile > and arch.h > > New patches are: > Signed-off-by: David Hendricks <dhendrix(a)google.com> > > > 2-2-add_tegra2_spi_controller.patch: > Index: flashrom-tegra2/processor_enable.c > =================================================================== > --- flashrom-tegra2.orig/processor_enable.c > +++ flashrom-tegra2/processor_enable.c > @@ -81,6 +81,48 @@ static int is_loongson(void) > } > #endif > > +#if defined(__arm__) > +#include <stdio.h> > +#include <string.h> > +#include <ctype.h> > + > +/* Returns true if the /proc/cpuinfo contains a line: "CPU part *: *0xc09". > + * TODO: need to extend in future for same SPI controller in chip family. > + */ > +static int is_tegra2(void) > +{ > + FILE *cpuinfo; > + uint32_t impl = 0, architecture = 0, variant = 0, part = 0; > + const char *name = "CPU part"; > + const char *value = "0xc09"; > + int ret = 0; > + > + cpuinfo = fopen("/proc/cpuinfo", "rb"); > Hm. Would it be possible to share some code with the Loongson cpuinfo parser? > + if (!cpuinfo) > + return 0; > + while (!feof(cpuinfo)) { > + char line[512], *ptr; > + if (fgets(line, sizeof(line), cpuinfo) == NULL) > + break; > + ptr = line; > + while (*ptr && isspace((unsigned char)*ptr)) > + ptr++; > + if (strncmp(ptr, name, strlen(name)) == 0) > + ptr += strlen(name); > + while (*ptr && isspace((unsigned char)*ptr)) > + ptr++; > + if (*ptr != ':') > + continue; > + ptr++; > + while (*ptr && isspace((unsigned char)*ptr)) > + ptr++; > + ret = (strncmp(ptr, value, strlen(value)) == 0); > + } > I'm going to trust you on this code. It seems to work for you. > + fclose(cpuinfo); > + return ret; > +} > +#endif > + > int processor_flash_enable(void) > { > /* FIXME: detect loongson on FreeBSD and OpenBSD as well. */ > @@ -90,6 +132,13 @@ int processor_flash_enable(void) > return 0; > } > #endif > + > +#if defined (__arm__) > + if (is_tegra2()) { > + msg_pdbg("Detected NVIDIA Tegra 2.\n"); > + return tegra2_spi_init(); > + } > +#endif > /* Not implemented yet. Oh well. */ > return 1; > } > Index: flashrom-tegra2/programmer.h > =================================================================== > --- flashrom-tegra2.orig/programmer.h > +++ flashrom-tegra2/programmer.h > @@ -524,6 +524,9 @@ enum spi_controller { > SPI_CONTROLLER_VIA, > SPI_CONTROLLER_WBSIO, > #endif > +#if defined(__arm__) > + SPI_CONTROLLER_TEGRA2, > +#endif > #endif > #if CONFIG_FT2232_SPI == 1 > SPI_CONTROLLER_FT2232, > @@ -589,6 +592,13 @@ int mcp6x_spi_init(int want_spi); > /* sb600spi.c */ > int sb600_probe_spi(struct pci_dev *dev); > > +/* tegra2_spi.c */ > +int tegra2_spi_init(void); > +int tegra2_spi_send_command(unsigned int writecnt, unsigned int readcnt, > + const unsigned char *writearr, unsigned char *readarr); > +int tegra2_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > +int tegra2_spi_write(struct flashchip *flash, uint8_t *buf, int start, int len); > Can you kill the two lines above? > + > /* wbsio_spi.c */ > int wbsio_check_for_spi(void); > #endif > Index: flashrom-tegra2/tegra2_spi.c > =================================================================== > --- /dev/null > +++ flashrom-tegra2/tegra2_spi.c > @@ -0,0 +1,405 @@ > +/* > + * This file is part of the flashrom project. > + * > + * Copyright (C) 2010 NVIDIA Corporation > + * Copyright (C) 2011 Google Inc > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#if defined(__arm__) > +#include <assert.h> > +#include <stdio.h> > +#include <stdlib.h> > +#include <string.h> > + > +#include "flash.h" > +#include "programmer.h" > +#include "tegra2_spi.h" > + > +static void *gpio_base, *clkrst_base, *apbmisc_base, *spi_base; > + > +#define SPI_TIMEOUT 50000 /* 100ms = 50000 * 2us */ > + > +/* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */ > +#define UART_DISABLE_PORT 8 > +#define UART_DISABLE_BIT 3 > + > +/* Config port:bit as GPIO, not SFPIO (default) */ > +static void __set_config(unsigned port, unsigned bit, int type) > Rename type to val? Names starting with __ do not really make me happy. How about tegra2_spi_set_config? Or are there compelling cosmetic reasons? > +{ > + u32 u; > + > + msg_pdbg("%s: port = %d, bit = %d, %s\n", __func__, > + port, bit, type ? "GPIO" : "SFPIO"); > + > + u = mmio_readl(GPIO_CNF(port)); > + if (type) /* GPIO */ > + u |= 1 << bit; > + else > + u &= ~(1 << bit); > + rmmio_writel(u, GPIO_CNF(port)); > +} > + > +/* Config GPIO port:bit as input or output (OE) */ > +static void __set_direction(unsigned port, unsigned bit, int output) > Function rename, please (see above). > +{ > + u32 u; > + > + msg_pdbg("%s: port = %d, bit = %d, %s\n", __func__, > + port, bit, output ? "OUT" : "IN"); > + > + u = mmio_readl(GPIO_OE(port)); > + if (output) > + u |= 1 << bit; > + else > + u &= ~(1 << bit); > + rmmio_writel(u, GPIO_OE(port)); > +} > + > +/* set GPIO OUT port:bit as 0 or 1 */ > +static void __set_level(unsigned port, unsigned bit, int high) > Rename high to val? > +{ > + u32 u; > + > + msg_pdbg("%s: port = %d, bit %d == %d\n", __func__, > + port, bit, high); > + > + u = mmio_readl(GPIO_OUT(port)); > + if (high) > + u |= 1 << bit; > + else > + u &= ~(1 << bit); > + rmmio_writel(u, GPIO_OUT(port)); > +} > + > +/* set GPIO port:bit as an output, with polarity 'value' */ > +static int tg2_gpio_direction_output(unsigned port, unsigned bit, int value) > Rename value to val? Or rename val to value everywhere else in this patch? > +{ > + msg_pdbg("%s: port = %d, bit = %d, value = %d\n", > + __func__, port, bit, value); > + > + /* Configure as a GPIO */ > + __set_config(port, bit, 1); > + > + /* Configure GPIO output value. */ > + __set_level(port, bit, value); > + > + /* Configure GPIO direction as output. */ > + __set_direction(port, bit, 1); > + > + return 0; > +} > + > +static void spi_cs_activate(void) > +{ > + uint32_t *spi_cmd = (uint32_t *)spi_base; > + > + /* > + * CS is negated on Tegra, so drive a 1 to get a 0 > + */ > + mmio_writel(mmio_readl(spi_cmd) | SPI_CMD_CS_VAL, spi_cmd); > + msg_pspew("%s: CS driven %s\n", __func__, > + (mmio_readl(spi_cmd) & SPI_CMD_CS_VAL) ? "LOW" : "HIGH"); > +} > + > +static void spi_cs_deactivate(void) > +{ > + uint32_t *spi_cmd = (uint32_t *)spi_base; > + > + > + /* > + * CS is negated on Tegra, so drive a 0 to get a 1 > + */ > + mmio_writel(mmio_readl(spi_cmd) & ~SPI_CMD_CS_VAL, spi_cmd); > + msg_pspew("%s: CS driven %s\n", __func__, > + (mmio_readl(spi_cmd) & SPI_CMD_CS_VAL) ? "LOW" : "HIGH"); > +} > + > +/* Helper function to calculate the clock cycle in this round. > + * Also updates the byte count remaining to be used this round. > + * > + * For example, we want to write 6 bytes to SPI and then read 5 bytes back. > + * > + * +---+---+---+---+---+---+ > + * | W | W | W | W | W | W | > + * +---+---+---+---+---+---+---+---+---+---+---+ > + * | R | R | R | R | R | > + * +---+---+---+---+---+ > + * |<-- round 0 -->| > + * |<-- round 1 -->| > + * |<-- round 2 -->| > + * > + * So that the continuous calling this function would get: > + * > + * round| RET| writecnt readcnt bits to_write to_read > + * -----+----+--------------------------------------------- > + * INIT | | 6 5 > + * 0 | 1 | 2 5 32 4 0 > + * 1 | 1 | 0 3 32 2 2 > + * 2 | 1 | 0 0 24 0 3 > + * 3 | 0 | - - - - - > + * > + */ > +int next4Bytes(uint32_t *writecnt, uint32_t *readcnt, int *num_bits, > + uint32_t *to_write, uint32_t *to_read) { > + assert(writecnt); > Won't this explode in round 1+2? > + assert(readcnt); > Won't this explode in round 2? > + assert(num_bits); > + assert(to_write); > Explosions in round 2? > + assert(to_read); > Explosions in round 0? > + > + *to_write = min(*writecnt, 4); > + *to_read = min(*readcnt, 4 - *to_write); > + > + *writecnt -= *to_write; > + *readcnt -= *to_read; > + > + *num_bits = (*to_write + *to_read) * 8; > + > + if (*num_bits) > + return 1; /* need to be called again. */ > + else > + return 0; /* handled write and read requests. */ > +} > + > +/* > + * Tegra2 FIFO design is ... interesting. For example, you want to Tx 2 bytes: > + * > + * +---+---+ > + * writearr[]: | 0 | 1 | > + * +---+---+ > + * \ \ > + * \ \ > + * \ \ > + * \ \ > + * \ \ > + * 31 +---+---+---+---+ 0 > + * tmp(32-bits): | X | X | 0 | 1 | > + * +---+---+---+---+ LSB > + * > + * It is neither little or big endian. The first bit for SPI controller to > + * transfer is the bit 15 in FIFO, neither bit 31 or bit 0, because the transfer > + * length is 16 bits (2 bytes). > + * > + * Rx follows the similar rule. First bit comes at bit 0, and the whole FIFO > + * left-shifts 1 bit for every bit comes in. Hence, after reading 3 bytes, > + * the first coming bit will reside in bit 23. > + */ > +int tegra2_spi_send_command(unsigned int writecnt, > + unsigned int readcnt, > + const unsigned char *writearr, > + unsigned char *readarr) > +{ > + int retval = 0; > + uint8_t *delayed_msg = NULL; /* for UART is disabled. */ > + uint32_t *spi_cmd = (uint32_t *)spi_base; > + uint32_t *spi_sts = (uint32_t *)(spi_base + 0x04); > + uint32_t *tx_fifo = (uint32_t *)(spi_base + 0x10); > + uint32_t *rx_fifo = (uint32_t *)(spi_base + 0x20); > + uint32_t status; > + uint32_t to_write, to_read; /* byte counts to fill FIFO. */ > + uint32_t bits; /* bit count to tell SPI controller. */ > + > + mmio_writel(mmio_readl(spi_sts), spi_sts); > + mmio_writel(mmio_readl(spi_cmd) | SPI_CMD_TXEN | SPI_CMD_RXEN, spi_cmd); > + spi_cs_activate(); > + > + while (next4Bytes(&writecnt, &readcnt, &bits, &to_write, &to_read)) { > + int i; > + uint32_t tmp; > + uint32_t tm; /* timeout counter */ > + > + /* prepare Tx FIFO */ > + for (tmp = 0, i = 0; i < to_write; ++i) { > + tmp |= (*writearr++) << ((bits / 8 - 1 - i) * 8); > + } > + mmio_writel(tmp, tx_fifo); > + > + /* Kick the SCLK running: Shift out TX FIFO, and receive RX. */ > + mmio_writel(mmio_readl(spi_cmd) & ~SPI_CMD_BIT_LENGTH_MASK, > + spi_cmd); > + mmio_writel(mmio_readl(spi_cmd) | (bits - 1), > + spi_cmd); > + mmio_writel(mmio_readl(spi_cmd) | SPI_CMD_GO, spi_cmd); > + > + /* Wait for controller completes the task. */ > + for (tm = 0; tm < SPI_TIMEOUT; ++tm) { > + if (((status = mmio_readl(spi_sts)) & > + (SPI_STAT_BSY | SPI_STAT_RDY)) == SPI_STAT_RDY) > + break; > + /* We setup clock to 6MHz, so that we shall come back > + * after: 1 / (6MHz) * 8 bits = 1.333us > + */ > + programmer_delay(2); > + } > + mmio_writel(mmio_readl(spi_sts) | SPI_STAT_RDY, spi_sts); > + > + /* Since the UART is disabled here, we delay printing the > + * message until spi_cs_deactivate() is called. > + */ > + if (tm >= SPI_TIMEOUT) { > + static uint8_t err[256]; > + retval = -1; > + snprintf(err, sizeof(err), > + "%s():%d BSY&RDY timeout, status = 0x%08x\n", > + __func__, __LINE__, status); > + delayed_msg = err; > + break; > + } > + > + /* read RX FIFO */ > + tmp = mmio_readl(rx_fifo); > + for (i = 0; i < to_read; ++i) { > + *readarr++ = (tmp >> ((to_read - 1 - i) * 8)) & 0xFF; > + } > + } > + > + mmio_writel(status = mmio_readl(spi_sts), spi_sts); > + > + spi_cs_deactivate(); > + if (delayed_msg) { > + msg_perr("%s\n", delayed_msg); > + } > + > + return retval; > +} > + > +int tegra2_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +{ > + return spi_read_chunked(flash, buf, start, len, > + spi_programmer->max_data_read); > +} > The function above is not needed anymore. > + > +int tegra2_spi_write(struct flashchip *flash, uint8_t *buf, int start, int len) > +{ > + return spi_write_chunked(flash, buf, start, len, > + spi_programmer->max_data_write); > +} > The function above is not needed anymore. > + > +/* Unmap register spaces */ > +int tegra2_spi_shutdown(void *data) > +{ > + physunmap(gpio_base, 4096); > + physunmap(clkrst_base, 4096); > + physunmap(apbmisc_base, 4096); > + physunmap(spi_base - 0x380, 4096); > + return 0; > +} > + > +static const struct spi_programmer spi_programmer_tegra2 = { > + .type = SPI_CONTROLLER_TEGRA2, > + /* FIFO depth is 32, packets can be up to 32-bits in length. */ > + .max_data_read = 128, > + .max_data_write = 128, > + .command = tegra2_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = tegra2_spi_read, > + .write_256 = tegra2_spi_write, > Please change .read and .write_256 to use the generic functions if possible. > +}; > + > +/* Map register spaces */ > +int tegra2_spi_init(void) > +{ > + u32 val; > + uint32_t *spi_cmd; > + uint32_t *spi_sts; > + > + buses_supported = CHIP_BUSTYPE_SPI; > AFAICS setting buses_supported is handled by register_spi_programmer. That said, you may want to set it to CHIP_BUSTYPE_NONE here (the handling of buses_supported for internal is a bit weird for historic reasons). > + register_spi_programmer(&spi_programmer_tegra2); > Way too early, needs to be at the end of the init function. > + > + gpio_base = physmap("GPIO", TEGRA2_GPIO_BASE, 4096); > + clkrst_base = physmap("CLK/RST", NV_ADDRESS_MAP_PPSB_CLK_RST_BASE, > + 4096); > + apbmisc_base = physmap("APB MISC", NV_ADDRESS_MAP_APB_MISC_BASE, 4096); > + /* non-page offset */ > + spi_base = physmap("SPI", TEGRA2_SPI_BASE - 0x380, 4096) + 0x380; > + > + register_shutdown(tegra2_spi_shutdown, NULL); > + > + flashbase = 0; /* FIXME: to make sanity check happy. */ > + > + /* Init variables */ > + spi_cmd = (uint32_t *)spi_base; > + spi_sts = (uint32_t *)(spi_base + 0x04); > + > + /* > + * SPI reset/clocks init - reset SPI, set clocks, release from reset > + */ > + > + /* SWE_SPI1_RST: Hold SPI controller 1 in reset */ > + val = mmio_readl(clkrst_base + 0x08) | 0x800; > + rmmio_writel(val, (clkrst_base + 0x08)); > + msg_pdbg("%s: ClkRst = %08x\n", __func__, val); > + > + /* CLK_ENB_SPI1: Enable clock to SPI 1 Controller */ > + val = mmio_readl(clkrst_base + 0x14) | 0x800; > + rmmio_writel(val, (clkrst_base + 0x14)); > + msg_pdbg("%s: ClkEnable = %08x\n", __func__, val); > + > + /* Change default SPI clock from 12MHz to 6MHz, same as BootROM */ > + val = mmio_readl(clkrst_base + 0x114) | 0x2; > + rmmio_writel(val, (clkrst_base + 0x114)); > + msg_pdbg("%s: ClkSrc = %08x\n", __func__, val); > + > + /* SWE_SPI1_RST: Clear SPI1 reset bit (take it out of reset), > + * use regular mmio_writel (restore callback already registered) */ > + val = mmio_readl(clkrst_base + 0x08) & 0xFFFFF7FF; > + mmio_writel(val, (clkrst_base + 0x08)); > + msg_pdbg("%s: ClkRst final = %08x\n", __func__, val); > + > + /* Clear stale status here */ > + mmio_writel(SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | > + SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF, spi_sts); > + msg_pdbg("%s: STATUS = %08x\n", __func__, mmio_readl(spi_sts)); > + > + /* > + * Use sw-controlled CS, so we can clock in data after ReadID, etc. > + */ > + mmio_writel(mmio_readl(spi_cmd) | SPI_CMD_CS_SOFT, spi_cmd); > + msg_pdbg("%s: COMMAND = %08x\n", __func__, mmio_readl(spi_cmd)); > + > + /* > + * SPI pins on Tegra2 are muxed - change pinmux last due to UART issue > + */ > + val = mmio_readl(apbmisc_base + 0x88) | 0xC0000000; > + rmmio_writel(val, (apbmisc_base + 0x88)); > + msg_pdbg("%s: PinMuxRegC = %08x\n", __func__, val); > + > + /* Set Z_LSPI to non-tristate mode */ > + val = mmio_readl(apbmisc_base + 0x20) & 0xFFFFFFFE; > + rmmio_writel(val, (apbmisc_base + 0x20)); > + msg_pdbg("%s: TriStateReg = %08x\n", __func__, val); > + > + /* delay 100ms so that all chars in buffer (1KB) can be flushed. */ > + programmer_delay(100000); > + > + /* > + * We need to dynamically change the pinmux, shared w/UART RXD/CTS! > + */ > + val = mmio_readl(apbmisc_base + 0x84) | 0x0000000C; /* 3 = SFLASH */ > + rmmio_writel(val, (apbmisc_base + 0x84)); > + msg_pdbg("%s: PinMuxRegB = %08x\n", __func__, val); > + > + /* On Seaboard, MOSI/MISO are shared w/UART. > + * Use GPIO I3 (UART_DISABLE) to tristate UART during SPI activity. > + * Enable UART later (cs_deactivate) so we can use it for U-Boot comms. > + */ > + msg_pdbg("%s: DISABLING UART!\n", __func__); > + tg2_gpio_direction_output(UART_DISABLE_PORT, UART_DISABLE_BIT, 1); > Here is the right place for register_spi_programmer. > + > + return 0; > +} > +#endif > Index: flashrom-tegra2/tegra2_spi.h > =================================================================== > --- /dev/null > +++ flashrom-tegra2/tegra2_spi.h > @@ -0,0 +1,81 @@ > +/* > + * This file is part of the flashrom project. > + * > + * Copyright (C) 2010 NVIDIA Corporation > + * Copyright (C) 2011 Google Inc > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#ifndef __TEGRA2_SPI_H__ > +#define __TEGRA2_SPI_H__ > + > +// *************************************************************************** > +// Hardware BARs > + > +#define TEGRA2_GPIO_BASE 0x6000D000 > +#define TEGRA2_SPI_BASE 0x7000C380 > +#define NV_ADDRESS_MAP_PPSB_CLK_RST_BASE 0x60006000 > +#define NV_ADDRESS_MAP_APB_MISC_BASE 0x70000000 > + > +// *************************************************************************** > +// Clock/reset controller > +#define CLK_RST_ENB_H_0_OFFSET 0x14 > +#define CLK_RST_ENB_H_0_SPI1 (1 << 11) > + > +// *************************************************************************** > +// GPIO controller > + > +#define GPIO_OFF(port) (((port / 4) * 128) + ((port % 4) * 4)) > +#define GPIO_CNF(port) (gpio_base + GPIO_OFF(port) + 0x00) > +#define GPIO_OE(port) (gpio_base + GPIO_OFF(port) + 0x10) > +#define GPIO_OUT(port) (gpio_base + GPIO_OFF(port) + 0x20) > +#define GPIO_IN(port) (gpio_base + GPIO_OFF(port) + 0x30) > +#define GPIO_INT_STA(port) (gpio_base + GPIO_OFF(port) + 0x40) > +#define GPIO_INT_ENB(port) (gpio_base + GPIO_OFF(port) + 0x50) > +#define GPIO_INT_LVL(port) (gpio_base + GPIO_OFF(port) + 0x60) > +#define GPIO_INT_CLR(port) (gpio_base + GPIO_OFF(port) + 0x70) > + > +#define SPI_CMD_GO (1 << 30) > +#define SPI_CMD_ACTIVE_SCLK (1 << 26) > +#define SPI_CMD_CK_SDA (1 << 21) > +#define SPI_CMD_ACTIVE_SDA (1 << 18) > +#define SPI_CMD_CS_POL (1 << 16) > +#define SPI_CMD_TXEN (1 << 15) > +#define SPI_CMD_RXEN (1 << 14) > +#define SPI_CMD_CS_VAL (1 << 13) > +#define SPI_CMD_CS_SOFT (1 << 12) > +#define SPI_CMD_CS_DELAY (1 << 9) > +#define SPI_CMD_CS3_EN (1 << 8) > +#define SPI_CMD_CS2_EN (1 << 7) > +#define SPI_CMD_CS1_EN (1 << 6) > +#define SPI_CMD_CS0_EN (1 << 5) > +#define SPI_CMD_BIT_LENGTH (1 << 4) > +#define SPI_CMD_BIT_LENGTH_MASK 0x0000001F > + > +#define SPI_STAT_BSY (1 << 31) > +#define SPI_STAT_RDY (1 << 30) > +#define SPI_STAT_RXF_FLUSH (1 << 29) > +#define SPI_STAT_TXF_FLUSH (1 << 28) > +#define SPI_STAT_RXF_UNR (1 << 27) > +#define SPI_STAT_TXF_OVF (1 << 26) > +#define SPI_STAT_RXF_EMPTY (1 << 25) > +#define SPI_STAT_RXF_FULL (1 << 24) > +#define SPI_STAT_TXF_EMPTY (1 << 23) > +#define SPI_STAT_TXF_FULL (1 << 22) > +#define SPI_STAT_SEL_TXRX_N (1 << 16) > +#define SPI_STAT_CUR_BLKCNT (1 << 15) > + > +#endif /* __TEGRA2_SPI_H__ */ > Index: flashrom-tegra2/Makefile > =================================================================== > --- flashrom-tegra2.orig/Makefile > +++ flashrom-tegra2/Makefile > @@ -310,6 +310,10 @@ PROGRAMMER_OBJS += processor_enable.o ch > ifeq ($(ARCH),"x86") > PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o > else > +ifeq ($(ARCH),"arm") > +PROGRAMMER_OBJS += tegra2_spi.o > +else > +endif > endif > NEED_PCI := yes > endif > My overall impression of the Tegra2 SPI driver is that the hardware is some weird bitbanging/bytewise combination and nobody is sure how to deal with it. Please note that this is still not a complete review, but it will allow to get the patch closer to a mergeable state. Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

[commit] r1367 - trunk
by repository service 07 Jul '11

07 Jul '11

Author: stefanct Date: Thu Jul 7 21:56:58 2011 New Revision: 1367 URL: http://flashrom.org/trac/flashrom/changeset/1367 Log: add a bunch of new/tested stuff and various small changes 4 - add Asus E35M1-I DELUXE to boards_known http://www.flashrom.org/pipermail/flashrom/2011-June/006918.html - add Asus M3A to boards_known http://www.flashrom.org/pipermail/flashrom/2011-July/007085.html - add Freetech P6F91i to boards_known http://www.flashrom.org/pipermail/flashrom/2011-June/006800.html - add GA-M720-US3 to boards_known http://www.flashrom.org/pipermail/flashrom/2011-July/007096.html - add GA-MA770-UD3 (rev. 2.1) to boards_known http://www.flashrom.org/pipermail/flashrom/2011-June/006879.html - add GA-965GM-S2 to boards_known http://www.flashrom.org/pipermail/flashrom/2011-June/006746.html - add HP xw4400 (0A68h) to boards_known http://paste.flashrom.org/view.php?id=686 - add MSI MS-6566 (845 Ultra-C) to boards_known http://www.flashrom.org/pipermail/flashrom/2011-June/006908.html - add MSI MS-7698 (E350IA-E45) to boards_known http://www.flashrom.org/pipermail/flashrom/2011-June/007003.html - add PCCHIPS M863G (V5.1A) to boards_known http://www.flashrom.org/pipermail/flashrom/2011-July/007084.html - modify the X8SIE entry in boards_known with the information from "fuzzy" http://paste.flashrom.org/view.php?id=669 - mark W29C020(C)/W29C022 as fully tested http://www.flashrom.org/pipermail/flashrom/2011-June/006800.html - mark W49V002A as fully tested http://www.flashrom.org/pipermail/flashrom/2011-July/007084.html - mark M25P128 as fully tested http://www.flashrom.org/pipermail/flashrom/2011-June/006843.html - mark SST39SF010A as fully tested http://www.flashrom.org/pipermail/flashrom/2011-July/007115.html - correct entries for GA-K8NS Pro-939 (was ultra before. thanks uwe!) - another tiny fix for "a small fix"/r1321 Without this you will get broken bus names "Unknow" and "Non-SP". Note to self: don't self-ack even fairly trivial patches. - fix spew output of spi_rems in spi25.c - add URL to ASUS M3A76-CM - rename all Winbond W25x chips to W25X - fixes some common misspellings/typos in comments: lenght->length 2 ocassional->occasional 1 unsucessfull->unsuccessful 1 upto->up to 5 the patch for M25P128 is Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan(a)gmail.com> the typos are Signed-off-by: Peter Huewe <peterhuewe(a)gmx.de> everything else is Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/buspirate_spi.c trunk/dmi.c trunk/flashchips.c trunk/print.c trunk/serprog-protocol.txt trunk/serprog.c trunk/spi25.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Thu Jul 7 08:59:18 2011 (r1366) +++ trunk/board_enable.c Thu Jul 7 21:56:58 2011 (r1367) @@ -986,7 +986,7 @@ /* * Suited for: - * - Gigabyte GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8 + * - GIGABYTE GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8 */ static int nvidia_mcp_gpio0a_raise(void) { Modified: trunk/buspirate_spi.c ============================================================================== --- trunk/buspirate_spi.c Thu Jul 7 08:59:18 2011 (r1366) +++ trunk/buspirate_spi.c Thu Jul 7 21:56:58 2011 (r1367) @@ -203,7 +203,7 @@ * sufficient either. Use a 1.5 ms delay inside the loop to make * mostly sure that at least one USB frame had time to arrive. * Looping only 5 times is not sufficient and causes the - * ocassional failure. + * occasional failure. * Folding the delay into the loop above is not reliable either. */ for (i = 0; i < 10; i++) { Modified: trunk/dmi.c ============================================================================== --- trunk/dmi.c Thu Jul 7 08:59:18 2011 (r1366) +++ trunk/dmi.c Thu Jul 7 21:56:58 2011 (r1367) @@ -119,7 +119,7 @@ while (!feof(dmidecode_pipe)) getc(dmidecode_pipe); if (pclose(dmidecode_pipe) != 0) { - msg_pinfo("dmidecode execution unsucessfull - continuing " + msg_pinfo("dmidecode execution unsuccessful - continuing " "without DMI info\n"); return NULL; } Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Thu Jul 7 08:59:18 2011 (r1366) +++ trunk/flashchips.c Thu Jul 7 21:56:58 2011 (r1367) @@ -5771,7 +5771,7 @@ .total_size = 128, .page_size = 4096, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, /* 150 ns */ .block_erasers = @@ -6705,7 +6705,7 @@ .model_id = ST_M25P128, .total_size = 16384, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -7776,7 +7776,7 @@ { .vendor = "Winbond", - .name = "W25x10", + .name = "W25X10", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = WINBOND_NEX_ID, .model_id = WINBOND_NEX_W25X10, @@ -7807,7 +7807,7 @@ { .vendor = "Winbond", - .name = "W25x20", + .name = "W25X20", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = WINBOND_NEX_ID, .model_id = WINBOND_NEX_W25X20, @@ -7838,7 +7838,7 @@ { .vendor = "Winbond", - .name = "W25x40", + .name = "W25X40", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = WINBOND_NEX_ID, .model_id = WINBOND_NEX_W25X40, @@ -7869,7 +7869,7 @@ { .vendor = "Winbond", - .name = "W25x80", + .name = "W25X80", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = WINBOND_NEX_ID, .model_id = WINBOND_NEX_W25X80, @@ -7900,7 +7900,7 @@ { .vendor = "Winbond", - .name = "W25x16", + .name = "W25X16", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = WINBOND_NEX_ID, .model_id = WINBOND_NEX_W25X16, @@ -7937,7 +7937,7 @@ { .vendor = "Winbond", - .name = "W25x32", + .name = "W25X32", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = WINBOND_NEX_ID, .model_id = WINBOND_NEX_W25X32, @@ -7974,7 +7974,7 @@ { .vendor = "Winbond", - .name = "W25x64", + .name = "W25X64", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = WINBOND_NEX_ID, .model_id = WINBOND_NEX_W25X64, @@ -8041,9 +8041,9 @@ .total_size = 256, .page_size = 128, .feature_bits = FEATURE_LONG_RESET, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, - .probe_timing = 10, + .probe_timing = 10, .block_erasers = { { @@ -8397,9 +8397,9 @@ .total_size = 256, .page_size = 128, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, - .probe_timing = 10, + .probe_timing = 10, .block_erasers = { { Modified: trunk/print.c ============================================================================== --- trunk/print.c Thu Jul 7 08:59:18 2011 (r1366) +++ trunk/print.c Thu Jul 7 21:56:58 2011 (r1367) @@ -34,13 +34,13 @@ { char *ret = calloc(1, 1); if (bustype == CHIP_BUSTYPE_UNKNOWN) { - ret = strcat_realloc(ret, "Unknown,"); + ret = strcat_realloc(ret, "Unknown, "); /* * FIXME: Once all chipsets and flash chips have been updated, NONSPI * will cease to exist and should be eliminated here as well. */ } else if (bustype == CHIP_BUSTYPE_NONSPI) { - ret = strcat_realloc(ret, "Non-SPI,"); + ret = strcat_realloc(ret, "Non-SPI, "); } else { if (bustype & CHIP_BUSTYPE_PARALLEL) ret = strcat_realloc(ret, "Parallel, "); @@ -431,6 +431,7 @@ B("ASUS", "A8V Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=tvpdgPNCPaABZRVU", NULL), B("ASUS", "A8V-E Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=hQBPIJWEZnnGAZEh", NULL), B("ASUS", "A8V-E SE", 1, "http://www.asus.com/product.aspx?P_ID=VMfiJJRYTHM4gXIi", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html"), + B("ASUS", "E35M1-I DELUXE", 1, "http://www.asus.com/product.aspx?P_ID=9BmKhMwWCwqyl1lz", NULL), B("ASUS", "K8V", 1, "http://www.asus.com/product.aspx?P_ID=fG2KZOWF7v6MRFRm", NULL), B("ASUS", "K8V SE Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=65HeDI8XM1u6Uy6o", NULL), B("ASUS", "K8V-X SE", 1, "http://www.asus.com/product.aspx?P_ID=lzDXlbBVHkdckHVr", NULL), @@ -443,7 +444,8 @@ B("ASUS", "M2NPV-VM", 1, "http://www.asus.com/product.aspx?P_ID=HGTVnGv5nGahCYgK", NULL), B("ASUS", "M2V", 1, "http://www.asus.com/product.aspx?P_ID=OqYlEDFfF6ZqZGvp", NULL), B("ASUS", "M2V-MX", 1, "http://www.asus.com/product.aspx?P_ID=7grf8Ci4yxnqzt3z", NULL), - B("ASUS", "M3A76-CM", 1, NULL, NULL), + B("ASUS", "M3A", 1, "http://www.asus.com/product.aspx?P_ID=P48rppKk4jrc9pNd", NULL), + B("ASUS", "M3A76-CM", 1, "http://www.asus.com/product.aspx?P_ID=aU8effdifLvraVze", NULL), B("ASUS", "M3A78-EM", 1, "http://www.asus.com/product.aspx?P_ID=KjpYqzmAd9vsTM2D", NULL), B("ASUS", "M4A78-EM", 1, "http://www.asus.com/product.aspx?P_ID=0KyowHKUFAQqH2DO", NULL), B("ASUS", "M4A785TD-M EVO", 1, "http://www.asus.com/product.aspx?P_ID=QHbvGVB1mXmmD8qQ", NULL), @@ -514,6 +516,7 @@ B("FIC", "VA-502", 0, "ftp://ftp.fic.com.tw/motherboard/manual/socket7/va-502/", "No public report found. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>. Seems the PCI subsystem IDs are identical with the Tekram P6Pro-A5. May work now."), B("Foxconn", "6150K8MD-8EKRSH", 1, "http://www.foxconnchannel.com/product/motherboards/detail_overview.aspx?id=…", NULL), B("Foxconn", "A6VMX", 1, "http://www.foxconnchannel.com/product/motherboards/detail_overview.aspx?id=…", NULL), + B("Freetech", "P6F91i", 1, "http://web.archive.org/web/20010417035034/http://www.freetech.com/prod/P6F9…", NULL), B("Fujitsu-Siemens", "ESPRIMO P5915", 1, "http://uk.ts.fujitsu.com/rl/servicesupport/techsupport/professionalpc/ESPRI…", "Mainboard model is D2312-A2."), B("GIGABYTE", "GA-2761GXDK", 1, "http://www.computerbase.de/news/hardware/mainboards/amd-systeme/2007/mai/gi…", NULL), B("GIGABYTE", "GA-6BXC", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1445", NULL), @@ -529,17 +532,20 @@ B("GIGABYTE", "GA-8IP775", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1830", NULL), B("GIGABYTE", "GA-8IRML", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1343", NULL), B("GIGABYTE", "GA-8PE667 Ultra 2", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1607", NULL), + B("GIGABYTE", "GA-965GM-S2 (rev. 2.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2617", NULL), B("GIGABYTE", "GA-965P-DS4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2288", NULL), B("GIGABYTE", "GA-EP35-DS3L", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2778", NULL), B("GIGABYTE", "GA-EX58-UD4P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2986", NULL), B("GIGABYTE", "GA-K8N-SLI", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1928", NULL), B("GIGABYTE", "GA-K8N51GMF", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1950", NULL), B("GIGABYTE", "GA-K8N51GMF-9", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1939", NULL), - B("GIGABYTE", "GA-K8NS Ultra-939", 0, "http://www.gigabyte.com/products/product-page.aspx?pid=1839", "Untested board enable."), + B("GIGABYTE", "GA-K8NS Pro-939", 0, "http://www.gigabyte.com/products/product-page.aspx?pid=1875", "Untested board enable."), B("GIGABYTE", "GA-M57SLI-S4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2287", NULL), B("GIGABYTE", "GA-M61P-S3", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2434", NULL), + B("GIGABYTE", "GA-M720-US3", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3006", NULL), B("GIGABYTE", "GA-MA69VM-S2", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2500", NULL), B("GIGABYTE", "GA-MA74GM-S2H (rev. 3.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3152", NULL), + B("GIGABYTE", "GA-MA770-UD3 (rev. 2.1)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3302", NULL), B("GIGABYTE", "GA-MA770T-UD3P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3096", NULL), B("GIGABYTE", "GA-MA780G-UD3H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3004", NULL), B("GIGABYTE", "GA-MA78G-DS3H (rev. 1.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2800", NULL), @@ -555,7 +561,8 @@ B("HP", "Puffer2-UL8E", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00300023", NULL), B("HP", "Vectra VL400", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c000…", NULL), B("HP", "Vectra VL420 SFF", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c000…", NULL), - B("HP", "xw9400", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?lang=en&cc=us&pro…", "Boot block is write protected unless the solder points next to F2 are shorted." ), + B("HP", "xw4400 (0A68h)", 0, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c007…", "ICH7 with SPI lock down, BIOS lock, flash block detection (SST25VF080B); see http://paste.flashrom.org/view.php?id=686"), + B("HP", "xw9400", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?lang=en&cc=us&pro…", "Boot block is write protected unless the solder points next to F2 are shorted."), B("IBASE", "MB899", 1, "http://www.ibase-i.com.tw/2009/mb899.html", NULL), B("IBM", "x3455", 1, "http://www-03.ibm.com/systems/x/hardware/rack/x3455/index.html", NULL), B("IEI", "PICOe-9452", 1, "http://www.ieiworld.com/product_groups/industrial/content.aspx?keyword=WSB&…", NULL), @@ -578,6 +585,7 @@ B("MSI", "MS-6330 (K7T Turbo)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=327", NULL), B("MSI", "MS-6391 (845 Pro4)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=293", NULL), B("MSI", "MS-6561 (745 Ultra)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=274", NULL), + B("MSI", "MS-6566 (845 Ultra-C)",1, "http://www.msi.com/product/mb/845-Ultra-C.html", NULL), B("MSI", "MS-6570 (K7N2)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=519", NULL), B("MSI", "MS-6577 (Xenon)", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?product=90390&lc=en&cc=us&dlc=e…", "This is an OEM board from HP, the HP name is Xenon."), B("MSI", "MS-6590 (KT4 Ultra)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=502", NULL), @@ -607,8 +615,10 @@ B("MSI", "MS-7599 (870-C45)", 1, "http://www.msi.com/product/mb/870-C45.html", NULL), B("MSI", "MS-7640 (890FXA-GD70)",1, "http://www.msi.com/product/mb/890FXA-GD70.html", "Reported by \"Linux User #330250\" http://flashrom.org/pipermail/flashrom/2011-March/006072.html"), B("MSI", "MS-7642 (890GXM-G65)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=2012", NULL), + B("MSI", "MS-7698 (E350IA-E45)", 1, "http://www.msi.com/product/mb/E350IA-E45.html", NULL), B("NEC", "PowerMate 2000", 1, "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/", NULL), B("Nokia", "IP530", 1, NULL, NULL), + B("PCCHIPS ", "M863G (V5.1A)", 1, "http://www.pcchips.com.tw/PCCWebSite/Products/ProductsDetail.aspx?CategoryI…", NULL), B("PC Engines", "Alix.1c", 1, "http://pcengines.ch/alix1c.htm", NULL), B("PC Engines", "Alix.2c2", 1, "http://pcengines.ch/alix2c2.htm", NULL), B("PC Engines", "Alix.2c3", 1, "http://pcengines.ch/alix2c3.htm", NULL), @@ -639,7 +649,7 @@ B("Supermicro", "X8DTH-6F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTH-6F.cfm", NULL), B("Supermicro", "X8DTT-F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTT-F.cfm", NULL), B("Supermicro", "X8DTU-F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTU-F.cfm", NULL), - B("Supermicro", "X8SIE", 0, "http://www.supermicro.com/products/motherboard/Xeon3000/3400/X8SIE.cfm?IPMI…", "Does not work with 0.9.2; see http://www.flashrom.org/pipermail/flashrom/2011-May/006554.html May work now, but please consult us before trying."), + B("Supermicro", "X8SIE(-F)", 0, "http://www.supermicro.com/products/motherboard/Xeon3000/3400/X8SIE.cfm?IPMI…", "Requires unlocking the ME although the registers are set up correctly by the descriptor/BIOS already (tested with swseq and hwseq)."), B("Supermicro", "X8STi", 1, "http://www.supermicro.com/products/motherboard/Xeon3000/X58/X8STi.cfm", NULL), B("T-Online", "S-100", 1, "http://wiki.freifunk-hannover.de/T-Online_S_100", NULL), B("Tekram", "P6Pro-A5", 1, "http://www.motherboard.cz/mb/tekram/P6Pro-A5.htm", NULL), Modified: trunk/serprog-protocol.txt ============================================================================== --- trunk/serprog-protocol.txt Thu Jul 7 08:59:18 2011 (r1366) +++ trunk/serprog-protocol.txt Thu Jul 7 21:56:58 2011 (r1367) @@ -88,7 +88,7 @@ #define S_CMD_Q_BUSTYPE 0x05 /* Query supported bustypes */ #define S_CMD_Q_CHIPSIZE 0x06 /* Query supported chipsize (2^n format) */ #define S_CMD_Q_OPBUF 0x07 /* Query operation buffer size */ -#define S_CMD_Q_WRNMAXLEN 0x08 /* Query Write to opbuf: Write-N maximum lenght */ +#define S_CMD_Q_WRNMAXLEN 0x08 /* Query Write to opbuf: Write-N maximum length */ #define S_CMD_R_BYTE 0x09 /* Read a single byte */ #define S_CMD_R_NBYTES 0x0A /* Read n bytes */ #define S_CMD_O_INIT 0x0B /* Initialize operation buffer */ Modified: trunk/serprog.c ============================================================================== --- trunk/serprog.c Thu Jul 7 08:59:18 2011 (r1366) +++ trunk/serprog.c Thu Jul 7 21:56:58 2011 (r1367) @@ -56,7 +56,7 @@ #define S_CMD_Q_BUSTYPE 0x05 /* Query supported bustypes */ #define S_CMD_Q_CHIPSIZE 0x06 /* Query supported chipsize (2^n format) */ #define S_CMD_Q_OPBUF 0x07 /* Query operation buffer size */ -#define S_CMD_Q_WRNMAXLEN 0x08 /* Query opbuf-write-N maximum lenght */ +#define S_CMD_Q_WRNMAXLEN 0x08 /* Query opbuf-write-N maximum length */ #define S_CMD_R_BYTE 0x09 /* Read a single byte */ #define S_CMD_R_NBYTES 0x0A /* Read n bytes */ #define S_CMD_O_INIT 0x0B /* Initialize operation buffer */ @@ -168,10 +168,10 @@ usleep(1000 * 1000); sp_flush_incoming(); - /* Then try upto 8 times to send syncnop and get the correct special * - * return of NAK+ACK. Timing note: upto 10 characters, 10*50ms = * - * upto 500ms per try, 8*0.5s = 4s; +1s (above) = upto 5s sync * - * attempt, ~1s if immediate success. */ + /* Then try up to 8 times to send syncnop and get the correct special * + * return of NAK+ACK. Timing note: up to 10 characters, 10*50ms = * + * up to 500ms per try, 8*0.5s = 4s; +1s (above) = up to 5s sync * + * attempt, ~1s if immediate success. */ for (i = 0; i < 8; i++) { int n; unsigned char c = S_CMD_SYNCNOP; @@ -180,7 +180,7 @@ msg_pdbg("."); fflush(stdout); for (n = 0; n < 10; n++) { - c = sp_sync_read_timeout(5); /* wait upto 50ms */ + c = sp_sync_read_timeout(5); /* wait up to 50ms */ if (c != S_NAK) continue; c = sp_sync_read_timeout(2); Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Thu Jul 7 08:59:18 2011 (r1366) +++ trunk/spi25.c Thu Jul 7 21:56:58 2011 (r1367) @@ -62,7 +62,7 @@ } if (ret) return ret; - msg_cspew("REMS returned %02x %02x. ", readarr[0], readarr[1]); + msg_cspew("REMS returned 0x%02x 0x%02x. ", readarr[0], readarr[1]); return 0; }

1 0

selective probing?
by Bernd Blaauw 07 Jul '11

07 Jul '11

Whenever I read the verbose logs I see *all* chips being probed, which is pretty fast already. Is there any point to "optimise"(?) this amount to "per size" ? Possibly followed by per-method? For example if I'd want to write a 8Mbit BIOS file, only scan for 1024KB eeproms (determine (uncompressed) BIOS file's filesize). Reading/erasing is more difficult ofcourse, or not worthwile, requiring you be able to enter a size parameter. So from: * alphabetical name for EEPROM * various sizes * various scan methods To: * filesize * scan method 1 * results in some EEPROMS * scan method 2 * results in other EEPROMS -- etc (this assumes 1 EEPROM only found through 1 method, or 1st method used, whatever). Probably not worthwile, though it would reduce the verbose log by 75% Maybe also mirror the user's entered commandline in the log (minus the prompt/directory) to allow more eyes to check user's input

3 2

Re: [flashrom] [PATCH] Autodetect target processor architecture
by Carl-Daniel Hailfinger 07 Jul '11

07 Jul '11

Am 07.07.2011 02:05 schrieb David Hendricks: > The latest revision fixed the issue seen on IRC where the ARCH string might > get duplicated. > > I tested it on both x86 and ARM (using the tegra2 patches) and it worked, > so: > Acked-by: David Hendricks <dhendrix(a)google.com> > Thanks for the review and the tests. Committed in r1366. Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

[commit] r1366 - trunk
by repository service 07 Jul '11

07 Jul '11

Author: hailfinger Date: Thu Jul 7 08:59:18 2011 New Revision: 1366 URL: http://flashrom.org/trac/flashrom/changeset/1366 Log: Autodetect target processor architecture. Enable architecture dependent compilation of individual sub-drivers for the internal programmer. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: David Hendricks <dhendrix(a)google.com> Added: trunk/arch.h Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Thu Jul 7 06:10:57 2011 (r1365) +++ trunk/Makefile Thu Jul 7 08:59:18 2011 (r1366) @@ -37,7 +37,10 @@ CFLAGS += -Werror endif -# FIXME We have to differentiate between host and target arch. +# Determine the destination processor architecture +override ARCH = $(strip $(shell LC_ALL=C $(CC) -E arch.h|grep -v '^\#')) + +# FIXME We have to differentiate between host and target OS architecture. OS_ARCH ?= $(shell uname) ifneq ($(OS_ARCH), SunOS) STRIP_ARGS = -s @@ -304,8 +307,10 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o -# FIXME: The PROGRAMMER_OBJS below should only be included on x86. +ifeq ($(ARCH),"x86") PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +else +endif NEED_PCI := yes endif @@ -500,6 +505,11 @@ echo "found." || ( echo "not found."; \ rm -f .test.c .test$(EXEC_SUFFIX); exit 1) @rm -f .test.c .test$(EXEC_SUFFIX) + @printf "ARCH is " + @# FreeBSD wc will output extraneous whitespace. + @echo $(ARCH)|wc -l|grep -q '^[[:blank:]]*1[[:blank:]]*$$' || \ + ( echo "unknown. Aborting."; exit 1) + @printf "%s\n" '$(ARCH)' ifeq ($(CHECK_LIBPCI), yes) pciutils: compiler Added: trunk/arch.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/arch.h Thu Jul 7 08:59:18 2011 (r1366) @@ -0,0 +1,31 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2011 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Header file for CPU architecture checking. + */ + +#if defined (__i386__) || defined (__x86_64__) +#define __FLASHROM_ARCH__ "x86" +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) +#define __FLASHROM_ARCH__ "mips" +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) +#define __FLASHROM_ARCH__ "ppc" +#endif +__FLASHROM_ARCH__

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Success erasing and writing a SST39SF010A with a Silicon Image 3124 card
by Tim Small 06 Jul '11

06 Jul '11

Erase: flashrom v0.9.3-r1364 on Linux 2.6.39-2-amd64 (x86_64), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 2496M loops per second, 10 myus = 10 us, 100 myus = 110 us, 1000 myus = 1011 us, 10000 myus = 10015 us, 4 myus = 6 us, OK. Initializing satasii programmer Found "Silicon Image SiI 3124 PCI-X SATA Ctrl" (1095:3124, BDF 05:00.0). Requested BAR is MEM, 64bit, not prefetchable Mapping SATA SIL registers at 0xf7fff000, unaligned size 0x100. Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BB, 1024 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BT, 1024 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002B, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C512, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT29C010A, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT29C020, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT29C040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT49BV512, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT49F020, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT49F002(N), 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT49F002(N)T, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Bright BM29F040, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for EMST F49B002UA, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Eon EN29F010, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 kB: probe_m29f400bt: id1 0x55, id2 0x78 Probing for Fujitsu MBM29F400TC, 512 kB: probe_m29f400bt: id1 0x55, id2 0x78 Probing for Hyundai HY29F002T, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Hyundai HY29F002B, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Hyundai HY29F040A, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Intel 28F001BN/BX-T, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: probe_82802ab: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 kB: probe_82802ab: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: probe_82802ab: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: probe_82802ab: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: probe_82802ab: id1 0x55, id2 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: probe_82802ab: id1 0x55, id2 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001B, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002B, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002T, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29C51000T, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29C51400B, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29C51400T, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29LC51000, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29LC51001, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29LC51002, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for PMC Pm29F002T, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST28SF040A, 512 kB: probe_82802ab: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST29LE010, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST29EE020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST29LE020, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39SF512, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39SF010A, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Found chip "SST SST39SF010A" (128 kB, Parallel) on satasii. Probing for SST SST39SF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39SF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39VF512, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39VF010, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39VF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39VF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39VF080, 1024 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for ST M29F002B, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 kB: probe_m29f400bt: id1 0x55, id2 0x78 Probing for ST M29F400BT, 512 kB: probe_m29f400bt: id1 0x55, id2 0x78 Probing for ST M29W010B, 128 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for TI TMS29F002RB, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 kB: probe_jedec_common: id1 0x55, id2 0xaa, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Winbond W29C040/P, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39L040, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Winbond W49F002U/N, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Winbond W49F020, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 === This flash part has status UNTESTED for operations: ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Erasing and writing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x000fff:E, 0x001000-0x001fff:E, 0x002000-0x002fff:E, 0x003000-0x003fff:E, 0x004000-0x004fff:E, 0x005000-0x005fff:E, 0x006000-0x006fff:E, 0x007000-0x007fff:E, 0x008000-0x008fff:E, 0x009000-0x009fff:E, 0x00a000-0x00afff:E, 0x00b000-0x00bfff:E, 0x00c000-0x00cfff:E, 0x00d000-0x00dfff:E, 0x00e000-0x00efff:E, 0x00f000-0x00ffff:E, 0x010000-0x010fff:E, 0x011000-0x011fff:E, 0x012000-0x012fff:E, 0x013000-0x013fff:E, 0x014000-0x014fff:E, 0x015000-0x015fff:E, 0x016000-0x016fff:E, 0x017000-0x017fff:E, 0x018000-0x018fff:E, 0x019000-0x019fff:E, 0x01a000-0x01afff:E, 0x01b000-0x01bfff:E, 0x01c000-0x01cfff:E, 0x01d000-0x01dfff:E, 0x01e000-0x01efff:E, 0x01f000-0x01ffff:E Done. Write: flashrom v0.9.3-r1364 on Linux 2.6.39-2-amd64 (x86_64), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 2496M loops per second, 10 myus = 10 us, 100 myus = 116 us, 1000 myus = 1012 us, 10000 myus = 10018 us, 4 myus = 5 us, OK. Initializing satasii programmer Found "Silicon Image SiI 3124 PCI-X SATA Ctrl" (1095:3124, BDF 05:00.0). Requested BAR is MEM, 64bit, not prefetchable Mapping SATA SIL registers at 0xf7fff000, unaligned size 0x100. Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BB, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BT, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C512, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT29C010A, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT29C020, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT29C040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT49BV512, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT49F020, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT49F002(N), 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Atmel AT49F002(N)T, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Bright BM29F040, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for EMST F49B002UA, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Eon EN29F010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Fujitsu MBM29F400TC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Hyundai HY29F002T, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Hyundai HY29F002B, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Hyundai HY29F040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Intel 28F001BN/BX-T, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29C51000T, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29C51400B, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29C51400T, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29LC51000, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29LC51001, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for MoselVitelic V29LC51002, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for PMC Pm29F002T, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST28SF040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST29LE010, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST29EE020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST29LE020, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39SF512, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39SF010A, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Found chip "SST SST39SF010A" (128 kB, Parallel) on satasii. Probing for SST SST39SF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39SF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39VF512, 64 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39VF010, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39VF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39VF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SST SST39VF080, 1024 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for ST M29F002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29F400BT, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29W010B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for TI TMS29F002RB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Winbond W29C040/P, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39L040, 512 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Winbond W49F002U/N, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 Probing for Winbond W49F020, 256 kB: probe_jedec_common: id1 0xbf, id2 0xb5 === This flash part has status UNTESTED for operations: ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Reading old flash chip contents... done. Erasing and writing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x000fff:W, 0x001000-0x001fff:W, 0x002000-0x002fff:W, 0x003000-0x003fff:W, 0x004000-0x004fff:W, 0x005000-0x005fff:W, 0x006000-0x006fff:W, 0x007000-0x007fff:W, 0x008000-0x008fff:W, 0x009000-0x009fff:W, 0x00a000-0x00afff:W, 0x00b000-0x00bfff:W, 0x00c000-0x00cfff:W, 0x00d000-0x00dfff:W, 0x00e000-0x00efff:W, 0x00f000-0x00ffff:W, 0x010000-0x010fff:S, 0x011000-0x011fff:S, 0x012000-0x012fff:S, 0x013000-0x013fff:S, 0x014000-0x014fff:S, 0x015000-0x015fff:S, 0x016000-0x016fff:S, 0x017000-0x017fff:S, 0x018000-0x018fff:S, 0x019000-0x019fff:S, 0x01a000-0x01afff:S, 0x01b000-0x01bfff:S, 0x01c000-0x01cfff:S, 0x01d000-0x01dfff:S, 0x01e000-0x01efff:S, 0x01f000-0x01ffff:W Done. Verifying flash... VERIFIED.

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Re: [flashrom] [PATCH 4/8] ichspi.c: preserve reserved bits in address registers
by Stefan Tauner 06 Jul '11

06 Jul '11

On Wed, 6 Jul 2011 20:51:06 -0700 David Hendricks <dhendrix(a)google.com> wrote: > On Thu, Jun 30, 2011 at 5:52 PM, Stefan Tauner < > stefan.tauner(a)student.tuwien.ac.at> wrote: > > > On Fri, 01 Jul 2011 01:21:33 +0200 > > Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> wrote: > > > > > Am 28.06.2011 05:33 schrieb Stefan Tauner: > > > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > > > > > > > > > > Makes sense, but I worry that this might eventually break something. Do > > > we (want to) report the inital address setting during programmer init, > > > especially the reserved bits? > > > > we do the usual register dumping for SPIA on ICH7 and VIA, but > > we dont print the equivalent FADDR in the ICH9 branch. patch appended. > > > Acked-by: David Hendricks <dhendrix(a)google.com> > thanks, r1365 -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1365 - trunk
by repository service 06 Jul '11

06 Jul '11

Author: stefanct Date: Thu Jul 7 06:10:57 2011 New Revision: 1365 URL: http://flashrom.org/trac/flashrom/changeset/1365 Log: ichspi.c: print FADDR in ich_init_spi We print the address registers for ICH7 and VIA at init. We should do so for ICH9 too. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: David Hendricks <dhendrix(a)google.com> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Mon Jul 4 09:27:17 2011 (r1364) +++ trunk/ichspi.c Thu Jul 7 06:10:57 2011 (r1365) @@ -1288,6 +1288,8 @@ msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); prettyprint_ich9_reg_hsfc(tmp2); + tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR); + msg_pdbg("0x08: 0x%08x (FADDR)\n", tmp); tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp));

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Re: [flashrom] [PATCH 4/8] ichspi.c: preserve reserved bits in address registers
by Carl-Daniel Hailfinger 06 Jul '11

06 Jul '11

Am 28.06.2011 05:33 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Makes sense, but I worry that this might eventually break something. Do we (want to) report the inital address setting during programmer init, especially the reserved bits? Anyway, this is Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [Patch] NVIDIA Tegra2 SPI controller support
by Carl-Daniel Hailfinger 06 Jul '11

06 Jul '11

Am 28.06.2011 01:52 schrieb David Hendricks: > This patch set makes Flashrom a bit more ARM-friendly and adds raw Tegra2 > SPI controller support. It isolates a few PCI-isms, adds some low-level > hardware access stubs, adds Tegra2 processor detection, and adds Tegra2 raw > SPI controller code. > Nice! > I've attached some logfiles for read/erase/write operations. This particular > patch set was tested using a board based off NVIDIA's Tegra2 reference board > ("Seaboard"). Earlier revisions were tested on a Seaboard. > > All three attached patches are: > Signed-off-by: David Hendricks <dhendrix(a)google.com> > > Much of the original U-Boot --> Flashrom porting work was done by Stefan > Reinauer <reinauer(a)google.com>, and the FIFO code updated / fixed up by > Louis Lo <yjlou(a)google.com>. > > A few notes: > 1. A few programmers must be disabled due to reliance on PCI. You can hack > up your Makefile or compile with "CONFIG_RAYER_SPI=no CONFIG_NIC3COM=no > CONFIG_NICREALTEK=no CONFIG_SATAMV=no". > Actually, it is a requirement for PCI port I/O space (well, the non-memmapped space specified in the PCI standard, usually accesses with in[bwl]/out[bwl] functions). We ought to detect unavailability of that at compile time, preferably in the Makefile. > 2. Due to issues with libpci, you can't use the same binary on machines with > PCI and without PCI. So for example, you can't program a SPI ROM onboard a > PCI card that is connected to your ARM SoC. > Could you explain more? IIRC some people were using flashrom on ARM (independent patch) with PCI support. Not calling any PCI functions should be enough to avoid any and all interactions between libpci and the hardware. > 4. The tegra2_spi code was originally contributed by NVIDIA to the Chromium > OS U-Boot<http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=blob;…> > branch > and was later grafted into Flashrom so we could more easily perform SPI ROM > updates from userspace. Please excuse minor style inconsistencies as we are > trying to stay reasonably close to the code checked into the U-Boot tree ;-) > Ah, that explains some of the quirks I saw. Could you explain the Tegra2 hardware a bit more? The code suggests that it is more or less a slightly intelligent bitbanging controller with a "special" programing interface. At a first glance, the following issues stick out: 1-3-isolate_pci_isms.patch This essentially declares ARM a no-PCI zone. That's OK for testing, but not for merge. What exactly is the problem with PCI probing here? Does it return errors? Does it crash or terminate the application? Does it mess with the machine in ways which might cause breakage? 2-3-add_arm_isms.patch Have you checked with an architecture guru that sync_primitive() can really be empty, not only for that arch in general, but also for accesses to a mmapped region the way flashrom does it? 3-3-add_tegra2_spi_controller.patch Not your fault, but we really need a way to detect the target architecture in the Makefile. The issues of which SPI masters to include for internal exists on all architectures. Any ideas? I experimented with uname calls in the past, but that checks the host arch, not the target arch. Grepping the preprocessor output for the compiler might be an option. echo|gcc -dM -E -|grep "whatever\|arch\|defines" Or you try this pretty straightforward solution: Create a file arch.h with these contents: #if defined (__i386__) #define __FLASHROM_ARCH__ "x86" #elif defined (__x86_64__) #define __FLASHROM_ARCH__ "x86_64" #elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) #define __FLASHROM_ARCH__ "mips" #elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) #define __FLASHROM_ARCH__ "ppc" #endif __FLASHROM_ARCH__ Then run gcc -E arch.h|grep -v ^# The result on my machine will be "x86" Side note: Such an arch.h file (with some extensions) might save us from having to check every possible arch define everywhere we need to differentiate between architectures. I will comment on the Tegra2 SPI driver later, we should get the infrastructure questions addressed first. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH] Autodetect target processor architecture
by Carl-Daniel Hailfinger 06 Jul '11

06 Jul '11

Thanks for the reviews! New version. Autodetect target processor architecture. Enable architecture dependent compilation of individual sub-drivers for the internal programmer. With this patch, you no longer have to edit the Makefile to compile the internal driver on MIPS/ARM/... Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-target_arch/Makefile =================================================================== --- flashrom-target_arch/Makefile (Revision 1364) +++ flashrom-target_arch/Makefile (Arbeitskopie) @@ -37,7 +37,10 @@ CFLAGS += -Werror endif -# FIXME We have to differentiate between host and target arch. +# Determine the destination processor architecture +ARCH = $(strip $(shell LC_ALL=C $(CC) -E arch.h|grep -v '^\#')) + +# FIXME We have to differentiate between host and target OS architecture. OS_ARCH ?= $(shell uname) ifneq ($(OS_ARCH), SunOS) STRIP_ARGS = -s @@ -304,8 +307,10 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o -# FIXME: The PROGRAMMER_OBJS below should only be included on x86. +ifeq ($(ARCH),"x86") PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +else +endif NEED_PCI := yes endif @@ -500,6 +505,11 @@ echo "found." || ( echo "not found."; \ rm -f .test.c .test$(EXEC_SUFFIX); exit 1) @rm -f .test.c .test$(EXEC_SUFFIX) + @printf "ARCH is " + @# FreeBSD wc will output extraneous whitespace. + @echo $(ARCH)|wc -l|grep -q '^[[:blank:]]*1[[:blank:]]*$$' || \ + ( echo "unknown. Aborting."; exit 1) + @printf "%s\n" '$(ARCH)' ifeq ($(CHECK_LIBPCI), yes) pciutils: compiler Index: flashrom-target_arch/arch.h =================================================================== --- flashrom-target_arch/arch.h (Revision 0) +++ flashrom-target_arch/arch.h (Revision 0) @@ -0,0 +1,31 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2011 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Header file for CPU architecture checking. + */ + +#if defined (__i386__) || defined (__x86_64__) +#define __FLASHROM_ARCH__ "x86" +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) +#define __FLASHROM_ARCH__ "mips" +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) +#define __FLASHROM_ARCH__ "ppc" +#endif +__FLASHROM_ARCH__ -- http://www.hailfinger.org/

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Re: [flashrom] PCCHIPS M863G V5.1A + Winbond W49V002AP - Write OK
by Stefan Tauner 06 Jul '11

06 Jul '11

On Sun, 3 Jul 2011 11:11:16 -0300 Marcos Felipe Rasia de Mello <marcosfrm(a)gmail.com> wrote: > 2011/7/3 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > > > > hello and thanks for your report! > > i have added the board to our supported hw list and marked the W49V002A > > as fully tested and will commit that later. > > > > You are welcome. > When should I send "lspci -nnvvxxx" output? Is only "flashrom -V" > output sufficient? > well, i would say for all reports that do not involve board enables (i.e. if there is no ""Disabling flash write protection for board" in the output), then flashrom -V is enough. but having the associated lspci data does not hurt (us) at all... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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AT26F004 support [PATCH]
by Tim Small 06 Jul '11

06 Jul '11

Hi, Back from holiday now - was wondering if there were any thoughts regarding the AT26F004 support patch? http://marc.info/?l=flashrom&m=130861563117389&w=2 <http://marc.info/?l=flashrom&m=130861563117389&w=2> Anything else needed to get it merged? Cheers! Tim.

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Re: [flashrom] SPI Controller ICH9 Flash driver
by Stefan Tauner 06 Jul '11

06 Jul '11

On Tue, 5 Jul 2011 23:27:31 +0000 "Branham, Paul" <paul.branham(a)hp.com> wrote: > Hello, > > We are using your open source flashrom driver for Intel PCH Ibex Peak. (SPI_Controller_ICH9 in the source code with generation>8 => ie. SPIBAR = 0x3800). > > The flash ROM driver works well using CS0 by design. > > What we are looking for is information on how to use the other chip select -CS1- for some other SPI device. All Intel documentation we have found for this SPI Controller only specifies how to use the Flash capabilities of CS0, but no information whatsoever on how to use CS1 for any other SPI device. > > Would you have any source code or other information that may be of help? > hello paul, most of the public documentation from Intel does not help a lot as you already have found out... :) as far as i understand it, using multiple chips is only supported with hardware sequencing. you can read about that in detail here: http://blogs.coreboot.org/blog/2011/06/11/gsoc-2011-flashrom-part-1/ we are working on that and you can look at the following patches for preliminary support: http://patchwork.coreboot.org/patch/3242/ http://patchwork.coreboot.org/patch/3243/ http://patchwork.coreboot.org/patch/3244/ http://patchwork.coreboot.org/patch/3253/ they should be applied to the current source files, see http://flashrom.org/Downloads#Installation_from_source for details if your flash descriptors are correct and indicate two attached devices it should already work with the above patches unless the ME or the FREG registers prohibits flashrom to access some regions (which is likely on ibex peak platforms). in that case flashrom is not an option yet. i am working on that too, but it is not ready yet. in any case, sending us verbose logs of running flashrom with the patches above applied would be much appreciated. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 3/3] ichspi.c: add support for Intel Hardware Sequencing
by Stefan Tauner 05 Jul '11

05 Jul '11

"fuzzy" on irc has tested the 6.1 patch set. the attached patch fixes the address checking. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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SPI Controller ICH9 Flash driver
by Branham, Paul 05 Jul '11

05 Jul '11

Hello, We are using your open source flashrom driver for Intel PCH Ibex Peak. (SPI_Controller_ICH9 in the source code with generation>8 => ie. SPIBAR = 0x3800). The flash ROM driver works well using CS0 by design. What we are looking for is information on how to use the other chip select -CS1- for some other SPI device. All Intel documentation we have found for this SPI Controller only specifies how to use the Flash capabilities of CS0, but no information whatsoever on how to use CS1 for any other SPI device. Would you have any source code or other information that may be of help? Thanks, - Paul Paul Branham Software Engineer, EB ESSN HPN Security Hewlett-Packard Company 512-681-8511

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