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Re: [flashrom] [PATCH 1/3] Refine Flash Component descriptor handling.
by Stefan Tauner 20 Aug '14

20 Aug '14

On Thu, 14 Aug 2014 15:13:45 -0600 Marc Jones <marcj303(a)gmail.com> wrote: > Switched to read, erase, and write with -VV -o for logs. > > It looks like there is an erase block issue or ivy/pantherpoint. I > have attached two different logs for that, 7472 and cc2. The devices > are MX25L12805(D) and W25Q64.V as identified with flashrom dediprog. > > testflashrom_ivypanther_7472.log > testflashrom_ivypanther_cc2.log Thanks a lot for testing this so thoroughly. Hm yes, that's exactly the same problem as described before. Does Intel's FPT work on these boards? To me it looks as they are impossible to write in situ without an external programmer. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1845 - in trunk: . util/ich_descriptors_tool
by repository service 20 Aug '14

20 Aug '14

Author: stefanct Date: Wed Aug 20 17:39:38 2014 New Revision: 1845 URL: http://flashrom.org/trac/flashrom/changeset/1845 Log: Add support for Intel Wildcat Point PCH. The Wildcat Point PCH can be paired with Broadwell or Haswell. This patch was essentially backported from ChromiumOS commit 9bd2af8. Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/chipset_enable.c trunk/ich_descriptors.c trunk/ich_descriptors.h trunk/programmer.h trunk/util/ich_descriptors_tool/ich_descriptors_tool.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Wed Aug 20 17:39:32 2014 (r1844) +++ trunk/chipset_enable.c Wed Aug 20 17:39:38 2014 (r1845) @@ -594,7 +594,7 @@ static const char *const straps_names_tunnel_creek[] = { "SPI", "LPC" }; static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" }; static const char *const straps_names_pch567[] = { "LPC", "reserved", "PCI", "SPI" }; - static const char *const straps_names_pch8_baytrail[] = { "LPC", "reserved", "reserved", "SPI" }; + static const char *const straps_names_pch89_baytrail[] = { "LPC", "reserved", "reserved", "SPI" }; static const char *const straps_names_pch8_lp[] = { "SPI", "LPC" }; static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" }; @@ -623,8 +623,9 @@ straps_names = straps_names_pch567; break; case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_9_SERIES_WILDCAT_POINT: case CHIPSET_BAYTRAIL: - straps_names = straps_names_pch8_baytrail; + straps_names = straps_names_pch89_baytrail; break; case CHIPSET_8_SERIES_LYNX_POINT_LP: straps_names = straps_names_pch8_lp; @@ -776,6 +777,12 @@ return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc); } +/* Wildcat Point */ +static int enable_flash_pch9(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc); +} + /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately. * @@ -1759,6 +1766,14 @@ {0x8086, 0x8d5d, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, {0x8086, 0x8d5e, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, {0x8086, 0x8d5f, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x9cc1, NT, "Intel", "Haswell U Sample", enable_flash_pch9}, + {0x8086, 0x9cc2, NT, "Intel", "Broadwell U Sample", enable_flash_pch9}, + {0x8086, 0x9cc3, NT, "Intel", "Broadwell U Premium", enable_flash_pch9}, + {0x8086, 0x9cc5, NT, "Intel", "Broadwell U Base", enable_flash_pch9}, + {0x8086, 0x9cc6, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9}, + {0x8086, 0x9cc7, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9}, + {0x8086, 0x9cc9, NT, "Intel", "Broadwell Y Base", enable_flash_pch9}, + {0x8086, 0x9ccb, NT, "Intel", "Broadwell H", enable_flash_pch9}, #endif {0}, }; Modified: trunk/ich_descriptors.c ============================================================================== --- trunk/ich_descriptors.c Wed Aug 20 17:39:32 2014 (r1844) +++ trunk/ich_descriptors.c Wed Aug 20 17:39:38 2014 (r1845) @@ -141,7 +141,8 @@ case CHIPSET_8_SERIES_LYNX_POINT: case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: - case CHIPSET_8_SERIES_WELLSBURG: { + case CHIPSET_8_SERIES_WELLSBURG: + case CHIPSET_9_SERIES_WILDCAT_POINT: { uint8_t size_enc; if (idx == 0) { size_enc = desc->component.new.comp1_density; @@ -184,6 +185,7 @@ case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: + case CHIPSET_9_SERIES_WILDCAT_POINT: return freq_str[value]; case CHIPSET_ICH_UNKNOWN: default: @@ -825,6 +827,7 @@ case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: + case CHIPSET_9_SERIES_WILDCAT_POINT: if (idx == 0) { size_enc = desc->component.new.comp1_density; } else { Modified: trunk/ich_descriptors.h ============================================================================== --- trunk/ich_descriptors.h Wed Aug 20 17:39:32 2014 (r1844) +++ trunk/ich_descriptors.h Wed Aug 20 17:39:38 2014 (r1845) @@ -117,7 +117,7 @@ * Wildcat Point/9: 50 ?? (multi I/O) ? ?:?, ?:? */ struct { - uint32_t :17, + uint32_t :17, freq_read :3, fastread :1, freq_fastread :3, Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Wed Aug 20 17:39:32 2014 (r1844) +++ trunk/programmer.h Wed Aug 20 17:39:38 2014 (r1845) @@ -603,6 +603,7 @@ CHIPSET_BAYTRAIL, /* Actually all with Silvermont architecture: Bay Trail, Avoton/Rangeley */ CHIPSET_8_SERIES_LYNX_POINT_LP, CHIPSET_8_SERIES_WELLSBURG, + CHIPSET_9_SERIES_WILDCAT_POINT, }; /* ichspi.c */ Modified: trunk/util/ich_descriptors_tool/ich_descriptors_tool.c ============================================================================== --- trunk/util/ich_descriptors_tool/ich_descriptors_tool.c Wed Aug 20 17:39:32 2014 (r1844) +++ trunk/util/ich_descriptors_tool/ich_descriptors_tool.c Wed Aug 20 17:39:38 2014 (r1845) @@ -123,6 +123,7 @@ "\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" "\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" "\t- \"8\" or \"lynx\" for Intel's 8 series chipsets.\n" +"\t- \"9\" or \"wildcat\" for Intel's 9 series chipsets.\n" "If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n" "the GbE blob that is required to initialize the GbE are also dumped to files.\n", argv[0], argv[0]); @@ -205,6 +206,9 @@ cs = CHIPSET_8_SERIES_LYNX_POINT; else if ((strcmp(csn, "silvermont") == 0)) cs = CHIPSET_BAYTRAIL; + else if ((strcmp(csn, "9") == 0) || + (strcmp(csn, "wildcat") == 0)) + cs = CHIPSET_9_SERIES_WILDCAT_POINT; } ret = read_ich_descriptors_from_dump(buf, len, &desc);

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[commit] r1844 - in trunk: . util/ich_descriptors_tool
by repository service 20 Aug '14

20 Aug '14

Author: stefanct Date: Wed Aug 20 17:39:32 2014 New Revision: 1844 URL: http://flashrom.org/trac/flashrom/changeset/1844 Log: Add support for Intel Silvermont: Bay Trail, Rangeley and Avoton. The core of this patch to support Bay Trail originally came from the Chromiumos flashrom repo and was modified by Sage to support the Rangeley/Avoton parts as well. Because that was not complicated enough already Stefan Tauner refactored and refined everything. Bay Trail seems to be the first Atom SoC able to support hwseq. No SPI Programming Guide could be obtained so it is handled similarly to Lynx Point which seems to be its nearest relative. Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Signed-off-by: Martin Roth <gaumless(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Tested-by: Marc Jones <marcj303(a)gmail.com> Tested-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Tested-by: Thomas Reardon <thomas_reardon(a)hotmail.com> Tested-by: Wen Wang <wen.wang(a)adiengineering.com> Acked-By: Marc Jones <marcj303(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/chipset_enable.c trunk/ich_descriptors.c trunk/ichspi.c trunk/programmer.h trunk/util/ich_descriptors_tool/ich_descriptors_tool.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Wed Aug 20 17:39:19 2014 (r1843) +++ trunk/chipset_enable.c Wed Aug 20 17:39:32 2014 (r1844) @@ -260,9 +260,13 @@ return 0; } -/* Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, in Poulsbo, Tunnel Creek and other Atom +/* Handle BIOS_CNTL (aka. BCR). Disable locks and enable writes. The register can either be in PCI config space + * at the offset given by 'bios_cntl' or at the memory-mapped address 'addr'. + * + * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, in Poulsbo, Tunnel Creek and other Atom * chipsets/SoCs it is even 32b, but just treating it as 8 bit wide seems to work fine in practice. */ -static int enable_flash_ich_bios_cntl(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) +static int enable_flash_ich_bios_cntl_common(enum ich_chipset ich_generation, void *addr, + struct pci_dev *dev, uint8_t bios_cntl) { uint8_t old, new, wanted; @@ -273,8 +277,8 @@ case CHIPSET_ICH: case CHIPSET_ICH2345: break; - /* Atom chipsets are special: The second byte of BIOS_CNTL (D9h) contains a prefetch bit similar to what - * other SPI-capable chipsets have at DCh. + /* Some Atom chipsets are special: The second byte of BIOS_CNTL (D9h) contains a prefetch bit similar to + * what other SPI-capable chipsets have at DCh. Others like Bay Trail use a memmapped register. * The Tunnel Creek datasheet contains a lot of details about the SPI controller, among other things it * mentions that the prefetching and caching does only happen for direct memory reads. * Therefore - at least for Tunnel Creek - it should not matter to flashrom because we use the @@ -285,9 +289,13 @@ old = pci_read_byte(dev, bios_cntl + 1); msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis"); break; + case CHIPSET_BAYTRAIL: case CHIPSET_ICH7: default: /* Future version might behave the same */ - old = (pci_read_byte(dev, bios_cntl) >> 2) & 0x3; + if (ich_generation == CHIPSET_BAYTRAIL) + old = (mmio_readl(addr) >> 2) & 0x3; + else + old = (pci_read_byte(dev, bios_cntl) >> 2) & 0x3; msg_pdbg("SPI Read Configuration: "); if (old == 3) msg_pdbg("invalid prefetching/caching settings, "); @@ -297,7 +305,11 @@ (old & 0x1) ? "dis" : "en"); } - wanted = old = pci_read_byte(dev, bios_cntl); + if (ich_generation == CHIPSET_BAYTRAIL) + wanted = old = mmio_readl(addr); + else + wanted = old = pci_read_byte(dev, bios_cntl); + /* * Quote from the 6 Series datasheet (Document Number: 324645-004): * "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP) @@ -327,8 +339,13 @@ /* Only write the register if it's necessary */ if (wanted != old) { - rpci_write_byte(dev, bios_cntl, wanted); - new = pci_read_byte(dev, bios_cntl); + if (ich_generation == CHIPSET_BAYTRAIL) { + rmmio_writel(wanted, addr); + new = mmio_readl(addr); + } else { + rpci_write_byte(dev, bios_cntl, wanted); + new = pci_read_byte(dev, bios_cntl); + } } else new = old; @@ -349,10 +366,22 @@ return 0; } +static int enable_flash_ich_bios_cntl_config_space(struct pci_dev *dev, enum ich_chipset ich_generation, + uint8_t bios_cntl) +{ + return enable_flash_ich_bios_cntl_common(ich_generation, NULL, dev, bios_cntl); +} + +static int enable_flash_ich_bios_cntl_memmapped(enum ich_chipset ich_generation, void *addr) +{ + return enable_flash_ich_bios_cntl_common(ich_generation, addr, NULL, 0); +} + static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich_generation) { uint8_t fwh_sel1 = 0, fwh_sel2 = 0, fwh_dec_en_lo = 0, fwh_dec_en_hi = 0; /* silence compilers */ bool implemented = 0; + void *ilb = NULL; /* Only for Baytrail */ switch (ich_generation) { case CHIPSET_ICH: /* FIXME: Unlike later chipsets, ICH and ICH-0 do only support mapping of the top-most 4MB @@ -373,6 +402,19 @@ case CHIPSET_CENTERTON: /* FIXME: Similar to above FWH_DEC_EN (D4h) and FWH_SEL (D0h). */ break; + case CHIPSET_BAYTRAIL: { + uint32_t ilb_base = pci_read_long(dev, 0x50) & 0xfffffe00; /* bits 31:9 */ + if (ilb_base == 0) { + msg_perr("Error: Invalid ILB_BASE_ADDRESS\n"); + return ERROR_FATAL; + } + ilb = rphysmap("BYT IBASE", ilb_base, 512); + fwh_sel1 = 0x18; + fwh_dec_en_lo = 0xd8; + fwh_dec_en_hi = 0xd9; + implemented = 1; + break; + } case CHIPSET_ICH6: case CHIPSET_ICH7: default: /* Future version might behave the same */ @@ -397,17 +439,27 @@ msg_perr("Error: fwh_idsel= specified, but value could not be converted.\n"); goto idsel_garbage_out; } - if (fwh_idsel & 0xffff000000000000ULL) { + uint64_t fwh_mask = 0xffffffff; + if (fwh_sel2 > 0) + fwh_mask |= (0xffffULL << 32); + if (fwh_idsel & ~fwh_mask) { msg_perr("Error: fwh_idsel= specified, but value had unused bits set.\n"); goto idsel_garbage_out; } - uint64_t fwh_idsel_old = pci_read_long(dev, fwh_sel1); - fwh_idsel_old <<= 16; - fwh_idsel_old |= pci_read_word(dev, fwh_sel2); + uint64_t fwh_idsel_old; + if (ich_generation == CHIPSET_BAYTRAIL) { + fwh_idsel_old = mmio_readl(ilb + fwh_sel1); + rmmio_writel(fwh_idsel, ilb + fwh_sel1); + } else { + fwh_idsel_old = pci_read_long(dev, fwh_sel1) << 16; + rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff); + if (fwh_sel2 > 0) { + fwh_idsel_old |= pci_read_word(dev, fwh_sel2); + rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff); + } + } msg_pdbg("Setting IDSEL from 0x%012" PRIx64 " to 0x%012" PRIx64 " for top 16 MB.\n", fwh_idsel_old, fwh_idsel); - rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff); - rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff); /* FIXME: Decode settings are not changed. */ } else if (idsel) { msg_perr("Error: fwh_idsel= specified, but no value given.\n"); @@ -429,7 +481,12 @@ */ int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0; bool contiguous = 1; - uint32_t fwh_conf = pci_read_long(dev, fwh_sel1); + uint32_t fwh_conf; + if (ich_generation == CHIPSET_BAYTRAIL) + fwh_conf = mmio_readl(ilb + fwh_sel1); + else + fwh_conf = pci_read_long(dev, fwh_sel1); + int i; /* FWH_SEL1 */ for (i = 7; i >= 0; i--) { @@ -444,18 +501,20 @@ contiguous = 0; } } - /* FWH_SEL2 */ - fwh_conf = pci_read_word(dev, fwh_sel2); - for (i = 3; i >= 0; i--) { - int tmp = (fwh_conf >> (i * 4)) & 0xf; - msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n", - (0xff4 + i) * 0x100000, - (0xff0 + i) * 0x100000, - tmp); - if ((tmp == 0) && contiguous) { - max_decode_fwh_idsel = (8 - i) * 0x100000; - } else { - contiguous = 0; + if (fwh_sel2 > 0) { + /* FWH_SEL2 */ + fwh_conf = pci_read_word(dev, fwh_sel2); + for (i = 3; i >= 0; i--) { + int tmp = (fwh_conf >> (i * 4)) & 0xf; + msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n", + (0xff4 + i) * 0x100000, + (0xff0 + i) * 0x100000, + tmp); + if ((tmp == 0) && contiguous) { + max_decode_fwh_idsel = (8 - i) * 0x100000; + } else { + contiguous = 0; + } } } contiguous = 1; @@ -502,7 +561,7 @@ return err; internal_buses_supported = BUS_FWH; - return enable_flash_ich_bios_cntl(dev, ich_generation, bios_cntl); + return enable_flash_ich_bios_cntl_config_space(dev, ich_generation, bios_cntl); } static int enable_flash_ich0(struct pci_dev *dev, const char *name) @@ -525,14 +584,17 @@ return enable_flash_ich_fwh(dev, CHIPSET_POULSBO, 0xd8); } -static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) +static void enable_flash_ich_handle_gcs(struct pci_dev *dev, enum ich_chipset ich_generation, uint32_t gcs, bool top_swap) { + msg_pdbg("GCS = 0x%x: ", gcs); + msg_pdbg("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); + static const char *const straps_names_EP80579[] = { "SPI", "reserved", "reserved", "LPC" }; static const char *const straps_names_ich7_nm10[] = { "reserved", "SPI", "PCI", "LPC" }; static const char *const straps_names_tunnel_creek[] = { "SPI", "LPC" }; static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" }; static const char *const straps_names_pch567[] = { "LPC", "reserved", "PCI", "SPI" }; - static const char *const straps_names_pch8[] = { "LPC", "reserved", "reserved", "SPI" }; + static const char *const straps_names_pch8_baytrail[] = { "LPC", "reserved", "reserved", "SPI" }; static const char *const straps_names_pch8_lp[] = { "SPI", "LPC" }; static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" }; @@ -561,7 +623,8 @@ straps_names = straps_names_pch567; break; case CHIPSET_8_SERIES_LYNX_POINT: - straps_names = straps_names_pch8; + case CHIPSET_BAYTRAIL: + straps_names = straps_names_pch8_baytrail; break; case CHIPSET_8_SERIES_LYNX_POINT_LP: straps_names = straps_names_pch8_lp; @@ -576,40 +639,40 @@ break; } - /* Get physical address of Root Complex Register Block */ - uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000; - msg_pdbg("Root Complex Register Block address = 0x%x\n", rcra); - - /* Map RCBA to virtual memory */ - void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000); - if (rcrb == ERROR_PTR) - return ERROR_FATAL; - - uint32_t gcs = mmio_readl(rcrb + 0x3410); - msg_pdbg("GCS = 0x%x: ", gcs); - msg_pdbg("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); - uint8_t bbs; switch (ich_generation) { case CHIPSET_TUNNEL_CREEK: bbs = (gcs >> 1) & 0x1; break; case CHIPSET_8_SERIES_LYNX_POINT_LP: - case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet - /* Lynx Point LP uses a single bit for GCS */ + /* Lynx Point LP uses a single bit for BBS */ bbs = (gcs >> 10) & 0x1; break; default: - /* Older chipsets use two bits for GCS */ + /* Other chipsets use two bits for BBS */ bbs = (gcs >> 10) & 0x3; break; } msg_pdbg("Boot BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); - if (ich_generation != CHIPSET_TUNNEL_CREEK && ich_generation != CHIPSET_CENTERTON) { - uint8_t buc = mmio_readb(rcrb + 0x3414); - msg_pdbg("Top Swap: %s\n", (buc & 1) ? "enabled (A16(+) inverted)" : "not enabled"); - } + /* Centerton has its TS bit in [GPE0BLK] + 0x30 while the exact location for Tunnel Creek is unknown. */ + if (ich_generation != CHIPSET_TUNNEL_CREEK && ich_generation != CHIPSET_CENTERTON) + msg_pdbg("Top Swap: %s\n", (top_swap) ? "enabled (A16(+) inverted)" : "not enabled"); +} + +static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) +{ + + /* Get physical address of Root Complex Register Block */ + uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000; + msg_pdbg("Root Complex Register Block address = 0x%x\n", rcra); + + /* Map RCBA to virtual memory */ + void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000); + if (rcrb == ERROR_PTR) + return ERROR_FATAL; + + enable_flash_ich_handle_gcs(dev, ich_generation, mmio_readl(rcrb + 0x3410), mmio_readb(rcrb + 0x3414)); /* Handle FWH-related parameters and initialization */ int ret_fwh = enable_flash_ich_fwh(dev, ich_generation, bios_cntl); @@ -619,6 +682,7 @@ /* SPIBAR is at RCRB+0x3020 for ICH[78], Tunnel Creek and Centerton, and RCRB+0x3800 for ICH9. */ uint16_t spibar_offset; switch (ich_generation) { + case CHIPSET_BAYTRAIL: case CHIPSET_ICH_UNKNOWN: return ERROR_FATAL; case CHIPSET_ICH7: @@ -712,6 +776,57 @@ return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc); } +/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. + * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately. + * + * Differences include: + * - RCBA at LPC config 0xF0 too but mapped range is only 4 B long instead of 16 kB. + * - GCS at [RCRB] + 0 (instead of [RCRB] + 0x3410). + * - TS (Top Swap) in GCS (instead of [RCRB] + 0x3414). + * - SPIBAR (coined SBASE) at LPC config 0x54 (instead of [RCRB] + 0x3800). + * - BIOS_CNTL (coined BCR) at [SPIBAR] + 0xFC (instead of LPC config 0xDC). + */ +static int enable_flash_silvermont(struct pci_dev *dev, const char *name) +{ + enum ich_chipset ich_generation = CHIPSET_BAYTRAIL; + + /* Get physical address of Root Complex Register Block */ + uint32_t rcba = pci_read_long(dev, 0xf0) & 0xfffffc00; + msg_pdbg("Root Complex Register Block address = 0x%x\n", rcba); + + /* Handle GCS (in RCRB) */ + void *rcrb = physmap("BYT RCRB", rcba, 4); + uint32_t gcs = mmio_readl(rcrb + 0); + enable_flash_ich_handle_gcs(dev, ich_generation, gcs, gcs & 0x2); + physunmap(rcrb, 4); + + /* Handle fwh_idsel parameter */ + int ret_fwh = enable_flash_ich_fwh_decode(dev, ich_generation); + if (ret_fwh == ERROR_FATAL) + return ret_fwh; + + internal_buses_supported = BUS_FWH; + + /* Get physical address of SPI Base Address and map it */ + uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00; + msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase); + void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */ + + /* Enable Flash Writes. + * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C). + */ + enable_flash_ich_bios_cntl_memmapped(ich_generation, spibar + 0xFC); + + int ret_spi = ich_init_spi(dev, spibar, ich_generation); + if (ret_spi == ERROR_FATAL) + return ret_spi; + + if (ret_fwh || ret_spi) + return ERROR_NONFATAL; + + return 0; +} + static int via_no_byte_merge(struct pci_dev *dev, const char *name) { uint8_t val; @@ -1471,6 +1586,10 @@ {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, {0x17f3, 0x6030, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610}, {0x8086, 0x0c60, NT, "Intel", "S12x0", enable_flash_s12x0}, + {0x8086, 0x0f1c, NT, "Intel", "Bay Trail", enable_flash_silvermont}, + {0x8086, 0x0f1d, NT, "Intel", "Bay Trail", enable_flash_silvermont}, + {0x8086, 0x0f1e, NT, "Intel", "Bay Trail", enable_flash_silvermont}, + {0x8086, 0x0f1f, NT, "Intel", "Bay Trail", enable_flash_silvermont}, {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, {0x8086, 0x1c44, DEP, "Intel", "Z68", enable_flash_pch6}, @@ -1505,7 +1624,11 @@ {0x8086, 0x1e5d, NT, "Intel", "HM75", enable_flash_pch7}, {0x8086, 0x1e5e, NT, "Intel", "HM70", enable_flash_pch7}, {0x8086, 0x1e5f, DEP, "Intel", "NM70", enable_flash_pch7}, - {0x8086, 0x2310, NT, "Intel", "DH89xxCC", enable_flash_pch7}, + {0x8086, 0x1f38, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, + {0x8086, 0x1f39, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, + {0x8086, 0x1f3a, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, + {0x8086, 0x1f3b, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, + {0x8086, 0x2310, NT, "Intel", "DH89xxCC (Cave Creek)", enable_flash_pch7}, {0x8086, 0x2390, NT, "Intel", "Coleto Creek", enable_flash_pch7}, {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich0}, {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich0}, @@ -1567,7 +1690,7 @@ {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4}, {0x8086, 0x8119, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo}, - {0x8086, 0x8186, OK, "Intel", "Atom E6xx(T)/Tunnel Creek", enable_flash_tunnelcreek}, + {0x8086, 0x8186, OK, "Intel", "Atom E6xx(T) (Tunnel Creek)", enable_flash_tunnelcreek}, {0x8086, 0x8c40, NT, "Intel", "Lynx Point", enable_flash_pch8}, {0x8086, 0x8c41, NT, "Intel", "Lynx Point Mobile Eng. Sample", enable_flash_pch8}, {0x8086, 0x8c42, NT, "Intel", "Lynx Point Desktop Eng. Sample",enable_flash_pch8}, Modified: trunk/ich_descriptors.c ============================================================================== --- trunk/ich_descriptors.c Wed Aug 20 17:39:19 2014 (r1843) +++ trunk/ich_descriptors.c Wed Aug 20 17:39:32 2014 (r1844) @@ -139,6 +139,7 @@ return size_str[size_enc]; } case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: { uint8_t size_enc; @@ -180,6 +181,7 @@ case CHIPSET_6_SERIES_COUGAR_POINT: case CHIPSET_7_SERIES_PANTHER_POINT: case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: return freq_str[value]; @@ -820,6 +822,7 @@ size_max = 5; break; case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: if (idx == 0) { Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Wed Aug 20 17:39:19 2014 (r1843) +++ trunk/ichspi.c Wed Aug 20 17:39:32 2014 (r1844) @@ -612,7 +612,8 @@ bbar_off = 0x50; break; case CHIPSET_ICH8: - msg_perr("BBAR offset is unknown on ICH8!\n"); + case CHIPSET_BAYTRAIL: + msg_pdbg("BBAR offset is unknown!\n"); return; case CHIPSET_ICH9: default: /* Future version might behave the same */ @@ -1739,9 +1740,12 @@ msg_pdbg("VSCC: "); prettyprint_ich_reg_vscc(tmp, MSG_DEBUG, true); } else { - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); - msg_pdbg("0xA0: 0x%08x (BBAR)\n", - ichspi_bbar); + if (ich_generation != CHIPSET_BAYTRAIL && desc_valid) { + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); + msg_pdbg("0xA0: 0x%08x (BBAR)\n", + ichspi_bbar); + ich_set_bbar(0); + } if (desc_valid) { tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); @@ -1757,10 +1761,8 @@ tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); } - ich_set_bbar(0); } - msg_pdbg("\n"); if (desc_valid) { if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == ICH_RET_OK) prettyprint_ich_descriptors(ich_gen, &desc); Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Wed Aug 20 17:39:19 2014 (r1843) +++ trunk/programmer.h Wed Aug 20 17:39:32 2014 (r1844) @@ -600,6 +600,7 @@ CHIPSET_6_SERIES_COUGAR_POINT, CHIPSET_7_SERIES_PANTHER_POINT, CHIPSET_8_SERIES_LYNX_POINT, + CHIPSET_BAYTRAIL, /* Actually all with Silvermont architecture: Bay Trail, Avoton/Rangeley */ CHIPSET_8_SERIES_LYNX_POINT_LP, CHIPSET_8_SERIES_WELLSBURG, }; Modified: trunk/util/ich_descriptors_tool/ich_descriptors_tool.c ============================================================================== --- trunk/util/ich_descriptors_tool/ich_descriptors_tool.c Wed Aug 20 17:39:19 2014 (r1843) +++ trunk/util/ich_descriptors_tool/ich_descriptors_tool.c Wed Aug 20 17:39:32 2014 (r1844) @@ -118,6 +118,7 @@ "\t- \"ich8\",\n" "\t- \"ich9\",\n" "\t- \"ich10\",\n" +"\t- \"silvermont\" for chipsets from Intel's Silvermont architecture (e.g. Bay Trail),\n" "\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" "\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" "\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" @@ -202,6 +203,8 @@ else if ((strcmp(csn, "8") == 0) || (strcmp(csn, "lynx") == 0)) cs = CHIPSET_8_SERIES_LYNX_POINT; + else if ((strcmp(csn, "silvermont") == 0)) + cs = CHIPSET_BAYTRAIL; } ret = read_ich_descriptors_from_dump(buf, len, &desc);

1 0

[commit] r1843 - in trunk: . util/ich_descriptors_tool
by repository service 20 Aug '14

20 Aug '14

Author: stefanct Date: Wed Aug 20 17:39:19 2014 New Revision: 1843 URL: http://flashrom.org/trac/flashrom/changeset/1843 Log: Refine Flash Component descriptor handling. Possible values as well as encodings have changed in newer chipsets as follows. - Pre-PCH (i.e. ICH) chipsets had a maximum frequency of 33 MHz for all operations - Since Cougar Point the chipsets support dual output fast reads (encoded in bit 30). - Flash component density encoding has changed from 3 to 4 bits with Lynx Point, currently allowing for up to 64 MB chips. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/ich_descriptors.c trunk/ich_descriptors.h trunk/ichspi.c trunk/util/ich_descriptors_tool/ich_descriptors_tool.c Modified: trunk/ich_descriptors.c ============================================================================== --- trunk/ich_descriptors.c Fri Aug 15 19:17:59 2014 (r1842) +++ trunk/ich_descriptors.c Wed Aug 20 17:39:19 2014 (r1843) @@ -45,14 +45,16 @@ #define min(a, b) (a < b) ? a : b #endif -void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity) +void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity, bool print_vcl) { print(verbosity, "BES=0x%x, ", (reg_val & VSCC_BES) >> VSCC_BES_OFF); print(verbosity, "WG=%d, ", (reg_val & VSCC_WG) >> VSCC_WG_OFF); print(verbosity, "WSR=%d, ", (reg_val & VSCC_WSR) >> VSCC_WSR_OFF); print(verbosity, "WEWS=%d, ", (reg_val & VSCC_WEWS) >> VSCC_WEWS_OFF); - print(verbosity, "EO=0x%x, ", (reg_val & VSCC_EO) >> VSCC_EO_OFF); - print(verbosity, "VCL=%d\n", (reg_val & VSCC_VCL) >> VSCC_VCL_OFF); + print(verbosity, "EO=0x%x", (reg_val & VSCC_EO) >> VSCC_EO_OFF); + if (print_vcl) + print(verbosity, ", VCL=%d", (reg_val & VSCC_VCL) >> VSCC_VCL_OFF); + print(verbosity, "\n"); } #define getFCBA(cont) (((cont)->FLMAP0 << 4) & 0x00000ff0) @@ -64,7 +66,7 @@ void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc) { prettyprint_ich_descriptor_content(&desc->content); - prettyprint_ich_descriptor_component(desc); + prettyprint_ich_descriptor_component(cs, desc); prettyprint_ich_descriptor_region(desc); prettyprint_ich_descriptor_master(&desc->master); #ifdef ICH_DESCRIPTORS_FROM_DUMP @@ -98,28 +100,97 @@ msg_pdbg2("\n"); } -void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc) +static const char *pprint_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx) +{ + if (idx > 1) { + msg_perr("Only ICH SPI component index 0 or 1 are supported yet.\n"); + return NULL; + } + + if (desc->content.NC == 0 && idx > 0) + return "unused"; + + static const char * const size_str[] = { + "512 kB", /* 0000 */ + "1 MB", /* 0001 */ + "2 MB", /* 0010 */ + "4 MB", /* 0011 */ + "8 MB", /* 0100 */ + "16 MB", /* 0101 */ /* Maximum up to Lynx Point (excl.) */ + "32 MB", /* 0110 */ + "64 MB", /* 0111 */ + }; + + switch (cs) { + case CHIPSET_ICH8: + case CHIPSET_ICH9: + case CHIPSET_ICH10: + case CHIPSET_5_SERIES_IBEX_PEAK: + case CHIPSET_6_SERIES_COUGAR_POINT: + case CHIPSET_7_SERIES_PANTHER_POINT: { + uint8_t size_enc; + if (idx == 0) { + size_enc = desc->component.old.comp1_density; + } else { + size_enc = desc->component.old.comp2_density; + } + if (size_enc > 5) + return "reserved"; + return size_str[size_enc]; + } + case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_8_SERIES_LYNX_POINT_LP: + case CHIPSET_8_SERIES_WELLSBURG: { + uint8_t size_enc; + if (idx == 0) { + size_enc = desc->component.new.comp1_density; + } else { + size_enc = desc->component.new.comp2_density; + } + if (size_enc > 7) + return "reserved"; + return size_str[size_enc]; + } + case CHIPSET_ICH_UNKNOWN: + default: + return "unknown"; + } +} + +static const char *pprint_freq(enum ich_chipset cs, uint8_t value) { static const char * const freq_str[8] = { "20 MHz", /* 000 */ "33 MHz", /* 001 */ "reserved", /* 010 */ "reserved", /* 011 */ - "50 MHz", /* 100 */ + "50 MHz", /* 100 */ /* New since Ibex Peak */ "reserved", /* 101 */ "reserved", /* 110 */ "reserved" /* 111 */ }; - static const char * const size_str[8] = { - "512 kB", /* 000 */ - " 1 MB", /* 001 */ - " 2 MB", /* 010 */ - " 4 MB", /* 011 */ - " 8 MB", /* 100 */ - " 16 MB", /* 101 */ - "reserved", /* 110 */ - "reserved", /* 111 */ - }; + + switch (cs) { + case CHIPSET_ICH8: + case CHIPSET_ICH9: + case CHIPSET_ICH10: + if (value > 1) + return "reserved"; + case CHIPSET_5_SERIES_IBEX_PEAK: + case CHIPSET_6_SERIES_COUGAR_POINT: + case CHIPSET_7_SERIES_PANTHER_POINT: + case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_8_SERIES_LYNX_POINT_LP: + case CHIPSET_8_SERIES_WELLSBURG: + return freq_str[value]; + case CHIPSET_ICH_UNKNOWN: + default: + return "unknown"; + } +} + +void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc) +{ msg_pdbg2("=== Component Section ===\n"); msg_pdbg2("FLCOMP 0x%08x\n", desc->component.FLCOMP); @@ -127,24 +198,21 @@ msg_pdbg2("\n"); msg_pdbg2("--- Details ---\n"); - msg_pdbg2("Component 1 density: %s\n", - size_str[desc->component.comp1_density]); + msg_pdbg2("Component 1 density: %s\n", pprint_density(cs, desc, 0)); if (desc->content.NC) - msg_pdbg2("Component 2 density: %s\n", - size_str[desc->component.comp2_density]); + msg_pdbg2("Component 2 density: %s\n", pprint_density(cs, desc, 1)); else msg_pdbg2("Component 2 is not used.\n"); - msg_pdbg2("Read Clock Frequency: %s\n", - freq_str[desc->component.freq_read]); - msg_pdbg2("Read ID and Status Clock Freq.: %s\n", - freq_str[desc->component.freq_read_id]); - msg_pdbg2("Write and Erase Clock Freq.: %s\n", - freq_str[desc->component.freq_write]); - msg_pdbg2("Fast Read is %ssupported.\n", - desc->component.fastread ? "" : "not "); - if (desc->component.fastread) + msg_pdbg2("Read Clock Frequency: %s\n", pprint_freq(cs, desc->component.common.freq_read)); + msg_pdbg2("Read ID and Status Clock Freq.: %s\n", pprint_freq(cs, desc->component.common.freq_read_id)); + msg_pdbg2("Write and Erase Clock Freq.: %s\n", pprint_freq(cs, desc->component.common.freq_write)); + msg_pdbg2("Fast Read is %ssupported.\n", desc->component.common.fastread ? "" : "not "); + if (desc->component.common.fastread) msg_pdbg2("Fast Read Clock Frequency: %s\n", - freq_str[desc->component.freq_fastread]); + pprint_freq(cs, desc->component.common.freq_fastread)); + if (cs > CHIPSET_6_SERIES_COUGAR_POINT) + msg_pdbg2("Dual Output Fast Read Support: %sabled\n", + desc->component.new.dual_output ? "dis" : "en"); if (desc->component.FLILL == 0) msg_pdbg2("No forbidden opcodes.\n"); else { @@ -273,7 +341,7 @@ msg_pdbg2("PCI Express Port Configuration Strap %d: ", off+1); off *= 4; - switch(conf){ + switch (conf){ case 0: msg_pdbg2("4x1 Ports %d-%d (x1)", 1+off, 4+off); break; @@ -630,7 +698,7 @@ msg_pdbg2(" "); /* indention */ prettyprint_rdid(jid); msg_pdbg2(" "); /* indention */ - prettyprint_ich_reg_vscc(vscc, 0); + prettyprint_ich_reg_vscc(vscc, 0, false); } msg_pdbg2("\n"); } @@ -723,29 +791,57 @@ #else /* ICH_DESCRIPTORS_FROM_DUMP */ /** Returns the integer representation of the component density with index -idx in bytes or 0 if a correct size can not be determined. */ -int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx) +\em idx in bytes or -1 if the correct size can not be determined. */ +int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx) { + if (idx > 1) { + msg_perr("Only ICH SPI component index 0 or 1 are supported yet.\n"); + return -1; + } + + if (desc->content.NC == 0 && idx > 0) + return 0; + uint8_t size_enc; - - switch(idx) { - case 0: - size_enc = desc->component.comp1_density; - break; - case 1: - if (desc->content.NC == 0) - return 0; - size_enc = desc->component.comp2_density; + uint8_t size_max; + + switch (cs) { + case CHIPSET_ICH8: + case CHIPSET_ICH9: + case CHIPSET_ICH10: + case CHIPSET_5_SERIES_IBEX_PEAK: + case CHIPSET_6_SERIES_COUGAR_POINT: + case CHIPSET_7_SERIES_PANTHER_POINT: + if (idx == 0) { + size_enc = desc->component.old.comp1_density; + } else { + size_enc = desc->component.old.comp2_density; + } + size_max = 5; + break; + case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_8_SERIES_LYNX_POINT_LP: + case CHIPSET_8_SERIES_WELLSBURG: + if (idx == 0) { + size_enc = desc->component.new.comp1_density; + } else { + size_enc = desc->component.new.comp2_density; + } + size_max = 7; break; + case CHIPSET_ICH_UNKNOWN: default: - msg_perr("Only ICH SPI component index 0 or 1 are supported yet.\n"); - return 0; + msg_pwarn("Density encoding is unknown on this chipset.\n"); + return -1; } - if (size_enc > 5) { - msg_perr("Density of ICH SPI component with index %d is invalid. Encoded density is 0x%x.\n", - idx, size_enc); - return 0; + + if (size_enc > size_max) { + msg_perr("Density of ICH SPI component with index %d is invalid." + "Encoded density is 0x%x while maximum allowed is 0x%x.\n", + idx, size_enc, size_max); + return -1; } + return (1 << (19 + size_enc)); } Modified: trunk/ich_descriptors.h ============================================================================== --- trunk/ich_descriptors.h Fri Aug 15 19:17:59 2014 (r1842) +++ trunk/ich_descriptors.h Wed Aug 20 17:39:19 2014 (r1843) @@ -64,7 +64,7 @@ #define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x01fff000) #define ICH_FREG_LIMIT(flreg) (((flreg) >> 4) & 0x01fff000) -void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity); +void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity, bool print_vcl); struct ich_desc_content { uint32_t FLVALSIG; /* 0x00 */ @@ -102,17 +102,44 @@ struct ich_desc_component { union { /* 0x00 */ uint32_t FLCOMP; /* Flash Components Register */ + /* FLCOMP encoding on various generations: + * + * Chipset/Generation max_speed dual_output density + * [MHz] bits max. bits + * ICH8: 33 N/A 5 0:2, 3:5 + * ICH9: 33 N/A 5 0:2, 3:5 + * ICH10: 33 N/A 5 0:2, 3:5 + * Ibex Peak/5: 50 N/A 5 0:2, 3:5 + * Cougar Point/6: 50 30 5 0:2, 3:5 + * Patsburg: 50 30 5 0:2, 3:5 + * Panther Point/7 50 30 5 0:2, 3:5 + * Lynx Point/8: 50 30 7 0:3, 4:7 + * Wildcat Point/9: 50 ?? (multi I/O) ? ?:?, ?:? + */ struct { - uint32_t comp1_density :3, - comp2_density :3, - :11, + uint32_t :17, freq_read :3, fastread :1, freq_fastread :3, freq_write :3, freq_read_id :3, :2; - }; + } common; + struct { + uint32_t comp1_density :3, + comp2_density :3, + :11, + :13, + :2; + } old; + struct { + uint32_t comp1_density :4, /* new since Lynx Point/8 */ + comp2_density :4, + :9, + :13, + dual_output :1, /* new since Cougar Point/6 */ + :1; + } new; }; union { /* 0x04 */ uint32_t FLILL; /* Flash Invalid Instructions Register */ @@ -555,7 +582,7 @@ void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc); void prettyprint_ich_descriptor_content(const struct ich_desc_content *content); -void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc); +void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc); void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); @@ -568,7 +595,7 @@ #else /* ICH_DESCRIPTORS_FROM_DUMP */ int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); -int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx); +int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx); #endif /* ICH_DESCRIPTORS_FROM_DUMP */ #endif /* __ICH_DESCRIPTORS_H__ */ Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Fri Aug 15 19:17:59 2014 (r1842) +++ trunk/ichspi.c Wed Aug 20 17:39:19 2014 (r1843) @@ -1737,7 +1737,7 @@ tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); msg_pdbg("VSCC: "); - prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG, true); } else { ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0xA0: 0x%08x (BBAR)\n", @@ -1747,12 +1747,12 @@ tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); msg_pdbg("LVSCC: "); - prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG, true); tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); msg_pdbg("UVSCC: "); - prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG, false); tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); @@ -1762,10 +1762,9 @@ msg_pdbg("\n"); if (desc_valid) { - if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == - ICH_RET_OK) - prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, - &desc); + if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == ICH_RET_OK) + prettyprint_ich_descriptors(ich_gen, &desc); + /* If the descriptor is valid and indicates multiple * flash devices we need to use hwseq to be able to * access the second flash device. @@ -1791,8 +1790,21 @@ "valid. Aborting.\n"); return ERROR_FATAL; } - hwseq_data.size_comp0 = getFCBA_component_density(&desc, 0); - hwseq_data.size_comp1 = getFCBA_component_density(&desc, 1); + + int tmpi = getFCBA_component_density(ich_generation, &desc, 0); + if (tmpi < 0) { + msg_perr("Could not determine density of flash component %d.\n", 0); + return ERROR_FATAL; + } + hwseq_data.size_comp0 = tmpi; + + tmpi = getFCBA_component_density(ich_generation, &desc, 1); + if (tmpi < 0) { + msg_perr("Could not determine density of flash component %d.\n", 1); + return ERROR_FATAL; + } + hwseq_data.size_comp1 = tmpi; + register_opaque_master(&opaque_master_ich_hwseq); } else { register_spi_master(&spi_master_ich9); Modified: trunk/util/ich_descriptors_tool/ich_descriptors_tool.c ============================================================================== --- trunk/util/ich_descriptors_tool/ich_descriptors_tool.c Fri Aug 15 19:17:59 2014 (r1842) +++ trunk/util/ich_descriptors_tool/ich_descriptors_tool.c Wed Aug 20 17:39:19 2014 (r1843) @@ -113,7 +113,7 @@ "where <image file name> points to an image of the contents of the SPI flash.\n" "In case the image is really in descriptor mode %s\n" "will pretty print some of the contained information.\n" -"To also print the data stored in the descriptor strap you have to indicate\n" +"To also print the data stored in the descriptor straps you have to indicate\n" "the chipset series with the '-c' parameter and one of the possible arguments:\n" "\t- \"ich8\",\n" "\t- \"ich9\",\n" @@ -121,6 +121,7 @@ "\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" "\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" "\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" +"\t- \"8\" or \"lynx\" for Intel's 8 series chipsets.\n" "If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n" "the GbE blob that is required to initialize the GbE are also dumped to files.\n", argv[0], argv[0]); @@ -198,6 +199,9 @@ else if ((strcmp(csn, "7") == 0) || (strcmp(csn, "panther") == 0)) cs = CHIPSET_7_SERIES_PANTHER_POINT; + else if ((strcmp(csn, "8") == 0) || + (strcmp(csn, "lynx") == 0)) + cs = CHIPSET_8_SERIES_LYNX_POINT; } ret = read_ich_descriptors_from_dump(buf, len, &desc);

1 0

Re: [flashrom] [PATCH 3/3] Refine physical address mapping of flash chips.
by Carl-Daniel Hailfinger 19 Aug '14

19 Aug '14

Am 08.08.2014 16:25 schrieb Stefan Tauner: > Previously we did map the physical memory corresponding to all chips, > even for SPI chips where it is completely unnecessary because we do > not use it in any SPI-capable programmer. Ahem. it87spi.c: it8716f_spi_chip_read() and it8716f_spi_page_program() uses that. > Also, the mapping was never undone before the program exited. > Mapping of additional flash registers was done within probing methods > instead of centrally. This patch changes the behaviour: In current HEAD, the mapping of registers only happens on successful probe. With this patch, it happens unconditionally (depending only on whether the chip supports it, not on whether the programmer supports it) before probe. If you really want to change that, it should be mentioned in the changelog. > Besides all of that, this patch also adds proper error handling for > mapping-related operations. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Sorry, no ack yet. > 82802ab.c | 2 -- > flash.h | 1 - > flashrom.c | 84 ++++++++++++++++++++++++++++++++++++++++++++++---------------- > jedec.c | 6 ----- > 4 files changed, 63 insertions(+), 30 deletions(-) > > diff --git a/82802ab.c b/82802ab.c > index 70c6af0..5d015ba 100644 > --- a/82802ab.c > +++ b/82802ab.c > @@ -83,8 +83,6 @@ int probe_82802ab(struct flashctx *flash) > if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id) > return 0; > > - if (flash->chip->feature_bits & FEATURE_REGISTERMAP) > - map_flash_registers(flash); > > return 1; > } > diff --git a/flash.h b/flash.h > index 82a8b74..998696c 100644 > --- a/flash.h > +++ b/flash.h > @@ -252,7 +252,6 @@ void tolower_string(char *str); > /* flashrom.c */ > extern const char flashrom_version[]; > extern const char *chip_to_probe; > -void map_flash_registers(struct flashctx *flash); > int read_memmapped(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); > int erase_flash(struct flashctx *flash); > int probe_flash(struct registered_master *mst, int startchip, struct flashctx *fill_flash, int force); > diff --git a/flashrom.c b/flashrom.c > index 0ff6b63..72bf157 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -528,12 +528,23 @@ void programmer_delay(unsigned int usecs) > programmer_table[programmer].delay(usecs); > } > > -void map_flash_registers(struct flashctx *flash) > +static int map_flash_registers(struct flashctx *flash) Can you leave that one untouched, please? It's code I dare not change because even I have no idea where (if at all) registers would be mapped for chips on masters mapping the chip to nonstandard locations. If you have access to Loongson and Elan SC520 datasheets, you're welcome to check and fix this. Until then, the known broken and documented broken code is IMHO better than speculative code that looks like it could work but was never checked against datasheets or hardware. > { > size_t size = flash->chip->total_size * 1024; > /* Flash registers live 4 MByte below the flash. */ > - /* FIXME: This is incorrect for nonstandard flashbase. */ > - flash->virtual_registers = (chipaddr)programmer_map_flash_region("flash chip registers", (0xFFFFFFFF - 0x400000 - size + 1), size); > + uintptr_t base = (flashbase != 0) ? flashbase : (0xffffffff - size + 1); > + if (base < 0x400000) { > + msg_perr("Base address is too low to map flash registers."); > + return 1; > + } > + base -= 0x400000; > + void *addr = programmer_map_flash_region("flash chip registers", base, size); > + if (addr == ERROR_PTR) { > + msg_perr("Could not map flash chip registers.\n"); > + return 1; > + } > + flash->virtual_registers = (chipaddr)addr; > + return 0; > } > > int read_memmapped(struct flashctx *flash, uint8_t *buf, unsigned int start, > @@ -1052,12 +1063,49 @@ unsigned int count_max_decode_exceedings(struct flashctx *flash) > return limitexceeded; > } > > +void unmap_flash(struct flashctx *flash) > +{ > + if (flash->chip->bustype & (BUS_PARALLEL | BUS_LPC | BUS_FWH)) { > + if (flash->virtual_memory != 0) { > + programmer_unmap_flash_region((void *)flash->virtual_memory, > + flash->chip->total_size * 1024); > + flash->virtual_memory = 0; > + } > + > + if (flash->chip->feature_bits & FEATURE_REGISTERMAP && flash->virtual_registers != 0) { > + programmer_unmap_flash_region((void *)flash->virtual_registers, > + flash->chip->total_size * 1024); > + flash->virtual_registers = 0; > + } > + } > +} > + > +int map_flash(struct flashctx *flash) > +{ > + const unsigned long size = flash->chip->total_size; > + if (flash->chip->bustype & (BUS_PARALLEL | BUS_LPC | BUS_FWH)) { > + uintptr_t base = flashbase ? flashbase : (0xffffffff - size + 1); > + void *addr = programmer_map_flash_region("flash chip", base, size); > + if (addr == ERROR_PTR) { > + msg_perr("Could not map flash chip registers.\n"); > + return 1; > + } > + flash->virtual_memory = (chipaddr)addr; > + > + if (flash->chip->feature_bits & FEATURE_REGISTERMAP) { > + if (map_flash_registers(flash) != 0) { > + unmap_flash(flash); > + return 1; > + } > + } > + } AFAICS this will segfault (NULL pointer dereference) on chips of 4 MBit and less on IT87 SPI. > + > + return 0; > +} > + > int probe_flash(struct registered_master *mst, int startchip, struct flashctx *flash, int force) > { > const struct flashchip *chip; > - unsigned long base = 0; > - char location[64]; > - uint32_t size; > enum chipbustype buses_common; > char *tmp; > > @@ -1082,9 +1130,8 @@ int probe_flash(struct registered_master *mst, int startchip, struct flashctx *f > memcpy(flash->chip, chip, sizeof(struct flashchip)); > flash->mst = mst; > > - size = chip->total_size * 1024; > - base = flashbase ? flashbase : (0xffffffff - size + 1); > - flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); > + if (map_flash(flash) != 0) > + return -1; > > /* We handle a forced match like a real match, we just avoid probing. Note that probe_flash() > * is only called with force=1 after normal probing failed. > @@ -1133,8 +1180,7 @@ int probe_flash(struct registered_master *mst, int startchip, struct flashctx *f > break; > /* Not the first flash chip detected on this bus, and it's just a generic match. Ignore it. */ > notfound: > - programmer_unmap_flash_region((void *)flash->virtual_memory, size); > - flash->virtual_memory = (chipaddr)NULL; > + unmap_flash(flash); > free(flash->chip); > flash->chip = NULL; > } > @@ -1142,16 +1188,9 @@ notfound: > if (!flash->chip) > return -1; > > -#if CONFIG_INTERNAL == 1 > - if (programmer_table[programmer].map_flash_region == physmap) > - snprintf(location, sizeof(location), "at physical address 0x%lx", base); > - else > -#endif > - snprintf(location, sizeof(location), "on %s", programmer_table[programmer].name); > - That info should not have disappeared, and we may soon have to extend it for funny constellations like two chips in a programmer (EC flash and chipset flash for laptops). > tmp = flashbuses_to_text(flash->chip->bustype); > - msg_cinfo("%s %s flash chip \"%s\" (%d kB, %s) %s.\n", force ? "Assuming" : "Found", > - flash->chip->vendor, flash->chip->name, flash->chip->total_size, tmp, location); > + msg_cinfo("%s %s flash chip \"%s\" (%d kB, %s).\n", force ? "Assuming" : "Found", > + flash->chip->vendor, flash->chip->name, flash->chip->total_size, tmp); > free(tmp); > > /* Flash registers will not be mapped if the chip was forced. Lock info > @@ -1872,7 +1911,8 @@ int doit(struct flashctx *flash, int force, const char *filename, int read_it, > flash->chip->unlock(flash); > > if (read_it) { > - return read_flash_to_file(flash, filename); > + ret = read_flash_to_file(flash, filename); > + goto unmap; > } > > oldcontents = malloc(size); > @@ -1991,5 +2031,7 @@ int doit(struct flashctx *flash, int force, const char *filename, int read_it, > out: > free(oldcontents); > free(newcontents); > +unmap: > + unmap_flash(flash); > return ret; > } > diff --git a/jedec.c b/jedec.c > index 358b850..1345b89 100644 > --- a/jedec.c > +++ b/jedec.c > @@ -166,9 +166,6 @@ int probe_jedec_29gl(struct flashctx *flash) > if (man_id != chip->manufacture_id || dev_id != chip->model_id) > return 0; > > - if (chip->feature_bits & FEATURE_REGISTERMAP) > - map_flash_registers(flash); > - > return 1; > } > > @@ -287,9 +284,6 @@ static int probe_jedec_common(struct flashctx *flash, unsigned int mask) > if (largeid1 != chip->manufacture_id || largeid2 != chip->model_id) > return 0; > > - if (chip->feature_bits & FEATURE_REGISTERMAP) > - map_flash_registers(flash); > - > return 1; > } > Regards, Carl-Daniel

2 4

Thinkpad X60s bug report
by Ted 19 Aug '14

19 Aug '14

>>>x60s@TedX60s:~/Downloads/libreboot_bin/flashrom$ sudo ./flashrom_lenovobios_sst -p internal -r factory.bin flashrom v0.9.7-unknown on Linux 3.2.0-60-generic (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel ICH7M". Enabling flash write... WARNING: SPI Configuration Lockdown activated. OK. Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org Trying to unmap a nonexisting mapping! Please report a bug at flashrom(a)flashrom.org No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically.

2 1

Re: [flashrom] Macronix MX25L12835FMI-10G, bus pirate and flashrom support
by Stefan Tauner 19 Aug '14

19 Aug '14

On Tue, 19 Aug 2014 14:43:09 +0200 Marli LI <marco.li.li.marco(a)gmail.com> wrote: > My output now is: > >> Found Macronix flash chip "MX25L12805(D)" (16384 kB, SPI). > >> This chip may contain one-time programmable memory. flashrom cannot read > >> and may never be able to write it, hence it may not be able to completely > >> clone the contents of this chip (see man page for details). > > I think I can now proceed w/ dumping the chip, right? Yes, even erase and write should work fine. The chips do not only share the same ID but also the most important opcodes. I am not expecting more trouble. > Can't flashrom somehow distinguish the different Macronix chips? The > label of mine should be MX25L12835FMI-10g . > If someone has an idea if such an improvement is possible, I would be > happy to test/analyze. With the current infrastructure it can't distinguish them. Improvements are on the way but even with them it might not be exactly trivial to accomplish that. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Re: [flashrom] Macronix MX25L12835FMI-10G, bus pirate and flashrom support
by Stefan Tauner 19 Aug '14

19 Aug '14

On Mon, 18 Aug 2014 17:38:04 +0200 Marli LI <marco.li.li.marco(a)gmail.com> wrote: > Hello all, > > I need some help to get this chip MX25L12835FMI-10G manufactured by > Macronix to work w/ flashrom. > > I already asked for help on #flashrom IRC channel, but I was referred > to ask on this mailing list. > In fact, before I connected everything I asked on IRC if this chip is > "already" supported, and someone from IRC did double-check it and said > that the other MX25L128 chip model that IS supported is very similar > and identifies itself w/ same code/id (he got this info from > spreadsheet that I've linked below). > > So here is my output of flashrom (I've tried both the svn version and > the one shipped with ubuntu packages w/ identical results): > http://paste.flashrom.org/view.php?id=2658 > > > The chip's datasheet should be this one: > http://www.macronix.com/Lists/Datasheet/Attachments/1587/MX25L12835F,%203V,… > On page 7 you can see the pin-out. The chip type I have has 16 (= 8x2) > pins. There are several NC labels in the pin-out therefore I didn't > connect those. > > For the rest of the connections I followed this site: > http://flashrom.org/Bus_Pirate (because I use a bus pirate w/ > hardware version 3.6 ). > The chip itself is directly attached to a pomona 5252 (SOIC-16) test clip. > > What follows are some pics of my setup + chip. > > Any hints and help would be very much appreciated because I am kind of stuck. > > Ps. Today I discovered something interesting in the spreadsheet; the > 10 (from -10g suffix) stands for 10: 104MHz . Do I need to set > spispeed to a higher level b/c of this? > > Thx again > > - - - IMAGES - - - > > Macronix MX25L12835FMI-10G chip (16 pins): http://postimg.org/image/y7ykedq6r/ > Pomona soic-16 test clip 5252 : http://postimg.org/image/gqru9oum7/ > Bus pirate hw version 3.6 : http://postimg.org/image/80a7zp0ub/ > Test clip + chip, direction (where point is): > http://postimg.org/image/koc4h655d/ > Chip attached: http://postimg.org/image/4ywrbnnst/ As discussed on IRC, this is probably caused by bad connections or not enough power supplied to the chip. The frequency stated for flash chip is a maximum and slower programmers work fine (most mainboards do not use more than ~50 MHz either). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

Re: [flashrom] FAILED: HP ChromeBook 14 (Falco)
by Stefan Tauner 18 Aug '14

18 Aug '14

On Mon, 18 Aug 2014 19:35:18 +0200 "Maria Roth" <rothm(a)mail.com> wrote: > Hi, > > I got that while using J. Lewis script to flash an HP Chromebook 14 (Falco) (without screw). > > flashrom v0.9.4 : 14ce0cf : Oct 09 2013 22:16:28 UTC on Linux 3.15.10-200.fc20.x86_64 (x86_64), built with libpci 3.1.10, GCC 4.7.x-google 20130114 (prerelease), little endian Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0 Verifying flash... VERIFY FAILED at 0x00000062! Expected=0xff, Read=0x0b, failed byte count from 0x00000000-0x007fffff: 0x4 Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with FAILED: your board name in the subject line! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! FAILED > > Can you help ? > > Thanks, > R. As discussed on IRC, and merely in the hope it might help someone in the future: if you see exactly this message (esp. the 0x4 after the range of memory addresses and the 0x0...62 after VERIFY FAILED) then you are safe. It is caused by a difference between the original flash contents and the image John Lewis is providing at his website (https://johnlewis.ie). The difference is in a copy-protected region that is not essential for the rest of the image and both versions are OK - they just can't be changed without an external programmer and that's why one gets the warning when using flashrom with the internal programmer. You have to nag John to get this fixed/changed, but it is in this form only a cosmetic nuisance. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

FAILED: HP ChromeBook 14 (Falco)
by Maria Roth 18 Aug '14

18 Aug '14

1 0

Macronix MX25L12835FMI-10G, bus pirate and flashrom support
by Marli LI 18 Aug '14

18 Aug '14

Hello all, I need some help to get this chip MX25L12835FMI-10G manufactured by Macronix to work w/ flashrom. I already asked for help on #flashrom IRC channel, but I was referred to ask on this mailing list. In fact, before I connected everything I asked on IRC if this chip is "already" supported, and someone from IRC did double-check it and said that the other MX25L128 chip model that IS supported is very similar and identifies itself w/ same code/id (he got this info from spreadsheet that I've linked below). So here is my output of flashrom (I've tried both the svn version and the one shipped with ubuntu packages w/ identical results): http://paste.flashrom.org/view.php?id=2658 The chip's datasheet should be this one: http://www.macronix.com/Lists/Datasheet/Attachments/1587/MX25L12835F,%203V,… On page 7 you can see the pin-out. The chip type I have has 16 (= 8x2) pins. There are several NC labels in the pin-out therefore I didn't connect those. For the rest of the connections I followed this site: http://flashrom.org/Bus_Pirate (because I use a bus pirate w/ hardware version 3.6 ). The chip itself is directly attached to a pomona 5252 (SOIC-16) test clip. What follows are some pics of my setup + chip. Any hints and help would be very much appreciated because I am kind of stuck. Ps. Today I discovered something interesting in the spreadsheet; the 10 (from -10g suffix) stands for 10: 104MHz . Do I need to set spispeed to a higher level b/c of this? Thx again - - - IMAGES - - - Macronix MX25L12835FMI-10G chip (16 pins): http://postimg.org/image/y7ykedq6r/ Pomona soic-16 test clip 5252 : http://postimg.org/image/gqru9oum7/ Bus pirate hw version 3.6 : http://postimg.org/image/80a7zp0ub/ Test clip + chip, direction (where point is): http://postimg.org/image/koc4h655d/ Chip attached: http://postimg.org/image/4ywrbnnst/

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[PATCH] Bus Pirate UART speedup
by Bernie Innocenti 17 Aug '14

17 Aug '14

I'm reposting this patch sent by Stefan Tauner in April, after rebasing it onto flashrom's svn trunk. Compared to the original, there's just one change: the original patch did set the host uart speed back to 115200 (which is a no-op). So I changed the baudrate to 2000000 (2Mbit), making the code agree with the description. I tested the patched flashrom with a Buspirate v3 running the 6.2beta firmware. While I didn't make any accurate measurements, I'd guesstimate a 10x speedup with my 8MB SPI flash. WOAH! --- original description follows ---- Increase PIC/FT232 UART speed to 2 Mbaud (instead of 115200 baud) in firmware 5.5 and newer. Given that UART speed is the biggest bottleneck for Bus Pirate communication (right now 90% of the read time is caused by slow BP<->host communication), this patch is absolutely needed to get any decent speed out of the Bus Pirate. WARNING: This patch may hang flashrom or corrupt data for any non-v3 Bus Pirate model. I haven't tested such models, and it might work without problems. Who knows. We would have to find someone with a v2 (or earlier) Bus Pirate and a firmware version >=v5.5 to test this. For Bus Pirate model v4 this patch may be completely superfluous. Anyway, activating fast UART only for some models is probably the way to go. We already have code to determine the hardware model in the init function, this just needs to be stored in some variable. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- buspirate_spi.c | 44 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/buspirate_spi.c b/buspirate_spi.c index d2ebc75..57da63a 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -178,7 +178,10 @@ static int buspirate_spi_shutdown(void *data) } /* Reset Bus Pirate (return to user terminal) */ bp_commbuf[0] = 0x0f; - ret = buspirate_sendrecv(bp_commbuf, 1, 0); + if ((ret = buspirate_sendrecv(bp_commbuf, 1, 0))) + goto out_shutdown; + if ((ret = serialport_config(sp_fd, 115200))) + goto out_shutdown; out_shutdown: /* Shut down serial port communication */ @@ -365,6 +368,45 @@ int buspirate_spi_init(void) spi_programmer_buspirate.command = buspirate_spi_send_command_v1; } + /* Increase PIC/FT232 UART speed to 2 Mbaud (instead of 115200 baud) in firmware 5.5 and newer. + * Although this is already possible in firmware 5.2, fast UART in combination with the old SPI + * command set causes hangs for bigger transactions. This is caused by a UART buffer overrun + * in the PIC, and all firmware versions up to (hopefully not including) 6.2 are affected. + */ + if (BP_FWVERSION(fw_version_major, fw_version_minor) >= BP_FWVERSION(5, 5)) { + // FIXME: Do this only for USB-based Bus Pirates... unless you're sure the UART can handle more. + int cmdlen; + /* Request setting the UART baud rate. */ + cmdlen = snprintf((char *)bp_commbuf, DEFAULT_BUFSIZE, "b\n"); + if ((ret = buspirate_sendrecv(bp_commbuf, cmdlen, 0))) + return ret; + if ((ret = buspirate_wait_for_string(bp_commbuf, ">"))) + return ret; + /* Request setting the UART clock divisor manually. */ + cmdlen = snprintf((char *)bp_commbuf, DEFAULT_BUFSIZE, "10\n"); + if ((ret = buspirate_sendrecv(bp_commbuf, cmdlen, 0))) + return ret; + if ((ret = buspirate_wait_for_string(bp_commbuf, ">"))) + return ret; + /* Set the UART clock divisor. New clock is 4000000/(divisor+1). */ + cmdlen = snprintf((char *)bp_commbuf, DEFAULT_BUFSIZE, "%i\n", 1); + if ((ret = buspirate_sendrecv(bp_commbuf, cmdlen, 0))) + return ret; + sleep(1); + if (serialport_config(sp_fd, 2000000) != 0) + return 1; + bp_commbuf[0] = ' '; + if ((ret = buspirate_sendrecv(bp_commbuf, 1, 0))) + return ret; + if ((ret = buspirate_wait_for_string(bp_commbuf, "HiZ>"))) + return ret; + msg_pdbg("Using fast 2 Mbaud for Bus Pirate <-> host communication.\n"); + } else { + msg_pinfo("Bus Pirate firmware 5.4 and older does not support fast Bus Pirate <-> host " + "communication. Limiting UART speed to 115200 Baud.\n"); + msg_pinfo("It is recommended to upgrade to firmware 6.2 or newer.\n"); + } + /* Workaround for broken speed settings in firmware 6.1 and older. */ if (BP_FWVERSION(fw_version_major, fw_version_minor) < BP_FWVERSION(6, 2)) if (spispeed > 0x4) { -- _ // Bernie Innocenti \X/ http://codewiz.org

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Re: [flashrom] [PATCH 2/3] Refine handling chips that exceed maximum programmer sizes.
by Carl-Daniel Hailfinger 15 Aug '14

15 Aug '14

Am 08.08.2014 16:25 schrieb Stefan Tauner: > - Change check_max_decode() to return the number of (common) busses > where the flash chip exceeds the supported size of the programmer. > - Refine its signature to use a flashctx pointer only. > - Move CLI-related bits to cli_classic.c. > - Rename check_max_decode() to count_max_decode_exceedings() to > better reflect what it (now) really does. > - Refine the messages printed by the caller to better integrate with the new > setup, and simplify them. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> I like it. One small comment below. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > diff --git a/flashrom.c b/flashrom.c > index eeed90b..0ff6b63 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -1079,9 +1073,6 @@ int probe_flash(struct registered_master *mst, int startchip, struct flashctx *f > continue; > } > > - size = chip->total_size * 1024; > - check_max_decode(buses_common, size); > - > /* Start filling in the dynamic data. */ > flash->chip = calloc(1, sizeof(struct flashchip)); > if (!flash->chip) { > @@ -1091,6 +1082,7 @@ int probe_flash(struct registered_master *mst, int startchip, struct flashctx *f > memcpy(flash->chip, chip, sizeof(struct flashchip)); > flash->mst = mst; > > + size = chip->total_size * 1024; At this point, it might be better to use "flash->chip->total_size * 1024" given that flash->chip is now valid (it wasn't valid at the old location). > base = flashbase ? flashbase : (0xffffffff - size + 1); > flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); > Regards, Carl-Daniel

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[commit] r1842 - trunk
by repository service 15 Aug '14

15 Aug '14

Author: stefanct Date: Fri Aug 15 19:17:59 2014 New Revision: 1842 URL: http://flashrom.org/trac/flashrom/changeset/1842 Log: Refine handling chips that exceed maximum programmer sizes. - Change check_max_decode() to return the number of (common) busses where the flash chip exceeds the supported size of the programmer. - Refine its signature to use a flashctx pointer only. - Move CLI-related bits to cli_classic.c. - Rename check_max_decode() to count_max_decode_exceedings() to better reflect what it (now) really does. - Refine the messages printed by the caller to better integrate with the new setup, and simplify them. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/cli_classic.c trunk/flashrom.c trunk/programmer.h Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Sat Aug 9 01:52:33 2014 (r1841) +++ trunk/cli_classic.c Fri Aug 15 19:17:59 2014 (r1842) @@ -91,7 +91,6 @@ int main(int argc, char *argv[]) { - unsigned long size; /* Probe for up to three flash chips. */ const struct flashchip *chip = NULL; struct flashctx flashes[6] = {{0}}; @@ -501,9 +500,18 @@ print_chip_support_status(fill_flash->chip); - size = fill_flash->chip->total_size * 1024; - if (check_max_decode(fill_flash->mst->buses_supported & fill_flash->chip->bustype, size) && (!force)) { - msg_cerr("Chip is too big for this programmer (-V gives details). Use --force to override.\n"); + unsigned int limitexceeded = count_max_decode_exceedings(fill_flash); + if (limitexceeded > 0 && !force) { + enum chipbustype commonbuses = fill_flash->mst->buses_supported & fill_flash->chip->bustype; + + /* Sometimes chip and programmer have more than one bus in common, + * and the limit is not exceeded on all buses. Tell the user. */ + if ((bitcount(commonbuses) > limitexceeded)) { + msg_pdbg("There is at least one interface available which could support the size of\n" + "the selected flash chip.\n"); + } + msg_cerr("This flash chip is too big for this programmer (--verbose/-V gives details).\n" + "Use --force/-f to override at your own risk.\n"); ret = 1; goto out_shutdown; } Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sat Aug 9 01:52:33 2014 (r1841) +++ trunk/flashrom.c Fri Aug 15 19:17:59 2014 (r1842) @@ -1009,9 +1009,13 @@ return 0; } -int check_max_decode(enum chipbustype buses, uint32_t size) +/* Returns the number of busses commonly supported by the current programmer and flash chip where the latter + * can not be completely accessed due to size/address limits of the programmer. */ +unsigned int count_max_decode_exceedings(const struct flashctx *flash) { - int limitexceeded = 0; + unsigned int limitexceeded = 0; + uint32_t size = flash->chip->total_size * 1024; + enum chipbustype buses = flash->mst->buses_supported & flash->chip->bustype; if ((buses & BUS_PARALLEL) && (max_rom_decode.parallel < size)) { limitexceeded++; @@ -1045,17 +1049,7 @@ "probe/read/erase/write may fail. ", size / 1024, max_rom_decode.spi / 1024, "SPI"); } - if (!limitexceeded) - return 0; - /* Sometimes chip and programmer have more than one bus in common, - * and the limit is not exceeded on all buses. Tell the user. - */ - if (bitcount(buses) > limitexceeded) - /* FIXME: This message is designed towards CLI users. */ - msg_pdbg("There is at least one common chip/programmer " - "interface which can support a chip of this size. " - "You can try --force at your own risk.\n"); - return 1; + return limitexceeded; } int probe_flash(struct registered_master *mst, int startchip, struct flashctx *flash, int force) @@ -1079,9 +1073,6 @@ continue; } - size = chip->total_size * 1024; - check_max_decode(buses_common, size); - /* Start filling in the dynamic data. */ flash->chip = calloc(1, sizeof(struct flashchip)); if (!flash->chip) { @@ -1091,6 +1082,7 @@ memcpy(flash->chip, chip, sizeof(struct flashchip)); flash->mst = mst; + size = flash->chip->total_size * 1024; base = flashbase ? flashbase : (0xffffffff - size + 1); flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sat Aug 9 01:52:33 2014 (r1841) +++ trunk/programmer.h Fri Aug 15 19:17:59 2014 (r1842) @@ -513,7 +513,7 @@ extern struct decode_sizes max_rom_decode; extern int programmer_may_write; extern unsigned long flashbase; -int check_max_decode(enum chipbustype buses, uint32_t size); +unsigned int count_max_decode_exceedings(const struct flashctx *flash); char *extract_programmer_param(const char *param_name); /* spi.c */

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Re: [flashrom] Chips requiring 12 volts on VPP for erase and write
by Stefan Tauner 14 Aug '14

14 Aug '14

On Thu, 14 Aug 2014 16:35:16 +0200 Daniele Forsi <dforsi(a)gmail.com> wrote: > Hello, > > I have an Intel P28F001 flash memory which flashrom knows as > INTEL_28F001T and lists with .tested = TEST_OK_PR > > I can confirm that reading works with -p internal but erasing and > writing don't work because according to its datasheet it needs 12 > volts on VPP (min 11.4 max 12.6) > > should this fact about 12V VPP recorded somewhere? > > the same for the B variant (which I haven't got) Yes, definitely. flashrom does not handle that yet explicitly. Maybe there are some board enables that enable that on single boards, I dont know... but there is nothing chip-specific AFAIK. I'd suggest a new feature flag for that, what do you think Carl-Daniel? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 1/3] Refine Flash Component descriptor handling.
by Stefan Tauner 14 Aug '14

14 Aug '14

On Tue, 12 Aug 2014 17:01:42 -0600 Marc Jones <marcj303(a)gmail.com> wrote: > I tested this branch on CC2: https://github.com/stefanct/flashrom/tree/intel > > See attached logs. > > > Flashrom views both chips as a single flash space. Yes, because the Intel chipsets do not allow the chip select pin to be controlled by software directly. One has to use hardware sequencing and there it does not make much sense to separate the two (although we know the boundaries and could do so), or are there use cases for that in the wild? Like using the first chip for everything but the BIOS region and the second chip for the BIOS region only...? > What is the correct > method for only updating a single descriptor area? There is only one descriptor (area), but I presume you are meaning a region. Using a layout file allows to write only a part, but there are patches that extend the usage to other actions as well. The second (i.e. write) log is more or less useless due to: "Warning: Chip content is identical to the requested image." Although it would be somewhat interesting... because the descriptor tells us that the flash chip has 256 B erase blocks, which is very improbable. Do you know which flash chips are mounted there? (The first one could be determined by forcing software sequencing via the -p internal:ich_spi_mode=swseq). I'd also like to see a -VV log (you could also use the -o <logfile> parameter ;) because with the flashrom prints more detailed information about the descriptor... and I think either the descriptor is wrong or they have changed something about the erase block sizes too... I need to verify that before committing. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] FAILED: Adlink NanoX-TC
by Stefan Tauner 14 Aug '14

14 Aug '14

On Thu, 14 Aug 2014 11:52:21 -0300 Ricardo Menzer <ricardomenzer(a)gmail.com> wrote: > (implicit question: is there a parameter to set SPI > frequency for the internal programmer?) Not for the Intel chipsets. But we use the lowest available frequency anyway (20 MHz), so it would probably not help you anyway. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] FAILED: Adlink NanoX-TC
by Carl-Daniel Hailfinger 14 Aug '14

14 Aug '14

Hi Ricardo, your log is weird in a way I've never seen before. Details below. Am 13.08.2014 21:24 schrieb Ricardo Menzer: > I have also found that if I probe the chip three times, it will work > only once. I mean, if I probe for the chip and it is found, the next > two probes will fail. The third will work, and the next two will fail > again, and so on. > I'm attaching the logs for three consecutive probes and also the > output of lspci -vvxxxnn. > > > > Ricardo Menzer > ricardomenzer(a)gmail.com > (32)8865-8805 > > > 2014-08-13 12:15 GMT-03:00 Ricardo Menzer <ricardomenzer(a)gmail.com>: >> > Hi guys! >> > I'm working with this COM Express module from Adlink >> > (http://www.adlinktech.com/PD/web/PD_detail.php?cKind=&pid=1001&seq=&id=&sid…) >> > and sometimes it doesn't recognize it's flash chip. >> > The following log happened after a failed probing. I then let the >> > board resting some time and tried to program again, with the results >> > bellow. >> > >> > This is a quite problematic module. Frequently it fails to probe the >> > flash chip. I have to reboot the system so it can see it again. It >> > also seems to corrupt the module flash even if I select to write to >> > the baseboard flash. I don't know if it's a flashrom issue or a >> > bios/hardware issue. >> > >> > I can safely reboot the system because we have a second flash on the baseboard. >> > >> > Right now I am using the module's flash to play with coreboot and i'm >> > maintaining a copy of the original BIOS on the baseboard. Changing the >> > role of both chips doesn't seem to change much, except for the >> > corruption issue (didn't made much tests yet, though). >> > >> > I have a Kontron module that I use in this same base board and it >> > works pretty well. >> > >> > >> > 14:55:12 root ~ # flashrom-0.9.7/flashrom -p internal -w >> > /media/sda1/coreboot.rom >> > flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) >> > flashrom is free software, get the source code at http://www.flashrom.org >> > >> > Calibrating delay loop... OK. >> > sh: dmidecode: command not found >> > dmidecode execution unsuccessful - continuing without DMI info >> > Warning: Can't autodetect MSC Q7-TCTC, DMI info unavailable. >> > Please supply the board vendor and model name with the -p >> > internal:mainboard=<vendor>:<model> option. >> > Found chipset "Intel Atom E6xx(T)/Tunnel Creek". Enabling flash write... OK. >> > Found SST flash chip "SST25VF016B" (2048 kB, SPI) at physical address >> > 0xffe00000. >> > Reading old flash chip contents... done. >> > Erasing and writing flash chip... timeout, ICH7_REG_SPIS=0x0001 >> > spi_block_erase_20 failed during command execution at address 0x0 >> > Reading current flash chip contents... Error: SCIP never cleared! >> > Can't read anymore! Aborting. >> > FAILED! >> > Uh oh. Erase/write failed. Checking if anything changed. >> > Error: SCIP never cleared! >> > Your flash chip is in an unknown state. >> > Get help on IRC at chat.freenode.net (channel #flashrom) or >> > mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! >> > ------------------------------------------------------------------------------- >> > DO NOT REBOOT OR POWEROFF! >> > 14:56:28 root ~ # flashrom-0.9.7/flashrom -p internal -w >> > /media/sda1/coreboot.rom >> > flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) >> > flashrom is free software, get the source code at http://www.flashrom.org >> > >> > Calibrating delay loop... OK. >> > sh: dmidecode: command not found >> > dmidecode execution unsuccessful - continuing without DMI info >> > Warning: Can't autodetect MSC Q7-TCTC, DMI info unavailable. >> > Please supply the board vendor and model name with the -p >> > internal:mainboard=<vendor>:<model> option. >> > Found chipset "Intel Atom E6xx(T)/Tunnel Creek". Enabling flash write... OK. >> > Error: SCIP never cleared! >> > Error: SCIP never cleared! > > flash1.log > flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) > flashrom is free software, get the source code at http://www.flashrom.org > > flashrom was built with libpci 3.2.0, GCC 4.8.2, little endian > Command line (3 args): /home/root/flashrom-0.9.7/flashrom -p internal -V > Calibrating delay loop... OS timer resolution is 4 usecs, 292M loops per second, 10 myus = 13 us, 100 myus = 101 us, 1000 myus = 1016 us, 10000 myus = 10057 us, 16 myus = 19 us, OK. > Initializing internal programmer > No coreboot table found. > Found Winbond Super I/O, id 0x52 > Please supply the board vendor and model name with the -p internal:mainboard=<vendor>:<model> option. > Found chipset "Intel Atom E6xx(T)/Tunnel Creek" with PCI ID 8086:8186. Enabling flash write... > BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled > BIOS Prefetch Enable: disabled, > Root Complex Register Block address = 0xfed1c000 > SPIBAR = 0xfed1c000 + 0x3020 > 0x00: 0x0004 (SPIS) > 0x02: 0x41c0 (SPIC) > 0x04: 0x00000000 (SPIA) > 0x08: 0x41414125 (SPID0) > 0x0c: 0x00000000 (SPID0+4) > 0x10: 0x00000000 (SPID1) > 0x14: 0x00000000 (SPID1+4) > 0x18: 0x00000000 (SPID2) > 0x1c: 0x00000000 (SPID2+4) > 0x20: 0x00000000 (SPID3) > 0x24: 0x00000000 (SPID3+4) > 0x28: 0x00000000 (SPID4) > 0x2c: 0x00000000 (SPID4+4) > 0x30: 0x00000000 (SPID5) > 0x34: 0x00000000 (SPID5+4) > 0x38: 0x00000000 (SPID6) > 0x3c: 0x00000000 (SPID6+4) > 0x40: 0x00000000 (SPID7) > 0x44: 0x00000000 (SPID7+4) > 0x50: 0x00000000 (BBAR) > 0x54: 0x5006 (PREOP) > 0x56: 0x063b (OPTYPE) > 0x58: 0x05200302 (OPMENU) > 0x5c: 0x0050019f (OPMENU+4) > 0x60: 0x00000000 (PBR0) > 0x64: 0x00000000 (PBR1) > 0x68: 0x00000000 (PBR2) > Programming OPCODES... done > SPI Read Configuration: prefetching disabled, caching enabled, OK. > The following protocols are supported: Parallel, LPC, FWH, SPI. > Probing for AMIC A25L05PT, 64 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0x41, id2 0xbf25 > Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0x25, id2 0x41bf > Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 > Probing for AMIC A25L10PU, 128 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0x41, id2 0xbf25 > Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0x25, id2 0x41bf > Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 > Probing for AMIC A25L40PT, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0x41, id2 0xbf25 > Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0x25, id2 0x41bf > Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 > Probing for AMIC A25L16PT, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0x41, id2 0xbf25 > Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0x25, id2 0x41bf > Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 > Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0x25, id2 0x41bf > Probing for AMIC A25L020, 256 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0x41, id2 0xbf25 As you can see, the chip continuously outputs 0xbf 0x25 0x41 in an endless loop. Normally, the SST SST25VF016B chip should always return the same ID response to probe_spi_rdid_generic: id1 0xbf, id2 0x2541. However, your chip seems to be cycling through shifted variants of that response. This indicates the chip never leaves ID (read JEDEC ID with command 0x9f) mode, probably because the CE# (chip enable) line is stuck on low. I've never seen that happen before, and it's certainly really weird. Do you have a multimeter to confirm that the CE# pin of the flash chip is indeed continuously at 0V? The Intel Tunnel Creek chipset may be at fault, or some other weird component is screwing things up. Two things I'd like you to try: - Compile latest flashrom from source, reboot and then write a log file with the new flashrom using -o logfile.txt . It needs to be the first run after the reboot or we'll get mostly random results. - Put an oscilloscope on the CE# line and check if it ever goes to high (3.3V) again after a flashrom run. Regards, Carl-Daniel

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Re: [flashrom] FAILED: Adlink NanoX-TC
by Stefan Tauner 14 Aug '14

14 Aug '14

On Wed, 13 Aug 2014 16:24:43 -0300 Ricardo Menzer <ricardomenzer(a)gmail.com> wrote: > I have also found that if I probe the chip three times, it will work > only once. I mean, if I probe for the chip and it is found, the next > two probes will fail. The third will work, and the next two will fail > again, and so on. > I'm attaching the logs for three consecutive probes and also the > output of lspci -vvxxxnn. Hi, the logs look really weird. Is it possible that the boot* SPI bus is shared with something else? The block diagram in the datasheet does not look very detailed. *IIRC that SoC has more than one SPI master. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Chips requiring 12 volts on VPP for erase and write
by Daniele Forsi 14 Aug '14

14 Aug '14

Hello, I have an Intel P28F001 flash memory which flashrom knows as INTEL_28F001T and lists with .tested = TEST_OK_PR I can confirm that reading works with -p internal but erasing and writing don't work because according to its datasheet it needs 12 volts on VPP (min 11.4 max 12.6) should this fact about 12V VPP recorded somewhere? the same for the B variant (which I haven't got) -- Daniele Forsi

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Re: [flashrom] FAILED: Adlink NanoX-TC
by Ricardo Menzer 13 Aug '14

13 Aug '14

I have also found that if I probe the chip three times, it will work only once. I mean, if I probe for the chip and it is found, the next two probes will fail. The third will work, and the next two will fail again, and so on. I'm attaching the logs for three consecutive probes and also the output of lspci -vvxxxnn. Ricardo Menzer ricardomenzer(a)gmail.com (32)8865-8805 2014-08-13 12:15 GMT-03:00 Ricardo Menzer <ricardomenzer(a)gmail.com>: > Hi guys! > I'm working with this COM Express module from Adlink > (http://www.adlinktech.com/PD/web/PD_detail.php?cKind=&pid=1001&seq=&id=&sid…) > and sometimes it doesn't recognize it's flash chip. > The following log happened after a failed probing. I then let the > board resting some time and tried to program again, with the results > bellow. > > This is a quite problematic module. Frequently it fails to probe the > flash chip. I have to reboot the system so it can see it again. It > also seems to corrupt the module flash even if I select to write to > the baseboard flash. I don't know if it's a flashrom issue or a > bios/hardware issue. > > I can safely reboot the system because we have a second flash on the baseboard. > > Right now I am using the module's flash to play with coreboot and i'm > maintaining a copy of the original BIOS on the baseboard. Changing the > role of both chips doesn't seem to change much, except for the > corruption issue (didn't made much tests yet, though). > > I have a Kontron module that I use in this same base board and it > works pretty well. > > > 14:55:12 root ~ # flashrom-0.9.7/flashrom -p internal -w > /media/sda1/coreboot.rom > flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > sh: dmidecode: command not found > dmidecode execution unsuccessful - continuing without DMI info > Warning: Can't autodetect MSC Q7-TCTC, DMI info unavailable. > Please supply the board vendor and model name with the -p > internal:mainboard=<vendor>:<model> option. > Found chipset "Intel Atom E6xx(T)/Tunnel Creek". Enabling flash write... OK. > Found SST flash chip "SST25VF016B" (2048 kB, SPI) at physical address > 0xffe00000. > Reading old flash chip contents... done. > Erasing and writing flash chip... timeout, ICH7_REG_SPIS=0x0001 > spi_block_erase_20 failed during command execution at address 0x0 > Reading current flash chip contents... Error: SCIP never cleared! > Can't read anymore! Aborting. > FAILED! > Uh oh. Erase/write failed. Checking if anything changed. > Error: SCIP never cleared! > Your flash chip is in an unknown state. > Get help on IRC at chat.freenode.net (channel #flashrom) or > mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! > ------------------------------------------------------------------------------- > DO NOT REBOOT OR POWEROFF! > 14:56:28 root ~ # flashrom-0.9.7/flashrom -p internal -w > /media/sda1/coreboot.rom > flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > sh: dmidecode: command not found > dmidecode execution unsuccessful - continuing without DMI info > Warning: Can't autodetect MSC Q7-TCTC, DMI info unavailable. > Please supply the board vendor and model name with the -p > internal:mainboard=<vendor>:<model> option. > Found chipset "Intel Atom E6xx(T)/Tunnel Creek". Enabling flash write... OK. > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > ^C > 14:58:09 root ~ # > > > Ricardo Menzer > ricardomenzer(a)gmail.com > (32)8865-8805

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FAILED: Adlink NanoX-TC
by Ricardo Menzer 13 Aug '14

13 Aug '14

Hi guys! I'm working with this COM Express module from Adlink (http://www.adlinktech.com/PD/web/PD_detail.php?cKind=&pid=1001&seq=&id=&sid…) and sometimes it doesn't recognize it's flash chip. The following log happened after a failed probing. I then let the board resting some time and tried to program again, with the results bellow. This is a quite problematic module. Frequently it fails to probe the flash chip. I have to reboot the system so it can see it again. It also seems to corrupt the module flash even if I select to write to the baseboard flash. I don't know if it's a flashrom issue or a bios/hardware issue. I can safely reboot the system because we have a second flash on the baseboard. Right now I am using the module's flash to play with coreboot and i'm maintaining a copy of the original BIOS on the baseboard. Changing the role of both chips doesn't seem to change much, except for the corruption issue (didn't made much tests yet, though). I have a Kontron module that I use in this same base board and it works pretty well. 14:55:12 root ~ # flashrom-0.9.7/flashrom -p internal -w /media/sda1/coreboot.rom flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. sh: dmidecode: command not found dmidecode execution unsuccessful - continuing without DMI info Warning: Can't autodetect MSC Q7-TCTC, DMI info unavailable. Please supply the board vendor and model name with the -p internal:mainboard=<vendor>:<model> option. Found chipset "Intel Atom E6xx(T)/Tunnel Creek". Enabling flash write... OK. Found SST flash chip "SST25VF016B" (2048 kB, SPI) at physical address 0xffe00000. Reading old flash chip contents... done. Erasing and writing flash chip... timeout, ICH7_REG_SPIS=0x0001 spi_block_erase_20 failed during command execution at address 0x0 Reading current flash chip contents... Error: SCIP never cleared! Can't read anymore! Aborting. FAILED! Uh oh. Erase/write failed. Checking if anything changed. Error: SCIP never cleared! Your flash chip is in an unknown state. Get help on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! 14:56:28 root ~ # flashrom-0.9.7/flashrom -p internal -w /media/sda1/coreboot.rom flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. sh: dmidecode: command not found dmidecode execution unsuccessful - continuing without DMI info Warning: Can't autodetect MSC Q7-TCTC, DMI info unavailable. Please supply the board vendor and model name with the -p internal:mainboard=<vendor>:<model> option. Found chipset "Intel Atom E6xx(T)/Tunnel Creek". Enabling flash write... OK. Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! ^C 14:58:09 root ~ # Ricardo Menzer ricardomenzer(a)gmail.com (32)8865-8805

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Re: [flashrom] Avoton patches for flashrom
by TR Reardon 13 Aug '14

13 Aug '14

One other additional thought regarding partial read/write: the current logic all will fail to erase&write all-zero newcontent. Instead, if the reader bails (read_all_first == 0), the copy_old_content() logic should still read old included regions. In other words, it should do the opposite of what it currently does. +Reardon On Tue, Aug 12, 2014 at 8:53 PM, TR Reardon <thomas_reardon(a)hotmail.com> wrote: > Ok, sorry for my misunderstanding. But even with that change, > copy_old_content() still gets called to copy the old non-readable > regions. Shouldn't copy_old_content() just set oldcontent and > newcontent to all-ones for excluded regions? > > The unselected regions are not automatically skipped by the "do I need > to erase and then update this block?" comparison logic in > need_erase(), correct? At least, when I run it, the excluded regions > are erased (rather than skipped), but then not written. > > Anyway, I made one minor adjustment to your layout patches for partial > read, else segfault: > > --- > diff --git a/flashrom.c b/flashrom.c > index 27d1736..e3639ae 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -1286,10 +1286,10 @@ int write_image_to_file(const unsigned char > *buf, unsigned long size, const char > l = get_next_included_romentry(0); > > while (l != NULL) { > - const char* name = (l->file[0] == '\0') ? l->name : l->file; > + const char* name = (l->file == NULL || l->file[0] == > '\0') ? l->name : l->file; > unsigned int len = l->end - l->start + 1; > msg_gdbg2("Writing \"%s\" to \"%s\" 0x%08x - 0x%08x (%uB)... ", > - l->name, l->file, l->start, l->end, len); > + l->name, name, l->start, l->end, len); > if (write_buf_to_file(buf + l->start, len, name) != 0) { > msg_gdbg2("failed.\n"); > return 1; > +Reardon > > > On Tue, Aug 12, 2014 at 4:33 PM, Stefan Tauner > <stefan.tauner(a)alumni.tuwien.ac.at> wrote: >> On Mon, 11 Aug 2014 19:14:53 -0400 >> TR Reardon <thomas_reardon(a)hotmail.com> wrote: >> >>> I'd like to start experimenting with partial-write support, now that >>> partial-read works well for me. But as of now doit() does a full read >>> before the write, which of course fails. Any updates that I could test? >>> Any useful log I can provide regarding successes? >>> >>> Note, I now have a buspirate so I can do full writes to recover, as needed >>> (this works successfully now, if slowly) >> >> As I wrote in my previous mail, (after applying the layout patches) you >> can disable the full read in doit() by setting read_all_first to 0. >> There are no further changes yet, because it does not make much sense >> until the proposed ones are merged... >> >> -- >> Kind regards/Mit freundlichen Grüßen, Stefan Tauner >>

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Re: [flashrom] flashrom Rangeley with WINDBOND25Q64
by Stefan Tauner 13 Aug '14

13 Aug '14

On Tue, 12 Aug 2014 15:54:20 -0600 Rich Futyma <rich.futyma(a)sanmina.com> wrote: > In addition to what Stefan described about ME descriptors, there is also > BIOS CNTL register, that if BIOS > enables it, you will not be able to write to flash using flashrom. Hello Rich, the above is true, but not relevant in this case, since the locking is disabled and writing enabled (according to the flashrom log). > CONFIDENTIALITY > This e-mail message and any attachments thereto, is intended only for use by the addressee(s) named herein and may contain legally privileged and/or confidential information. If you are not the intended recipient of this e-mail message, you are hereby notified that any dissemination, distribution or copying of this e-mail message, and any attachments thereto, is strictly prohibited. If you have received this e-mail message in error, please immediately notify the sender and permanently delete the original and any copies of this email and any prints thereof. > ABSENT AN EXPRESS STATEMENT TO THE CONTRARY HEREINABOVE, THIS E-MAIL IS NOT INTENDED AS A SUBSTITUTE FOR A WRITING. Notwithstanding the Uniform Electronic Transactions Act or the applicability of any other law of similar substance and effect, absent an express statement to the contrary hereinabove, this e-mail message its contents, and any attachments hereto are not intended to represent an offer or acceptance to enter into a contract and are not otherwise intended to bind the sender, Sanmina Corporation (or any of its subsidiaries), or any other person or entity. > You will be ridiculed sooner or later for using such a signature on public mailing lists ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Avoton patches for flashrom
by TR Reardon 12 Aug '14

12 Aug '14

Attempted write failed. Log attached. Haven't looked at further, but seems like partial reads work, but partial writes fail, due to early full-read before attempted partial-write. I use the term "partial" to mean a single region in the layout file. +Reardon

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