flashrom February 2015

flashrom@flashrom.org

30 participants
77 discussions

Re: [flashrom] [PATCH] Add support for SPARC (maybe).
by Carl-Daniel Hailfinger 10 Feb '15

10 Feb '15

On 07.02.2015 19:49, Stefan Tauner wrote: > Was implemented by SPARC newbies, does (cross-)compile but is not run-tested. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Thanks! Quoting wikipedia: > The endianness of the 32-bit SPARC V8 architecture is purely > big-endian. The 64-bit SPARC V9 architecture uses big-endian > instructions, but can access data in either big-endian or > little-endian byte order, chosen either at the application instruction > (load/store) level or at the memory page level (via an MMU setting). > The latter is often used for accessing data from inherently > little-endian devices, such as those on PCI buses. If that is true, we are totally screwed. How can we even begin to influence the instructions emitted by the compiler? And if the compiler emits bigendian instructions by default, can that be overridden via MMU setting? If yes, does Linux use the endianness manipulation via MMU for PCI devices, in which case we'd have to treat the architecture as littleendian from a flashrom POV? This is a nightmare. Does anyone on this mailing list have access to a real SPARC machine with PCI or PCIe slots running Linux? Regards, Carl-Daniel > Well, it is NOT compile-tested yet... because 64b gcc for SPARC > seems to be kind of broken... but I am working on it and it will be > before I commit it. > > Makefile | 2 +- > hwaccess.c | 24 ++++++++++++++++++++---- > hwaccess.h | 8 ++++++++ > platform.h | 5 ++++- > 4 files changed, 33 insertions(+), 6 deletions(-) > > diff --git a/Makefile b/Makefile > index bf79866..edd85cc 100644 > --- a/Makefile > +++ b/Makefile > @@ -318,7 +318,7 @@ endif > # below uses CC itself. > override ARCH := $(strip $(shell LC_ALL=C $(CC) $(CPPFLAGS) -E archtest.c 2>/dev/null | grep -v '^\#' | grep '"' | cut -f 2 -d'"')) > > -# PCI port I/O support is unimplemented on PPC/MIPS and unavailable on ARM. > +# PCI port I/O support is unimplemented on PPC/MIPS/SPARC and unavailable on ARM. > # Right now this means the drivers below only work on x86. > ifneq ($(ARCH), x86) > ifeq ($(CONFIG_NIC3COM), yes) > diff --git a/hwaccess.c b/hwaccess.c > index c90490b..0b7d7c3 100644 > --- a/hwaccess.c > +++ b/hwaccess.c > @@ -49,13 +49,29 @@ int io_fd; > */ > static inline void sync_primitive(void) > { > -/* This is needed only on PowerPC because... > - * - x86 uses uncached accesses which have a strongly ordered memory model and > - * - MIPS uses uncached accesses in mode 2 on /dev/mem which has also a strongly ordered memory model > - * - ARM uses a strongly ordered memory model for device memories. > +/* This is not needed for... > + * - x86: uses uncached accesses which have a strongly ordered memory model. > + * - MIPS: uses uncached accesses in mode 2 on /dev/mem which has also a strongly ordered memory model. > + * - ARM: uses a strongly ordered memory model for device memories. > + * > + * See also https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Docume… > */ > #if IS_PPC // cf. http://lxr.free-electrons.com/source/arch/powerpc/include/asm/barrier.h > asm("eieio" : : : "memory"); > +#elif IS_SPARC > +#ifdef defined(__sparc_v9__) || defined(__sparcv9) > + /* Sparc V9 CPUs support three different memory orderings that range from x86-like TSO to PowerPC-like > + * RMO. The modes can be switched at runtime thus to make sure we maintain the right order of access we > + * use the strongest hardware memory barriers that exist on Sparc V9. */ > + asm volatile ("membar #Sync" ::: "memory"); > +#elif defined(__sparc_v8__) || defined(__sparcv8) > + /* On SPARC V8 there is no RMO just PSO and that does not apply to I/O accesses... but if V8 code is run > + * on V9 CPUs it might apply... or not... we issue a write barrier anyway. That's the most suitable > + * operation in the V8 instruction set anyway. If you know better then please tell us. */ > + asm volatile ("stbar"); > +#else > + #error Unknown and/or unsupported SPARC instruction set version detected. > +#endif > #endif > } > > diff --git a/hwaccess.h b/hwaccess.h > index a4fd502..5378361 100644 > --- a/hwaccess.h > +++ b/hwaccess.h > @@ -89,6 +89,10 @@ > #define __FLASHROM_LITTLE_ENDIAN__ 1 > #endif > > +#elif IS_SPARC > +/* SPARC is big endian in general (but allows to access data in little endian too). */ > +#define __FLASHROM_BIG_ENDIAN__ 1 > + > #endif /* IS_? */ > > #if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) > @@ -357,6 +361,10 @@ int libpayload_wrmsr(int addr, msr_t msr); > > /* PCI port I/O is not yet implemented on MIPS. */ > > +#elif IS_SPARC > + > +/* PCI port I/O is not yet implemented on SPARC. */ > + > #elif IS_ARM > > /* Non memory mapped I/O is not supported on ARM. */ > diff --git a/platform.h b/platform.h > index f57fd12..9cde054 100644 > --- a/platform.h > +++ b/platform.h > @@ -45,9 +45,12 @@ > defined(__aarch64__) > #define __FLASHROM_ARCH__ "arm" > #define IS_ARM 1 > +#elif defined (__sparc__) || defined (__sparc) > + #define __FLASHROM_ARCH__ "sparc" > + #define IS_SPARC 1 > #endif > > -#if !(IS_X86 || IS_MIPS || IS_PPC || IS_ARM) > +#if !(IS_X86 || IS_MIPS || IS_PPC || IS_ARM || IS_SPARC) > #error Unknown architecture > #endif >

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[commit] r1882 - trunk
by repository service 10 Feb '15

10 Feb '15

Author: stefanct Date: Tue Feb 10 09:03:10 2015 New Revision: 1882 URL: http://flashrom.org/trac/flashrom/changeset/1882 Log: Add support for SPARC (maybe). Was implemented by SPARC newbies, does (cross-)compile but is not run-tested. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/Makefile trunk/hwaccess.c trunk/hwaccess.h trunk/platform.h Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sun Feb 8 22:58:10 2015 (r1881) +++ trunk/Makefile Tue Feb 10 09:03:10 2015 (r1882) @@ -328,7 +328,7 @@ # below uses CC itself. override ARCH := $(strip $(shell LC_ALL=C $(CC) $(CPPFLAGS) -E archtest.c 2>/dev/null | grep -v '^\#' | grep '"' | cut -f 2 -d'"')) -# PCI port I/O support is unimplemented on PPC/MIPS and unavailable on ARM. +# PCI port I/O support is unimplemented on PPC/MIPS/SPARC and unavailable on ARM. # Right now this means the drivers below only work on x86. ifneq ($(ARCH), x86) ifeq ($(CONFIG_NIC3COM), yes) Modified: trunk/hwaccess.c ============================================================================== --- trunk/hwaccess.c Sun Feb 8 22:58:10 2015 (r1881) +++ trunk/hwaccess.c Tue Feb 10 09:03:10 2015 (r1882) @@ -49,13 +49,29 @@ */ static inline void sync_primitive(void) { -/* This is needed only on PowerPC because... - * - x86 uses uncached accesses which have a strongly ordered memory model and - * - MIPS uses uncached accesses in mode 2 on /dev/mem which has also a strongly ordered memory model - * - ARM uses a strongly ordered memory model for device memories. +/* This is not needed for... + * - x86: uses uncached accesses which have a strongly ordered memory model. + * - MIPS: uses uncached accesses in mode 2 on /dev/mem which has also a strongly ordered memory model. + * - ARM: uses a strongly ordered memory model for device memories. + * + * See also https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Docume… */ #if IS_PPC // cf. http://lxr.free-electrons.com/source/arch/powerpc/include/asm/barrier.h asm("eieio" : : : "memory"); +#elif IS_SPARC +#if defined(__sparc_v9__) || defined(__sparcv9) + /* Sparc V9 CPUs support three different memory orderings that range from x86-like TSO to PowerPC-like + * RMO. The modes can be switched at runtime thus to make sure we maintain the right order of access we + * use the strongest hardware memory barriers that exist on Sparc V9. */ + asm volatile ("membar #Sync" ::: "memory"); +#elif defined(__sparc_v8__) || defined(__sparcv8) + /* On SPARC V8 there is no RMO just PSO and that does not apply to I/O accesses... but if V8 code is run + * on V9 CPUs it might apply... or not... we issue a write barrier anyway. That's the most suitable + * operation in the V8 instruction set anyway. If you know better then please tell us. */ + asm volatile ("stbar"); +#else + #error Unknown and/or unsupported SPARC instruction set version detected. +#endif #endif } Modified: trunk/hwaccess.h ============================================================================== --- trunk/hwaccess.h Sun Feb 8 22:58:10 2015 (r1881) +++ trunk/hwaccess.h Tue Feb 10 09:03:10 2015 (r1882) @@ -89,6 +89,10 @@ #define __FLASHROM_LITTLE_ENDIAN__ 1 #endif +#elif IS_SPARC +/* SPARC is big endian in general (but allows to access data in little endian too). */ +#define __FLASHROM_BIG_ENDIAN__ 1 + #endif /* IS_? */ #if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) @@ -357,6 +361,10 @@ /* PCI port I/O is not yet implemented on MIPS. */ +#elif IS_SPARC + +/* PCI port I/O is not yet implemented on SPARC. */ + #elif IS_ARM /* Non memory mapped I/O is not supported on ARM. */ Modified: trunk/platform.h ============================================================================== --- trunk/platform.h Sun Feb 8 22:58:10 2015 (r1881) +++ trunk/platform.h Tue Feb 10 09:03:10 2015 (r1882) @@ -45,9 +45,12 @@ defined(__aarch64__) #define __FLASHROM_ARCH__ "arm" #define IS_ARM 1 +#elif defined (__sparc__) || defined (__sparc) + #define __FLASHROM_ARCH__ "sparc" + #define IS_SPARC 1 #endif -#if !(IS_X86 || IS_MIPS || IS_PPC || IS_ARM) +#if !(IS_X86 || IS_MIPS || IS_PPC || IS_ARM || IS_SPARC) #error Unknown architecture #endif

1 0

new flash please add support of it
by Антон 10 Feb '15

10 Feb '15

PCT 25vfo32b

2 1

Unknown state report
by Kaloyan Mihaylov 09 Feb '15

09 Feb '15

flashrom.exe -p ft2232_spi:type=arm-usb-tiny-h - E flashrom v0.9.6.1-r1704 on Windows 6.1 (x86) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Winbond flash chip "W25Q64.V" (8192 kB, SPI) on ft2232_spi. Erasing and writing flash chip... FAILED at 0x00000000! Expected=0xff, Found=0xe 5, failed byte count from 0x00000000-0x00000fff: 0x9ca ERASE FAILED! Reading current flash chip contents... done. FAILED at 0x00008000! Expected=0xff , Found=0x85, failed byte count from 0x00008000-0x0000ffff: 0x4bb9 ERASE FAILED! Reading current flash chip contents... done. FAILED at 0x00008000! Expected=0xff , Found=0x85, failed byte count from 0x00000000-0x0000ffff: 0x4cb2 ERASE FAILED! Reading current flash chip contents... done. FAILED at 0x00050200! Expected=0xff , Found=0x00, failed byte count from 0x00000000-0x007fffff: 0x30e ERASE FAILED! Reading current flash chip contents... done. FAILED at 0x002e9800! Expected=0xff , Found=0x00, failed byte count from 0x00000000-0x007fffff: 0x700 ERASE FAILED! FAILED! Your flash chip is in an unknown state. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks!

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Re: [flashrom] Can ft2232_spi mode give access to GPIO bits?
by Stefan Tauner 09 Feb '15

09 Feb '15

On Thu, 29 Jan 2015 00:41:21 +0000 Phillip Vallejo <pvallejo(a)pacificbiosciences.com> wrote: > In using the FT2232H chip in MPSSE with SPI there are many GPIO bits on other pins. I have 2 questions about flashrom with ft2232_spi mode: > > 1. Is there access through flashrom to those GPIO bits? (if so, where is the description?) > > 2. If not, If I use a different program before flashrom to set GPIO bits, will flashrom reset GPIO bits to a particular state? Hi, the ft2232_spi.c driver sets some non-SPI GPIO pins for some programmer models that require it. That's what the cs_bits and pindir variables are for. Check out the comments at the declaration and around accesses of those variables. I guess your programmer needs something similar too? Can you please explain why? There is no way to apply these settings from the command line (so far), and I am not sure if that would be a good idea either... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[PATCH] Add programmer for the MSTAR I2C ISP protocol
by Alexandre Boeglin 09 Feb '15

09 Feb '15

Hi, Here is a patch, that provides support for the MSTAR ISP protocol. Basically, among other chips, MSTAR manufactures SoCs that equip TV sets and computer screens, and it seems that all of their products use the same in-system programming protocol. Basically, they use the DDC channel of VGA or DVI connectors, which is actually an I2C bus, to encapsulate SPI frames (the flash chip is connected to the SoC through an SPI bus). I wrote this patch since the screen I bought had a software bug, and the manufacturer only released a new firmware binary, but no tool or instructions on flashing it. More details can be found here: http://boeglin.org/blog/index.php?entry=Flashing-a-BenQ-Z-series-for-free(d… I only read code from Linux kernel archives published by Acer to figure out the protocol (for a touchscreen controller and a NFC chip, both by MSTAR, that shared the same ISP protocol), so I don't think there are any legal problems with it. Please let me know what you think about this patch, and whether you're interested in including it. Best regards, Alex -- Alexandre Boeglin email: alex (at) boeglin (dot) org jabber: alex (at) im (dot) boeglin (dot) org website: http://boeglin.org/

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Re: [flashrom] Add PICkit2 as an SPI programmer
by Stefan Tauner 09 Feb '15

09 Feb '15

On Fri, 26 Dec 2014 20:53:47 -0500 Justin Chevrier <jchevrier(a)gmail.com> wrote: > Hi Stefan, > > It seems you're correct. Signed off is below. > > Signed-off-by: Justin Chevrier <jchevrier(a)gmail.com> > Does the option to set voltage=0V really make sense? But since this is even possible... I would rather set it to 0V at shutdown. If that turns off the drivers completely it might be very useful while doing in-circuit programming because the programmer could remain attached even when the target is running. Why do we restrict the levels to 3 values although the API seems to allow to transmit a much finer resolution? What does the hardware actually do with these values? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 2

[commit] r1881 - trunk
by repository service 08 Feb '15

08 Feb '15

Author: stefanct Date: Sun Feb 8 22:58:10 2015 New Revision: 1881 URL: http://flashrom.org/trac/flashrom/changeset/1881 Log: Add support for the Microchip PICkit2 as an SPI programmer. This patch was inspired by the code in AVRDude (open source Atmel AVR programmer) to support the PICkit2 written by Doug Brown [1]. The Dediprog code in flashrom was used as the template for this code with some reference to the ft2232 code as well. [1] - https://github.com/steve-m/avrdude/blob/master/pickit2.c Signed-off-by: Justin Chevrier <jchevrier(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Added: trunk/pickit2_spi.c (contents, props changed) Modified: trunk/Makefile trunk/flashrom.8.tmpl trunk/flashrom.c trunk/programmer.h Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sun Feb 8 22:58:04 2015 (r1880) +++ trunk/Makefile Sun Feb 8 22:58:10 2015 (r1881) @@ -138,7 +138,7 @@ else override CONFIG_PONY_SPI = no endif -# Dediprog, USB-Blaster and FT2232 are not supported under DOS (missing USB support). +# Dediprog, USB-Blaster, PICkit2 and FT2232 are not supported under DOS (missing USB support). ifeq ($(CONFIG_DEDIPROG), yes) UNSUPPORTED_FEATURES += CONFIG_DEDIPROG=yes else @@ -154,6 +154,11 @@ else override CONFIG_USBBLASTER_SPI = no endif +ifeq ($(CONFIG_PICKIT2_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_PICKIT2_SPI=yes +else +override CONFIG_PICKIT2_SPI = no +endif endif # FIXME: Should we check for Cygwin/MSVC as well? @@ -277,7 +282,7 @@ else override CONFIG_PONY_SPI = no endif -# Dediprog, USB-Blaster and FT2232 are not supported with libpayload (missing libusb support) +# Dediprog, USB-Blaster, PICkit2 and FT2232 are not supported with libpayload (missing libusb support) ifeq ($(CONFIG_DEDIPROG), yes) UNSUPPORTED_FEATURES += CONFIG_DEDIPROG=yes else @@ -293,6 +298,11 @@ else override CONFIG_USBBLASTER_SPI = no endif +ifeq ($(CONFIG_PICKIT2_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_PICKIT2_SPI=yes +else +override CONFIG_PICKIT2_SPI = no +endif endif ifneq ($(TARGET_OS), Linux) @@ -429,6 +439,9 @@ # MSTAR DDC support needs more tests/reviews/cleanups. CONFIG_MSTARDDC_SPI ?= no +# Always enable PICkit2 SPI dongles for now. +CONFIG_PICKIT2_SPI ?= yes + # Always enable dummy tracing for now. CONFIG_DUMMY ?= yes @@ -614,6 +627,12 @@ PROGRAMMER_OBJS += usbblaster_spi.o endif +ifeq ($(CONFIG_PICKIT2_SPI), yes) +FEATURE_CFLAGS += -D'CONFIG_PICKIT2_SPI=1' +PROGRAMMER_OBJS += pickit2_spi.o +NEED_USB := yes +endif + ifeq ($(NEED_FTDI), yes) FTDILIBS := $(shell ([ -n "$(PKG_CONFIG_LIBDIR)" ] && export PKG_CONFIG_LIBDIR="$(PKG_CONFIG_LIBDIR)" ); pkg-config --libs libftdi || printf "%s" "-lftdi -lusb") FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "FT232H := yes" .features && printf "%s" "-D'HAVE_FT232H=1'") Modified: trunk/flashrom.8.tmpl ============================================================================== --- trunk/flashrom.8.tmpl Sun Feb 8 22:58:04 2015 (r1880) +++ trunk/flashrom.8.tmpl Sun Feb 8 22:58:10 2015 (r1881) @@ -229,6 +229,8 @@ .sp .BR "* mstarddc_spi" " (for SPI flash ROMs accessible through DDC in MSTAR-equipped displays)" .sp +.BR "* pickit2_spi" " (for SPI flash ROMs accessible via Microchip PICkit2)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER-SPECIFIC INFORMATION @@ -736,6 +738,34 @@ .BR "http://dangerousprototypes.com/docs/Practical_guide_to_Bus_Pirate_pull-up_r… " . Only the external supply voltage (Vpu) is supported as of this writing. .SS +.BR "pickit2_spi " programmer +An optional +.B voltage +parameter specifies the voltage the PICkit2 should use. The default unit is Volt if no unit is specified. +You can use +.BR mV ", " millivolt ", " V " or " Volt +as unit specifier. Syntax is +.sp +.B " flashrom \-p pickit2_spi:voltage=value" +.sp +where +.B value +can be +.BR 0V ", " 1.8V ", " 2.5V ", " 3.5V +or the equivalent in mV. +.sp +An optional +.B spispeed +parameter specifies the frequency of the SPI bus. Syntax is +.sp +.B " flashrom \-p pickit2_spi:spispeed=frequency" +.sp +where +.B frequency +can be +.BR 250k ", " 333k ", " 500k " or " 1M " +(in Hz). The default is a frequency of 1 MHz. +.SS .BR "dediprog " programmer An optional .B voltage @@ -992,7 +1022,7 @@ .B buspirate_spi needs userspace access to a serial port. .sp -.BR dediprog ", " ft2232_spi " and " usbblaster_spi +.BR dediprog ", " ft2232_spi " and " usbblaster_spi and " pickit2_spi need access to the USB device via libusb. .sp .B dummy @@ -1002,7 +1032,7 @@ .BR gfxnvidia ", " drkaiser ", " satasii ", " satamv ", " atahpt" and " atavia have to be run as superuser/root, and need additional raw access permission. .sp -.BR serprog ", " buspirate_spi ", " dediprog ", " usbblaster_spi " and " ft2232_spi +.BR serprog ", " buspirate_spi ", " dediprog ", " usbblaster_spi " and " ft2232_spi and " pickit2_spi can be run as normal user on most operating systems if appropriate device permissions are set. .sp Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sun Feb 8 22:58:04 2015 (r1880) +++ trunk/flashrom.c Sun Feb 8 22:58:10 2015 (r1881) @@ -366,6 +366,19 @@ }, #endif +#if CONFIG_PICKIT2_SPI == 1 + { + .name = "pickit2_spi", + .type = OTHER, + /* FIXME */ + .devs.note = "Microchip PICkit2\n", + .init = pickit2_spi_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + {0}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; Added: trunk/pickit2_spi.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/pickit2_spi.c Sun Feb 8 22:58:10 2015 (r1881) @@ -0,0 +1,505 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Carl-Daniel Hailfinger + * Copyright (C) 2014 Justin Chevrier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Connections are as follows: + * + * +------+-----+----------+ + * | SPI | Pin | PICkit2 | + * +------+-----+----------+ + * | /CS | 1 | VPP/MCLR | + * | VCC | 2 | VDD | + * | GND | 3 | GND | + * | MISO | 4 | PGD | + * | SCLK | 5 | PDC | + * | MOSI | 6 | AUX | + * +------+-----+----------+ + * + * Inspiration and some specifics of the interface came via the AVRDude + * PICkit2 code: https://github.com/steve-m/avrdude/blob/master/pickit2.c + */ + +#include "platform.h" + +#include <stdlib.h> +#include <stdio.h> +#include <string.h> +#include <limits.h> +#include <errno.h> + +#if IS_WINDOWS +#include <lusb0_usb.h> +#else +#include <usb.h> +#endif + +#include "flash.h" +#include "chipdrivers.h" +#include "programmer.h" +#include "spi.h" + +static usb_dev_handle *pickit2_handle; + +/* Default USB transaction timeout in ms */ +#define DFLT_TIMEOUT 10000 + +#define CMD_LENGTH 64 +#define ENDPOINT_OUT 0x01 +#define ENDPOINT_IN 0x81 + +#define PICKIT2_VID 0x04D8 +#define PICKIT2_PID 0x0033 + +#define CMD_GET_VERSION 0x76 +#define CMD_SET_VDD 0xA0 +#define CMD_SET_VPP 0xA1 +#define CMD_READ_VDD_VPP 0xA3 +#define CMD_EXEC_SCRIPT 0xA6 +#define CMD_CLR_DLOAD_BUFF 0xA7 +#define CMD_DOWNLOAD_DATA 0xA8 +#define CMD_CLR_ULOAD_BUFF 0xA9 +#define CMD_UPLOAD_DATA 0xAA +#define CMD_END_OF_BUFFER 0xAD + +#define SCR_SPI_READ_BUF 0xC5 +#define SCR_SPI_WRITE_BUF 0xC6 +#define SCR_SET_AUX 0xCF +#define SCR_LOOP 0xE9 +#define SCR_SET_ICSP_CLK_PERIOD 0xEA +#define SCR_SET_PINS 0xF3 +#define SCR_BUSY_LED_OFF 0xF4 +#define SCR_BUSY_LED_ON 0xF5 +#define SCR_MCLR_GND_OFF 0xF6 +#define SCR_MCLR_GND_ON 0xF7 +#define SCR_VPP_PWM_OFF 0xF8 +#define SCR_VPP_PWM_ON 0xF9 +#define SCR_VPP_OFF 0xFA +#define SCR_VPP_ON 0xFB +#define SCR_VDD_OFF 0xFE +#define SCR_VDD_ON 0xFF + +/* Copied from dediprog.c */ +/* Might be useful for other USB devices as well. static for now. */ +/* device parameter allows user to specify one device of multiple installed */ +static struct usb_device *get_device_by_vid_pid(uint16_t vid, uint16_t pid, unsigned int device) +{ + struct usb_bus *bus; + struct usb_device *dev; + + for (bus = usb_get_busses(); bus; bus = bus->next) + for (dev = bus->devices; dev; dev = dev->next) + if ((dev->descriptor.idVendor == vid) && + (dev->descriptor.idProduct == pid)) { + if (device == 0) + return dev; + device--; + } + + return NULL; +} + +static int pickit2_get_firmware_version(void) +{ + int ret; + uint8_t command[CMD_LENGTH] = {CMD_GET_VERSION, CMD_END_OF_BUFFER}; + + ret = usb_interrupt_write(pickit2_handle, ENDPOINT_OUT, (char *)command, CMD_LENGTH, DFLT_TIMEOUT); + ret = usb_interrupt_read(pickit2_handle, ENDPOINT_IN, (char *)command, CMD_LENGTH, DFLT_TIMEOUT); + + msg_pdbg("PICkit2 Firmware Version: %d.%d\n", (int)command[0], (int)command[1]); + if (ret != CMD_LENGTH) { + msg_perr("Command Get Firmware Version failed (%s)!\n", usb_strerror()); + return 1; + } + + return 0; +} + +static int pickit2_set_spi_voltage(int millivolt) +{ + double voltage_selector; + switch (millivolt) { + case 0: + /* Admittedly this one is an assumption. */ + voltage_selector = 0; + break; + case 1800: + voltage_selector = 1.8; + break; + case 2500: + voltage_selector = 2.5; + break; + case 3500: + voltage_selector = 3.5; + break; + default: + msg_perr("Unknown voltage %i mV! Aborting.\n", millivolt); + return 1; + } + msg_pdbg("Setting SPI voltage to %u.%03u V\n", millivolt / 1000, + millivolt % 1000); + + uint8_t command[CMD_LENGTH] = { + CMD_SET_VDD, + voltage_selector * 2048 + 672, + (voltage_selector * 2048 + 672) / 256, + voltage_selector * 36, + CMD_SET_VPP, + 0x40, + voltage_selector * 18.61, + voltage_selector * 13, + CMD_END_OF_BUFFER + }; + + int ret = usb_interrupt_write(pickit2_handle, ENDPOINT_OUT, (char *)command, CMD_LENGTH, DFLT_TIMEOUT); + + if (ret != CMD_LENGTH) { + msg_perr("Command Set Voltage failed (%s)!\n", usb_strerror()); + return 1; + } + + return 0; +} + +struct pickit2_spispeeds { + const char *const name; + const int speed; +}; + +static const struct pickit2_spispeeds spispeeds[] = { + { "1M", 0x1 }, + { "500k", 0x2 }, + { "333k", 0x3 }, + { "250k", 0x4 }, + { NULL, 0x0 }, +}; + +static int pickit2_set_spi_speed(unsigned int spispeed_idx) +{ + msg_pdbg("SPI speed is %sHz\n", spispeeds[spispeed_idx].name); + + uint8_t command[CMD_LENGTH] = { + CMD_EXEC_SCRIPT, + 2, + SCR_SET_ICSP_CLK_PERIOD, + spispeed_idx, + CMD_END_OF_BUFFER + }; + + int ret = usb_interrupt_write(pickit2_handle, ENDPOINT_OUT, (char *)command, CMD_LENGTH, DFLT_TIMEOUT); + + if (ret != CMD_LENGTH) { + msg_perr("Command Set SPI Speed failed (%s)!\n", usb_strerror()); + return 1; + } + + return 0; +} + +static int pickit2_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + + /* Maximum number of bytes per transaction (including command overhead) is 64. Lets play it safe + * and always assume the worst case scenario of 20 bytes command overhead. + */ + if (writecnt + readcnt + 20 > CMD_LENGTH) { + msg_perr("\nTotal packetsize (%i) is greater than 64 supported, aborting.\n", + writecnt + readcnt + 20); + return 1; + } + + uint8_t buf[CMD_LENGTH] = {CMD_DOWNLOAD_DATA, writecnt}; + int i = 2; + for (; i < writecnt + 2; i++) { + buf[i] = writearr[i - 2]; + } + + buf[i++] = CMD_CLR_ULOAD_BUFF; + buf[i++] = CMD_EXEC_SCRIPT; + + /* Determine script length based on number of bytes to be read or written */ + if (writecnt == 1 && readcnt == 1) + buf[i++] = 7; + else if (writecnt == 1 || readcnt == 1) + buf[i++] = 10; + else + buf[i++] = 13; + + /* Assert CS# */ + buf[i++] = SCR_VPP_OFF; + buf[i++] = SCR_MCLR_GND_ON; + + buf[i++] = SCR_SPI_WRITE_BUF; + + if (writecnt > 1) { + buf[i++] = SCR_LOOP; + buf[i++] = 1; /* Loop back one instruction */ + buf[i++] = writecnt - 1; /* Number of times to loop */ + } + + if (readcnt) + buf[i++] = SCR_SPI_READ_BUF; + + if (readcnt > 1) { + buf[i++] = SCR_LOOP; + buf[i++] = 1; /* Loop back one instruction */ + buf[i++] = readcnt - 1; /* Number of times to loop */ + } + + /* De-assert CS# */ + buf[i++] = SCR_MCLR_GND_OFF; + buf[i++] = SCR_VPP_PWM_ON; + buf[i++] = SCR_VPP_ON; + + buf[i++] = CMD_UPLOAD_DATA; + buf[i++] = CMD_END_OF_BUFFER; + + int ret = usb_interrupt_write(pickit2_handle, ENDPOINT_OUT, (char *)buf, CMD_LENGTH, DFLT_TIMEOUT); + + if (ret != CMD_LENGTH) { + msg_perr("Send SPI failed, expected %i, got %i %s!\n", writecnt, ret, usb_strerror()); + return 1; + } + + if (readcnt) { + ret = usb_interrupt_read(pickit2_handle, ENDPOINT_IN, (char *)buf, CMD_LENGTH, DFLT_TIMEOUT); + + if (ret != CMD_LENGTH) { + msg_perr("Receive SPI failed, expected %i, got %i %s!\n", readcnt, ret, usb_strerror()); + return 1; + } + + /* First byte indicates number of bytes transferred from upload buffer */ + if (buf[0] != readcnt) { + msg_perr("Unexpected number of bytes transferred, expected %i, got %i!\n", + readcnt, ret); + return 1; + } + + /* Actual data starts at byte number two */ + memcpy(readarr, &buf[1], readcnt); + } + + return 0; +} + +/* Copied from dediprog.c */ +/* Might be useful for other USB devices as well. static for now. */ +static int parse_voltage(char *voltage) +{ + char *tmp = NULL; + int i; + int millivolt = 0, fraction = 0; + + if (!voltage || !strlen(voltage)) { + msg_perr("Empty voltage= specified.\n"); + return -1; + } + millivolt = (int)strtol(voltage, &tmp, 0); + voltage = tmp; + /* Handle "," and "." as decimal point. Everything after it is assumed + * to be in decimal notation. + */ + if ((*voltage == '.') || (*voltage == ',')) { + voltage++; + for (i = 0; i < 3; i++) { + fraction *= 10; + /* Don't advance if the current character is invalid, + * but continue multiplying. + */ + if ((*voltage < '0') || (*voltage > '9')) + continue; + fraction += *voltage - '0'; + voltage++; + } + /* Throw away remaining digits. */ + voltage += strspn(voltage, "0123456789"); + } + /* The remaining string must be empty or "mV" or "V". */ + tolower_string(voltage); + + /* No unit or "V". */ + if ((*voltage == '\0') || !strncmp(voltage, "v", 1)) { + millivolt *= 1000; + millivolt += fraction; + } else if (!strncmp(voltage, "mv", 2) || + !strncmp(voltage, "millivolt", 9)) { + /* No adjustment. fraction is discarded. */ + } else { + /* Garbage at the end of the string. */ + msg_perr("Garbage voltage= specified.\n"); + return -1; + } + return millivolt; +} + +static const struct spi_master spi_master_pickit2 = { + .type = SPI_CONTROLLER_PICKIT2, + .max_data_read = 40, + .max_data_write = 40, + .command = pickit2_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, +}; + +static int pickit2_shutdown(void *data) +{ + /* Set all pins to float and turn voltages off */ + uint8_t command[CMD_LENGTH] = { + CMD_EXEC_SCRIPT, + 8, + SCR_SET_PINS, + 3, /* Bit-0=1(PDC In), Bit-1=1(PGD In), Bit-2=0(PDC LL), Bit-3=0(PGD LL) */ + SCR_SET_AUX, + 1, /* Bit-0=1(Aux In), Bit-1=0(Aux LL) */ + SCR_MCLR_GND_OFF, + SCR_VPP_OFF, + SCR_VDD_OFF, + SCR_BUSY_LED_OFF, + CMD_END_OF_BUFFER + }; + + int ret = usb_interrupt_write(pickit2_handle, ENDPOINT_OUT, (char *)command, CMD_LENGTH, DFLT_TIMEOUT); + + if (ret != CMD_LENGTH) { + msg_perr("Command Shutdown failed (%s)!\n", usb_strerror()); + ret = 1; + } + if (usb_release_interface(pickit2_handle, 0) != 0) { + msg_perr("Could not release USB interface!\n"); + ret = 1; + } + if (usb_close(pickit2_handle) != 0) { + msg_perr("Could not close USB device!\n"); + ret = 1; + } + return ret; +} + +int pickit2_spi_init(void) +{ + unsigned int usedevice = 0; // FIXME: allow to select one of multiple devices + + uint8_t buf[CMD_LENGTH] = { + CMD_EXEC_SCRIPT, + 10, /* Script length */ + SCR_SET_PINS, + 2, /* Bit-0=0(PDC Out), Bit-1=1(PGD In), Bit-2=0(PDC LL), Bit-3=0(PGD LL) */ + SCR_SET_AUX, + 0, /* Bit-0=0(Aux Out), Bit-1=0(Aux LL) */ + SCR_VDD_ON, + SCR_MCLR_GND_OFF, /* Let CS# float */ + SCR_VPP_PWM_ON, + SCR_VPP_ON, /* Pull CS# high */ + SCR_BUSY_LED_ON, + CMD_CLR_DLOAD_BUFF, + CMD_CLR_ULOAD_BUFF, + CMD_END_OF_BUFFER + }; + + + int spispeed_idx = 0; + char *spispeed = extract_programmer_param("spispeed"); + if (spispeed != NULL) { + int i = 0; + for (; spispeeds[i].name; i++) { + if (strcasecmp(spispeeds[i].name, spispeed) == 0) { + spispeed_idx = i; + break; + } + } + if (spispeeds[i].name == NULL) { + msg_perr("Error: Invalid 'spispeed' value.\n"); + free(spispeed); + return 1; + } + free(spispeed); + } + + int millivolt = 3500; + char *voltage = extract_programmer_param("voltage"); + if (voltage != NULL) { + millivolt = parse_voltage(voltage); + free(voltage); + if (millivolt < 0) + return 1; + } + + /* Here comes the USB stuff */ + usb_init(); + (void)usb_find_busses(); + (void)usb_find_devices(); + struct usb_device *dev = get_device_by_vid_pid(PICKIT2_VID, PICKIT2_PID, usedevice); + if (dev == NULL) { + msg_perr("Could not find a PICkit2 on USB!\n"); + return 1; + } + msg_pdbg("Found USB device (%04x:%04x).\n", dev->descriptor.idVendor, dev->descriptor.idProduct); + + pickit2_handle = usb_open(dev); + int ret = usb_set_configuration(pickit2_handle, 1); + if (ret != 0) { + msg_perr("Could not set USB device configuration: %i %s\n", ret, usb_strerror()); + if (usb_close(pickit2_handle) != 0) + msg_perr("Could not close USB device!\n"); + return 1; + } + ret = usb_claim_interface(pickit2_handle, 0); + if (ret != 0) { + msg_perr("Could not claim USB device interface %i: %i %s\n", 0, ret, usb_strerror()); + if (usb_close(pickit2_handle) != 0) + msg_perr("Could not close USB device!\n"); + return 1; + } + + if (register_shutdown(pickit2_shutdown, NULL) != 0) { + return 1; + } + + if (pickit2_get_firmware_version()) { + return 1; + } + + /* Command Set SPI Speed */ + if (pickit2_set_spi_speed(spispeed_idx)) { + return 1; + } + + /* Command Set SPI Voltage */ + msg_pdbg("Setting voltage to %i mV.\n", millivolt); + if (pickit2_set_spi_voltage(millivolt) != 0) { + return 1; + } + + /* Perform basic setup. + * Configure pin directions and logic levels, turn Vdd on, turn busy LED on and clear buffers. */ + ret = usb_interrupt_write(pickit2_handle, ENDPOINT_OUT, (char *)buf, CMD_LENGTH, DFLT_TIMEOUT); + if (ret != CMD_LENGTH) { + msg_perr("Command Setup failed (%s)!\n", usb_strerror()); + return 1; + } + + register_spi_master(&spi_master_pickit2); + + return 0; +} Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sun Feb 8 22:58:04 2015 (r1880) +++ trunk/programmer.h Sun Feb 8 22:58:10 2015 (r1881) @@ -102,6 +102,9 @@ #if CONFIG_MSTARDDC_SPI == 1 PROGRAMMER_MSTARDDC_SPI, #endif +#if CONFIG_PICKIT2_SPI == 1 + PROGRAMMER_PICKIT2_SPI, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -480,6 +483,11 @@ int mstarddc_spi_init(void); #endif +/* pickit2_spi.c */ +#if CONFIG_PICKIT2_SPI == 1 +int pickit2_spi_init(void); +#endif + /* rayer_spi.c */ #if CONFIG_RAYER_SPI == 1 int rayer_spi_init(void); @@ -564,6 +572,9 @@ #if CONFIG_MSTARDDC_SPI == 1 SPI_CONTROLLER_MSTARDDC, #endif +#if CONFIG_PICKIT2_SPI == 1 + SPI_CONTROLLER_PICKIT2, +#endif }; #define MAX_DATA_UNSPECIFIED 0

1 0

[commit] r1880 - trunk
by repository service 08 Feb '15

08 Feb '15

Author: stefanct Date: Sun Feb 8 22:58:04 2015 New Revision: 1880 URL: http://flashrom.org/trac/flashrom/changeset/1880 Log: Refine version check of libpci function pci_get_dev. The way more elegant check for the header fails unfortunately on CentOS 4.9 because PCI_LIB_VERSION is not defined at all although the domain parameter is present. This patch jumps through the hoops via an additional check in the Makefile to determine if the function accepts 5 parameters (new version) or not (old version). Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/Makefile trunk/board_enable.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sun Feb 8 22:57:52 2015 (r1879) +++ trunk/Makefile Sun Feb 8 22:58:04 2015 (r1880) @@ -713,6 +713,8 @@ ifeq ($(NEED_PCI), yes) CHECK_LIBPCI = yes FEATURE_CFLAGS += -D'NEED_PCI=1' +FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "OLD_PCI_GET_DEV := yes" .libdeps && printf "%s" "-D'OLD_PCI_GET_DEV=1'") + PROGRAMMER_OBJS += pcidev.o physmap.o hwaccess.o ifeq ($(TARGET_OS), NetBSD) # The libpci we want is called libpciutils on NetBSD and needs NetBSD libpci. @@ -842,6 +844,27 @@ endef export LIBPCI_TEST +define PCI_GET_DEV_TEST +/* Avoid a failing test due to libpci header symbol shadowing breakage */ +#define index shadow_workaround_index +#if !defined __NetBSD__ +#include <pci/pci.h> +#else +#include <pciutils/pci.h> +#endif +struct pci_access *pacc; +struct pci_dev *dev = {0}; +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + pacc = pci_alloc(); + dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1); + return 0; +} +endef +export PCI_GET_DEV_TEST + define LIBUSB0_TEST #include "platform.h" #if IS_WINDOWS @@ -869,6 +892,11 @@ echo "Please install libpci headers (package pciutils-devel)."; \ echo "See README for more information."; echo; \ rm -f .test.c .test.o; exit 1) + @printf "Checking version of pci_get_dev... " + @echo "$$PCI_GET_DEV_TEST" > .test.c + @$(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o >/dev/null 2>&1 && \ + ( echo "new version (including PCI domain parameter)."; echo "OLD_PCI_GET_DEV := no" >> .libdeps ) || \ + ( echo "old version (without PCI domain parameter)."; echo "OLD_PCI_GET_DEV := yes" >> .libdeps ) @printf "Checking if libpci is present and sufficient... " @$(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(PCILIBS) >/dev/null && \ echo "yes." || ( echo "no."; \ Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sun Feb 8 22:57:52 2015 (r1879) +++ trunk/board_enable.c Sun Feb 8 22:58:04 2015 (r1880) @@ -1047,7 +1047,7 @@ return -1; } -#if PCI_LIB_VERSION >= 0x020200 +#if !defined(OLD_PCI_GET_DEV) dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1); #else /* pciutils/libpci before version 2.2 is too old to support

1 0

[commit] r1879 - trunk
by repository service 08 Feb '15

08 Feb '15

Author: stefanct Date: Sun Feb 8 22:57:52 2015 New Revision: 1879 URL: http://flashrom.org/trac/flashrom/changeset/1879 Log: Add a bunch of new/tested stuff and various small changes 22. Tested mainboards: OK: - AOpen UK79G-1394 (used in EZ18 barebones) Reported by Lawrence Gough - ASUS M4N78 SE Reported by Dima Veselov - ASUS P5LD2-VM Mark board enable as tested (reported by Dima Veselov) - GIGABYTE GA-970A-UD3P (rev. 2.0) Reported by trucmar on IRC - GIGABYTE GA-990FXA-UD3 (rev. 4.0) Reported by ROKO__ on IRC - GIGABYTE GA-H77-DS3H (rev. 1.1) Reported by Evgeniy Edigarev - GIGABYTE GA-P55-USB3 (rev. 2.0) Reported by Måns Thörnqvist - MSI MS-7817 (H81M-E33) Reported by Igor Kolker Chipsets: - Marked Intel Bay Trail (0x0f1c) as tested OK Reported by Antonio Ospite - Refine Intel IDs * Add IDs for Braswell * Add IDs for 9 Series PCHs (e.g. H97, Z97) * Rename Wellsburg devices slightly Flash chips: - Atmel AT25DF041A to PREW (+PREW) Reported by Tai-hwa Liang - Atmel AT26DF161 to PREW (+EW) Reported by Steve Shenton - Atmel AT45DB011D to PREW (+PREW) Reported by The Raven - Atmel AT45DB642D to PREW (+PREW) Reported by Mahesh Mokal - Eon EN25F32 to PREW (+PREW) Reported by Arman Khodabande - Eon EN25F40 to PREW (+REW) Reported by Jerrad Pierce - Eon EN25QH16 to PREW (+EW) Reported by Ben Johnson - GigaDevice GD25Q20(B) to PREW (+PREW) Reported by Gilles Aurejac - Macronix MX25U6435E/F to PR (+PR) Reported by Matt Taggart - PMC Pm25LV512(A) to PREW (+PREW) Reported by The Raven - SST SST39VF020 to PREW (+PREW) Reported by Urja Rannikko - Winbond W25Q40.V to PREW (+EW) Reported by Torben Nielsen - Add E variants of MX25Lx006 (MX25L2006E, MX25L4006E, MX25L8006E). - Add MX25L6465E variant. - There was never a MX25L12805 AFAICT. - Split MX25L12805 from models with the same ID but an additional 32 kB eraser: MX25L12835F/MX25L12845E/MX25L12865E. - Add a bunch of ST parallel NOR flash chip IDs. Miscellaneous: - Whitelist ThinkPad X200. - Constify master parameter of register_master(). - Remove FEATURE_BYTEWRITES because it was never used at all. - Refine hwseq messages and make them less prominent. - Fix the yet unused PRIxCHIPADDR format string thingy. - Fix copy&paste error in spi_prettyprint_status_register_bp(). Spotted by Pablo Cases. - Add an additional SMBus controller revision to identify another Yangtze model. Thanks to Dan Christensen for reporting this issue. - dediprog: add missing include for stdlib.h. This fixes (at least) building on FreeBSD and DragonflyBSD with gcc. - Remove references to struct pci_filter from programmer.h. It is only needed in internal.c where it has a complete type. Having it in programmer.h provokes a warning by some old versions of gcc. - Tiny other stuff. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/Makefile trunk/board_enable.c trunk/chipset_enable.c trunk/dediprog.c trunk/flash.h trunk/flashchips.c trunk/flashchips.h trunk/flashrom.8.tmpl trunk/flashrom.c trunk/ichspi.c trunk/nicintel_eeprom.c trunk/print.c trunk/programmer.c trunk/programmer.h trunk/sb600spi.c trunk/spi25_statusreg.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Tue Jan 27 19:07:50 2015 (r1878) +++ trunk/Makefile Sun Feb 8 22:57:52 2015 (r1879) @@ -138,7 +138,7 @@ else override CONFIG_PONY_SPI = no endif -# Dediprog and FT2232 are not supported under DOS (missing USB support). +# Dediprog, USB-Blaster and FT2232 are not supported under DOS (missing USB support). ifeq ($(CONFIG_DEDIPROG), yes) UNSUPPORTED_FEATURES += CONFIG_DEDIPROG=yes else @@ -277,7 +277,7 @@ else override CONFIG_PONY_SPI = no endif -# Dediprog and FT2232 are not supported with libpayload (missing libusb support) +# Dediprog, USB-Blaster and FT2232 are not supported with libpayload (missing libusb support) ifeq ($(CONFIG_DEDIPROG), yes) UNSUPPORTED_FEATURES += CONFIG_DEDIPROG=yes else @@ -914,6 +914,7 @@ endif define FTDI_TEST +#include <stdlib.h> #include <ftdi.h> struct ftdi_context *ftdic = NULL; int main(int argc, char **argv) Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Tue Jan 27 19:07:50 2015 (r1878) +++ trunk/board_enable.c Sun Feb 8 22:57:52 2015 (r1879) @@ -2377,7 +2377,7 @@ {0x8086, 0x27b8, 0x1043, 0x2a22, 0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$", NULL, NULL, P3, "ASUS", "P5LP-LE (Epson OEM)", 0, OK, intel_ich_gpio34_raise}, {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b0, 0x1043, 0x8179, "^P5LD2-MQ$", NULL, NULL, P3, "ASUS", "P5LD2-MQ", 0, OK, intel_ich_gpio16_raise}, - {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2-VM$", NULL, NULL, P3, "ASUS", "P5LD2-VM", 0, NT, intel_ich_gpio16_raise}, + {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2-VM$", NULL, NULL, P3, "ASUS", "P5LD2-VM", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x27b0, 0x1043, 0x8179, 0x8086, 0x2770, 0x1043, 0x817a, "^P5LD2-VM DH$", NULL, NULL, P3, "ASUS", "P5LD2-VM DH", 0, OK, intel_ich_gpio16_raise}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x829E, "^P5N-D$", NULL, NULL, P3, "ASUS", "P5N-D", 0, OK, it8718f_gpio63_raise}, @@ -2427,6 +2427,7 @@ {0x8086, 0x1E22, 0x17AA, 0x21F6, 0x8086, 0x1E55, 0x17AA, 0x21F6, "^ThinkPad T530", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T530", 0, OK, p2_whitelist_laptop}, {0x8086, 0x27a0, 0x17aa, 0x2015, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60", 0, OK, p2_whitelist_laptop}, {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60(s)", 0, OK, p2_whitelist_laptop}, + {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad X200$", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X200", 0, OK, p2_whitelist_laptop}, {0x8086, 0x3B07, 0x17AA, 0x2166, 0x8086, 0x3B30, 0x17AA, 0x2167, "^Lenovo X201", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X201", 0, OK, p2_whitelist_laptop}, {0x8086, 0x1E22, 0x17AA, 0x21FA, 0x8086, 0x1E55, 0x17AA, 0x21FA, "^ThinkPad X230", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X230", 0, OK, p2_whitelist_laptop}, {0x8086, 0x27A0, 0x17AA, 0x2017, 0x8086, 0x27B9, 0x17AA, 0x2009, "^ThinkPad X60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X60(s)", 0, OK, p2_whitelist_laptop}, Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Tue Jan 27 19:07:50 2015 (r1878) +++ trunk/chipset_enable.c Sun Feb 8 22:57:52 2015 (r1879) @@ -451,7 +451,7 @@ fwh_idsel_old = mmio_readl(ilb + fwh_sel1); rmmio_writel(fwh_idsel, ilb + fwh_sel1); } else { - fwh_idsel_old = pci_read_long(dev, fwh_sel1) << 16; + fwh_idsel_old = (uint64_t)pci_read_long(dev, fwh_sel1) << 16; rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff); if (fwh_sel2 > 0) { fwh_idsel_old |= pci_read_word(dev, fwh_sel2); @@ -1593,7 +1593,7 @@ {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, {0x17f3, 0x6030, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610}, {0x8086, 0x0c60, NT, "Intel", "S12x0", enable_flash_s12x0}, - {0x8086, 0x0f1c, NT, "Intel", "Bay Trail", enable_flash_silvermont}, + {0x8086, 0x0f1c, OK, "Intel", "Bay Trail", enable_flash_silvermont}, {0x8086, 0x0f1d, NT, "Intel", "Bay Trail", enable_flash_silvermont}, {0x8086, 0x0f1e, NT, "Intel", "Bay Trail", enable_flash_silvermont}, {0x8086, 0x0f1f, NT, "Intel", "Bay Trail", enable_flash_silvermont}, @@ -1635,6 +1635,7 @@ {0x8086, 0x1f39, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, {0x8086, 0x1f3a, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, {0x8086, 0x1f3b, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, + {0x8086, 0x229c, NT, "Intel", "Braswell", enable_flash_silvermont}, {0x8086, 0x2310, NT, "Intel", "DH89xxCC (Cave Creek)", enable_flash_pch7}, {0x8086, 0x2390, NT, "Intel", "Coleto Creek", enable_flash_pch7}, {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich0}, @@ -1730,42 +1731,47 @@ {0x8086, 0x8c5d, NT, "Intel", "Lynx Point", enable_flash_pch8}, {0x8086, 0x8c5e, NT, "Intel", "Lynx Point", enable_flash_pch8}, {0x8086, 0x8c5f, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8cc1, NT, "Intel", "9 Series", enable_flash_pch9}, + {0x8086, 0x8cc2, NT, "Intel", "9 Series Engineering Sample", enable_flash_pch9}, + {0x8086, 0x8cc3, NT, "Intel", "9 Series", enable_flash_pch9}, + {0x8086, 0x8cc4, NT, "Intel", "Z97", enable_flash_pch9}, + {0x8086, 0x8cc6, NT, "Intel", "H97", enable_flash_pch9}, + {0x8086, 0x8d40, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d41, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d42, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d43, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d44, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d45, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d46, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d47, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d48, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d49, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d4a, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d4b, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d4c, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d4d, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d4e, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d4f, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d50, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d51, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d52, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d53, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d54, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d55, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d56, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d57, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d58, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d59, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d5a, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d5b, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d5c, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d5d, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d5e, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, + {0x8086, 0x8d5f, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, {0x8086, 0x9c41, NT, "Intel", "Lynx Point LP Eng. Sample", enable_flash_pch8_lp}, {0x8086, 0x9c43, NT, "Intel", "Lynx Point LP Premium", enable_flash_pch8_lp}, {0x8086, 0x9c45, NT, "Intel", "Lynx Point LP Mainstream", enable_flash_pch8_lp}, {0x8086, 0x9c47, NT, "Intel", "Lynx Point LP Value", enable_flash_pch8_lp}, - {0x8086, 0x8d40, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d41, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d42, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d43, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d44, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d45, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d46, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d47, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d48, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d49, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d4a, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d4b, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d4c, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d4d, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d4e, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d4f, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d50, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d51, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d52, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d53, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d54, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d55, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d56, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d57, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d58, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d59, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d5a, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d5b, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d5c, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d5d, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d5e, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d5f, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, {0x8086, 0x9cc1, NT, "Intel", "Haswell U Sample", enable_flash_pch9}, {0x8086, 0x9cc2, NT, "Intel", "Broadwell U Sample", enable_flash_pch9}, {0x8086, 0x9cc3, NT, "Intel", "Broadwell U Premium", enable_flash_pch9}, @@ -1807,10 +1813,10 @@ msg_pdbg(" with PCI ID %04x:%04x", chipset_enables[i].vendor_id, chipset_enables[i].device_id); - msg_pinfo(". "); + msg_pinfo(".\n"); if (chipset_enables[i].status == NT) { - msg_pinfo("\nThis chipset is marked as untested. If " + msg_pinfo("This chipset is marked as untested. If " "you are using an up-to-date version\nof " "flashrom *and* were (not) able to " "successfully update your firmware with it,\n" Modified: trunk/dediprog.c ============================================================================== --- trunk/dediprog.c Tue Jan 27 19:07:50 2015 (r1878) +++ trunk/dediprog.c Sun Feb 8 22:57:52 2015 (r1879) @@ -19,6 +19,7 @@ #include "platform.h" +#include <stdlib.h> #include <stdio.h> #include <string.h> #include <limits.h> Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Tue Jan 27 19:07:50 2015 (r1878) +++ trunk/flash.h Sun Feb 8 22:57:52 2015 (r1879) @@ -107,7 +107,6 @@ /* Feature bits used for non-SPI only */ #define FEATURE_REGISTERMAP (1 << 0) -#define FEATURE_BYTEWRITES (1 << 1) #define FEATURE_LONG_RESET (0 << 4) #define FEATURE_SHORT_RESET (1 << 4) #define FEATURE_EITHER_RESET FEATURE_LONG_RESET Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Tue Jan 27 19:07:50 2015 (r1878) +++ trunk/flashchips.c Sun Feb 8 22:57:52 2015 (r1879) @@ -1276,7 +1276,7 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enhance (sic!) */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, @@ -1449,7 +1449,7 @@ .total_size = 512, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -2173,7 +2173,7 @@ .total_size = 2048, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -2435,7 +2435,7 @@ /* does not support EWSR nor WREN and has no writable status register bits whatsoever */ /* OTP: 128B total, 64B pre-programmed; read 0x77; write 0x9B */ .feature_bits = FEATURE_OTP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_at45db, .probe_timing = TIMING_ZERO, .block_erasers = @@ -2772,7 +2772,7 @@ /* does not support EWSR nor WREN and has no writable status register bits whatsoever */ /* OTP: 128B total, 64B pre-programmed; read 0x77; write 0x9B */ .feature_bits = FEATURE_OTP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_at45db, .probe_timing = TIMING_ZERO, .block_erasers = @@ -4220,7 +4220,7 @@ .total_size = 512, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PROBE, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -4325,7 +4325,7 @@ .total_size = 4096, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -4619,7 +4619,7 @@ /* OTP: 512B total; enter 0x3A */ /* QPI enable 0x38, disable 0xFF */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -5583,7 +5583,7 @@ .total_size = 256, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -6727,7 +6727,7 @@ { .vendor = "Macronix", - .name = "MX25L2005(C)", + .name = "MX25L2005(C)/MX25L2006E", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L2005, @@ -6765,7 +6765,7 @@ { .vendor = "Macronix", - .name = "MX25L4005(A/C)", + .name = "MX25L4005(A/C)/MX25L4006E", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L4005, @@ -6803,7 +6803,7 @@ { .vendor = "Macronix", - .name = "MX25L8005/MX25V8005", + .name = "MX25L8005/MX25L8006E/MX25V8005", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L8005, @@ -6907,7 +6907,7 @@ }, }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* MX25L1605A bp2 only */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, @@ -6942,7 +6942,7 @@ }, }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6: Continuously Program (CP) mode */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ .voltage = {2700, 3600}, @@ -6978,7 +6978,7 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, @@ -7014,7 +7014,7 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, @@ -7085,7 +7085,7 @@ }, }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6: CP mode */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and dual I/O supported */ .voltage = {2700, 3600}, @@ -7124,7 +7124,7 @@ }, }, .printlock = spi_prettyprint_status_register_bp3_srwd, - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and dual I/O supported */ .voltage = {2700, 3600}, @@ -7163,7 +7163,7 @@ }, }, .printlock = spi_prettyprint_status_register_bp3_srwd, - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and dual I/O supported */ .voltage = {2700, 3600}, @@ -7199,7 +7199,7 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, @@ -7235,7 +7235,7 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 has different meanings */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, @@ -7271,7 +7271,7 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 for 36E is quad enable */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, @@ -7279,7 +7279,7 @@ { .vendor = "Macronix", - .name = "MX25L6445E/MX25L6473E", + .name = "MX25L6445E/MX25L6465E/MX25L6473E", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L6405, @@ -7311,7 +7311,7 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, @@ -7319,13 +7319,13 @@ { .vendor = "Macronix", - .name = "MX25L12805(D)", + .name = "MX25L12805D", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, - .model_id = MACRONIX_MX25L12805, + .model_id = MACRONIX_MX25L12805D, .total_size = 16384, .page_size = 256, - /* MX25L12805D has 64B of OTP; enter 0xB1, exit 0xC1 */ + /* OTP: 64B total; enter 0xB1, exit 0xC1 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, @@ -7347,9 +7347,49 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L12835F/MX25L12845E/MX25L12865E", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L12805D, + .total_size = 16384, + .page_size = 256, + /* OTP: 512B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + /* TODO: security register and SBLK/SBULK; MX25L12835F: configuration register */ + .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, - .read = spi_chip_read, /* MX25L12805D: Fast read (0x0B) supported */ + .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, }, @@ -7364,7 +7404,7 @@ /* OTP: 512B total; enter 0xB1, exit 0xC1 */ /* QPI enable 0x35, disable 0xF5 (0xFF et al. work too) */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PR, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -7388,7 +7428,7 @@ }, /* TODO: security register */ .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -7430,7 +7470,7 @@ }, /* TODO: security register */ .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -7472,7 +7512,7 @@ }, /* TODO: security register */ .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8028,7 +8068,7 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* TODO: check */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, @@ -8062,7 +8102,7 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* TODO: check */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_1, /* 128 */ .read = spi_chip_read, .voltage = {2700, 3600}, @@ -8091,7 +8131,7 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* TODO: check */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, @@ -8121,7 +8161,7 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* TODO: check */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_1, /* 128 */ .read = spi_chip_read, .voltage = {2700, 3600}, @@ -8208,7 +8248,7 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* TODO: check */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, @@ -8237,7 +8277,7 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* TODO: check */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -8265,7 +8305,7 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* TODO: check */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, @@ -8294,7 +8334,7 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* TODO: check */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, @@ -8323,7 +8363,7 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* TODO: check */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, @@ -8352,7 +8392,7 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* TODO: check */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, @@ -8381,7 +8421,7 @@ } }, .printlock = spi_prettyprint_status_register_bp3_srwd, /* TODO: check */ - .unlock = spi_disable_blockprotect, + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, @@ -9635,7 +9675,7 @@ .total_size = 64, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_res2, /* The continuation code is transferred as the 3rd byte m( */ .probe_timing = TIMING_ZERO, .block_erasers = @@ -12014,7 +12054,7 @@ .total_size = 256, .page_size = 4096, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, /* 150 ns */ .block_erasers = @@ -12898,7 +12938,7 @@ }, .block_erase = erase_block_82802ab, }, { - .eraseblocks = { {256 * 1024, 1}, }, + .eraseblocks = { {256 * 1024, 1} }, .block_erase = NULL, /* Only in A/A mux mode */ } }, @@ -13330,7 +13370,7 @@ /* supports SFDP */ /* OTP: 756B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Tue Jan 27 19:07:50 2015 (r1878) +++ trunk/flashchips.h Sun Feb 8 22:57:52 2015 (r1879) @@ -27,7 +27,7 @@ /* * Please keep this list sorted alphabetically by manufacturer. The first * entry of each section should be the manufacturer ID, followed by the - * list of devices from that manufacturer (sorted by device IDs). + * list of devices from that manufacturer (sorted by device ID). * * Most LPC/FWH parts (parallel flash) have 8-bit device IDs if there is no * continuation code. @@ -303,6 +303,8 @@ #define EON_EN29LV010 0x7F6E #define EON_EN29LV040 0x4F /* Same as EN29LV040A */ #define EON_EN29LV640B 0xCB +#define EON_EN29LV640T 0xC9 +#define EON_EN29LV640U 0x7E #define EON_EN29F002T 0x7F92 /* Same as EN29F002A */ #define EON_EN29F002B 0x7F97 /* Same as EN29F002AN */ #define EON_EN29GL064HL 0x7E0C01 /* Uniform Sectors, WP protects Top OR Bottom sector */ @@ -466,13 +468,13 @@ * and use the same set of IDs. */ #define MACRONIX_MX25L512 0x2010 /* Same as MX25L512E, MX25V512, MX25V512C */ #define MACRONIX_MX25L1005 0x2011 /* Same as MX25L1005C, MX25L1006E */ -#define MACRONIX_MX25L2005 0x2012 /* Same as MX25L2005C */ -#define MACRONIX_MX25L4005 0x2013 /* Same as MX25L4005A, MX25L4005C */ -#define MACRONIX_MX25L8005 0x2014 /* Same as MX25V8005; FIXME: MX25L8073E (4k 0x20) */ +#define MACRONIX_MX25L2005 0x2012 /* Same as MX25L2005C, MX25L2006E */ +#define MACRONIX_MX25L4005 0x2013 /* Same as MX25L4005A, MX25L4005C, MX25L4006E */ +#define MACRONIX_MX25L8005 0x2014 /* Same as MX25V8005, MX25L8006E, FIXME: MX25L8073E (4k 0x20) */ #define MACRONIX_MX25L1605 0x2015 /* MX25L1605 (64k 0x20); MX25L1605A/MX25L1606E (4k 0x20, 64k 0x52); MX25L1605D/MX25L1608D/MX25L1673E (4k 0x20) */ #define MACRONIX_MX25L3205 0x2016 /* MX25L3205, MX25L3205A (64k 0x20); MX25L3205D/MX25L3208D (4k 0x20); MX25L3206E (4k 0x20, 64k 0x52); MX25L3273E (4k 0x20, 32k 0x52) */ -#define MACRONIX_MX25L6405 0x2017 /* MX25L6405, MX25L6405D (64k 0x20); MX25L6406E/MX25L6436E (4k 0x20); MX25L6445E/MX25L6473E (4k 0x20, 32k 0x52) */ -#define MACRONIX_MX25L12805 0x2018 /* Same as MX25L12805D, MX25L12835F, MX25L12845E (the latter two support completely new ID commands) */ +#define MACRONIX_MX25L6405 0x2017 /* MX25L6405, MX25L6405D (64k 0x20); MX25L6406E/MX25L6436E (4k 0x20); MX25L6445E/MX25L6465E/MX25L6473E (4k 0x20, 32k 0x52) */ +#define MACRONIX_MX25L12805D 0x2018 /* MX25L12805D (no 32k); MX25L12865E, MX25L12835F, MX25L12845E (32k 0x52) */ #define MACRONIX_MX25L25635F 0x2019 /* Same as MX25L25639F, but the latter seems to not support REMS */ #define MACRONIX_MX25L1635D 0x2415 #define MACRONIX_MX25L1635E 0x2515 /* MX25L1635{E} */ @@ -784,6 +786,48 @@ #define ST_M29W010B 0x23 #define ST_M29W040B 0xE3 #define ST_M29W512B 0x27 +#define ST_M28W160ECB 0x88CF +#define ST_M28W160ECT 0x88CE +#define ST_M28W320FCB 0x88BB +#define ST_M28W320FCT 0x88BA +#define ST_M28W640HCB 0x8849 +#define ST_M28W640HCT 0x8848 +#define ST_M29DW127G 0x7E2004 +#define ST_M29W128GH 0x7E2101 +#define ST_M29W128GL 0x7E2100 +#define ST_M29W160EB 0x2249 +#define ST_M29W160ET 0x22C4 +#define ST_M29W256GH 0x7E21xx +#define ST_M29W256GL 0x7E21xx +#define ST_M29W320DB 0x88CB +#define ST_M29W320DT 0x88CA +#define ST_M29W400FB 0x00EF +#define ST_M29W400FT 0x00EE +#define ST_M29W512GH 0x7E2301 +#define ST_M29W640FB 0x22FD +#define ST_M29W640FT 0x22ED +#define ST_M29W640GB 0x7E1000 +#define ST_M29W640GH 0x7E0C01 +#define ST_M29W640GL 0x7E0C00 +#define ST_M29W640GT 0x7E1001 +#define ST_M29W800FB 0x225B +#define ST_M29W800FT 0x22D7 +#define ST_M58BW16FB 0x8839 +#define ST_M58BW16FT 0x883A +#define ST_M58BW32FB 0x8837 +#define ST_M58BW32FT 0x8838 +#define ST_M58WR016KB 0x8813 +#define ST_M58WR016KT 0x8812 +#define ST_M58WR032KB 0x8815 +#define ST_M58WR032KT 0x8814 +#define ST_M58WR064KB 0x8811 +#define ST_M58WR064KT 0x8810 +#define ST_MT28GU01G___1 0x88B0 +#define ST_MT28GU01G___2 0x88B1 +#define ST_MT28GU256___1 0x8901 +#define ST_MT28GU256___2 0x8904 +#define ST_MT28GU512___1 0x887E +#define ST_MT28GU512___2 0x8881 #define ST_N25Q016__1E 0xBB15 /* N25Q016, 1.8V, (uniform sectors expected) */ #define ST_N25Q032__3E 0xBA16 /* N25Q032, 3.0V, (uniform sectors expected) */ #define ST_N25Q032__1E 0xBB16 /* N25Q032, 1.8V, (uniform sectors expected) */ Modified: trunk/flashrom.8.tmpl ============================================================================== --- trunk/flashrom.8.tmpl Tue Jan 27 19:07:50 2015 (r1878) +++ trunk/flashrom.8.tmpl Sun Feb 8 22:57:52 2015 (r1879) @@ -1094,6 +1094,8 @@ .br Joshua Roys .br +Ky\[:o]sti M\[:a]lkki +.br Luc Verhaegen .br Li-Ta Lo @@ -1140,7 +1142,7 @@ .br some others, please see the flashrom svn changelog for details. .br -All authors can be reached via email at <flashrom(a)flashrom.org>. +All still active authors can be reached via email at <flashrom(a)flashrom.org>. .PP This manual page was written by Uwe Hermann <uwe(a)hermann-uwe.de>, Carl-Daniel Hailfinger and others. Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Tue Jan 27 19:07:50 2015 (r1878) +++ trunk/flashrom.c Sun Feb 8 22:57:52 2015 (r1879) @@ -2020,7 +2020,7 @@ // //////////////////////////////////////////////////////////// if (write_it && erase_and_write_flash(flash, oldcontents, newcontents)) { - msg_cerr("Uh oh. Erase/write failed."); + msg_cerr("Uh oh. Erase/write failed. "); if (read_all_first) { msg_cerr("Checking if anything has changed.\n"); msg_cinfo("Reading current flash chip contents... "); Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Tue Jan 27 19:07:50 2015 (r1878) +++ trunk/ichspi.c Sun Feb 8 22:57:52 2015 (r1879) @@ -1195,7 +1195,7 @@ struct block_eraser *eraser; total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1; - msg_cdbg("Found %d attached SPI flash chip", + msg_cdbg("Hardware sequencing reports %d attached SPI flash chip", (hwseq_data.size_comp1 != 0) ? 2 : 1); if (hwseq_data.size_comp1 != 0) msg_cdbg("s with a combined"); @@ -1210,14 +1210,14 @@ erase_size_high = ich_hwseq_get_erase_block_size(boundary); if (boundary == 0) { - msg_cdbg("There is only one partition containing the whole " + msg_cdbg2("There is only one partition containing the whole " "address space (0x%06x - 0x%06x).\n", 0, size_high-1); eraser->eraseblocks[0].size = erase_size_high; eraser->eraseblocks[0].count = size_high / erase_size_high; - msg_cdbg("There are %d erase blocks with %d B each.\n", + msg_cdbg2("There are %d erase blocks with %d B each.\n", size_high / erase_size_high, erase_size_high); } else { - msg_cdbg("The flash address space (0x%06x - 0x%06x) is divided " + msg_cdbg2("The flash address space (0x%06x - 0x%06x) is divided " "at address 0x%06x in two partitions.\n", 0, total_size-1, boundary); size_low = total_size - size_high; Modified: trunk/nicintel_eeprom.c ============================================================================== --- trunk/nicintel_eeprom.c Tue Jan 27 19:07:50 2015 (r1878) +++ trunk/nicintel_eeprom.c Sun Feb 8 22:57:52 2015 (r1879) @@ -275,7 +275,7 @@ .erase = nicintel_ee_erase, }; -static int nicintel_spi_shutdown(void *eecp) +static int nicintel_ee_shutdown(void *eecp) { uint32_t old_eec = *(uint32_t *)eecp; /* Request bitbanging and unselect the chip first to be safe. */ @@ -323,7 +323,7 @@ return 1; *eecp = eec; - if (register_shutdown(nicintel_spi_shutdown, eecp)) + if (register_shutdown(nicintel_ee_shutdown, eecp)) return 1; } Modified: trunk/print.c ============================================================================== --- trunk/print.c Tue Jan 27 19:07:50 2015 (r1878) +++ trunk/print.c Sun Feb 8 22:57:52 2015 (r1879) @@ -141,7 +141,7 @@ msg_ginfo(" "); msg_gdbg("range [V]"); msg_ginfo("\n\n"); - msg_ginfo("(P = PROBE, R = READ, E = ERASE, W = WRITE)\n\n"); + msg_ginfo("(P = PROBE, R = READ, E = ERASE, W = WRITE, - = N/A)\n\n"); for (chip = flashchips; chip->name != NULL; chip++) { /* Don't print generic entries. */ @@ -403,12 +403,14 @@ for (i = 0; i < maxboardlen - strlen(b->name); i++) msg_ginfo(" "); - if (b->working == OK) - msg_ginfo("OK "); - else if (b->working == NT) - msg_ginfo("NT "); - else - msg_ginfo("BAD "); + switch (b->working) { + case OK: msg_ginfo("OK "); break; + case NT: msg_ginfo("NT "); break; + case DEP: msg_ginfo("DEP "); break; + case NA: msg_ginfo("N/A "); break; + case BAD: + default: msg_ginfo("BAD "); break; + } for (e = board_matches; e->vendor_name != NULL; e++) { if (strcmp(e->vendor_name, b->vendor) @@ -548,7 +550,8 @@ B("Albatron", "PM266A Pro", OK, "http://www.albatron.com.tw/English/Product/MB/pro_detail.asp?rlink=Overview…", NULL), /* FIXME */ B("Alienware", "Aurora-R2", BAD, NULL, "Mainboard model is 0RV30W. Probing works (Macronix MX25L3205, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("AOpen", "i945GMx-VFX", OK, NULL, "This is (also?) an OEM board from FSC (used in e.g. ESPRIMO Q5010 with designation D2544-B1)."), - B("AOpen", "vKM400Am-S", OK, "http://usa.aopen.com/products_detail.aspx?Auno=824", NULL), + B("AOpen", "UK79G-1394", OK, "http://global.aopen.com/products_detail.aspx?auno=9", "Used in EZ18 barebones"), + B("AOpen", "vKM400Am-S", OK, "http://global.aopen.com/products_detail.aspx?Auno=824", NULL), B("Artec Group","DBE61", OK, "http://wiki.thincan.org/DBE61", NULL), B("Artec Group","DBE62", OK, "http://wiki.thincan.org/DBE62", NULL), B("ASI", "MB-5BLMP", OK, "http://www.hojerteknik.com/winnet.htm", "Used in the IGEL WinNET III thin client."), @@ -644,6 +647,7 @@ B("ASUS", "M4A89GTD PRO", OK, "http://www.asus.com/Motherboards/AMD_AM3/M4A89GTD_PRO/", NULL), B("ASUS", "M4N68T V2", OK, "http://www.asus.com/Motherboards/AMD_AM3/M4N68T_V2/", NULL), B("ASUS", "M4N78 PRO", OK, "http://www.asus.com/Motherboards/AMD_AM2Plus/M4N78_PRO/", NULL), + B("ASUS", "M4N78 SE", OK, "http://www.asus.com/Motherboards/AMD_AM2Plus/M4N78_SE/", NULL), B("ASUS", "M5A78L-M LX", OK, "http://www.asus.com/Motherboards/AMD_AM3Plus/M5A78LM_LX/", "The MAC address of the onboard LAN NIC is stored in flash, hence overwritten by flashrom; see http://www.flashrom.org/pipermail/flashrom/2012-May/009200.html"), B("ASUS", "M5A97 (rev. 1.0)", OK, "http://www.asus.com/Motherboard/M5A97/", NULL), B("ASUS", "M5A99X EVO", OK, "http://www.asus.com/Motherboards/AMD_AM3Plus/M5A99X_EVO/", NULL), @@ -698,7 +702,7 @@ B("ASUS", "P5L-VM 1394", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LVM_1394/", NULL), B("ASUS", "P5LD2", OK, NULL, NULL), B("ASUS", "P5LD2-MQ", OK, "http://support.asus.com/download.aspx?SLanguage=en&p=8&s=12&m=Vintage-PH2&o…", "Found in ASUS Vintage-PH2 barebones."), - B("ASUS", "P5LD2-VM", NT, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LD2VM/", "Untested board enable."), + B("ASUS", "P5LD2-VM", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LD2VM/", NULL), B("ASUS", "P5LD2-VM DH", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LD2VM_DH/", NULL), B("ASUS", "P5LP-LE (Lithium-UL8E)", OK, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00379616&tmp_task=prod…", "This is an OEM board from HP."), B("ASUS", "P5LP-LE (Epson OEM)", OK, NULL, "This is an OEM board from Epson (e.g. Endeavor MT7700)."), @@ -824,6 +828,8 @@ B("GIGABYTE", "GA-965GM-S2 (rev. 2.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2617", NULL), B("GIGABYTE", "GA-965P-DS4", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2288", NULL), B("GIGABYTE", "GA-970A-D3P (rev. 1.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4642", NULL), + B("GIGABYTE", "GA-970A-UD3P (rev. 2.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=5194", "Primary flash chip is a Macronix MX25L3206E."), + B("GIGABYTE", "GA-990FXA-UD3 (rev. 4.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4672", NULL), B("GIGABYTE", "GA-A75M-UD2H", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3928", NULL), B("GIGABYTE", "GA-B85M-D3H", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4567", NULL), B("GIGABYTE", "GA-EP31-DS3L (rev. 2.1)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2964", NULL), @@ -833,6 +839,7 @@ B("GIGABYTE", "GA-H61M-D2-B3", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3773", NULL), B("GIGABYTE", "GA-H61M-D2H-USB3", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4004", NULL), B("GIGABYTE", "GA-H77-D3H", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4141", "Does only work with -p internal:ich_spi_mode=hwseq due to an evil twin of MX25L6405 and ICH SPI lockdown."), + B("GIGABYTE", "GA-H77-DS3H (rev. 1.1)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4318", NULL), B("GIGABYTE", "GA-H77M-D3H", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=4388", NULL), B("GIGABYTE", "GA-K8N51GMF-9", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=1939", NULL), B("GIGABYTE", "GA-K8N51GMF", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=1950", NULL), @@ -853,6 +860,7 @@ B("GIGABYTE", "GA-MA790FX-DQ6", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2690", NULL), B("GIGABYTE", "GA-MA790GP-DS4H", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=2887", NULL), B("GIGABYTE", "GA-MA790XT-UD4P (rev. 1.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3010", NULL), + B("GIGABYTE", "GA-P55-USB3 (rev. 2.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3440", NULL), B("GIGABYTE", "GA-P55A-UD4 (rev. 1.0)", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3436", NULL), B("GIGABYTE", "GA-P55A-UD7" , OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3324", NULL), B("GIGABYTE", "GA-P67A-UD3P", OK, "http://www.gigabyte.com/products/product-page.aspx?pid=3649", NULL), @@ -975,6 +983,7 @@ B("MSI", "MS-7756 (H77MA-G43)", OK, "http://www.msi.com/product/mb/H77MA-G43.html", NULL), B("MSI", "MS-7808 (B75MA-E33)", OK, "http://www.msi.com/product/mb/B75MA-E33.html", NULL), B("MSI", "MS-7816 (H87-G43)", OK, "http://www.msi.com/product/mb/H87-G43.html", NULL), + B("MSI", "MS-7817 (H81M-E33)", OK, "http://www.msi.com/product/mb/H81ME33.html", NULL), B("MSI", "MS-9830 (IM-945GSE-A, A9830IMS)", OK, "http://www.msi.com/product/ipc/IM-945GSE-A.html", NULL), B("NEC", "PowerMate 2000", OK, "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/", NULL), B("Nokia", "IP530", OK, NULL, NULL), @@ -1131,7 +1140,7 @@ B("IBM/Lenovo", "ThinkPad T420", BAD, "http://www.thinkwiki.org/wiki/Category:T420", "Probing works (Macronix MX25L6405, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."), B("IBM/Lenovo", "ThinkPad T410s", BAD, "http://www.thinkwiki.org/wiki/Category:T410s", "Probing works (Winbond W25X64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."), B("IBM/Lenovo", "ThinkPad X1", BAD, "http://www.thinkwiki.org/wiki/Category:X1", "Probing works (ST M25PX64, 8192 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs) and ME is locked. Also, a Protected Range is locking the top range of the BIOS region (presumably the boot block)."), - B("IBM/Lenovo", "ThinkPad T530", OK, "http://www.thinkwiki.org/wiki/Category:T530", "Works fine but only with coreboot (due to locked regions and additional PR restrictions)."), + B("IBM/Lenovo", "ThinkPad T530", DEP, "http://www.thinkwiki.org/wiki/Category:T530", "Works fine but only with coreboot (due to locked regions and additional PR restrictions)."), B("IBM/Lenovo", "ThinkPad 240", BAD, "http://www.stanford.edu/~bresnan//tp240.html", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later."), B("IBM/Lenovo", "3000 V100 TF05Cxx", OK, "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo3…", NULL), //B("MSI", "GT60-2OD", OK, "http://www.msi.com/product/nb/GT60_2OD.html", NULL), requires layout patches Modified: trunk/programmer.c ============================================================================== --- trunk/programmer.c Tue Jan 27 19:07:50 2015 (r1878) +++ trunk/programmer.c Sun Feb 8 22:57:52 2015 (r1879) @@ -119,7 +119,7 @@ int registered_master_count = 0; /* This function copies the struct registered_master parameter. */ -int register_master(struct registered_master *mst) +int register_master(const struct registered_master *mst) { if (registered_master_count >= MASTERS_MAX) { msg_perr("Tried to register more than %i master " Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Tue Jan 27 19:07:50 2015 (r1878) +++ trunk/programmer.h Sun Feb 8 22:57:52 2015 (r1879) @@ -321,8 +321,6 @@ #define SUPERIO_VENDOR_WINBOND 0x2 #endif #if NEED_PCI == 1 -struct pci_filter; -struct pci_dev *pci_dev_find_filter(struct pci_filter filter); struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t devclass); struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device, @@ -691,7 +689,7 @@ }; extern struct registered_master registered_masters[]; extern int registered_master_count; -int register_master(struct registered_master *mst); +int register_master(const struct registered_master *mst); /* serprog.c */ #if CONFIG_SERPROG == 1 Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Tue Jan 27 19:07:50 2015 (r1878) +++ trunk/sb600spi.c Sun Feb 8 22:57:52 2015 (r1879) @@ -141,7 +141,7 @@ } else if (rev == 0x16) { amd_gen = CHIPSET_BOLTON; msg_pdbg("Bolton detected.\n"); - } else if (rev >= 0x39 && rev <= 0x3A) { + } else if ((rev >= 0x39 && rev <= 0x3A) || rev == 0x42) { amd_gen = CHIPSET_YANGTZE; msg_pdbg("Yangtze detected.\n"); } else { @@ -498,7 +498,7 @@ free(arg); /* TODO: we should not only look at IntegratedImcPresent (LPC Dev 20, Func 3, 40h) but also at - * IMCEnable(Strap) and Override EcEnable(Strap) (sb8xx, sb9xx?, a50: Misc_Reg: 80h-87h; + * IMCEnable(Strap) and Override EcEnable(Strap) (sb8xx, sb9xx?, a50, Bolton: Misc_Reg: 80h-87h; * sb7xx, sp5100: PM_Reg: B0h-B1h) etc. */ uint8_t reg = pci_read_byte(dev, 0x40); if ((reg & (1 << 7)) == 0) { Modified: trunk/spi25_statusreg.c ============================================================================== --- trunk/spi25_statusreg.c Tue Jan 27 19:07:50 2015 (r1878) +++ trunk/spi25_statusreg.c Sun Feb 8 22:57:52 2015 (r1879) @@ -260,7 +260,7 @@ /* Fall through. */ case 4: msg_cdbg("Chip status register: Block Protect 4 (BP4) is %sset\n", - (status & (1 << 5)) ? "" : "not "); + (status & (1 << 6)) ? "" : "not "); case 3: msg_cdbg("Chip status register: Block Protect 3 (BP3) is %sset\n", (status & (1 << 5)) ? "" : "not ");

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flashrom February 2015