flashrom July 2014

flashrom@flashrom.org

21 participants
70 discussions

[commit] r1830 - trunk
by repository service 15 Jul '14

15 Jul '14

Author: stefanct Date: Tue Jul 15 15:50:58 2014 New Revision: 1830 URL: http://flashrom.org/trac/flashrom/changeset/1830 Log: Add support for AMD Bolton chipset. SPI controller on the bolton chipset uses the same 3-bit speed settings as Yangtze, but is otherwise the same as the Hudson chips. Note that the Bolton RRG doesn't specify a speed setting for the bit setting of 0b111, so I'm assuming that it's the same setting as Yangtze. Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/sb600spi.c Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Tue Jul 15 15:50:17 2014 (r1829) +++ trunk/sb600spi.c Tue Jul 15 15:50:58 2014 (r1830) @@ -51,6 +51,7 @@ CHIPSET_SB7XX, /* SP5100 too */ CHIPSET_SB89XX, /* Hudson-1 too */ CHIPSET_HUDSON234, + CHIPSET_BOLTON, CHIPSET_YANGTZE, }; static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; @@ -137,6 +138,9 @@ if (rev >= 0x11 && rev <= 0x15) { amd_gen = CHIPSET_HUDSON234; msg_pdbg("Hudson-2/3/4 detected.\n"); + } else if (rev == 0x16) { + amd_gen = CHIPSET_BOLTON; + msg_pdbg("Bolton detected.\n"); } else if (rev >= 0x39 && rev <= 0x3A) { amd_gen = CHIPSET_YANGTZE; msg_pdbg("Yangtze detected.\n"); @@ -409,23 +413,11 @@ } /* See the chipset support matrix for SPI Base_Addr below for an explanation of the symbols used. - * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson234 yangtze + * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson234 bolton/yangtze * 18 rsvd <- fastReadEnable ? <- ? SpiReadMode[0] * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1] */ - if (amd_gen >= CHIPSET_YANGTZE) { - tmp = mmio_readb(sb600_spibar + 0x20); - msg_pdbg("UseSpi100 is %sabled\n", (tmp & 0x1) ? "en" : "dis"); - if ((tmp & 0x1) == 0) { - rmmio_writeb(tmp | 0x1, sb600_spibar + 0x20); - tmp = mmio_readb(sb600_spibar + 0x20) & 0x1; - if (tmp == 0) { - msg_perr("Enabling Spi100 failed.\n"); - return 1; - } - msg_pdbg("Enabling Spi100 succeeded.\n"); - } - + if (amd_gen >= CHIPSET_BOLTON) { static const char *spireadmodes[] = { "Normal (up to 33 MHz)", /* 0 */ "Reserved", /* 1 */ @@ -434,7 +426,7 @@ "Dual IO (1-2-2)", /* 4 */ "Quad IO (1-4-4)", /* 5 */ "Normal (up to 66 MHz)", /* 6 */ - "Fast Read", /* 7 */ + "Fast Read", /* 7 (Not defined in the Bolton datasheet.) */ }; tmp = mmio_readl(sb600_spibar + 0x00); uint8_t read_mode = ((tmp >> 28) & 0x6) | ((tmp >> 18) & 0x1); @@ -448,11 +440,25 @@ msg_pdbg("Setting read mode to \"%s\" succeeded.\n", spireadmodes[read_mode]); } - tmp = mmio_readw(sb600_spibar + 0x22); /* SPI 100 Speed Config */ - msg_pdbg("NormSpeedNew is %s\n", spispeeds[(tmp >> 12) & 0xf].name); - msg_pdbg("FastSpeedNew is %s\n", spispeeds[(tmp >> 8) & 0xf].name); - msg_pdbg("AltSpeedNew is %s\n", spispeeds[(tmp >> 4) & 0xf].name); - msg_pdbg("TpmSpeedNew is %s\n", spispeeds[(tmp >> 0) & 0xf].name); + if (amd_gen >= CHIPSET_YANGTZE) { + tmp = mmio_readb(sb600_spibar + 0x20); + msg_pdbg("UseSpi100 is %sabled\n", (tmp & 0x1) ? "en" : "dis"); + if ((tmp & 0x1) == 0) { + rmmio_writeb(tmp | 0x1, sb600_spibar + 0x20); + tmp = mmio_readb(sb600_spibar + 0x20) & 0x1; + if (tmp == 0) { + msg_perr("Enabling Spi100 failed.\n"); + return 1; + } + msg_pdbg("Enabling Spi100 succeeded.\n"); + } + + tmp = mmio_readw(sb600_spibar + 0x22); /* SPI 100 Speed Config */ + msg_pdbg("NormSpeedNew is %s\n", spispeeds[(tmp >> 12) & 0xf].name); + msg_pdbg("FastSpeedNew is %s\n", spispeeds[(tmp >> 8) & 0xf].name); + msg_pdbg("AltSpeedNew is %s\n", spispeeds[(tmp >> 4) & 0xf].name); + msg_pdbg("TpmSpeedNew is %s\n", spispeeds[(tmp >> 0) & 0xf].name); + } } else { if (amd_gen >= CHIPSET_SB89XX && amd_gen <= CHIPSET_HUDSON234) { bool fast_read = (mmio_readl(sb600_spibar + 0x00) >> 18) & 0x1;

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[commit] r1829 - trunk
by repository service 15 Jul '14

15 Jul '14

Author: stefanct Date: Tue Jul 15 15:50:17 2014 New Revision: 1829 URL: http://flashrom.org/trac/flashrom/changeset/1829 Log: Refine messages regarding AMD FCH flash protections. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Mon Jul 14 20:04:15 2014 (r1828) +++ trunk/chipset_enable.c Tue Jul 15 15:50:17 2014 (r1829) @@ -999,20 +999,23 @@ /* No protection flags for this region?*/ if ((prot & 0x3) == 0) continue; - msg_pinfo("SB600 %s%sprotected from 0x%08x to 0x%08x\n", - (prot & 0x1) ? "write " : "", + msg_pdbg("Chipset %s%sprotected flash from 0x%08x to 0x%08x, unlocking...", (prot & 0x2) ? "read " : "", + (prot & 0x1) ? "write " : "", (prot & 0xfffff800), (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff)); prot &= 0xfffffffc; rpci_write_byte(dev, reg, prot); prot = pci_read_long(dev, reg); - if (prot & 0x3) - msg_perr("SB600 %s%sunprotect failed from 0x%08x to 0x%08x\n", - (prot & 0x1) ? "write " : "", + if ((prot & 0x3) != 0) { + msg_perr("Disabling %s%sprotection of flash addresses from 0x%08x to 0x%08x failed.\n", (prot & 0x2) ? "read " : "", + (prot & 0x1) ? "write " : "", (prot & 0xfffff800), (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff)); + continue; + } + msg_pdbg("done.\n"); } internal_buses_supported = BUS_LPC | BUS_FWH;

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test report for GD25Q16(B)
by YounJaeRho 14 Jul '14

14 Jul '14

programmar : raspberry pichip : GD25Q16BSIG operation : read(success), write(fail) I attached log file, thx for developing good program :)

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New motherboard
by Dima Veselov 14 Jul '14

14 Jul '14

Hello, I have an Asus Barebone system, called Asus Vintage 2 PH1. SVN-trunk flashrom version won't flash it initially, but I found a way to do it. Few words about it: Barebone has its own story, own BIOSes to download, but it looks in strange way: some soft think its Asus P5KPML motherboard, BIOS says its P5LD2-VM, flashrom show P5LD2-MQ. Motherboard tag says "DP_MB/V2-PH1<GA>" Anyway, it has same problem as P5LD2, but a bit different hardware. So I added motherboard to a copy of trunk version and flashed it successfully. I attach diff file and put log files to download: http://kab00m.ru/temp/flashrom.txz Hope this will help. -- Sincerelly yours

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[commit] r1828 - trunk
by repository service 14 Jul '14

14 Jul '14

Author: stefanct Date: Mon Jul 14 20:04:15 2014 New Revision: 1828 URL: http://flashrom.org/trac/flashrom/changeset/1828 Log: Add Board Enable for ASUS Vintage 2 PH1 (P5LD2-MQ). ASUS Vintage 2 PH1 barebone systems have a mainboard from the P5LD2 series, namely the P5LD2-MQ (although it is labeled V2-PH1). Pin 16 GPIO needs to be raised to enable write/erase like on other boards of the series. NB: it uses a ICH7DH southbridge and hence requires different PCI IDs. Signed-off-by: Dima Veselov <kab00m(a)lich.phys.spbu.ru> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Mon Jul 14 01:53:40 2014 (r1827) +++ trunk/board_enable.c Mon Jul 14 20:04:15 2014 (r1828) @@ -1663,6 +1663,7 @@ * - abit IP35: Intel P35 + ICH9R * - abit IP35 Pro: Intel P35 + ICH9R * - ASUS P5LD2 + * - ASUS P5LD2-MQ * - ASUS P5LD2-VM * - ASUS P5LD2-VM DH */ @@ -2374,6 +2375,7 @@ {0x8086, 0x27b8, 0x103c, 0x2a22, 0x8086, 0x2770, 0x103c, 0x2a22, "^LITHIUM$", NULL, NULL, P3, "ASUS", "P5LP-LE (Lithium-UL8E)",0, OK, intel_ich_gpio34_raise}, {0x8086, 0x27b8, 0x1043, 0x2a22, 0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$", NULL, NULL, P3, "ASUS", "P5LP-LE (Epson OEM)", 0, OK, intel_ich_gpio34_raise}, {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise}, + {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b0, 0x1043, 0x8179, "^P5LD2-MQ$", NULL, NULL, P3, "ASUS", "P5LD2-MQ", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2-VM$", NULL, NULL, P3, "ASUS", "P5LD2-VM", 0, NT, intel_ich_gpio16_raise}, {0x8086, 0x27b0, 0x1043, 0x8179, 0x8086, 0x2770, 0x1043, 0x817a, "^P5LD2-VM DH$", NULL, NULL, P3, "ASUS", "P5LD2-VM DH", 0, OK, intel_ich_gpio16_raise}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Mon Jul 14 01:53:40 2014 (r1827) +++ trunk/print.c Mon Jul 14 20:04:15 2014 (r1828) @@ -749,6 +749,7 @@ B("ASUS", "P5L-MX", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LMX/", NULL), B("ASUS", "P5L-VM 1394", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LVM_1394/", NULL), B("ASUS", "P5LD2", NT, NULL, "Untested board enable."), + B("ASUS", "P5LD2-MQ", OK, "http://support.asus.com/download.aspx?SLanguage=en&p=8&s=12&m=Vintage-PH2&o…", "Found in ASUS Vintage-PH2 barebones."), B("ASUS", "P5LD2-VM", NT, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LD2VM/", "Untested board enable."), B("ASUS", "P5LD2-VM DH", OK, "http://www.asus.com/Motherboards/Intel_Socket_775/P5LD2VM_DH/", NULL), B("ASUS", "P5LP-LE (Lithium-UL8E)", OK, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00379616&tmp_task=prod…", "This is an OEM board from HP."),

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Re: [flashrom] [PATCH] Improve messages on failed erases with default verbosity.
by Stefan Tauner 13 Jul '14

13 Jul '14

On Sun, 1 Jun 2014 03:38:29 +0200 Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > From: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > > Without this... > Erasing and writing flash chip... ERASE FAILED at 0x00001000! Expected=0xff, Read=0xb4, failed byte count from 0x00000000-0x0000ffff: 0xef09 > ERASE FAILED! > Reading current flash chip contents... done. > <loooooong break while the next eraser and writing is tried> > Erase/write done. > Verifying flash... VERIFIED. > > Even if there is not a long temporal pause, it is very confusing for > the user to first see a failed erase, followed by a read, a done > message and eventually the verification message. > This patch inserts "Looking for another erase function." where there is > just a silent break above. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Self-acked and committed in r1827. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1827 - trunk
by repository service 13 Jul '14

13 Jul '14

Author: stefanct Date: Mon Jul 14 01:53:40 2014 New Revision: 1827 URL: http://flashrom.org/trac/flashrom/changeset/1827 Log: Improve messages on failed erases with default verbosity. Without this... Erasing and writing flash chip... ERASE FAILED at 0x00001000! Expected=0xff, Read=0xb4, failed byte count from 0x00000000-0x0000ffff: 0xef09 ERASE FAILED! Reading current flash chip contents... done. <loooooong break while the next eraser and writing is tried> Erase/write done. Verifying flash... VERIFIED. Even if there is not a long temporal pause, it is very confusing for the user to first see a failed erase, followed by a read, a done message and eventually the verification message. This patch inserts "Looking for another erase function." where there is just a silent pause above. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/flashrom.c Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sun Jul 13 19:06:11 2014 (r1826) +++ trunk/flashrom.c Mon Jul 14 01:53:40 2014 (r1827) @@ -1463,9 +1463,9 @@ for (k = 0; k < NUM_ERASEFUNCTIONS; k++) { if (k != 0) - msg_cdbg("Looking for another erase function.\n"); + msg_cinfo("Looking for another erase function.\n"); if (!usable_erasefunctions) { - msg_cdbg("No usable erase functions left.\n"); + msg_cinfo("No usable erase functions left.\n"); break; } msg_cdbg("Trying erase function %i... ", k);

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Re: [flashrom] [PATCH 1/5] Fix FWH IDSEL message printing.
by Stefan Tauner 13 Jul '14

13 Jul '14

On Mon, 9 Jun 2014 14:41:15 +0200 Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Self-acked and committed in r1826. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1826 - trunk
by repository service 13 Jul '14

13 Jul '14

Author: stefanct Date: Sun Jul 13 19:06:11 2014 New Revision: 1826 URL: http://flashrom.org/trac/flashrom/changeset/1826 Log: Fix Intel FWH IDSEL message printing. This should get rid of extra and/or missing line breaks in verbose(+) output on Intel chipsets. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Sun Jul 13 16:53:45 2014 (r1825) +++ trunk/chipset_enable.c Sun Jul 13 19:06:11 2014 (r1826) @@ -404,7 +404,7 @@ uint64_t fwh_idsel_old = pci_read_long(dev, fwh_sel1); fwh_idsel_old <<= 16; fwh_idsel_old |= pci_read_word(dev, fwh_sel2); - msg_pdbg("\nSetting IDSEL from 0x%012" PRIx64 " to 0x%012" PRIx64 " for top 16 MB.", + msg_pdbg("Setting IDSEL from 0x%012" PRIx64 " to 0x%012" PRIx64 " for top 16 MB.\n", fwh_idsel_old, fwh_idsel); rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff); rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff); @@ -418,7 +418,7 @@ free(idsel); if (!implemented) { - msg_pdbg2("FWH IDSEL handling is not implemented on this chipset."); + msg_pdbg2("FWH IDSEL handling is not implemented on this chipset.\n"); return 0; } @@ -434,7 +434,7 @@ /* FWH_SEL1 */ for (i = 7; i >= 0; i--) { int tmp = (fwh_conf >> (i * 4)) & 0xf; - msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x", + msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n", (0x1ff8 + i) * 0x80000, (0x1ff0 + i) * 0x80000, tmp); @@ -448,7 +448,7 @@ fwh_conf = pci_read_word(dev, fwh_sel2); for (i = 3; i >= 0; i--) { int tmp = (fwh_conf >> (i * 4)) & 0xf; - msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x", + msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n", (0xff4 + i) * 0x100000, (0xff0 + i) * 0x100000, tmp); @@ -465,7 +465,7 @@ fwh_conf |= pci_read_byte(dev, fwh_dec_en_lo); for (i = 7; i >= 0; i--) { int tmp = (fwh_conf >> (i + 0x8)) & 0x1; - msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled", + msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n", (0x1ff8 + i) * 0x80000, (0x1ff0 + i) * 0x80000, tmp ? "en" : "dis"); @@ -477,7 +477,7 @@ } for (i = 3; i >= 0; i--) { int tmp = (fwh_conf >> i) & 0x1; - msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled", + msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n", (0xff4 + i) * 0x100000, (0xff0 + i) * 0x100000, tmp ? "en" : "dis"); @@ -488,7 +488,7 @@ } } max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode); - msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh); + msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode.fwh); return 0; }

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Re: [flashrom] Help read/writing ATMEL 120 25020N SI27 A
by Stefan Tauner 13 Jul '14

13 Jul '14

On Tue, 1 Jul 2014 08:44:20 +0200 Markus Moser <mosimobile(a)googlemail.com> wrote: > Hey, > > i've just played around with your software, and so far i'm pretty excited :) > i couldn't get the GUI to compile, but the console version works fine :) > i use it on a raspberry pi but i can't read from a chip i have on hand > here... > Because i need to preserve the data on the chip, i can't test writing right > now, > but i hope you can help me though :) > > Attatched you'll find a picture of the EEPROM, and the log file - but i > doubt you can get anything useful from it, at least i couldn't :D > > I really hope you can help me with this - i struggle with this thing for > days now x) Hello Markus, looks like the chip is not responding at all. From the picture it looks like it is still soldered in another system. In that case you might have problems like those mentioned in the wiki: http://flashrom.org/ISP -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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flashrom July 2014