flashrom July 2014

flashrom@flashrom.org

21 participants
70 discussions

[PATCH] Enable Dediprog SF100 programmers with FW 5.5.1
by Pablo Cases 31 Jul '14

31 Jul '14

This patch enables Dediprog SF100 programmers with FW 5.5.1 to work properly with flashrom. The following functionality has been fixed and verified on a W25Q64.V flash chip. All fixes relate to changes in the USB commands issued to the SF100 programmer: * chip discovery (flashrom could not read out the ManufacturerID and DeviceID fields properly, got parts of the devicestring instead) * chip data readout (SF100 issued SPI Fast Read from address 0xF30000 instead of 0x0) * chip data write (SF100 issued SPI Page Program to address 0xF30000 instead of 0x0) * chip erase (verification failed as a consequence of that chip data readout was problematic) * SF100 LED management (LEDs could be turned on but not turned off) Signed-off-by: Pablo Cases <pablo.cases at flatfrog.com> Index: dediprog.c =================================================================== --- dediprog.c (revision 1832) +++ dediprog.c (working copy) @@ -101,8 +101,13 @@ target_leds = leds; } - ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, target_leds, + if (dediprog_firmwareversion >= FIRMWARE_VERSION(5,5,1)) + ret = usb_control_msg(dediprog_handle, 0x42, 0x07, (target_leds << 8) | 0x09, 0x0, NULL, 0x0, DEFAULT_TIMEOUT); + else + ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, target_leds, + NULL, 0x0, DEFAULT_TIMEOUT); + if (ret != 0x0) { msg_perr("Command Set LED 0x%x failed (%s)!\n", leds, usb_strerror()); @@ -216,8 +221,22 @@ const char count_and_chunk[] = {count & 0xff, (count >> 8) & 0xff, chunksize & 0xff, - (chunksize >> 8) & 0xff}; + (chunksize >> 8) & 0xff, + 0xFF, 0,0,0,0,0}; + unsigned int count_and_chunk_size; + /* Reverse engineering note: + * ======================== + * Omitting the {0xFF, 0,0,0,0,0} appendage of SF100 FW 5.5.1 + * results in SF100 to incorrectly issue 0x0B (Fast Read) command with + * start at SPI address 0xF30000 instead of the expected address 0x0. + * (On a 8MiB W25Q64.V chip this wraps around to physical address 0x730000) + */ + if (dediprog_firmwareversion >= FIRMWARE_VERSION(5,5,1)) + count_and_chunk_size = 10; + else + count_and_chunk_size = 4; + if ((start % chunksize) || (len % chunksize)) { msg_perr("%s: Unaligned start=%i, len=%i! Please report a bug " "at flashrom(a)flashrom.org\n", __func__, start, len); @@ -232,8 +251,8 @@ */ ret = usb_control_msg(dediprog_handle, 0x42, 0x20, start % 0x10000, start / 0x10000, (char *)count_and_chunk, - sizeof(count_and_chunk), DEFAULT_TIMEOUT); - if (ret != sizeof(count_and_chunk)) { + count_and_chunk_size, DEFAULT_TIMEOUT); + if (ret != count_and_chunk_size) { msg_perr("Command Read SPI Bulk failed, %i %s!\n", ret, usb_strerror()); return 1; @@ -316,9 +335,27 @@ * space in a USB bulk transfer must be filled with 0xff padding. */ const unsigned int count = len / chunksize; - const char count_and_cmd[] = {count & 0xff, (count >> 8) & 0xff, 0x00, dedi_spi_cmd}; + const char count_and_cmd[] = {count & 0xff, (count >> 8) & 0xff, 0x00, dedi_spi_cmd, 0xFF, 0,0,0,0,0}; + unsigned int count_and_cmd_size; char usbbuf[512]; - + + /* Reverse engineering note: + * ======================== + * Omitting the {0xFF, 0,0,0,0,0} appendage of SF100 FW 5.5.1 + * results in SF100 to incorrectly issue 0x02 (Page Program) command with + * start at SPI address 0xF30000 instead of the expected address 0x0. + * (On a 8MiB W25Q64.V chip this wraps around to physical address 0x730000) + * Issuing a single spi_bulk_write() command with this appendage will + * correct the addressing so that all further spi_bulk_write() commands + * (with or without the appendage) will start at SPI address 0x0. + * Only a power cycle of the SF100 will reset the behavior + * (i.e. reintroduce the error). + */ + if (dediprog_firmwareversion >= FIRMWARE_VERSION(5,5,1)) + count_and_cmd_size = 10; + else + count_and_cmd_size = 4; + /* * We should change this check to * chunksize > 512 @@ -343,8 +380,8 @@ * SPI side. */ ret = usb_control_msg(dediprog_handle, 0x42, 0x30, start % 0x10000, start / 0x10000, - (char *)count_and_cmd, sizeof(count_and_cmd), DEFAULT_TIMEOUT); - if (ret != sizeof(count_and_cmd)) { + (char *)count_and_cmd, count_and_cmd_size, DEFAULT_TIMEOUT); + if (ret != count_and_cmd_size) { msg_perr("Command Write SPI Bulk failed, %i %s!\n", ret, usb_strerror()); return 1; @@ -447,10 +484,29 @@ msg_perr("Untested readcnt=%i, aborting.\n", readcnt); return 1; } - - ret = usb_control_msg(dediprog_handle, 0x42, 0x1, 0xff, - readcnt ? 0x1 : 0x0, (char *)writearr, writecnt, - DEFAULT_TIMEOUT); + + if (dediprog_firmwareversion >= FIRMWARE_VERSION(5,5,1)) + if (writecnt == 1 && + (*writearr == 0x6 || // Write Enable + *writearr == 0x60 || *writearr == 0xc7 ||// Chip Erase + *writearr == 0x52 || *writearr == 0xd8 ||// Block Erase + *writearr == 0x20)) // Sector Erase + /* These commands are treated differently otherwise + * Read Status Register-1 (05h) will return incorrect + * results for WEL and WIP bits + * (at least on Winbond W25Q64BV Flash) + */ + ret = usb_control_msg(dediprog_handle, 0x42, 0x1, 0x0, + 0x0, (char *)writearr, writecnt, + DEFAULT_TIMEOUT); + else + ret = usb_control_msg(dediprog_handle, 0x42, 0x1, 0x1, + 0x0, (char *)writearr, writecnt, + DEFAULT_TIMEOUT); + else + ret = usb_control_msg(dediprog_handle, 0x42, 0x1, 0xff, + readcnt ? 0x1 : 0x0, (char *)writearr, writecnt, + DEFAULT_TIMEOUT); if (ret != writecnt) { msg_perr("Send SPI failed, expected %i, got %i %s!\n", writecnt, ret, usb_strerror()); @@ -459,8 +515,13 @@ if (!readcnt) return 0; memset(readarr, 0, readcnt); - ret = usb_control_msg(dediprog_handle, 0xc2, 0x01, 0xbb8, 0x0000, - (char *)readarr, readcnt, DEFAULT_TIMEOUT); + + if (dediprog_firmwareversion >= FIRMWARE_VERSION(5,5,1)) + ret = usb_control_msg(dediprog_handle, 0xc2, 0x1, 0x1, 0x0, + (char *)readarr, readcnt, DEFAULT_TIMEOUT); + else + ret = usb_control_msg(dediprog_handle, 0xc2, 0x1, 0xbb8, 0x0000, + (char *)readarr, readcnt, DEFAULT_TIMEOUT); if (ret != readcnt) { msg_perr("Receive SPI failed, expected %i, got %i %s!\n", readcnt, ret, usb_strerror()); @@ -485,6 +546,12 @@ " String!\n"); return 1; } + /* Reverse engineering note: + * ======================== + * Dediprog Software SF6.0.4.33 application sends the devicestring + * command with wValue and wIndex values of 0x0 instead of 0xFF. + * Both commands yield the same result, so nothing is changed for now. + */ /* Command Receive Device String. */ memset(buf, 0, sizeof(buf)); ret = usb_control_msg(dediprog_handle, 0xc2, 0x8, 0xff, 0xff, buf, ---------------------------------------------------------------------- Pablo Cases, M.Sc. Senior Software Engineer FlatFrog Laboratories AB

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[PATCH 2/2] Add support for Atmel AT49LH004 and AT49LH00B4.
by Stefan Tauner 29 Jul '14

29 Jul '14

Also, slightly refine the definition of AT49LH002. TODO: unlocking is mandatory because the chips are write-protected by default. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- flashchips.c | 84 +++++++++++++++++++++++++++++++++++++++++++++++++++++++----- flashchips.h | 2 ++ 2 files changed, 80 insertions(+), 6 deletions(-) diff --git a/flashchips.c b/flashchips.c index 489f7c3..e8ac789 100644 --- a/flashchips.c +++ b/flashchips.c @@ -3049,10 +3049,10 @@ const struct flashchip flashchips[] = { .model_id = ATMEL_AT49LH002, .total_size = 256, .page_size = 0, /* unused */ - .feature_bits = FEATURE_REGISTERMAP, /* TODO: LPC OK too? */ + .feature_bits = FEATURE_REGISTERMAP, .tested = TEST_UNTESTED, - .probe = probe_82802ab, /* TODO: 0xff cmd not documented? */ - .probe_timing = TIMING_FIXME, + .probe = probe_82802ab, + .probe_timing = TIMING_ZERO, .block_erasers = { { @@ -3062,16 +3062,88 @@ const struct flashchip flashchips[] = { {8 * 1024, 2}, {16 * 1024, 1}, }, - .block_erase = erase_block_82802ab, + .block_erase = NULL, /* TODO: Implement. */ }, { .eraseblocks = { {64 * 1024, 4}, }, + .block_erase = erase_block_82802ab, + }, + }, + .printlock = printlock_regspace2_block_eraser_0, + .unlock = unlock_regspace2_block_eraser_0, + .write = write_82802ab, + .read = read_memmapped, + .voltage = {3000, 3600}, + }, + + { + .vendor = "Atmel", + .name = "AT49LH00B4", + .bustype = BUS_LPC | BUS_FWH, /* A/A Mux */ + .manufacture_id = ATMEL_ID, + .model_id = ATMEL_AT49LH00B4, + .total_size = 512, + .page_size = 0, /* unused */ + .feature_bits = FEATURE_REGISTERMAP, + .tested = TEST_UNTESTED, + .probe = probe_82802ab, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {8 * 1024, 2}, + {16 * 1024, 1}, + {32 * 1024, 1}, + {64 * 1024, 7}, + }, + .block_erase = NULL, /* TODO: Implement. */ + }, { + .eraseblocks = { + {64 * 1024, 8}, + }, + .block_erase = erase_block_82802ab, + }, + }, + .printlock = printlock_regspace2_block_eraser_0, + .unlock = unlock_regspace2_block_eraser_0, + .write = write_82802ab, + .read = read_memmapped, + .voltage = {3000, 3600}, + }, + + { + .vendor = "Atmel", + .name = "AT49LH004", + .bustype = BUS_LPC | BUS_FWH, /* A/A Mux */ + .manufacture_id = ATMEL_ID, + .model_id = ATMEL_AT49LH004, + .total_size = 512, + .page_size = 0, /* unused */ + .feature_bits = FEATURE_REGISTERMAP, + .tested = TEST_UNTESTED, + .probe = probe_82802ab, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 7}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_block_82802ab, + }, { + .eraseblocks = { + {64 * 1024, 8}, + }, .block_erase = NULL, /* TODO: Implement. */ }, }, - .printlock = NULL, /* TODO */ - .unlock = NULL, /* unlock_82802ab() not correct(?) */ + .printlock = printlock_regspace2_block_eraser_0, + .unlock = unlock_regspace2_block_eraser_0, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, diff --git a/flashchips.h b/flashchips.h index 174ab3b..5589714 100644 --- a/flashchips.h +++ b/flashchips.h @@ -190,6 +190,8 @@ #define ATMEL_AT49BV512 0x03 #define ATMEL_AT49F002N 0x07 /* for AT49F002(N) */ #define ATMEL_AT49LH002 0xE9 +#define ATMEL_AT49LH00B4 0xED +#define ATMEL_AT49LH004 0xEE #define ATMEL_AT49F002NT 0x08 /* for AT49F002(N)T */ #define ATMEL_AT49F010 0x17 /* Same as AT49HF010 */ #define ATMEL_AT49F020 0x0B -- Kind regards, Stefan Tauner

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Re: [flashrom] [PATCH] Refactor unlocking of many chips with locking at register space address +2.
by Stefan Tauner 29 Jul '14

29 Jul '14

On Thu, 29 May 2014 19:13:33 +0200 Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > This includes PMC Pm49*, SST 49LF00*, ST M50* and Winbond W39* family. > The erase and write test status bits of all affected chips have been reset. > > Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Also, the W39V040FA's unlock method should be unlock_regspace2_uniform_64k() instead of unlock_sst_fwhub(). Fixed locally. BTW, the whole sst_fwhub.c could be unified with the rest too. They are just missing the read lock bit AFAICS. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] Add support for a bunch of 29GL parallel flash chips.
by Stefan Tauner 29 Jul '14

29 Jul '14

On Sun, 25 May 2014 05:44:18 +0100 Gilbert Klzo <gigimorphe(a)yahoo.com> wrote: > Hi Stefan > Thank you for email > Soon I've done it I will emIl you > Regards > Gilbert Hi, any progress? :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] LR-C1037TN
by Stefan Tauner 29 Jul '14

29 Jul '14

On Tue, 29 Jul 2014 00:24:20 +0100 Luis Manuel Ramos Da Costa <aliasbody(a)gmail.com> wrote: > Hello Everyone, > > So just as requested here are all the informations about this motherboard : > > *Manufacturer : *SZ Realan > *Board Model : *LR-C1037TN v1.3 > *Serial :* LRC1037TN14050466 > *FCC :* TT RU E326167 TC-1 03-01 1404 > *BIOS Chip :* GD25Q32PIG POG497 BH1309 > > *File provided by manufacturer to flash BIOS (with FPT) : * > http://paste.flashrom.org/view.php?id=2648 > > *Full flashrom log :* > http://paste.flashrom.org/view.php?id=2649 > > *"sudo lspci -vv" Log :* > http://paste.flashrom.org/view.php?id=2650 > > If there is a need for any other information please tell. Hello Luis, the output of 'sudo lspci -vvxx' and 'sudo dmidecode' would be nice to have. With that we could look for a way to whitelist the board to be not a laptop (as its DMI data indicates erroneously). Although I doubt there is anything to distinguish this board from other similarly crappy boards... :) Apart from that I don't see any problems with the board in the log... as long as you use the correct binary file of the firmware for the board (and always use the -p internal:laptop=... parameter to override the behavior discussed above), flashrom should just work with it. Did you receive a proper binary firmware for the board from the vendor? I am asking because you referred to the flash chip list of fpt a few times but never to any real firmware yet. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[Aliasbody] Flashrom Mailing List
by Luis Manuel Ramos Da Costa 28 Jul '14

28 Jul '14

Hello Everyone, So just as requested here are all the informations about this motherboard : *Manufacturer : *SZ Realan *Board Model : *LR-C1037TN v1.3 *Serial :* LRC1037TN14050466 *FCC :* TT RU E326167 TC-1 03-01 1404 *BIOS Chip :* GD25Q32PIG POG497 BH1309 *File provided by manufacturer to flash BIOS (with FPT) : * http://paste.flashrom.org/view.php?id=2648 *Full flashrom log :* http://paste.flashrom.org/view.php?id=2649 *"sudo lspci -vv" Log :* http://paste.flashrom.org/view.php?id=2650 If there is a need for any other information please tell. Best Regards, Luis Da Costa

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Re: [flashrom] [PATCH] Add new programmer for SPI EEPROMs attached to Intel 82580 NICs.
by Stefan Tauner 28 Jul '14

28 Jul '14

On Mon, 28 Jul 2014 12:01:54 +0200 Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> wrote: > Tested-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> > Thank you. It was committed in r1832. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1832 - trunk
by repository service 28 Jul '14

28 Jul '14

Author: stefanct Date: Mon Jul 28 22:35:21 2014 New Revision: 1832 URL: http://flashrom.org/trac/flashrom/changeset/1832 Log: Add new programmer for SPI EEPROMs attached to Intel 82580 NICs. This patch lets you read and write the EEPROM on 82580-based gigabit NIC cards. So far it has been tested on copper NICs only, but other variants employing this controller should work too. It is a nice substitution for the official eeupdate tool. Speed is quite decent: less than 4 seconds for erases or writes of 32 kB. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Tested-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Added: trunk/nicintel_eeprom.c (contents, props changed) Modified: trunk/Makefile trunk/flashrom.8.tmpl trunk/flashrom.c trunk/programmer.h Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sun Jul 20 00:03:29 2014 (r1831) +++ trunk/Makefile Mon Jul 28 22:35:21 2014 (r1832) @@ -227,6 +227,11 @@ else override CONFIG_NICINTEL = no endif +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) +UNSUPPORTED_FEATURES += CONFIG_NICINTEL_EEPROM=yes +else +override CONFIG_NICINTEL_EEPROM = no +endif ifeq ($(CONFIG_NICINTEL_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_NICINTEL_SPI=yes else @@ -426,6 +431,9 @@ # Always enable SPI on Intel NICs for now. CONFIG_NICINTEL_SPI ?= yes +# Always enable EEPROM on Intel NICs for now. +CONFIG_NICINTEL_EEPROM ?= yes + # Always enable SPI on OGP cards for now. CONFIG_OGP_SPI ?= yes @@ -626,6 +634,12 @@ NEED_PCI := yes endif +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) +FEATURE_CFLAGS += -D'CONFIG_NICINTEL_EEPROM=1' +PROGRAMMER_OBJS += nicintel_eeprom.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_OGP_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_OGP_SPI=1' PROGRAMMER_OBJS += ogp_spi.o Modified: trunk/flashrom.8.tmpl ============================================================================== --- trunk/flashrom.8.tmpl Sun Jul 20 00:03:29 2014 (r1831) +++ trunk/flashrom.8.tmpl Mon Jul 28 22:35:21 2014 (r1832) @@ -225,6 +225,8 @@ .sp .BR "* usbblaster_spi" " (for SPI flash ROMs attached to an Altera USB-Blaster compatible cable)" .sp +.BR "* nicintel_eeprom" " (for SPI EEPROMs on Intel Gigabit network cards)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER SPECIFIC INFO @@ -591,7 +593,7 @@ .B content is an 8-bit hexadecimal value. .SS -.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel"\ +.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\ , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\ , " satamv" , " atahpt" ", " atavia " and " it8212 " programmers These programmers have an option to specify the PCI address of the card @@ -625,6 +627,14 @@ .nh .B http://flashrom.org/VT6421A .SS +.BR "nicintel_eeprom " programmer +This is the first programmer module in flashrom that does not provide access to NOR flash chips but EEPROMs +mounted on gigabit Ethernet cards based on Intel's 82580 NIC. Because EEPROMs normally do not announce their +size nor allow to be identified, the controller relies on correct size values written to predefined addresses +within the chip. Flashrom follows this scheme but assumes the minimum size of 16 kB (128 kb) if an unprogrammed +EEPROM/card is detected. Intel specifies following EEPROMs to be compatible: Atmel AT25128, AT25256, Micron (ST) +M95128, M95256 and OnSemi (Catalyst) CAT25CS128. +.SS .BR "ft2232_spi " programmer An optional parameter specifies the controller type and channel/interface/port it should support. For that you have to use the @@ -922,8 +932,8 @@ .B rayer_spi needs raw I/O port access. .sp -.B satasii -needs PCI configuration space read access and raw memory access. +.BR satasii ", " nicintel ", " nicintel_eeprom " and " nicintel_spi +need PCI configuration space read access and raw memory access. .sp .B satamv needs PCI configuration space read access, raw I/O port access and raw memory Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sun Jul 20 00:03:29 2014 (r1831) +++ trunk/flashrom.c Mon Jul 28 22:35:21 2014 (r1832) @@ -297,6 +297,18 @@ }, #endif +#if CONFIG_NICINTEL_EEPROM == 1 + { + .name = "nicintel_eeprom", + .type = PCI, + .devs.dev = nics_intel_ee, + .init = nicintel_ee_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + #if CONFIG_OGP_SPI == 1 { .name = "ogp_spi", Added: trunk/nicintel_eeprom.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/nicintel_eeprom.c Mon Jul 28 22:35:21 2014 (r1832) @@ -0,0 +1,331 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2013 Ricardo Ribalda - Qtechnology A/S + * Copyright (C) 2011, 2014 Stefan Tauner + * + * Based on nicinctel_spi.c and ichspi.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +/* + * Datasheet: Intel 82580 Quad/Dual Gigabit Ethernet LAN Controller Datasheet + * 3.3.1.4: General EEPROM Software Access + * 4.7: Access to shared resources (FIXME: we should probably use this semaphore interface) + * 7.4: Register Descriptions + */ + +#include <stdlib.h> +#include <unistd.h> +#include "flash.h" +#include "spi.h" +#include "programmer.h" +#include "hwaccess.h" + +#define PCI_VENDOR_ID_INTEL 0x8086 +#define MEMMAP_SIZE (0x14 + 3) /* Only EEC and EERD are needed. */ + +#define EEC 0x10 /* EEPROM/Flash Control Register */ +#define EERD 0x14 /* EEPROM Read Register */ + +/* EPROM/Flash Control Register bits */ +#define EE_SCK 0 +#define EE_CS 1 +#define EE_SI 2 +#define EE_SO 3 +#define EE_REQ 6 +#define EE_GNT 7 +#define EE_PRES 8 +#define EE_SIZE 11 +#define EE_SIZE_MASK 0xf + +/* EEPROM Read Register bits */ +#define EERD_START 0 +#define EERD_DONE 1 +#define EERD_ADDR 2 +#define EERD_DATA 16 + +#define BIT(x) (1<<x) +#define PAGE_MASK 0x3f + +static uint8_t *nicintel_eebar; +static struct pci_dev *nicintel_pci; + +#define UNPROG_DEVICE 0x1509 + +const struct dev_entry nics_intel_ee[] = { + {PCI_VENDOR_ID_INTEL, 0x150e, OK, "Intel", "82580 Quad Gigabit Ethernet Controller (Copper)"}, + {PCI_VENDOR_ID_INTEL, 0x150f, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Fiber)"}, + {PCI_VENDOR_ID_INTEL, 0x1510, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Backplane)"}, + {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Ext. PHY)"}, + {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Dual Gigabit Ethernet Controller (Copper)"}, + {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"}, + {0}, +}; + +static int nicintel_ee_probe(struct flashctx *flash) +{ + if (nicintel_pci->device_id == UNPROG_DEVICE) + flash->chip->total_size = 16; /* Fall back to minimum supported size. */ + else { + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); + tmp = ((tmp >> EE_SIZE) & EE_SIZE_MASK); + switch (tmp) { + case 7: + flash->chip->total_size = 16; + break; + case 8: + flash->chip->total_size = 32; + break; + default: + msg_cerr("Unsupported chip size 0x%x\n", tmp); + return 0; + } + } + + flash->chip->page_size = PAGE_MASK + 1; + flash->chip->tested = TEST_OK_PREW; + flash->chip->gran = write_gran_1byte_implicit_erase; + flash->chip->block_erasers->eraseblocks[0].size = (PAGE_MASK + 1); + flash->chip->block_erasers->eraseblocks[0].count = (flash->chip->total_size * 1024) / (PAGE_MASK + 1); + + return 1; +} + +static int nicintel_ee_read_word(unsigned int addr, uint16_t *word) +{ + uint32_t tmp = BIT(EERD_START) | (addr << EERD_ADDR); + pci_mmio_writel(tmp, nicintel_eebar + EERD); + + /* Poll done flag. 10.000.000 cycles seem to be enough. */ + uint32_t i; + for (i = 0; i < 10000000; i++) { + tmp = pci_mmio_readl(nicintel_eebar + EERD); + if (tmp & BIT(EERD_DONE)) { + *word = (tmp >> EERD_DATA) & 0xffff; + return 0; + } + } + + return -1; +} + +static int nicintel_ee_read(struct flashctx *flash, uint8_t *buf, unsigned int addr, unsigned int len) +{ + uint16_t word; + + /* The NIC interface always reads 16 b words so we need to convert the address and handle odd address + * explicitly at the start (and also at the end in the loop below). */ + if (addr & 1) { + if (nicintel_ee_read_word(addr / 2, &word)) + return -1; + *buf++ = word & 0xff; + addr++; + len--; + } + + while (len > 0) { + if (nicintel_ee_read_word(addr / 2, &word)) + return -1; + *buf++ = word & 0xff; + addr++; + len--; + if (len > 0) { + *buf++ = (word >> 8) & 0xff; + addr++; + len--; + } + } + + return 0; +} + +static int nicintel_ee_bitset(int reg, int bit, bool val) +{ + uint32_t tmp; + + tmp = pci_mmio_readl(nicintel_eebar + reg); + if (val) + tmp |= BIT(bit); + else + tmp &= ~BIT(bit); + pci_mmio_writel(tmp, nicintel_eebar + reg); + + return -1; +} + +/* Shifts one byte out while receiving another one by bitbanging (denoted "direct access" in the datasheet). */ +static int nicintel_ee_bitbang(uint8_t mosi, uint8_t *miso) +{ + uint8_t out = 0x0; + + int i; + for (i = 7; i >= 0; i--) { + nicintel_ee_bitset(EEC, EE_SI, mosi & BIT(i)); + nicintel_ee_bitset(EEC, EE_SCK, 1); + if (miso != NULL) { + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); + if (tmp & BIT(EE_SO)) + out |= BIT(i); + } + nicintel_ee_bitset(EEC, EE_SCK, 0); + } + + if (miso != NULL) + *miso = out; + + return 0; +} + +/* Polls the WIP bit of the status register of the attached EEPROM via bitbanging. */ +static int nicintel_ee_ready(void) +{ + unsigned int i; + for (i = 0; i < 1000; i++) { + nicintel_ee_bitset(EEC, EE_CS, 0); + + nicintel_ee_bitbang(JEDEC_RDSR, NULL); + uint8_t rdsr; + nicintel_ee_bitbang(0x00, &rdsr); + + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + if (!(rdsr & SPI_SR_WIP)) { + return 0; + } + } + return -1; +} + +/* Requests direct access to the SPI pins. */ +static int nicintel_ee_req(void) +{ + uint32_t tmp; + nicintel_ee_bitset(EEC, EE_REQ, 1); + + tmp = pci_mmio_readl(nicintel_eebar + EEC); + if (!(tmp & BIT(EE_GNT))) { + msg_perr("Enabling eeprom access failed.\n"); + return 1; + } + + nicintel_ee_bitset(EEC, EE_SCK, 0); + return 0; +} + +static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) +{ + if (nicintel_ee_req()) + return -1; + + int ret = -1; + if (nicintel_ee_ready()) + goto out; + + while (len > 0) { + /* WREN */ + nicintel_ee_bitset(EEC, EE_CS, 0); + nicintel_ee_bitbang(JEDEC_WREN, NULL); + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + + /* data */ + nicintel_ee_bitset(EEC, EE_CS, 0); + nicintel_ee_bitbang(JEDEC_BYTE_PROGRAM, NULL); + nicintel_ee_bitbang((addr >> 8) & 0xff, NULL); + nicintel_ee_bitbang(addr & 0xff, NULL); + while (len > 0) { + nicintel_ee_bitbang((buf) ? *buf++ : 0xff, NULL); + len--; + addr++; + if (!(addr & PAGE_MASK)) + break; + } + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + if (nicintel_ee_ready()) + goto out; + } + ret = 0; +out: + nicintel_ee_bitset(EEC, EE_REQ, 0); /* Give up direct access. */ + return ret; +} + +static int nicintel_ee_erase(struct flashctx *flash, unsigned int addr, unsigned int len) +{ + return nicintel_ee_write(flash, NULL, addr, len); +} + +static const struct opaque_master opaque_master_nicintel_ee = { + .probe = nicintel_ee_probe, + .read = nicintel_ee_read, + .write = nicintel_ee_write, + .erase = nicintel_ee_erase, +}; + +static int nicintel_spi_shutdown(void *eecp) +{ + uint32_t old_eec = *(uint32_t *)eecp; + /* Request bitbanging and unselect the chip first to be safe. */ + if (nicintel_ee_req() || nicintel_ee_bitset(EEC, EE_CS, 1)) + return -1; + + /* Try to restore individual bits we care about. */ + int ret = nicintel_ee_bitset(EEC, EE_SCK, old_eec & BIT(EE_SCK)); + ret |= nicintel_ee_bitset(EEC, EE_SI, old_eec & BIT(EE_SI)); + ret |= nicintel_ee_bitset(EEC, EE_CS, old_eec & BIT(EE_CS)); + /* REQ will be cleared by hardware anyway after 2 seconds of inactivity on the SPI pins (3.3.2.1). */ + ret |= nicintel_ee_bitset(EEC, EE_REQ, old_eec & BIT(EE_REQ)); + + free(eecp); + return ret; +} + +int nicintel_ee_init(void) +{ + if (rget_io_perms()) + return 1; + + struct pci_dev *dev = pcidev_init(nics_intel_ee, PCI_BASE_ADDRESS_0); + if (!dev) + return 1; + + uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; + + nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", io_base_addr, MEMMAP_SIZE); + nicintel_pci = dev; + if (dev->device_id != UNPROG_DEVICE) { + uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); + + /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting the EE_PRES definition), + * and 3.3.1.7 for possible recovery. */ + if (!(eec & BIT(EE_PRES))) { + msg_perr("Controller reports no EEPROM is present.\n"); + return 1; + } + + uint32_t *eecp = malloc(sizeof(uint32_t)); + if (eecp == NULL) + return 1; + *eecp = eec; + + if (register_shutdown(nicintel_spi_shutdown, eecp)) + return 1; + } + + return register_opaque_master(&opaque_master_nicintel_ee); +} Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sun Jul 20 00:03:29 2014 (r1831) +++ trunk/programmer.h Mon Jul 28 22:35:21 2014 (r1832) @@ -84,6 +84,9 @@ #if CONFIG_NICINTEL_SPI == 1 PROGRAMMER_NICINTEL_SPI, #endif +#if CONFIG_NICINTEL_EEPROM == 1 + PROGRAMMER_NICINTEL_EEPROM, +#endif #if CONFIG_OGP_SPI == 1 PROGRAMMER_OGP_SPI, #endif @@ -416,6 +419,12 @@ extern const struct dev_entry nics_intel_spi[]; #endif +/* nicintel_eeprom.c */ +#if CONFIG_NICINTEL_EEPROM == 1 +int nicintel_ee_init(void); +extern const struct dev_entry nics_intel_ee[]; +#endif + /* ogp_spi.c */ #if CONFIG_OGP_SPI == 1 int ogp_spi_init(void);

1 0

Re: [flashrom] [PATCH] Add new programmer for SPI EEPROMs attached to Intel 82580 NICs.
by Ricardo Ribalda Delgado 28 Jul '14

28 Jul '14

Tested-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Hello I have tested it on 32kb mode: root@qt5022:~# time ./flashrom -p nicintel_eeprom:pci=02:00.0 -r kk.out flashrom v0.9.7-r1831 on Linux 3.16.0-rc6-qtec-standard+ (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Programmer flash chip "Opaque flash chip" (32 kB, Programmer-specific) on nicintel_eeprom. Reading flash... done. real 0m1.645s user 0m1.631s sys 0m0.014s root@qt5022:~# time ./flashrom -p nicintel_eeprom:pci=02:00.0 -E flashrom v0.9.7-r1831 on Linux 3.16.0-rc6-qtec-standard+ (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Programmer flash chip "Opaque flash chip" (32 kB, Programmer-specific) on nicintel_eeprom. Erasing and writing flash chip... Erase/write done. real 0m3.926s user 0m3.905s sys 0m0.021s root@qt5022:~# time ./flashrom -p nicintel_eeprom:pci=02:00.0 -w kk.out flashrom v0.9.7-r1831 on Linux 3.16.0-rc6-qtec-standard+ (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Programmer flash chip "Opaque flash chip" (32 kB, Programmer-specific) on nicintel_eeprom. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. real 0m3.773s user 0m3.753s sys 0m0.020s On Mon, Jul 28, 2014 at 2:10 AM, Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > This patch lets you read and write the EEPROM on 82580-based gigabit NIC > cards. So far it has been tested on copper NICs only, but other variants > employing this controller should work too. > It is a nice substitution for the official eeupdate tool. > > Speed is quite decent: less than 5 seconds for erases or writes. > > Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > --- > Rebased on r1831 because that breaks the previous version. > Ricardo, if you don't have time or motivation to re-test this then > please make a short note. I'll commit this patch then without any > tested state, thanks. > > Makefile | 14 +++ > flashrom.8.tmpl | 16 ++- > flashrom.c | 12 ++ > nicintel_eeprom.c | 331 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ > programmer.h | 9 ++ > 5 files changed, 379 insertions(+), 3 deletions(-) > create mode 100644 nicintel_eeprom.c > > diff --git a/Makefile b/Makefile > index 7a48889..64798c9 100644 > --- a/Makefile > +++ b/Makefile > @@ -227,6 +227,11 @@ UNSUPPORTED_FEATURES += CONFIG_NICINTEL=yes > else > override CONFIG_NICINTEL = no > endif > +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) > +UNSUPPORTED_FEATURES += CONFIG_NICINTEL_EEPROM=yes > +else > +override CONFIG_NICINTEL_EEPROM = no > +endif > ifeq ($(CONFIG_NICINTEL_SPI), yes) > UNSUPPORTED_FEATURES += CONFIG_NICINTEL_SPI=yes > else > @@ -426,6 +431,9 @@ CONFIG_NICINTEL ?= yes > # Always enable SPI on Intel NICs for now. > CONFIG_NICINTEL_SPI ?= yes > > +# Always enable EEPROM on Intel NICs for now. > +CONFIG_NICINTEL_EEPROM ?= yes > + > # Always enable SPI on OGP cards for now. > CONFIG_OGP_SPI ?= yes > > @@ -626,6 +634,12 @@ PROGRAMMER_OBJS += nicintel_spi.o > NEED_PCI := yes > endif > > +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) > +FEATURE_CFLAGS += -D'CONFIG_NICINTEL_EEPROM=1' > +PROGRAMMER_OBJS += nicintel_eeprom.o > +NEED_PCI := yes > +endif > + > ifeq ($(CONFIG_OGP_SPI), yes) > FEATURE_CFLAGS += -D'CONFIG_OGP_SPI=1' > PROGRAMMER_OBJS += ogp_spi.o > diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl > index 0b4867d..153591a 100644 > --- a/flashrom.8.tmpl > +++ b/flashrom.8.tmpl > @@ -225,6 +225,8 @@ bitbanging adapter) > .sp > .BR "* usbblaster_spi" " (for SPI flash ROMs attached to an Altera USB-Blaster compatible cable)" > .sp > +.BR "* nicintel_eeprom" " (for SPI EEPROMs on Intel Gigabit network cards)" > +.sp > Some programmers have optional or mandatory parameters which are described > in detail in the > .B PROGRAMMER SPECIFIC INFO > @@ -591,7 +593,7 @@ syntax where > .B content > is an 8-bit hexadecimal value. > .SS > -.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel"\ > +.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\ > , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\ > , " satamv" , " atahpt" ", " atavia " and " it8212 " programmers > These programmers have an option to specify the PCI address of the card > @@ -625,6 +627,14 @@ For more information please see > .nh > .B http://flashrom.org/VT6421A > .SS > +.BR "nicintel_eeprom " programmer > +This is the first programmer module in flashrom that does not provide access to NOR flash chips but EEPROMs > +mounted on gigabit Ethernet cards based on Intel's 82580 NIC. Because EEPROMs normally do not announce their > +size nor allow to be identified, the controller relies on correct size values written to predefined addresses > +within the chip. Flashrom follows this scheme but assumes the minimum size of 16 kB (128 kb) if an unprogrammed > +EEPROM/card is detected. Intel specifies following EEPROMs to be compatible: Atmel AT25128, AT25256, Micron (ST) > +M95128, M95256 and OnSemi (Catalyst) CAT25CS128. > +.SS > .BR "ft2232_spi " programmer > An optional parameter specifies the controller > type and channel/interface/port it should support. For that you have to use the > @@ -922,8 +932,8 @@ need PCI configuration space access and raw memory access. > .B rayer_spi > needs raw I/O port access. > .sp > -.B satasii > -needs PCI configuration space read access and raw memory access. > +.BR satasii ", " nicintel ", " nicintel_eeprom " and " nicintel_spi > +need PCI configuration space read access and raw memory access. > .sp > .B satamv > needs PCI configuration space read access, raw I/O port access and raw memory > diff --git a/flashrom.c b/flashrom.c > index 83bc89a..fc8b073 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -297,6 +297,18 @@ const struct programmer_entry programmer_table[] = { > }, > #endif > > +#if CONFIG_NICINTEL_EEPROM == 1 > + { > + .name = "nicintel_eeprom", > + .type = PCI, > + .devs.dev = nics_intel_ee, > + .init = nicintel_ee_init, > + .map_flash_region = fallback_map, > + .unmap_flash_region = fallback_unmap, > + .delay = internal_delay, > + }, > +#endif > + > #if CONFIG_OGP_SPI == 1 > { > .name = "ogp_spi", > diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c > new file mode 100644 > index 0000000..44bc773 > --- /dev/null > +++ b/nicintel_eeprom.c > @@ -0,0 +1,331 @@ > +/* > + * This file is part of the flashrom project. > + * > + * Copyright (C) 2013 Ricardo Ribalda - Qtechnology A/S > + * Copyright (C) 2011, 2014 Stefan Tauner > + * > + * Based on nicinctel_spi.c and ichspi.c > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; version 2 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see http://www.gnu.org/licenses/. > + */ > + > +/* > + * Datasheet: Intel 82580 Quad/Dual Gigabit Ethernet LAN Controller Datasheet > + * 3.3.1.4: General EEPROM Software Access > + * 4.7: Access to shared resources (FIXME: we should probably use this semaphore interface) > + * 7.4: Register Descriptions > + */ > + > +#include <stdlib.h> > +#include <unistd.h> > +#include "flash.h" > +#include "spi.h" > +#include "programmer.h" > +#include "hwaccess.h" > + > +#define PCI_VENDOR_ID_INTEL 0x8086 > +#define MEMMAP_SIZE (0x14 + 3) /* Only EEC and EERD are needed. */ > + > +#define EEC 0x10 /* EEPROM/Flash Control Register */ > +#define EERD 0x14 /* EEPROM Read Register */ > + > +/* EPROM/Flash Control Register bits */ > +#define EE_SCK 0 > +#define EE_CS 1 > +#define EE_SI 2 > +#define EE_SO 3 > +#define EE_REQ 6 > +#define EE_GNT 7 > +#define EE_PRES 8 > +#define EE_SIZE 11 > +#define EE_SIZE_MASK 0xf > + > +/* EEPROM Read Register bits */ > +#define EERD_START 0 > +#define EERD_DONE 1 > +#define EERD_ADDR 2 > +#define EERD_DATA 16 > + > +#define BIT(x) (1<<x) > +#define PAGE_MASK 0x3f > + > +static uint8_t *nicintel_eebar; > +static struct pci_dev *nicintel_pci; > + > +#define UNPROG_DEVICE 0x1509 > + > +const struct dev_entry nics_intel_ee[] = { > + {PCI_VENDOR_ID_INTEL, 0x150e, OK, "Intel", "82580 Quad Gigabit Ethernet Controller (Copper)"}, > + {PCI_VENDOR_ID_INTEL, 0x150f, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Fiber)"}, > + {PCI_VENDOR_ID_INTEL, 0x1510, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Backplane)"}, > + {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Ext. PHY)"}, > + {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Dual Gigabit Ethernet Controller (Copper)"}, > + {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"}, > + {0}, > +}; > + > +static int nicintel_ee_probe(struct flashctx *flash) > +{ > + if (nicintel_pci->device_id == UNPROG_DEVICE) > + flash->chip->total_size = 16; /* Fall back to minimum supported size. */ > + else { > + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); > + tmp = ((tmp >> EE_SIZE) & EE_SIZE_MASK); > + switch (tmp) { > + case 7: > + flash->chip->total_size = 16; > + break; > + case 8: > + flash->chip->total_size = 32; > + break; > + default: > + msg_cerr("Unsupported chip size 0x%x\n", tmp); > + return 0; > + } > + } > + > + flash->chip->page_size = PAGE_MASK + 1; > + flash->chip->tested = TEST_OK_PREW; > + flash->chip->gran = write_gran_1byte_implicit_erase; > + flash->chip->block_erasers->eraseblocks[0].size = (PAGE_MASK + 1); > + flash->chip->block_erasers->eraseblocks[0].count = (flash->chip->total_size * 1024) / (PAGE_MASK + 1); > + > + return 1; > +} > + > +static int nicintel_ee_read_word(unsigned int addr, uint16_t *word) > +{ > + uint32_t tmp = BIT(EERD_START) | (addr << EERD_ADDR); > + pci_mmio_writel(tmp, nicintel_eebar + EERD); > + > + /* Poll done flag. 10.000.000 cycles seem to be enough. */ > + uint32_t i; > + for (i = 0; i < 10000000; i++) { > + tmp = pci_mmio_readl(nicintel_eebar + EERD); > + if (tmp & BIT(EERD_DONE)) { > + *word = (tmp >> EERD_DATA) & 0xffff; > + return 0; > + } > + } > + > + return -1; > +} > + > +static int nicintel_ee_read(struct flashctx *flash, uint8_t *buf, unsigned int addr, unsigned int len) > +{ > + uint16_t word; > + > + /* The NIC interface always reads 16 b words so we need to convert the address and handle odd address > + * explicitly at the start (and also at the end in the loop below). */ > + if (addr & 1) { > + if (nicintel_ee_read_word(addr / 2, &word)) > + return -1; > + *buf++ = word & 0xff; > + addr++; > + len--; > + } > + > + while (len > 0) { > + if (nicintel_ee_read_word(addr / 2, &word)) > + return -1; > + *buf++ = word & 0xff; > + addr++; > + len--; > + if (len > 0) { > + *buf++ = (word >> 8) & 0xff; > + addr++; > + len--; > + } > + } > + > + return 0; > +} > + > +static int nicintel_ee_bitset(int reg, int bit, bool val) > +{ > + uint32_t tmp; > + > + tmp = pci_mmio_readl(nicintel_eebar + reg); > + if (val) > + tmp |= BIT(bit); > + else > + tmp &= ~BIT(bit); > + pci_mmio_writel(tmp, nicintel_eebar + reg); > + > + return -1; > +} > + > +/* Shifts one byte out while receiving another one by bitbanging (denoted "direct access" in the datasheet). */ > +static int nicintel_ee_bitbang(uint8_t mosi, uint8_t *miso) > +{ > + uint8_t out = 0x0; > + > + int i; > + for (i = 7; i >= 0; i--) { > + nicintel_ee_bitset(EEC, EE_SI, mosi & BIT(i)); > + nicintel_ee_bitset(EEC, EE_SCK, 1); > + if (miso != NULL) { > + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); > + if (tmp & BIT(EE_SO)) > + out |= BIT(i); > + } > + nicintel_ee_bitset(EEC, EE_SCK, 0); > + } > + > + if (miso != NULL) > + *miso = out; > + > + return 0; > +} > + > +/* Polls the WIP bit of the status register of the attached EEPROM via bitbanging. */ > +static int nicintel_ee_ready(void) > +{ > + unsigned int i; > + for (i = 0; i < 1000; i++) { > + nicintel_ee_bitset(EEC, EE_CS, 0); > + > + nicintel_ee_bitbang(JEDEC_RDSR, NULL); > + uint8_t rdsr; > + nicintel_ee_bitbang(0x00, &rdsr); > + > + nicintel_ee_bitset(EEC, EE_CS, 1); > + programmer_delay(1); > + if (!(rdsr & SPI_SR_WIP)) { > + return 0; > + } > + } > + return -1; > +} > + > +/* Requests direct access to the SPI pins. */ > +static int nicintel_ee_req(void) > +{ > + uint32_t tmp; > + nicintel_ee_bitset(EEC, EE_REQ, 1); > + > + tmp = pci_mmio_readl(nicintel_eebar + EEC); > + if (!(tmp & BIT(EE_GNT))) { > + msg_perr("Enabling eeprom access failed.\n"); > + return 1; > + } > + > + nicintel_ee_bitset(EEC, EE_SCK, 0); > + return 0; > +} > + > +static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) > +{ > + if (nicintel_ee_req()) > + return -1; > + > + int ret = -1; > + if (nicintel_ee_ready()) > + goto out; > + > + while (len > 0) { > + /* WREN */ > + nicintel_ee_bitset(EEC, EE_CS, 0); > + nicintel_ee_bitbang(JEDEC_WREN, NULL); > + nicintel_ee_bitset(EEC, EE_CS, 1); > + programmer_delay(1); > + > + /* data */ > + nicintel_ee_bitset(EEC, EE_CS, 0); > + nicintel_ee_bitbang(JEDEC_BYTE_PROGRAM, NULL); > + nicintel_ee_bitbang((addr >> 8) & 0xff, NULL); > + nicintel_ee_bitbang(addr & 0xff, NULL); > + while (len > 0) { > + nicintel_ee_bitbang((buf) ? *buf++ : 0xff, NULL); > + len--; > + addr++; > + if (!(addr & PAGE_MASK)) > + break; > + } > + nicintel_ee_bitset(EEC, EE_CS, 1); > + programmer_delay(1); > + if (nicintel_ee_ready()) > + goto out; > + } > + ret = 0; > +out: > + nicintel_ee_bitset(EEC, EE_REQ, 0); /* Give up direct access. */ > + return ret; > +} > + > +static int nicintel_ee_erase(struct flashctx *flash, unsigned int addr, unsigned int len) > +{ > + return nicintel_ee_write(flash, NULL, addr, len); > +} > + > +static const struct opaque_master opaque_master_nicintel_ee = { > + .probe = nicintel_ee_probe, > + .read = nicintel_ee_read, > + .write = nicintel_ee_write, > + .erase = nicintel_ee_erase, > +}; > + > +static int nicintel_spi_shutdown(void *eecp) > +{ > + uint32_t old_eec = *(uint32_t *)eecp; > + /* Request bitbanging and unselect the chip first to be safe. */ > + if (nicintel_ee_req() || nicintel_ee_bitset(EEC, EE_CS, 1)) > + return -1; > + > + /* Try to restore individual bits we care about. */ > + int ret = nicintel_ee_bitset(EEC, EE_SCK, old_eec & BIT(EE_SCK)); > + ret |= nicintel_ee_bitset(EEC, EE_SI, old_eec & BIT(EE_SI)); > + ret |= nicintel_ee_bitset(EEC, EE_CS, old_eec & BIT(EE_CS)); > + /* REQ will be cleared by hardware anyway after 2 seconds of inactivity on the SPI pins (3.3.2.1). */ > + ret |= nicintel_ee_bitset(EEC, EE_REQ, old_eec & BIT(EE_REQ)); > + > + free(eecp); > + return ret; > +} > + > +int nicintel_ee_init(void) > +{ > + if (rget_io_perms()) > + return 1; > + > + struct pci_dev *dev = pcidev_init(nics_intel_ee, PCI_BASE_ADDRESS_0); > + if (!dev) > + return 1; > + > + uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); > + if (!io_base_addr) > + return 1; > + > + nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", io_base_addr, MEMMAP_SIZE); > + nicintel_pci = dev; > + if (dev->device_id != UNPROG_DEVICE) { > + uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); > + > + /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting the EE_PRES definition), > + * and 3.3.1.7 for possible recovery. */ > + if (!(eec & BIT(EE_PRES))) { > + msg_perr("Controller reports no EEPROM is present.\n"); > + return 1; > + } > + > + uint32_t *eecp = malloc(sizeof(uint32_t)); > + if (eecp == NULL) > + return 1; > + *eecp = eec; > + > + if (register_shutdown(nicintel_spi_shutdown, eecp)) > + return 1; > + } > + > + return register_opaque_master(&opaque_master_nicintel_ee); > +} > diff --git a/programmer.h b/programmer.h > index 093240b..3ad553a 100644 > --- a/programmer.h > +++ b/programmer.h > @@ -84,6 +84,9 @@ enum programmer { > #if CONFIG_NICINTEL_SPI == 1 > PROGRAMMER_NICINTEL_SPI, > #endif > +#if CONFIG_NICINTEL_EEPROM == 1 > + PROGRAMMER_NICINTEL_EEPROM, > +#endif > #if CONFIG_OGP_SPI == 1 > PROGRAMMER_OGP_SPI, > #endif > @@ -416,6 +419,12 @@ int nicintel_spi_init(void); > extern const struct dev_entry nics_intel_spi[]; > #endif > > +/* nicintel_eeprom.c */ > +#if CONFIG_NICINTEL_EEPROM == 1 > +int nicintel_ee_init(void); > +extern const struct dev_entry nics_intel_ee[]; > +#endif > + > /* ogp_spi.c */ > #if CONFIG_OGP_SPI == 1 > int ogp_spi_init(void); > -- > Kind regards, Stefan Tauner > -- Ricardo Ribalda

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[PATCH] Add new programmer for SPI EEPROMs attached to Intel 82580 NICs.
by Stefan Tauner 27 Jul '14

27 Jul '14

This patch lets you read and write the EEPROM on 82580-based gigabit NIC cards. So far it has been tested on copper NICs only, but other variants employing this controller should work too. It is a nice substitution for the official eeupdate tool. Speed is quite decent: less than 5 seconds for erases or writes. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- Rebased on r1831 because that breaks the previous version. Ricardo, if you don't have time or motivation to re-test this then please make a short note. I'll commit this patch then without any tested state, thanks. Makefile | 14 +++ flashrom.8.tmpl | 16 ++- flashrom.c | 12 ++ nicintel_eeprom.c | 331 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ programmer.h | 9 ++ 5 files changed, 379 insertions(+), 3 deletions(-) create mode 100644 nicintel_eeprom.c diff --git a/Makefile b/Makefile index 7a48889..64798c9 100644 --- a/Makefile +++ b/Makefile @@ -227,6 +227,11 @@ UNSUPPORTED_FEATURES += CONFIG_NICINTEL=yes else override CONFIG_NICINTEL = no endif +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) +UNSUPPORTED_FEATURES += CONFIG_NICINTEL_EEPROM=yes +else +override CONFIG_NICINTEL_EEPROM = no +endif ifeq ($(CONFIG_NICINTEL_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_NICINTEL_SPI=yes else @@ -426,6 +431,9 @@ CONFIG_NICINTEL ?= yes # Always enable SPI on Intel NICs for now. CONFIG_NICINTEL_SPI ?= yes +# Always enable EEPROM on Intel NICs for now. +CONFIG_NICINTEL_EEPROM ?= yes + # Always enable SPI on OGP cards for now. CONFIG_OGP_SPI ?= yes @@ -626,6 +634,12 @@ PROGRAMMER_OBJS += nicintel_spi.o NEED_PCI := yes endif +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) +FEATURE_CFLAGS += -D'CONFIG_NICINTEL_EEPROM=1' +PROGRAMMER_OBJS += nicintel_eeprom.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_OGP_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_OGP_SPI=1' PROGRAMMER_OBJS += ogp_spi.o diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 0b4867d..153591a 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -225,6 +225,8 @@ bitbanging adapter) .sp .BR "* usbblaster_spi" " (for SPI flash ROMs attached to an Altera USB-Blaster compatible cable)" .sp +.BR "* nicintel_eeprom" " (for SPI EEPROMs on Intel Gigabit network cards)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER SPECIFIC INFO @@ -591,7 +593,7 @@ syntax where .B content is an 8-bit hexadecimal value. .SS -.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel"\ +.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\ , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\ , " satamv" , " atahpt" ", " atavia " and " it8212 " programmers These programmers have an option to specify the PCI address of the card @@ -625,6 +627,14 @@ For more information please see .nh .B http://flashrom.org/VT6421A .SS +.BR "nicintel_eeprom " programmer +This is the first programmer module in flashrom that does not provide access to NOR flash chips but EEPROMs +mounted on gigabit Ethernet cards based on Intel's 82580 NIC. Because EEPROMs normally do not announce their +size nor allow to be identified, the controller relies on correct size values written to predefined addresses +within the chip. Flashrom follows this scheme but assumes the minimum size of 16 kB (128 kb) if an unprogrammed +EEPROM/card is detected. Intel specifies following EEPROMs to be compatible: Atmel AT25128, AT25256, Micron (ST) +M95128, M95256 and OnSemi (Catalyst) CAT25CS128. +.SS .BR "ft2232_spi " programmer An optional parameter specifies the controller type and channel/interface/port it should support. For that you have to use the @@ -922,8 +932,8 @@ need PCI configuration space access and raw memory access. .B rayer_spi needs raw I/O port access. .sp -.B satasii -needs PCI configuration space read access and raw memory access. +.BR satasii ", " nicintel ", " nicintel_eeprom " and " nicintel_spi +need PCI configuration space read access and raw memory access. .sp .B satamv needs PCI configuration space read access, raw I/O port access and raw memory diff --git a/flashrom.c b/flashrom.c index 83bc89a..fc8b073 100644 --- a/flashrom.c +++ b/flashrom.c @@ -297,6 +297,18 @@ const struct programmer_entry programmer_table[] = { }, #endif +#if CONFIG_NICINTEL_EEPROM == 1 + { + .name = "nicintel_eeprom", + .type = PCI, + .devs.dev = nics_intel_ee, + .init = nicintel_ee_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + #if CONFIG_OGP_SPI == 1 { .name = "ogp_spi", diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c new file mode 100644 index 0000000..44bc773 --- /dev/null +++ b/nicintel_eeprom.c @@ -0,0 +1,331 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2013 Ricardo Ribalda - Qtechnology A/S + * Copyright (C) 2011, 2014 Stefan Tauner + * + * Based on nicinctel_spi.c and ichspi.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +/* + * Datasheet: Intel 82580 Quad/Dual Gigabit Ethernet LAN Controller Datasheet + * 3.3.1.4: General EEPROM Software Access + * 4.7: Access to shared resources (FIXME: we should probably use this semaphore interface) + * 7.4: Register Descriptions + */ + +#include <stdlib.h> +#include <unistd.h> +#include "flash.h" +#include "spi.h" +#include "programmer.h" +#include "hwaccess.h" + +#define PCI_VENDOR_ID_INTEL 0x8086 +#define MEMMAP_SIZE (0x14 + 3) /* Only EEC and EERD are needed. */ + +#define EEC 0x10 /* EEPROM/Flash Control Register */ +#define EERD 0x14 /* EEPROM Read Register */ + +/* EPROM/Flash Control Register bits */ +#define EE_SCK 0 +#define EE_CS 1 +#define EE_SI 2 +#define EE_SO 3 +#define EE_REQ 6 +#define EE_GNT 7 +#define EE_PRES 8 +#define EE_SIZE 11 +#define EE_SIZE_MASK 0xf + +/* EEPROM Read Register bits */ +#define EERD_START 0 +#define EERD_DONE 1 +#define EERD_ADDR 2 +#define EERD_DATA 16 + +#define BIT(x) (1<<x) +#define PAGE_MASK 0x3f + +static uint8_t *nicintel_eebar; +static struct pci_dev *nicintel_pci; + +#define UNPROG_DEVICE 0x1509 + +const struct dev_entry nics_intel_ee[] = { + {PCI_VENDOR_ID_INTEL, 0x150e, OK, "Intel", "82580 Quad Gigabit Ethernet Controller (Copper)"}, + {PCI_VENDOR_ID_INTEL, 0x150f, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Fiber)"}, + {PCI_VENDOR_ID_INTEL, 0x1510, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Backplane)"}, + {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Ext. PHY)"}, + {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Dual Gigabit Ethernet Controller (Copper)"}, + {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"}, + {0}, +}; + +static int nicintel_ee_probe(struct flashctx *flash) +{ + if (nicintel_pci->device_id == UNPROG_DEVICE) + flash->chip->total_size = 16; /* Fall back to minimum supported size. */ + else { + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); + tmp = ((tmp >> EE_SIZE) & EE_SIZE_MASK); + switch (tmp) { + case 7: + flash->chip->total_size = 16; + break; + case 8: + flash->chip->total_size = 32; + break; + default: + msg_cerr("Unsupported chip size 0x%x\n", tmp); + return 0; + } + } + + flash->chip->page_size = PAGE_MASK + 1; + flash->chip->tested = TEST_OK_PREW; + flash->chip->gran = write_gran_1byte_implicit_erase; + flash->chip->block_erasers->eraseblocks[0].size = (PAGE_MASK + 1); + flash->chip->block_erasers->eraseblocks[0].count = (flash->chip->total_size * 1024) / (PAGE_MASK + 1); + + return 1; +} + +static int nicintel_ee_read_word(unsigned int addr, uint16_t *word) +{ + uint32_t tmp = BIT(EERD_START) | (addr << EERD_ADDR); + pci_mmio_writel(tmp, nicintel_eebar + EERD); + + /* Poll done flag. 10.000.000 cycles seem to be enough. */ + uint32_t i; + for (i = 0; i < 10000000; i++) { + tmp = pci_mmio_readl(nicintel_eebar + EERD); + if (tmp & BIT(EERD_DONE)) { + *word = (tmp >> EERD_DATA) & 0xffff; + return 0; + } + } + + return -1; +} + +static int nicintel_ee_read(struct flashctx *flash, uint8_t *buf, unsigned int addr, unsigned int len) +{ + uint16_t word; + + /* The NIC interface always reads 16 b words so we need to convert the address and handle odd address + * explicitly at the start (and also at the end in the loop below). */ + if (addr & 1) { + if (nicintel_ee_read_word(addr / 2, &word)) + return -1; + *buf++ = word & 0xff; + addr++; + len--; + } + + while (len > 0) { + if (nicintel_ee_read_word(addr / 2, &word)) + return -1; + *buf++ = word & 0xff; + addr++; + len--; + if (len > 0) { + *buf++ = (word >> 8) & 0xff; + addr++; + len--; + } + } + + return 0; +} + +static int nicintel_ee_bitset(int reg, int bit, bool val) +{ + uint32_t tmp; + + tmp = pci_mmio_readl(nicintel_eebar + reg); + if (val) + tmp |= BIT(bit); + else + tmp &= ~BIT(bit); + pci_mmio_writel(tmp, nicintel_eebar + reg); + + return -1; +} + +/* Shifts one byte out while receiving another one by bitbanging (denoted "direct access" in the datasheet). */ +static int nicintel_ee_bitbang(uint8_t mosi, uint8_t *miso) +{ + uint8_t out = 0x0; + + int i; + for (i = 7; i >= 0; i--) { + nicintel_ee_bitset(EEC, EE_SI, mosi & BIT(i)); + nicintel_ee_bitset(EEC, EE_SCK, 1); + if (miso != NULL) { + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); + if (tmp & BIT(EE_SO)) + out |= BIT(i); + } + nicintel_ee_bitset(EEC, EE_SCK, 0); + } + + if (miso != NULL) + *miso = out; + + return 0; +} + +/* Polls the WIP bit of the status register of the attached EEPROM via bitbanging. */ +static int nicintel_ee_ready(void) +{ + unsigned int i; + for (i = 0; i < 1000; i++) { + nicintel_ee_bitset(EEC, EE_CS, 0); + + nicintel_ee_bitbang(JEDEC_RDSR, NULL); + uint8_t rdsr; + nicintel_ee_bitbang(0x00, &rdsr); + + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + if (!(rdsr & SPI_SR_WIP)) { + return 0; + } + } + return -1; +} + +/* Requests direct access to the SPI pins. */ +static int nicintel_ee_req(void) +{ + uint32_t tmp; + nicintel_ee_bitset(EEC, EE_REQ, 1); + + tmp = pci_mmio_readl(nicintel_eebar + EEC); + if (!(tmp & BIT(EE_GNT))) { + msg_perr("Enabling eeprom access failed.\n"); + return 1; + } + + nicintel_ee_bitset(EEC, EE_SCK, 0); + return 0; +} + +static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) +{ + if (nicintel_ee_req()) + return -1; + + int ret = -1; + if (nicintel_ee_ready()) + goto out; + + while (len > 0) { + /* WREN */ + nicintel_ee_bitset(EEC, EE_CS, 0); + nicintel_ee_bitbang(JEDEC_WREN, NULL); + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + + /* data */ + nicintel_ee_bitset(EEC, EE_CS, 0); + nicintel_ee_bitbang(JEDEC_BYTE_PROGRAM, NULL); + nicintel_ee_bitbang((addr >> 8) & 0xff, NULL); + nicintel_ee_bitbang(addr & 0xff, NULL); + while (len > 0) { + nicintel_ee_bitbang((buf) ? *buf++ : 0xff, NULL); + len--; + addr++; + if (!(addr & PAGE_MASK)) + break; + } + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + if (nicintel_ee_ready()) + goto out; + } + ret = 0; +out: + nicintel_ee_bitset(EEC, EE_REQ, 0); /* Give up direct access. */ + return ret; +} + +static int nicintel_ee_erase(struct flashctx *flash, unsigned int addr, unsigned int len) +{ + return nicintel_ee_write(flash, NULL, addr, len); +} + +static const struct opaque_master opaque_master_nicintel_ee = { + .probe = nicintel_ee_probe, + .read = nicintel_ee_read, + .write = nicintel_ee_write, + .erase = nicintel_ee_erase, +}; + +static int nicintel_spi_shutdown(void *eecp) +{ + uint32_t old_eec = *(uint32_t *)eecp; + /* Request bitbanging and unselect the chip first to be safe. */ + if (nicintel_ee_req() || nicintel_ee_bitset(EEC, EE_CS, 1)) + return -1; + + /* Try to restore individual bits we care about. */ + int ret = nicintel_ee_bitset(EEC, EE_SCK, old_eec & BIT(EE_SCK)); + ret |= nicintel_ee_bitset(EEC, EE_SI, old_eec & BIT(EE_SI)); + ret |= nicintel_ee_bitset(EEC, EE_CS, old_eec & BIT(EE_CS)); + /* REQ will be cleared by hardware anyway after 2 seconds of inactivity on the SPI pins (3.3.2.1). */ + ret |= nicintel_ee_bitset(EEC, EE_REQ, old_eec & BIT(EE_REQ)); + + free(eecp); + return ret; +} + +int nicintel_ee_init(void) +{ + if (rget_io_perms()) + return 1; + + struct pci_dev *dev = pcidev_init(nics_intel_ee, PCI_BASE_ADDRESS_0); + if (!dev) + return 1; + + uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; + + nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", io_base_addr, MEMMAP_SIZE); + nicintel_pci = dev; + if (dev->device_id != UNPROG_DEVICE) { + uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); + + /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting the EE_PRES definition), + * and 3.3.1.7 for possible recovery. */ + if (!(eec & BIT(EE_PRES))) { + msg_perr("Controller reports no EEPROM is present.\n"); + return 1; + } + + uint32_t *eecp = malloc(sizeof(uint32_t)); + if (eecp == NULL) + return 1; + *eecp = eec; + + if (register_shutdown(nicintel_spi_shutdown, eecp)) + return 1; + } + + return register_opaque_master(&opaque_master_nicintel_ee); +} diff --git a/programmer.h b/programmer.h index 093240b..3ad553a 100644 --- a/programmer.h +++ b/programmer.h @@ -84,6 +84,9 @@ enum programmer { #if CONFIG_NICINTEL_SPI == 1 PROGRAMMER_NICINTEL_SPI, #endif +#if CONFIG_NICINTEL_EEPROM == 1 + PROGRAMMER_NICINTEL_EEPROM, +#endif #if CONFIG_OGP_SPI == 1 PROGRAMMER_OGP_SPI, #endif @@ -416,6 +419,12 @@ int nicintel_spi_init(void); extern const struct dev_entry nics_intel_spi[]; #endif +/* nicintel_eeprom.c */ +#if CONFIG_NICINTEL_EEPROM == 1 +int nicintel_ee_init(void); +extern const struct dev_entry nics_intel_ee[]; +#endif + /* ogp_spi.c */ #if CONFIG_OGP_SPI == 1 int ogp_spi_init(void); -- Kind regards, Stefan Tauner

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flashrom July 2014