flashrom March 2014

flashrom@flashrom.org

41 participants
124 discussions

[PATCH] CID1130000: Unchecked return value
by Stefan Reinauer 26 Apr '14

26 Apr '14

CID1130000: Unchecked return value If the function returns an error value, the error value may be mistaken for a normal value. In default_spi_write_aai: Value returned from a function is not checked for errors before being used Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Index: spi25.c =================================================================== --- spi25.c (revision 1763) +++ spi25.c (working copy) @@ -1146,8 +1146,10 @@ while (pos < start + len - 1) { cmd[1] = buf[pos++ - start]; cmd[2] = buf[pos++ - start]; - spi_send_command(flash, JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, - cmd, NULL); + result = spi_send_command(flash, JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, + 0, cmd, NULL); + if (result != 0) + msg_cerr("%s failed.\n", __func__); while (spi_read_status_register(flash) & SPI_SR_WIP) programmer_delay(10); }

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[PATCH] CID1130006: Resource leak
by Stefan Reinauer 26 Apr '14

26 Apr '14

CID1130006: Resource leak The system resource will not be reclaimed and reused, reducing the future availability of the resource. In buspirate_spi_init: Leak of memory or pointers to system resources Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Index: buspirate_spi.c =================================================================== --- buspirate_spi.c (revision 1763) +++ buspirate_spi.c (working copy) @@ -250,6 +250,7 @@ if (!bp_commbuf) { bp_commbufsize = 0; msg_perr("Out of memory!\n"); + free(dev); return ERROR_OOM; } bp_commbufsize = DEFAULT_BUFSIZE;

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[PATCH] CID1130002: Logically dead code
by Stefan Reinauer 26 Apr '14

26 Apr '14

CID1130002: Logically dead code The indicated dead code may have performed some action; that action will never occur. In satamv_init: Code can never be reached because of a logical contradiction What we really want to do is check whether PCI_BASE_ADDRESS_2 is valid at this point, and not PCI_BASE_ADDRESS_0. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Index: satamv.c =================================================================== --- satamv.c (revision 1763) +++ satamv.c (working copy) @@ -139,7 +139,7 @@ /* Get I/O BAR location. */ tmp = pcidev_readbar(dev, PCI_BASE_ADDRESS_2); - if (!addr) + if (!tmp) return 1; /* Truncate to reachable range.

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Re: [flashrom] error reporting
by Idwer Vollering 30 Mar '14

30 Mar '14

2014-03-30 14:28 GMT+02:00 Adam Vegh <devilke(a)zioncity.hu>: > Erase/write done. > Verifying flash... FAILED at 0x0055bc8b! Expected=0x71, Found=0x48, failed > byte count from 0x00000000-0x007fffff: 0x217dbe > Your flash chip is in an unknown state. Hello Adam, Can you supply all output (like which version of flashrom errors out on which chipset and mainboard)? Run flashrom with at least one level of verbosity, add a -V parameter. Newer versions of flashrom can save output to a file with '-o <name of logfile>'. HTH, Idwer

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error reporting
by Adam Vegh 30 Mar '14

30 Mar '14

Erase/write done. Verifying flash... FAILED at 0x0055bc8b! Expected=0x71, Found=0x48, failed byte count from 0x00000000-0x007fffff: 0x217dbe Your flash chip is in an unknown state. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks!

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Donation
by GJ 29 Mar '14

29 Mar '14

Hi, With the help of stefanct I successfully used flashrom to dump and write data on a bricked BIOS and thus reviving a laptop, I am willing to donate a small amount of money as a sign of gratitude, to your project. This Is a Great, free, tool. I can send like, 20€. Paypal would be nice. Regards, Silkut

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HM77 probe, read, write OK
by Vasiliy Vylegzhanin 27 Mar '14

27 Mar '14

flashrom code is slightly modified for region write and predefined ICH descriptor regions, but chipset-related code is vanilla. In fact, only flashrom.c and layout.c is patched.

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MCP73M01H1: flashrom -V
by Alister Hood 27 Mar '14

27 Mar '14

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flashrom-related GSoC 2014 project
by Stefan Tauner 26 Mar '14

26 Mar '14

Hi everyone, I will attempt to participate as a student again - and of course my project should be something very closely related to flashrom to exploit my knowledge in that area. I have already submitted a first alpha-stage proposal that basically includes the standard repertoire of things I do while working on flashrom in general, and also which I ended up doing in the past GSoC projects. Namely a mixture of maintenance, improvement and integration of existing patches, development of new features for flashrom. For me that worked out well and I believe it was very good for flashrom and worthwhile for the coreboot community as a whole too. I have not received too much feedback so I am not sure if everybody agrees with that and thinks that another such summer would be a good thing as well (if there are other candidates and/or proposals to choose from). If you think the GSoC slots of coreboot deserve something better, or more project-like then I could also try to work on something more confined/focused. There are a number of project ideas that might fit my profile quite well. The "End user flash tool" proposal would allow me to eventually finish libflashrom and the layout patches, maybe clean up the bios_extract repository and help those users that are fighting with vgabios extractions etc. :) Then there is the panic room idea which AFAIK is not finished and has some room for improvements, but I am not sure about its current state and if Kyösti wants to work on that this year...? Somehow related to both points above is an idea for a project I had for some time. A coreboot payload (probably)... for user flash updates that verifies a cryptographically signed image before flashing it. While currently this is relatively useless it might become interesting for distributing libreboot binary images for example. (even though I have to admit it is a bit ironic to ship binary images of a firmware that is blobfree :) IIRC the Chromebooks have a write-protected primary loader that verifies the remaining firmware etc... basically what secure boot demands. That solves a similar problem, but recovery for an end user is way more unpleasant than getting warned early before any modifications are done. Another advantage would be to have an OS-independent update mechanism... OTOH flashrom runs on every OS I deem worthy to run coreboot. :) The last project idea to be mentioned here that suits me well is what David proposed last year, see his post for details: http://www.flashrom.org/pipermail/flashrom/2013-March/010704.html So... I would be glad to get your feedback. What do you think would help us most? Do you have other ideas/wishes related to flashrom? I don't care too much on which project I work... they are all worthwhile IMHO. My preference would be to work freely on flashrom itself because it really needs it (there is no one else doing it) and I have the most knowledge in that field. But OTOH I can learn much more in every other project mentioned above and that's also very motivating. Naturally, I don't want to write multiple proposals if we can agree on one topic already... and time is rather short too :) PS: I have an asrock imb-180-h, an SPI programmer and lots of flash chips available to tinker with. There is also some ancient intel BX-based PC somewhere that I could port... I'd need to build a parallel flasher for that first though (cortex m3 board and stuff already collecting dust...) but that would probably be based on serprog and peter would veto for sure ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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W836xx: MSI 865PE Neo2-PLS (601-6728-100) : flashrom -V
by Glen Christensen 26 Mar '14

26 Mar '14

root@sysresccd /root % flashrom -V -p internal flashrom v0.9.6.1-r1564 on Linux 3.10.32-std410-i586 (i686) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.1, GCC 4.4.7, little endian Command line (3 args): flashrom -V -p internal Calibrating delay loop... OS timer resolution is 1 usecs, 1643M loops per second, 10 myus = 11 us, 100 myus = 98 us, 1000 myus = 980 us, 10000 myus = 9886 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "MICRO-STAR INC." DMI string system-product-name: "MS-6728" DMI string system-version: "2.00" DMI string baseboard-manufacturer: "MICRO-STAR INC." DMI string baseboard-product-name: "MS-6728" DMI string baseboard-version: "2.00" DMI string chassis-type: "Desktop" Found Winbond Super I/O, id 82 W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: f7. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found chipset "Intel ICH5/ICH5R" with PCI ID 8086:24d0. Enabling flash write... BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 OK. The following protocols are supported: FWH. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x38, id2 0x9b, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Found SST flash chip "SST49LF004A/B" (512 kB, FWH) at physical address 0xfff80000. Lock status for 0x000000 (size 0x010000) is 00, full access Lock status for 0x010000 (size 0x010000) is 00, full access Lock status for 0x020000 (size 0x010000) is 00, full access Lock status for 0x030000 (size 0x010000) is 00, full access Lock status for 0x040000 (size 0x010000) is 00, full access Lock status for 0x050000 (size 0x010000) is 00, full access Lock status for 0x060000 (size 0x010000) is 00, full access Lock status for 0x070000 (size 0x010000) is 00, full access Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x38, id2 0x9b, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xbf, id2 0x60 Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xbf, id2 0x60 Found SST flash chip "SST49LF004A/B" (512 kB, FWH). No operations were specified. Restoring PCI config space for 00:1f:0 reg 0x4e root@sysresccd /root %

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flashrom March 2014