flashrom March 2014

flashrom@flashrom.org

41 participants
124 discussions

Re: [flashrom] GSoC-2014 Flashrom project "Locking and unlocking of access protections of flash chips"
by David Hendricks 19 Mar '14

19 Mar '14

On Wed, Mar 19, 2014 at 5:58 AM, Allen Yan <lexkde(a)gmail.com> wrote: > Hi, David, > I was reading flashrom code base following the internal programmer > way. I also read mail > "http://www.flashrom.org/pipermail/flashrom/2013-March/010704.html" > and checked the Ibex peak datasheet about ME firmware. Here are some > questions: > about "Locking and unlocking of access protections of flash chips" > 1 which mechanism locks the flash?a software way or a hardware way > by the programmer. As in the Atmel AT25DL161, the protection ways are > "hardware protection, using WP pin", "Sector lockdown with permanent > freeze option", "individual sector protection with global > protect/unprotect feature". > All of the above :-) You will need to determine: - Which write-protection scheme is in place? Is it intended to prevent erroneous software from writing to the flash, or is it intended to prevent any re-writing of the flash? - Can it be disabled / worked around so that content can be updated? - How to restore the settings when you are finished. > 2 Does this problem concerns the ME firmware issue. > Yes. > 3 How to do the test? Is the test at specific mainboard and flash chip > enough? > IIRC Flashrom already tests for motherboards which are known to require a workaround, for example if a GPIO must be inverted in order to de-assert /WP. board_enable.c has many of these tests. It also knows about block protect bits in SPI ROMs. I think the main issue with modern systems (Intel in particular) is the management engine. > 4 How to value the work at last as stefan mentioned in the suggestion? > > > Actually, a little frustrating after I saw stefanct's mail. > It's very valuable :-) I put some effort into this functionality for ChromeOS, since handling write-protection is a requirement for Chromebooks. Here are some examples: Skip regions locked via flash descriptor for Intel platforms: https://chromium.googlesource.com/chromiumos/third_party/flashrom/+/1ed1d35… writeprotect.c, which contains block protect mapping for several flash chips: https://chromium.googlesource.com/chromiumos/third_party/flashrom/+/master/… Unfortunately we never reached a consensus regarding how to port this code to upstream. It would be nice if somebody like you can help to re-factor this code so that it can be accepted upstream. > On 3/18/14, Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > > On Mon, 17 Mar 2014 09:56:43 +0800 > > 严进一 <lexkde(a)gmail.com> wrote: > > > >> Hi, > >> I am Jinyi Yan , a second year PhD candidate from Shanghai Institute of > >> Micro-system and Information Technology, Chinese Academy of Sciences. I > >> used to be a mainboard BIOS engineer in ASUS Technology Suzhou Co., Ltd > >> for about two years (2007.7~2009.2). My major now is optoelectronics. > But > >> I have a lot of fun while programming, in my heart the working > experience > >> of being a BIOS engineer is still very exciting. > >> I think GsoC is a nice platform for me to participate the open source > >> community. When I search the GsoC projects and organizations, the > coreboot > >> and flashrom projects are definitely the right choices for me. I have a > >> spare ASUS P5KPL PC at my hand, but the chipset is not in the support > list > >> of coreboot project. So I consider the flashrom project is the better > >> choice. I also have a home-made flash programmer based on uspasp. > >> I'd like to choose “Locking and unlocking of access protections of flash > >> chips” for GSoC 2014. > >> Now I'm not very familiar with the program structure of flashrom, so I > >> expect your guidence and hope to contribute for flashrom and coreboot > even > >> if my application is not accpeted. > >> Thanks! Look forward to your kind advice! > > > > Hello Jinyi, > > > > thanks for your interest in flashrom. I have been the most active > > flashrom developer in the last years and would probably be responsible > > to integrate your work and answer questions if you get stuck. I agree > > that the coreboot-related projects are probably the best choice for you > > (there are not many low-level projects participating sadly... that's > > how I ended up here too ;). I also have to admit that the P5KPL is > > probably not very helpful AFAICT. But I don't think that this is a show > > stopper regarding coreboot (or seabios) projects and that your skills > > and insights obtained at ASUS regarding x86 might be more useful in a > > non-flashrom project. Also, the project you chose requires to > > understand two code bases ("ours" and that maintained by google/ > > chromiumos ppl) and interact with two communities and persuade at least > > one of them that your solution is sound and profitable. On the other > > hand, I am biased because I will apply for a flashrom GSoC project > > myself probably. ;) > > The code bases have a very similar core so that should not be a big > > issue at all. Producing something that will be praised by everyone on > > the other hand is really hard. The vanilla flashrom community is > > traditionally very (very) picky regarding changes, especially user > > interface changes. This is also the reason why there is a chromiumos > > fork of flashrom... > > > > I have talked to David (dhendrix) and he is willing to mentor you this > > year. If you want to pursue this project (and the patch you sent seems > > to indicate that ;) I suggest you talk to him directly about details > > of the assignment (here or on IRC). > > > > Adding new flash chips as you have done is a very good first step to > > get to know flashrom a bit better. The fun begins with the awkward > > models though :) > > I suggest you test flashrom on any hardware available to you (including > > network cards for example)... there is always room for improvement and > > learning a foreign code base is always easier when on has a specific > > goal to reach. > > -- > > Kind regards/Mit freundlichen Grüßen, Stefan Tauner > > > > _______________________________________________ > > flashrom mailing list > > flashrom(a)flashrom.org > > http://www.flashrom.org/mailman/listinfo/flashrom > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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FAILED: PCENGINES APU
by markus 19 Mar '14

19 Mar '14

C:\>flashrom -p internal:laptop=this_is_not_a_laptop -c MX25L1605A/MX25L1606E -w APUBIO.ROM flashrom v0.9.6.1-r1705 on FreeDOS 7 (i786) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... delay loop is unreliable, trying to continue OK. pcilib: Bus 00 seen twice (firmware bug). Ignored. coreboot table found at 0x7e17cc00. Bad command or filename - "dmidecode". Bad command or filename - "dmidecode". Bad command or filename - "dmidecode". Bad command or filename - "dmidecode". Bad command or filename - "dmidecode". Bad command or filename - "dmidecode". Bad command or filename - "dmidecode". ======================================================================== WARNING! You may be running flashrom on an unsupported laptop. We could not detect this for sure because your vendor has not setup the SMBIOS tables correctly. You can enforce execution by adding '-p internal:laptop=this_is_not_a_laptop' to the command line, but please read the following warning if you are not sure. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See the manpage and http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Proceeding anyway because user forced us to. Found chipset "AMD SB7x0/SB8x0/SB9x0". Enabling flash write... OK. Found Macronix flash chip "MX25L1605A/MX25L1606E" (2048 kB, SPI) at physical address 0xffe00000. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... FAILED at 0x00000000! Expected=0x4c, Found=0xcc, failed byte count from 0x00000000-0x001fffff: 0xe2a0 Your flash chip is in an unknown state. Get help on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! -- Best regards, Markus Better Privacy with PGP encrypted Mail: http://activezone.de/pgp/ Fingerprint: 58C5 8BAF 6FCE B24F 1881 B5B8 F2A8 E1D0 484B 0054 Threema ID: 7ZRET2JY „Wer die Freiheit aufgibt um Sicherheit zu gewinnen, der wird am Ende beides verlieren.“ -- Benjamin Franklin

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[commit] r1769 - trunk
by repository service 19 Mar '14

19 Mar '14

Author: stefanct Date: Wed Mar 19 18:17:06 2014 New Revision: 1769 URL: http://flashrom.org/trac/flashrom/changeset/1769 Log: linux_spi: Stop messing up the units of SPI speed. 'speed' is stored in Hz, so rename the variable to 'speed_hz' to clarify any potential confusion. Also, when printing the speed after setting it with an ioctl, convert it to kHz to match the units given in the message. Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/linux_spi.c Modified: trunk/linux_spi.c ============================================================================== --- trunk/linux_spi.c Wed Mar 19 18:17:00 2014 (r1768) +++ trunk/linux_spi.c Wed Mar 19 18:17:06 2014 (r1769) @@ -60,7 +60,7 @@ int linux_spi_init(void) { char *p, *endp, *dev; - uint32_t speed = 0; + uint32_t speed_hz = 0; /* FIXME: make the following configurable by CLI options. */ /* SPI mode 0 (beware this also includes: MSB first, CS active low and others */ const uint8_t mode = SPI_MODE_0; @@ -68,7 +68,7 @@ p = extract_programmer_param("spispeed"); if (p && strlen(p)) { - speed = (uint32_t)strtoul(p, &endp, 10) * 1000; + speed_hz = (uint32_t)strtoul(p, &endp, 10) * 1000; if (p == endp) { msg_perr("%s: invalid clock: %s kHz\n", __func__, p); free(p); @@ -98,14 +98,14 @@ return 1; /* We rely on the shutdown function for cleanup from here on. */ - if (speed > 0) { - if (ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed) == -1) { + if (speed_hz > 0) { + if (ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed_hz) == -1) { msg_perr("%s: failed to set speed to %d Hz: %s\n", - __func__, speed, strerror(errno)); + __func__, speed_hz, strerror(errno)); return 1; } - msg_pdbg("Using %d kHz clock\n", speed); + msg_pdbg("Using %d kHz clock\n", speed_hz/1000); } if (ioctl(fd, SPI_IOC_WR_MODE, &mode) == -1) {

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[commit] r1768 - trunk
by repository service 19 Mar '14

19 Mar '14

Author: stefanct Date: Wed Mar 19 18:17:00 2014 New Revision: 1768 URL: http://flashrom.org/trac/flashrom/changeset/1768 Log: linux_spi: Fix conversion from kHz to Hz. A kilohertz is exactly 1000 hertz, not 1024 hertz. Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/linux_spi.c Modified: trunk/linux_spi.c ============================================================================== --- trunk/linux_spi.c Mon Mar 17 23:07:29 2014 (r1767) +++ trunk/linux_spi.c Wed Mar 19 18:17:00 2014 (r1768) @@ -68,7 +68,7 @@ p = extract_programmer_param("spispeed"); if (p && strlen(p)) { - speed = (uint32_t)strtoul(p, &endp, 10) * 1024; + speed = (uint32_t)strtoul(p, &endp, 10) * 1000; if (p == endp) { msg_perr("%s: invalid clock: %s kHz\n", __func__, p); free(p);

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Intel S5000PAL: Flash Not Found
by Sean Everson 19 Mar '14

19 Mar '14

*All,I have a number of Intel S5000PAL motherboards that I would like to use FLASHROM to manage if at all possible. According to the Intel Docs at:http://download.intel.com/support/motherboards/server/s5000pal/sb/s5000p… <http://download.intel.com/support/motherboards/server/s5000pal/sb/s5000pal_…>The box contains the 6321ESB chipset which is listed as supported on the flashrom.org <http://flashrom.org> wiki page.When I try to use FLASHROM to read the flash I get an error message that the flash is not found. Can someone provide me with some guidance on what additional information or steps I can take to investigate this further?I am including the output from flashrom -V below.Thanks for your help!--Sean# ./flashrom -V -p internal -r /tmp/bios.binflashrom v0.9.7-r1764 on Linux 2.6.32.24 (x86_64)flashrom is free software, get the source code at http://www.flashrom.org <http://www.flashrom.org>flashrom was built with libpci 3.2.1, GCC 4.7.1, little endianCommand line (5 args): ./flashrom -V -p internal -r /tmp/bios.binCalibrating delay loop... OS timer resolution is 1 usecs, 2824M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 999 us, 10000 myus = 10025 us, 4 myus = 4 us, OK.Initializing internal programmerNo coreboot table found.Using Internal DMI decoder.DMI string chassis-type: "Rack Mount Chassis"DMI string system-manufacturer: "Intel"DMI string system-product-name: "T5000PAL"DMI string system-version: "Not Specified"DMI string baseboard-manufacturer: "Intel"DMI string baseboard-product-name: "T5000PAL0 "DMI string baseboard-version: "FRU Ver 0.05"W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect.Active config mode, unknown reg 0x20 ID: f2.Please send the output of "flashrom -V" to flashrom(a)flashrom.org <flashrom(a)flashrom.org> with W836xx: your board name: flashrom -Vas the subject to help us finish support for your Super I/O. Thanks.Found chipset "Intel 631xESB/632xESB/3100" with PCI ID 8086:2670. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x00xfff00000/0xffb00000 FWH IDSEL: 0x00xffe80000/0xffa80000 FWH IDSEL: 0x00xffe00000/0xffa00000 FWH IDSEL: 0x00xffd80000/0xff980000 FWH IDSEL: 0x00xffd00000/0xff900000 FWH IDSEL: 0x00xffc80000/0xff880000 FWH IDSEL: 0x00xffc00000/0xff800000 FWH IDSEL: 0x00xff700000/0xff300000 FWH IDSEL: 0x40xff600000/0xff200000 FWH IDSEL: 0x50xff500000/0xff100000 FWH IDSEL: 0x60xff400000/0xff000000 FWH IDSEL: 0x70xfff80000/0xffb80000 FWH decode enabled0xfff00000/0xffb00000 FWH decode enabled0xffe80000/0xffa80000 FWH decode enabled0xffe00000/0xffa00000 FWH decode enabled0xffd80000/0xff980000 FWH decode enabled0xffd00000/0xff900000 FWH decode enabled0xffc80000/0xff880000 FWH decode enabled0xffc00000/0xff800000 FWH decode enabled0xff700000/0xff300000 FWH decode disabled0xff600000/0xff200000 FWH decode disabled0xff500000/0xff100000 FWH decode disabled0xff400000/0xff000000 FWH decode disabledMaximum FWH chip size: 0x400000 bytesSPI Read Configuration: prefetching disabled, caching enabled, BIOS_CNTL = 0x03: BIOS Lock Enable: enabled, BIOS Write Enable: enabledWarning: Setting Bios Control at 0xdc from 0x02 to 0x01 failed.New value is 0x03.OK.The following protocols are supported: FWH.Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash contentProbing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentProbing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xc9, id2 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash contentProbing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentProbing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xc9, id2 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash contentProbing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentProbing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentProbing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xc9, id2 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xc9, id2 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xc9, id2 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xc9, id2 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FW002, 256 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FW016, 2048 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FW040, 512 kB: probe_82802ab: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xc9, id2 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentProbing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentProbing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentProbing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash contentProbing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xc9, id2 0x78, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x9b, id2 0x0c, id1 is normal flash content, id2 is normal flash contentNo EEPROM/flash device found.Note: flashrom can never write if the flash chip isn't found automatically.Restoring PCI config space for 00:1f:0 reg 0xdc*

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GSoC-2014 Flashrom project "Locking and unlocking of access protections of flash chips"
by 严进一 19 Mar '14

19 Mar '14

Hi, I am Jinyi Yan , a second year PhD candidate from Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences. I used to be a mainboard BIOS engineer in ASUS Technology Suzhou Co., Ltd for about two years (2007.7~2009.2). My major now is optoelectronics. But I have a lot of fun while programming, in my heart the working experience of being a BIOS engineer is still very exciting. I think GsoC is a nice platform for me to participate the open source community. When I search the GsoC projects and organizations, the coreboot and flashrom projects are definitely the right choices for me. I have a spare ASUS P5KPL PC at my hand, but the chipset is not in the support list of coreboot project. So I consider the flashrom project is the better choice. I also have a home-made flash programmer based on uspasp. I'd like to choose “Locking and unlocking of access protections of flash chips” for GSoC 2014. Now I'm not very familiar with the program structure of flashrom, so I expect your guidence and hope to contribute for flashrom and coreboot even if my application is not accpeted. Thanks! Look forward to your kind advice! Regards, Jinyi Yan

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Micron N25Q512, or at least its lower quarter
by David Madl 19 Mar '14

19 Mar '14

Hi, I have a new prototype development board here, with an 512 MBit Flash chip, Micron N25Q512 (precise type is N25Q512A11G40). I managed to create a config [1] that reads fine, but fails to write [2]. I understand that flashrom cannot access chips larger than 16 MBytes, but the chip should still be able to work in 3-byte addressing mode for the lower 16 MBytes. This is what I have created in flashchips.c (copy & pasted, then adapted from the part N25Q128, assuming with a bit of good faith and some datasheet comparison that they should behave alike). Has anyone ever successfully written to a small part of a 4-byte flash chip? Thanks, David ========================= [1] new stuff for flashchips.c { .vendor = "Micron/Numonyx/ST", .name = "N25Q512..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, .model_id = ST_N25Q512__3E, /* .total_size = 65536,*/ .total_size = 16384, .page_size = 256, /* supports SFDP */ /* OTP: 64B total; read 0x4B, write 0x42 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { /*.eraseblocks = { {4 * 1024, 16384 } },*/ .eraseblocks = { {4 * 1024, 4096 } }, .block_erase = spi_block_erase_20, }, { /*.eraseblocks = { {64 * 1024, 1024} },*/ .eraseblocks = { {64 * 1024, 256} }, .block_erase = spi_block_erase_d8, }, { /*.eraseblocks = { {65536 * 1024, 1} },*/ .eraseblocks = { {16384 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ .write = spi_chip_write_256, /* Multi I/O supported */ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, ========================= [2] output from flashrom trying to write, and failing: # /root/flashrom -p ft2232_spi:type=232H,divisor=8 -c 'N25Q512..3E' -V -w flash.rom flashrom v0.9.7-r1711 on Linux 3.13.6-1-ARCH (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.1, GCC 4.8.2 20140206 (prerelease), little endian Command line (7 args): /root/flashrom -p ft2232_spi:type=232H,divisor=8 -c N25Q512..3E -V -w flash.rom Calibrating delay loop... OS timer resolution is 1 usecs, 1588M loops per second, 10 myus = 9 us, 100 myus = 117 us, 1000 myus = 1005 us, 10000 myus = 10324 us, 4 myus = 4 us, OK. Initializing ft2232_spi programmer Using device type FTDI FT232H channel A. Disable divide-by-5 front stage Set clock divisor MPSSE clock: 60.000000 MHz, divisor: 8, SPI clock: 7.500000 MHz No loopback of TDI/DO TDO/DI Set data bits The following protocols are supported: SPI. Probing for Micron/Numonyx/ST N25Q512..3E, 16384 kB: probe_spi_rdid_generic: id1 0x20, id2 0xba20 Found Micron/Numonyx/ST flash chip "N25Q512..3E" (16384 kB, SPI) on ft2232_spi. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Top/Bottom (TB) is top Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:W, 0x001000-0x001fff:E FAILED at 0x00001000! Expected=0xff, Found=0x00, failed byte count from 0x00001000-0x00001fff: 0x1000 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. Trying erase function 1... 0x000000-0x00ffff:E FAILED at 0x00000000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x0000ffff: 0x10000 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. Trying erase function 2... 0x000000-0xffffff:E FAILED at 0x00000000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x00ffffff: 0x1000000 ERASE FAILED! Looking for another erase function. No usable erase functions left. FAILED! Uh oh. Erase/write failed. Checking if anything changed. Your flash chip is in an unknown state. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks!

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Re: [flashrom] CHIPSET: ALIX 2d13
by Stefan Tauner 18 Mar '14

18 Mar '14

On Tue, 18 Mar 2014 21:44:10 +0100 Idwer Vollering <vidwer(a)gmail.com> wrote: > 2014-03-18 18:49 GMT+01:00 Timo Buhrmester <timo(a)math.uni-bonn.de>: > > > flashrom on debian wheezy told me to mail you. > > The board in question is this one: http://pcengines.ch/alix2d13.htm > > > > > Found chipset "AMD CS5536". Enabling flash write... OK. > > > WARNING: unexpected second chipset match: "AMD CS5536" > > > ignoring, please report lspci and board URL to flashrom(a)flashrom.org > > > with 'CHIPSET: your board name' in the subject line. > > > Found SST flash chip "SST49LF080A" (1024 kB, LPC) at physical address > > 0xfff00000. > > > Reading flash... done. > > > > # lspci -vvvxxx > > 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] > > Host Bridge (rev 33) > > Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] > > Host Bridge > > Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- > > ParErr- Stepping- SERR- FastB2B- DisINTx- > > Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- > > <TAbort- <MAbort- >SERR- <PERR- INTx- > > Latency: 248, Cache Line Size: 32 bytes > > Region 0: I/O ports at ac1c [size=4] > > 00: 22 10 80 20 05 00 20 02 33 00 00 06 08 f8 80 00 > > > ^^^^^^ ^^^^^^ > The above numbers read as 0x1022, 0x2080 > > Only one line should match, see > https://github.com/stefanct/flashrom/blob/master/chipset_enable.c#L1375 > Which version of flashrom are you using? THAT device is only matched ONCE, but 00:0f.0 is 0x1022, 0x2090: 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03) […] 00: 22 10 90 20 09 00 a0 02 03 00 01 06 08 40 80 00 -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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CHIPSET: ALIX 2d13
by Timo Buhrmester 18 Mar '14

18 Mar '14

flashrom on debian wheezy told me to mail you. The board in question is this one: http://pcengines.ch/alix2d13.htm > Found chipset "AMD CS5536". Enabling flash write... OK. > WARNING: unexpected second chipset match: "AMD CS5536" > ignoring, please report lspci and board URL to flashrom(a)flashrom.org > with 'CHIPSET: your board name' in the subject line. > Found SST flash chip "SST49LF080A" (1024 kB, LPC) at physical address 0xfff00000. > Reading flash... done. # lspci -vvvxxx 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 33) Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 248, Cache Line Size: 32 bytes Region 0: I/O ports at ac1c [size=4] 00: 22 10 80 20 05 00 20 02 33 00 00 06 08 f8 80 00 10: 1d ac 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 80 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block Subsystem: Advanced Micro Devices [AMD] Geode LX AES Security Block Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 9 Region 0: Memory at efff4000 (32-bit, non-prefetchable) [size=16K] Kernel driver in use: Geode LX AES 00: 22 10 82 20 06 00 a0 02 00 00 10 10 08 00 00 00 10: 00 40 ff ef 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 82 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 09 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:09.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) Subsystem: VIA Technologies, Inc. Device 0106 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (750ns min, 2000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 10 Region 0: I/O ports at 1000 [size=256] Region 1: Memory at e0000000 (32-bit, non-prefetchable) [size=256] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: via-rhine 00: 06 11 53 30 97 00 10 02 96 00 00 02 08 40 00 00 10: 01 10 00 00 00 00 00 e0 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 06 01 30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 01 03 08 40: 01 00 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0a.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) Subsystem: VIA Technologies, Inc. Device 0106 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (750ns min, 2000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at 1400 [size=256] Region 1: Memory at e0040000 (32-bit, non-prefetchable) [size=256] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: via-rhine 00: 06 11 53 30 97 00 10 02 96 00 00 02 08 40 00 00 10: 01 14 00 00 00 00 04 e0 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 06 01 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 03 08 40: 01 00 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0b.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) Subsystem: VIA Technologies, Inc. Device 0106 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (750ns min, 2000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 15 Region 0: I/O ports at 1800 [size=256] Region 1: Memory at e0080000 (32-bit, non-prefetchable) [size=256] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: via-rhine 00: 06 11 53 30 97 00 10 02 96 00 00 02 08 40 00 00 10: 01 18 00 00 00 00 08 e0 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 06 01 30: 00 00 00 00 40 00 00 00 00 00 00 00 0f 01 03 08 40: 01 00 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03) Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA Control: I/O+ Mem- BusMaster- SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Region 0: I/O ports at 6000 [size=8] Region 1: I/O ports at 6100 [size=256] Region 2: I/O ports at 6200 [size=64] Region 3: I/O ports at <unassigned> Region 4: I/O ports at 9d00 [size=128] Region 5: I/O ports at 9c00 [size=64] Kernel driver in use: cs5535-mfd 00: 22 10 90 20 09 00 a0 02 03 00 01 06 08 40 80 00 10: 01 60 00 00 01 61 00 00 01 62 00 00 01 00 00 00 20: 01 9d 00 00 01 9c 00 00 00 00 00 00 22 10 90 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01) (prog-if 80 [Master]) Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 248, Cache Line Size: 32 bytes Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [size=8] Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [size=1] Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [size=8] Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [size=1] Region 4: I/O ports at ff00 [size=16] Kernel driver in use: pata_amd 00: 22 10 9a 20 05 00 a0 02 01 80 01 01 08 f8 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 ff 00 00 00 00 00 00 00 00 00 00 22 10 9a 20 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 02 f0 00 00 00 00 00 00 00 00 99 20 2a 00 00 20 50: 00 00 03 c6 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0f.4 USB controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02) (prog-if 10 [OHCI]) Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin D routed to IRQ 12 Region 0: Memory at efffe000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ohci_hcd 00: 22 10 94 20 06 00 30 02 02 10 03 0c 08 00 00 00 10: 00 e0 ff ef 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 94 20 30: 00 00 00 00 40 00 00 00 00 00 00 00 0c 04 00 00 40: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0f.5 USB controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02) (prog-if 20 [EHCI]) Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin D routed to IRQ 12 Region 0: Memory at efffd000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ehci_hcd 00: 22 10 95 20 06 00 30 02 02 20 03 0c 08 00 00 00 10: 00 d0 ff ef 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 95 20 30: 00 00 00 00 40 00 00 00 00 00 00 00 0c 04 00 00 40: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ------------>8------------------------------------------------- Kind Regards, Timo Buhrmester

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Re: [flashrom] [PATCH] Add support for 82574L to nicintel_spi.c
by Bill Paul 17 Mar '14

17 Mar '14

Of all the gin joints in all the towns in all the world, Idwer Vollering had to walk into mine at 02:09:35 on Friday 14 March 2014 and say: > 2014-03-13 22:59 GMT+01:00 Bill Paul <wpaul(a)windriver.com>: > > I recently found a need to re-flash the option ROM on an Intel 82574L > > gigabit > > ethernet card. These are a bit more common these days than the 82571 and > > 82572 > > and relatively cheap. It turns out this works with flashrom, but it > > doesn't detect the PCI ID for the device out of the box. Below is a > > patch add it to nicintel_spi.c. Note that there are probably other > > devices in the PRO/1000 family that would work too. > > > > Here's an example run with the latest code from svn: > > > > [...] > > flashrom v0.9.7-unknown on FreeBSD 10.0-RELEASE (amd64) > > flashrom is free software, get the source code at http://www.flashrom.org > > > > Calibrating delay loop... OK. > > Found Winbond flash chip "W25X40" (512 kB, SPI) on nicintel_spi. > > Reading old flash chip contents... done. > > Erasing and writing flash chip... Erase/write done. > > Verifying flash... VERIFIED. > > [...] > > > > FreeBSD detects the device as follows: > > > > em1@pci0:2:0:0: class=0x020000 card=0xa01f8086 chip=0x10d38086 rev=0x00 > > hdr=0x00 > > > > vendor = 'Intel Corporation' > > device = '82574L Gigabit Network Connection' > > class = network > > subclass = ethernet > > > > I also added links to the Intel PCIe ethernet controllers programming > > manual > > and the 82574 datasheet. > > > > Incidentally, thanks to everyone involved for their work in this project. > > It > > helped me out of a bit of a jam. > > > > -Bill > > > > Signed-off-by: Bill Paul <wpaul(a)windriver.com> > > This patch is Acked-by: Idwer Vollering <vidwer(a)gmail.com> > when you adjust the PDF URL in a follow-up patch, see below. Updated patch is below. -Bill Signed-off-by: Bill Paul <wpaul(a)windriver.com> Index: nicintel_spi.c =================================================================== --- nicintel_spi.c (revision 1766) +++ nicintel_spi.c (working copy) @@ -17,14 +17,20 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /* - * Datasheet: + * Datasheets: * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx - * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf + * http://www.intel.com/content/www/us/en/ethernet-controllers/pci-pci-x- family-gbe-controllers-software-dev-manual.html + * + * PCIe GbE Controllers Open Source Software Developer's Manual + * http://www.intel.com/content/www/us/en/ethernet-controllers/pcie-gbe- controllers-open-source-manual.html + * + * Intel 82574 Gigabit Ethernet Controller Family Datasheet + * http://www.intel.com/content/www/us/en/ethernet-controllers/82574l-gbe- controller-datasheet.html */ #include <stdlib.h> #include <unistd.h> #include "flash.h" @@ -70,10 +76,11 @@ const struct dev_entry nics_intel_spi[] = { {PCI_VENDOR_ID_INTEL, 0x105e, OK, "Intel", "82571EB Gigabit Ethernet Controller"}, {PCI_VENDOR_ID_INTEL, 0x1076, OK, "Intel", "82541GI Gigabit Ethernet Controller"}, {PCI_VENDOR_ID_INTEL, 0x107c, OK, "Intel", "82541PI Gigabit Ethernet Controller"}, {PCI_VENDOR_ID_INTEL, 0x10b9, OK, "Intel", "82572EI Gigabit Ethernet Controller"}, + {PCI_VENDOR_ID_INTEL, 0x10d3, OK, "Intel", "82574L Gigabit Ethernet Controller"}, {0}, }; static void nicintel_request_spibus(void) -- ============================================================================= -Bill Paul (510) 749-2329 | Senior Member of Technical Staff, wpaul(a)windriver.com | Master of Unix-Fu - Wind River Systems ============================================================================= "I put a dollar in a change machine. Nothing changed." - George Carlin =============================================================================

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flashrom March 2014