March 2014 - flashrom - mail.coreboot.org

flashrom -V
by Volker Twer March 1, 2014

March 1, 2014

Hey, I'm thinking about upgrading my BIOS and found "flashrom" in DEBIAN-repositories. Running a "read" on the builtin BIOS I saw the request for sending you some information - so here you are. Does "guesswork" mean, it might be unsafe to use this software on this board/bios? Thanks for your work! Greetings, Volker This ist the requested output flashrom v0.9.6.1-r1563 on Linux 3.13-3.slh.2-aptosid-686 (i686) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.9, GCC 4.7.1, little endian Command line (3 args): flashrom -V -p internal Calibrating delay loop... OS timer resolution is 2 usecs, 1238M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 1001 us, 10000 myus = 9989 us, 8 myus = 9 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System Manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "NF-M2SV" DMI string baseboard-product-name: "www.abit.com.tw " DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8726 on port 0x2e Found chipset "NVIDIA MCP61" with PCI ID 10de:03e0. Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:03eb at 00:01:1 MCP SPI BAR is at 0x00000000 MCP SPI is not used. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. Super I/O ID 0x8726 is not on the list of flash capable controllers. The following protocols are supported: LPC. Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x40, id2 0x07, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xda, id2 0x50 Found Winbond flash chip "W39V040C" (512 kB, LPC) at physical address 0xfff80000. Lockout bits: Hardware bootblock locking (#TBL) is not active. Hardware remaining chip locking (#WP) is not active.. Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xda, id2 0x50 Found Winbond flash chip "W39V040C" (512 kB, LPC). No operations were specified. Restoring PCI config space for 00:01:0 reg 0x6d Restoring PCI config space for 00:01:0 reg 0x90 Restoring PCI config space for 00:01:0 reg 0x8c Restoring PCI config space for 00:01:0 reg 0x88

2 1

Re: [flashrom] Tested AT25DF161
by Stefan Tauner March 1, 2014

March 1, 2014

On Sun, 2 Mar 2014 00:28:16 +0400 Alex K <lepik.stv(a)gmail.com> wrote: > Sorry, I do not quite understand your question, but I'll try to answer. > I forgot when recording chip, specify a log file entry. Because I have a > log file cleanup, and reading to compare the recorded information. > To clean the chip pin WP, I connect to the GND. For writing and reading > from the chip, pin WP connects to the VCC. > > […] > > I hope this information will help you. Yes, thank you. I'll mark the chip as fully tested. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Re: [flashrom] Tested AT25DF161
by Stefan Tauner March 1, 2014

March 1, 2014

On Sat, 1 Mar 2014 23:12:15 +0400 Alex K <lepik.stv(a)gmail.com> wrote: > Hello I tested for cleaning work, reading, writing, memory AT25DF161 using > Bus Pirate v4. > Used: > flashrom v0.9.6.1-r1704 on Windows 6.1 (x86) > flashrom was built with GCC 4.7.2, little endian > Baud rate is 115200. > Detected Bus Pirate hardware v4 > Detected Bus Pirate firmware 6.2 ("v6.2-beta1") > Using SPI command set v2. > SPI speed is 8MHz > Raw bitbang mode version 1 > Raw SPI mode version 1 > The following protocols are supported: SPI. > Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 > 0x4602 > Found Atmel flash chip "AT25DF161" (2048 kB, SPI) on buspirate_spi. > Ignoring security lockdown (if present) > Ignoring status register byte 2 > Chip status register is 0x0c. > Chip status register: Sector Protection Register Lock (SRPL) is not set > Chip status register: Bit 6 is not set > Chip status register: Erase/Program Error (EPE) is not set > Chip status register: WP# pin (WPP) is asserted > Chip status register: Software Protection Status (SWP): all sectors are > protected > Chip status register: Write Enable Latch (WEL) is not set > Chip status register: Write In Progress (WIP/BUSY) is not set > === > > Initially, there was a problem with the use of long cables (> 20 cm). > After verification of the firmware did not pass. > Replaced wires from Bus Pirate at length (10cm), all turned out. Many > thanks for the utility. I think that you can remove the status UNTESTED > with this chip. Thank you again. > I think it is reasonable to point out the page on the wiki that the length > of wire for the Bus Pirate is very desirable <= 10 cm, to avoid many > mistakes. This saves the trouble of starting recording, reading chips. > > Sorry for my bad english, I'm from Russia. Hello Alex, thanks for your report! I am wondering a bit about the status register bits. According to your log the software write protection is enabled (and the parsing of the raw value 0x0c seems to be correct, so this is not only a cosmetic problem). Did you change anything since you wrote to the chip? Regarding the cable lengths: The troubleshooting section of the bus pirate wiki page links to this: http://flashrom.org/ISP and the first problem mentioned there are too long cables ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

Tested AT25DF161
by Alex K March 1, 2014

March 1, 2014

Hello I tested for cleaning work, reading, writing, memory AT25DF161 using Bus Pirate v4. Used: flashrom v0.9.6.1-r1704 on Windows 6.1 (x86) flashrom was built with GCC 4.7.2, little endian Baud rate is 115200. Detected Bus Pirate hardware v4 Detected Bus Pirate firmware 6.2 ("v6.2-beta1") Using SPI command set v2. SPI speed is 8MHz Raw bitbang mode version 1 Raw SPI mode version 1 The following protocols are supported: SPI. Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4602 Found Atmel flash chip "AT25DF161" (2048 kB, SPI) on buspirate_spi. Ignoring security lockdown (if present) Ignoring status register byte 2 Chip status register is 0x0c. Chip status register: Sector Protection Register Lock (SRPL) is not set Chip status register: Bit 6 is not set Chip status register: Erase/Program Error (EPE) is not set Chip status register: WP# pin (WPP) is asserted Chip status register: Software Protection Status (SWP): all sectors are protected Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set === Initially, there was a problem with the use of long cables (> 20 cm). After verification of the firmware did not pass. Replaced wires from Bus Pirate at length (10cm), all turned out. Many thanks for the utility. I think that you can remove the status UNTESTED with this chip. Thank you again. I think it is reasonable to point out the page on the wiki that the length of wire for the Bus Pirate is very desirable <= 10 cm, to avoid many mistakes. This saves the trouble of starting recording, reading chips. Sorry for my bad english, I'm from Russia. -- С уважением Алексей

1 0