On Mon, 30 May 2011 02:45:44 +0200
Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote:
> this patch also changes the display width of all addresses in physmap.c to 16 hex characters.
>
> FIXME: what about unmappings?
> munmap is safe.
> djgpp's __dpmi_free_physical_address_mapping: unknown.
> DirectHW's unmap_physical: unknown.
>
> FIXME: jakllsch suggested using PRIx64 instead of x, because it's more portable
FIXME: in the case we can not map and 'mayfail' is true we should return
ERROR_PTR instead of ERROR_PTR + diff
--
Kind regards/Mit freundlichen Grüßen, Stefan Tauner
Hi,
I post a success story about a VIA VT6421A based SATA/PATA PCI controller. The flashrom can probe/read/write successfully the onboard PMC Pm49FL004 chip. I downloaded the patch from http://patchwork.coreboot.org/patch/3214/. Just one thing... "BAR type unknown..." I don't known the meaning, but it worked for me without errors. Please add the patch from above to the trunk. I attached a verbose probe output too.
flashrom v0.9.3-r1362 on Linux 2.6.38-std220-i586 (i686), built with libpci 3.0.0, GCC 4.3.2, little endian
flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OK.
Found "VIA VT6421A" (1106:3249, BDF 00:0a.0).
BAR type unknown, please report a bug at flashrom(a)flashrom.org
===
This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output
to flashrom(a)flashrom.org if it works for you. Please add the name of your
PCI device to the subject. Thank you for your help!
===
Found chip "PMC Pm49FL004" (512 kB, LPC, FWH) on atavia.
Reading flash... done.
Best regards,
Szabolcs Magyar
P.S.: Sorry for my english.
Hello folks,
I would like to use a flashrom utility to access 2 serial flashes on
the SPI bus of my x86 board, but I'm struggling with the second one.
So I'm looking for any help, hints or advices which can help me to
solve this issue.
I have custom x86 board (Atom n450 CPU, ICH8M chipset) which have 2
serial flashes installed on it.
The first one is SST25VF016B and the second one is Numonyx M45PE16.
The M45PE16 is pretty the similar to the M25PE16.
Both this chips are connected to the SPI bus of the ICH8M chipset, the
CS (chip select) signal of the SST25VF is routed to the SPI_CS0 and
the CS signal of the M45PE16 is routed to the SPI_CS1.
I can successfully read, erase and write the SST flash.
Trying to figure out if flashrom utility can find the second Numonyx
flash I've added the proper description for it to the flashchips.c
(actually I've leaved it the same as for M25PE16 but changed model_id
field). Unfortunately it didn't help me at all.
So I'm wondering if flashrom can't find M45PE16 flash because of
cleared SPI_CS1 signal and how can I enable it?
Does flashrom utility support such kind of configurations or does it
simply searching for the flash on CS0?
Probably some of you have some ideas on enabling SPI_CS1 or even some
useful links etc.
Unfortunately the official Intel ICH8M documentation looks kind of
complicated and no so clear to me.
I'll of course digg into it but any help, hints or advices are highly
appreciated!
Thanks in advance,
xborodax.
#5: Winbond W25Q128 for ICH
----------------------------------+---------------------------
Reporter: rheneus.paul@… | Owner: hailfinger
Type: defect | Status: new
Priority: critical | Milestone:
Component: flashrom | Version:
Keywords: | Dependencies:
Patch Status: there is no patch |
----------------------------------+---------------------------
I could not use flashrom 0.9.3 -r1205 to detect Winbond W25Q128 to program
BIOS. Attached the read log
Just by adding WINBOND_NEX_W25Q128 0x4018 in flashchips.c for W25Q128,
similar to W25Q64 throws run Opcode 0x3 error for read.
Attached Verbose log of read
--
Ticket URL: <http://www.flashrom.org/trac/flashrom/ticket/5>
flashrom <http://www.flashrom.org/>
Hello,
I have an ASUS P5LD2-VM, and I try to update bios, first with flashrom
v0.9.2-r1028 ( http://paste.flashrom.org/view.php?id=489 )
then with 0.9.3 ( http://paste.flashrom.org/view.php?id=490 also, the
ROM is at http://paste.flashrom.org/uploads/491.bin )
but:
Writing flash chip... Erasing flash chip... Looking at blockwise erase
function 0... trying... 0x000000-0x000fff, 0x001000-0x001fff,
0x002000-0x002fff, 0x003000-0xff, 0x004000-0x004fff, 0x005000-0x005fff,
ERASE FAILED at 0x00005760! Expected=0xff, Read=0x50, failed byte count
from 0x00005000-0x00005fff: 0x87a
ERASE FAILED!
Can you help whit this?
I'm carco on freenode/#flashrom channel
Thank you,
Emil Sirbu
Hi!
I'm going to flash Gembird PCI 3SATA+1IDE controller's BIOS, there is W39V040C. I found an excellent professionaly modified ROM for this device. I will try to do it on board of ASUS P4P800E-DELUX. Just let me know, is it possible in the moment or I have to wait for a new version of flashrom.exe? This device have unfriendly relations to Radeon X1600 AGP, on board of ASRock P4i45E MB, so I found only new modified ROM of PCI controller can help.
Waiting for Your answer, Alexey.
This patch is for testing only, and not for immediate merge.
libpci unhelpfully calls exit(1) instead of reporting an error if init
fails.
Fortunately, that part of libpci has not changed since the year 2000, so
we can use a really evil hack to avoid that.
We supply an alternative error printing function (which does not
exit(1)) and this function detects which error is happening and hacks
internal libpci structures in a way that avoids a later segfault due to
NULL pointer dereference.
We MUST absolutely make sure that pci_init() in libpci will not change
or this hack will explode spectacularly. Once we decide that this hack
is the way to go, notifying the libpci maintainer is essential.
Apply this patch, then compile flashrom with
make CONFIG_DUMMY=no CONFIG_INTERNAL=o CONFIG_SERPROG=no
CONFIG_RAYER_SPI=no CONFIG_NIC3COM=no CONFIG_GFXNVIDIA=no
CONFIG_SATASII=no CONFIG_FT2232_SPI=no CONFIG_DRKAISER=no
CONFIG_NICREALTEK=no CONFIG_NICINTEL_SPI=no CONFIG_BUSPIRATE_SPI=no
CONFIG_OGP_SPI=no CONFIG_SATAMV=no CONFIG_NICINTEL=yes
To check if the hack works, run "flashrom -V" and respond to this mail
with the output. You should get a message near the end which says that
programmer initialization failed.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Index: flashrom-libpci_hack_avoid_exit1_during_init/pcidev.c
===================================================================
--- flashrom-libpci_hack_avoid_exit1_during_init/pcidev.c (Revision 1362)
+++ flashrom-libpci_hack_avoid_exit1_during_init/pcidev.c (Arbeitskopie)
@@ -21,6 +21,8 @@
#include <stdlib.h>
#include <string.h>
+#include <stdio.h>
+#include <stdarg.h>
#include "flash.h"
#include "programmer.h"
@@ -188,6 +190,58 @@
return 0;
}
+/* Ugliest hack ever in flashrom! Should work for all libpci versions released
+ * in the year 2000 or later. Checked to make sense until at least version
+ * 3.1.8-test1.
+ */
+static void fake_libpci_method_init(struct pci_access *foo)
+{
+ msg_pinfo("Working around another pcilib crash\n");
+ return;
+}
+
+static struct {
+ char *name; /* name in all libpci versions */
+ char *dummy1; /* Only present in some libpci versions */
+ void *dummy2;
+ void (*init1)(struct pci_access *); /* init in older versions */
+ void (*init2)(struct pci_access *); /* init in newer versions */
+ void *dummy3;
+ void *dummy4;
+ void *dummy5;
+ void *dummy6;
+ void *dummy7;
+ void *dummy8;
+ void *dummy9;
+ void *dummy10;
+} fake_libpci_methods = {
+ .name = "None",
+ .init1 = &fake_libpci_method_init,
+ .init2 = &fake_libpci_method_init,
+};
+
+static int pci_init_failed = 0;
+
+static void my_libpci_generic_error(char *msg, ...)
+{
+ va_list ap;
+
+ msg_pinfo("pcilib: ");
+ va_start(ap, msg);
+ vprintf(msg, ap);
+ va_end(ap);
+ msg_pinfo("\n");
+ if (!strcmp(msg, "Cannot find any working access method.")) {
+ /* Workaround for crash, very ugly. */
+ msg_pinfo("Working around pcilib crash\n");
+ pacc->methods = (void *)&fake_libpci_methods;
+ pci_init_failed = 1;
+ } else {
+ /* Any error in libpci would result in exit(1) by default. */
+ exit(1);
+ }
+}
+
uintptr_t pcidev_init(int bar, const struct pcidev_status *devs)
{
struct pci_dev *dev;
@@ -198,7 +252,14 @@
uintptr_t addr = 0, curaddr = 0;
pacc = pci_alloc(); /* Get the pci_access structure */
+ pacc->error = &my_libpci_generic_error;
pci_init(pacc); /* Initialize the PCI library */
+ /* pci_init returns void, so we have to hack it. */
+ if (pci_init_failed) {
+ /* Yes, technically we would have to free stuff... */
+ return 1;
+ }
+
pci_scan_bus(pacc); /* We want to get the list of devices */
pci_filter_init(pacc, &filter);
--
http://www.hailfinger.org/
Hi,
Last changes I submitted have been vs. trunk 1424. Since there is a new
version out, I will resubmit the changes built against the new flashrom
trunk version:
The Intel Tunnel Creek chipset supports both an SPI and an LPC bus. Set
chipset table entry for Tunnel Creek to new function
"enable_flash_tunnelcreek", which will read the hardware straps and
return support for the bus that has been used for booting. This function
uses "ich_init_spi" with ich_generation set to 7 for initializing the
SPI bus if necessary.
SPI functionality tested on actual hardware (see attached file
flashrom.log), Tunnel Creek LPC interface not tested yet (missing
hardware for that).
The attached patch has been created vs. flashrom trunk 1427.
Signed-off-by: Ingo Feldschmid <ifel(a)msc-ge.com>
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