August 2011 - flashrom - mail.coreboot.org

External programmers
by Carl-Daniel Hailfinger 25 Dec '15

25 Dec '15

Hi, I'm trying to find out which external programmers should be supported next. 1. There was talk of an AVR-based new programmer using the serprog protocol on IRC by someone with the nick "coldelectrons", but I have no idea if he/she is reading this mail. IMHO more hardware using the serprog protocol is always a good idea. 2. All those Willem/Sivava variants. People regularly request those, but I don't think anyone in here owns the hardware. 3. RayeR's SPIPGM. I have a preliminary patch which could work, but I don't have the hardware. Will send the patch to the list soon. 4. LPC^2, Milksop, CheapLPC and other programmers from the Xbox modding community. 5. Dozens of SPI programmer hardware projects scattered over the net. Too many to count, and I'm not sure which of them has more than one user. In general, it seems creating a new programmer hardware design is like writing IRC clients: A nice way to get started in the field. I have no problems merging flashrom support for all of them, but I won't implement support for all of them myself. Regards, Carl-Daniel -- http://www.hailfinger.org/

8 13

Re: [flashrom] [PATCH] dummyflasher.c: add an "empty" parameter and initialize with random bytes by default
by Carl-Daniel Hailfinger 09 May '14

09 May '14

Am 21.07.2011 17:54 schrieb Stefan Tauner: > previously the dummies were initialized to be empty (all ones), which makes writes skip > erasing altogether. with this patch the default is to fill it with random bytes instead and the > old behavior can be enforced with stating "empty=yes" on the command line. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Does the following not work for you? dd if=/dev/urandom bs=1k count=4k of=oldimage.bin flashrom -p dummy:emulate=SST25VF032B,image=oldimage.bin -w newimage.bin Regards, Carl-Daniel -- http://www.hailfinger.org/

5 8

Add timeout check to SPI bitbang bus request
by Carl-Daniel Hailfinger 29 Apr '14

29 Apr '14

Hi Iain, your Intel 82540EM which hangs on a flashrom run should spew "Timeout!" messages with this patch. It would be nice if you could tell us how long it waits for each chip probe so I can adjust the timeout value. Please note that this patch will _not_ fix the underlying issue, but I believe that an endless loop on possibly broken hardware is worse than aborting. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-bitbang_timeout/flash.h =================================================================== --- flashrom-bitbang_timeout/flash.h (Revision 1185) +++ flashrom-bitbang_timeout/flash.h (Arbeitskopie) @@ -35,6 +35,9 @@ #define ERROR_PTR ((void*)-1) +/* Error codes */ +#define TIMEOUT_ERROR -101 + typedef unsigned long chipaddr; int register_shutdown(void (*function) (void *data), void *data); Index: flashrom-bitbang_timeout/bitbang_spi.c =================================================================== --- flashrom-bitbang_timeout/bitbang_spi.c (Revision 1185) +++ flashrom-bitbang_timeout/bitbang_spi.c (Arbeitskopie) @@ -53,10 +53,11 @@ return bitbang_spi_master->get_miso(); } -static void bitbang_spi_request_bus(void) +static int bitbang_spi_request_bus(void) { if (bitbang_spi_master->request_bus) - bitbang_spi_master->request_bus(); + return bitbang_spi_master->request_bus(); + return 0; } static void bitbang_spi_release_bus(void) @@ -86,7 +87,7 @@ bitbang_spi_master = master; bitbang_spi_half_period = halfperiod; - /* FIXME: Run bitbang_spi_request_bus here or in programmer init? */ + /* FIXME: Run bitbang_spi_request_bus here or per command? */ bitbang_spi_set_cs(1); bitbang_spi_set_sck(0); bitbang_spi_set_mosi(0); @@ -131,13 +132,15 @@ int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - int i; + int i, ret; /* FIXME: Run bitbang_spi_request_bus here or in programmer init? * Requesting and releasing the SPI bus is handled in here to allow the * programmer to use its own SPI engine for native accesses. */ - bitbang_spi_request_bus(); + ret = bitbang_spi_request_bus(); + if (ret) + return ret; bitbang_spi_set_cs(0); for (i = 0; i < writecnt; i++) bitbang_spi_readwrite_byte(writearr[i]); Index: flashrom-bitbang_timeout/nicintel_spi.c =================================================================== --- flashrom-bitbang_timeout/nicintel_spi.c (Revision 1185) +++ flashrom-bitbang_timeout/nicintel_spi.c (Arbeitskopie) @@ -58,6 +58,8 @@ // #define FL_BUSY 30 // #define FL_ER 31 +#define MAX_REQUEST_LOOPS 10000 + uint8_t *nicintel_spibar; const struct pcidev_status nics_intel_spi[] = { @@ -68,16 +70,27 @@ {}, }; -static void nicintel_request_spibus(void) +static void nicintel_release_spibus(void); + +static int nicintel_request_spibus(void) { uint32_t tmp; + int i = 0; tmp = pci_mmio_readl(nicintel_spibar + FLA); tmp |= 1 << FL_REQ; pci_mmio_writel(tmp, nicintel_spibar + FLA); /* Wait until we are allowed to use the SPI bus. */ - while (!(pci_mmio_readl(nicintel_spibar + FLA) & (1 << FL_GNT))) ; + while (!(pci_mmio_readl(nicintel_spibar + FLA) & (1 << FL_GNT))) { + if (i++ > MAX_REQUEST_LOOPS) { + nicintel_release_spibus(); + msg_perr("%s: Timeout! Aborting.\n", __func__); + return TIMEOUT_ERROR; + } + } + + return 0; } static void nicintel_release_spibus(void) Index: flashrom-bitbang_timeout/mcp6x_spi.c =================================================================== --- flashrom-bitbang_timeout/mcp6x_spi.c (Revision 1185) +++ flashrom-bitbang_timeout/mcp6x_spi.c (Arbeitskopie) @@ -40,22 +40,37 @@ #define MCP6X_SPI_REQUEST 0 #define MCP6X_SPI_GRANT 8 +#define MAX_REQUEST_LOOPS 10000 + void *mcp6x_spibar = NULL; /* Cached value of last GPIO state. */ static uint8_t mcp_gpiostate; -static void mcp6x_request_spibus(void) +static void mcp6x_release_spibus(void); + +static int mcp6x_request_spibus(void) { + int i = 0; + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); mcp_gpiostate |= 1 << MCP6X_SPI_REQUEST; mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); /* Wait until we are allowed to use the SPI bus. */ - while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_GRANT))) ; + while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_GRANT))) { + if (i++ > MAX_REQUEST_LOOPS) { + /* Update the cache. */ + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + mcp6x_release_spibus(); + msg_perr("%s: Timeout! Aborting.\n", __func__); + return TIMEOUT_ERROR; + } + } /* Update the cache. */ mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + return 0; } static void mcp6x_release_spibus(void) Index: flashrom-bitbang_timeout/programmer.h =================================================================== --- flashrom-bitbang_timeout/programmer.h (Revision 1185) +++ flashrom-bitbang_timeout/programmer.h (Arbeitskopie) @@ -131,7 +131,7 @@ void (*set_sck) (int val); void (*set_mosi) (int val); int (*get_miso) (void); - void (*request_bus) (void); + int (*request_bus) (void); void (*release_bus) (void); }; -- http://www.hailfinger.org/

4 15

Flashrom stuck using 100% cpu while probing for a chip
by GatoLoko 28 Apr '14

28 Apr '14

I've tried to run flashrom -V to see if it could identify the chip on my new board (AsRock M3A-GLAN), and it got stuck while probing for the first chip. I've tried commenting out that specific chip (AMIC A25L05PT) and then it gets stuck on the next one. Then commented out all AMIC chips, and it got stuck on the next one (the first ATMEL on the list) I've tried with an older flashrom (0.9.2-r1141). It skipped some AMD chips, then got stuck on AMIC again. Talked with "tlt" and "stefanct" on irc and they asked for a strace and a gdb backtrace. Strace produced no results. Gdb log is attached. "stefanct" tried and reproduced it on a machine with nicintel_spi, but warned it was with an unsupported nic: http://paste.flashrom.org/view.php?id=738 -- GatoLoko

4 11

[PATCH] Add git support to the Makefile
by Carl-Daniel Hailfinger 21 Aug '13

21 Aug '13

flashrom relies on svn to export tarballs and only prints the last svn revision in the version message even if flashrom is in a git tree. Print extended version information (version, svn revision, git hash, repository URL). Allow exporting from git trees. This should make git users first-class citizens like svn users. Side note: If anyone has an idea how to make the export target more beautiful (80 column limit etc.), please tell me. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-gitfriendly/Makefile =================================================================== --- flashrom-gitfriendly/Makefile (Revision 1145) +++ flashrom-gitfriendly/Makefile (Arbeitskopie) @@ -97,13 +97,15 @@ # of the checked out flashrom files. # Note to packagers: Any tree exported with "make export" or "make tarball" # will not require subversion. The downloadable snapshots are already exported. -SVNVERSION := $(shell LC_ALL=C svnversion -cn . 2>/dev/null | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || LC_ALL=C svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || LC_ALL=C git svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || echo unknown) +SCMVERSION := $(shell LC_ALL=C svnversion -cn . 2>/dev/null | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || LC_ALL=C svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || LC_ALL=C git svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || echo unknown) +SCMEXTVERSION := $(shell LC_ALL=C git rev-parse HEAD 2>/dev/null | sed 's/^./-\0/') +SCMURL := $(shell LC_ALL=C svn info 2>/dev/null | grep URL: | sed 's/.*URL:[[:blank:]]*//' | grep ^. || LC_ALL=C git remote show origin 2>/dev/null |grep URL: | sed 's/.*URL:[[:blank:]]*//' | grep ^. || echo unknown ) RELEASE := 0.9.2 -VERSION := $(RELEASE)-r$(SVNVERSION) +VERSION := $(RELEASE)-r$(SCMVERSION)$(SCMEXTVERSION) RELEASENAME ?= $(VERSION) -SVNDEF := -D'FLASHROM_VERSION="$(VERSION)"' +SCMDEF := -D'FLASHROM_VERSION="$(VERSION)"' -D'FLASHROM_SCMURL="$(SCMURL)"' # Always enable internal/onboard support for now. CONFIG_INTERNAL ?= yes @@ -310,7 +312,7 @@ TAROPTIONS = $(shell LC_ALL=C tar --version|grep -q GNU && echo "--owner=root --group=root") %.o: %.c .features - $(CC) -MMD $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) $(SVNDEF) -o $@ -c $< + $(CC) -MMD $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) $(SCMDEF) -o $@ -c $< # Make sure to add all names of generated binaries here. # This includes all frontends and libflashrom. @@ -420,9 +422,12 @@ export: @rm -rf $(EXPORTDIR)/flashrom-$(RELEASENAME) - @svn export -r BASE . $(EXPORTDIR)/flashrom-$(RELEASENAME) - @sed "s/^SVNVERSION.*/SVNVERSION := $(SVNVERSION)/" Makefile >$(EXPORTDIR)/flashrom-$(RELEASENAME)/Makefile - @LC_ALL=C svn log >$(EXPORTDIR)/flashrom-$(RELEASENAME)/ChangeLog + @svn export -r BASE . $(EXPORTDIR)/flashrom-$(RELEASENAME) 2>/dev/null || git checkout-index -a -f --prefix=$(EXPORTDIR)/flashrom-$(RELEASENAME)/ + @# If SCMVERSION or SCMEXTVERSION contain a slash or SCMURL contains a hash, this will explode + @sed "s/^SCMVERSION.*/SCMVERSION := $(SCMVERSION)/;s/^SCMEXTVERSION.*/SCMEXTVERSION := $(SCMEXTVERSION)/;s#^SCMURL.*#SCMURL := $(SCMURL)#" Makefile >$(EXPORTDIR)/flashrom-$(RELEASENAME)/Makefile + @# ChangeLog should be in English, but we want UTF-8 for names. + @( LC_ALL=en_US.UTF-8 svn log 2>/dev/null || LC_ALL=en_US.UTF-8 git log 2>/dev/null || echo "Unable to extract log from SCM" ) >$(EXPORTDIR)/flashrom-$(RELEASENAME)/ChangeLog + @rm -f $(EXPORTDIR)/flashrom-$(RELEASENAME)/.gitignore $(EXPORTDIR)/flashrom-$(RELEASENAME)/.gitattributes $(EXPORTDIR)/flashrom-$(RELEASENAME)/.gitmodules @echo Exported $(EXPORTDIR)/flashrom-$(RELEASENAME)/ tarball: export Index: flashrom-gitfriendly/flashrom.c =================================================================== --- flashrom-gitfriendly/flashrom.c (Revision 1145) +++ flashrom-gitfriendly/flashrom.c (Arbeitskopie) @@ -1355,6 +1355,7 @@ void print_version(void) { msg_ginfo("flashrom v%s", flashrom_version); + msg_ginfo(" from " FLASHROM_SCMURL ","); print_sysinfo(); } @@ -1362,7 +1363,6 @@ { msg_ginfo("flashrom is free software, get the source code at " "http://www.flashrom.org\n"); - msg_ginfo("\n"); } int selfcheck(void) -- http://www.hailfinger.org/

5 11

Re: [flashrom] [coreboot] Dualbios on GA-MA770-UD3
by Carl-Daniel Hailfinger 10 Aug '13

10 Aug '13

Hi Vadim, thanks for your mail. I have added the flashrom mailing list in CC: because we should develop a generic way to handle DualBIOS and similar techniques. On 09.04.2010 08:12, Vadim Girlin wrote: > I'm going to try coreboot on Gigabyte GA-MA770-UD3. > It's AMD 770 (RX780 / SB700). > > My motherboard supports hardware dual bios - with two chips on it. > I'm going to try flashing backup chip and boot from it. It seems to be > possible - I've tested it (flashing at least). Chips on this board could > be switched by changing bit 0 at undocumented register EF on LDN 7 of > IT8720. I can use slightly patched flashrom for accessing any chip I > want without any problems. And this is tested many times. > > My idea is to use backup chip for debugging - that always keeps my > chance to reboot from main bios chip. And removes the need for > desoldering etc. > > And second problem is that original bios is checking second chip - and > trying to recover it by flashing the bios from main chip on reboot? > rewriting coreboot. AFAICS this could be solved by including some > signatures etc. It seems to be easy to find out. May be someone is > working on this? > > BTW I can send the patch for flashrom - but I think that with > information I mentioned above somebody could make it much better than my > ugly hack. I hope the regs should be the same for all latest Gigabyte > MBs using IT8720/18 > It would be great if you could send that patch. It will help us make a flashrom design decision that works for all boards with multiple flash chips. By the way, some of us have good contacts at ITE, so we can ask ITE for details about the undocumented registers. Regards, Carl-Daniel -- http://www.hailfinger.org/

5 12

[RFC] Layout handling...
by Carl-Daniel Hailfinger 12 Jul '13

12 Jul '13

Hi, before we change flashrom to work with current layout requirements, we should summarize the features we need/want, and then decide how to handle the individual layout regions internally. Terms: "write strategy" describes a combination of erase+write commands with a given block size, touching some blocks. "read protected" describes a region which can not be read. "write protected" describes a region which can not be written. "write once" describes a region which can be written exactly once in the chip lifetime. If you add a feature to the list, please give it a nickname so we know which feature people are referring to. Some of the features below might not be desirable, but I want to list them anyway so we can explicitly declare them as unsupported if needed. fullwrite-unrestricted: Write a chip-sized image, no special read/write restrictions of the chip, no layout file needs to be specified. Default write case right now. fullwrite-noread: Write a chip-sized image, reading anything from the chip is not possible. Many DVD writers fall in that category. No verification, violates our reliability guarantees. fullwrite-postread: Write a chip-sized image, reading anything from the chip is only possible after write. Chips which are read-locked until a full erase/write fall in that category. Do those exist as standalone flash chips or only integrated into processors? fullwrite-partialread: Write a chip-sized image, reading is only possible in some chip regions. Only partial verification, violates our reliability guarantees. fullwrite-partialwrite: Write a chip-sized image, but writing is only possible in some regions. This is obviously a conflict unless the image has the same contents as the chip in the write-protected regions and there is a possible write strategy for the whole image which does not touch the write-protected regions. Should flashrom always refuse this scenario, or only refuse it in case of conflicts? partialwrite-unrestricted: Write only parts of an image, the rest of the chip contents is kept, no special read/write restrictions. partialwrite-partialread: Write only parts of an image, the rest of the chip contents is kept, reading is only possible in some chip regions. If no read-protected regions are written and a suitable write strategy exists, should flashrom warn? If a read-protected region is written, should flashrom warn/refuse due to reliability requirements? partialwrite-partialwrite: Write only parts of an image, the rest of the chip contents is kept, writing is only possible in some chip regions. If no write-protected regions are written and a suitable write strategy exists, should flashrom warn? flashrom will refuse to write a write-protected region. fullread-unrestricted: Read the full chip, no special read restrictions of the chip. partialread-unrestricted: Read only parts of a chip, no special read restrictions of the chip. partialread-partialread: Read only parts of a chip, some regions are read-protected. flashrom should refuse to read any read-protected regions. partialread-imagefiller: If only parts of a chip are read and the read image has full chip size, what should be used as filler for unread regions? 0x00 or 0xff? partialread-layout-imagesize: If only parts of a chip are read, should the read image still have full chip size with all read regions filled in at the respective locations? partialread-layout-split: If only parts of a chip are read, should it be possible to write each region (or a combination thereof) to a separate image file, and would that mapping be specified in the layout file? partialwrite-layout-split: If only parts of a chip are written, should it be possible to collect each part of the new image from a separate image file, and would that mapping be specified in the layout file? readwrite-protection-time: Which read protection and write protection times exist? Temporary lock until unlock, temporary lock until chip soft reset, temporary lock until chip/programmer hard reset (powerdown or reset line), permanent eternal lock. readwrite-protection-type: Which read protection and write protection types exist? Programmer lock (e.g. Intel SPI), hardware chip lock (WP pin), software chip lock (chip command). readwrite-protection-interaction: How should we express this situation: A region is write-locked with a software chip lock, but to remove that software chip lock, a hardware chip lock has to be disabled first, then the software chip lock can be disabled. partialaccess-crash: Some regions in the chip are really off-limits and will cause an unrecoverable error (system crash) when accessed (read or write). That seems to be the case for some EC/flash interactions. Comments? Any forks of flashrom (e.g. chromium) which need infrastructure features not mentioned above? Regards, Carl-Daniel -- http://www.hailfinger.org/

5 12

Re: [flashrom] [PATCH] automatically round address ranges requested from physmap_common to page boundaries
by Stefan Tauner 31 Dec '12

31 Dec '12

On Mon, 30 May 2011 02:45:44 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > this patch also changes the display width of all addresses in physmap.c to 16 hex characters. > > FIXME: what about unmappings? > munmap is safe. > djgpp's __dpmi_free_physical_address_mapping: unknown. > DirectHW's unmap_physical: unknown. > > FIXME: jakllsch suggested using PRIx64 instead of x, because it's more portable FIXME: in the case we can not map and 'mayfail' is true we should return ERROR_PTR instead of ERROR_PTR + diff -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 1

[PATCH] Enable VX855 chipset
by John Schmerge 21 Oct '12

21 Oct '12

This patch adds support for the Via VX855 chipset

4 8

VIA VT6421A
by Magyar Szabolcs 30 Sep '12

30 Sep '12

Hi, I post a success story about a VIA VT6421A based SATA/PATA PCI controller. The flashrom can probe/read/write successfully the onboard PMC Pm49FL004 chip. I downloaded the patch from http://patchwork.coreboot.org/patch/3214/. Just one thing... "BAR type unknown..." I don't known the meaning, but it worked for me without errors. Please add the patch from above to the trunk. I attached a verbose probe output too. flashrom v0.9.3-r1362 on Linux 2.6.38-std220-i586 (i686), built with libpci 3.0.0, GCC 4.3.2, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found "VIA VT6421A" (1106:3249, BDF 00:0a.0). BAR type unknown, please report a bug at flashrom(a)flashrom.org === This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output to flashrom(a)flashrom.org if it works for you. Please add the name of your PCI device to the subject. Thank you for your help! === Found chip "PMC Pm49FL004" (512 kB, LPC, FWH) on atavia. Reading flash... done. Best regards, Szabolcs Magyar P.S.: Sorry for my english.

3 5

2 flashes on SPI bus
by Andrei Dolnikov 23 Sep '12

23 Sep '12

Hello folks, I would like to use a flashrom utility to access 2 serial flashes on the SPI bus of my x86 board, but I'm struggling with the second one. So I'm looking for any help, hints or advices which can help me to solve this issue. I have custom x86 board (Atom n450 CPU, ICH8M chipset) which have 2 serial flashes installed on it. The first one is SST25VF016B and the second one is Numonyx M45PE16. The M45PE16 is pretty the similar to the M25PE16. Both this chips are connected to the SPI bus of the ICH8M chipset, the CS (chip select) signal of the SST25VF is routed to the SPI_CS0 and the CS signal of the M45PE16 is routed to the SPI_CS1. I can successfully read, erase and write the SST flash. Trying to figure out if flashrom utility can find the second Numonyx flash I've added the proper description for it to the flashchips.c (actually I've leaved it the same as for M25PE16 but changed model_id field). Unfortunately it didn't help me at all. So I'm wondering if flashrom can't find M45PE16 flash because of cleared SPI_CS1 signal and how can I enable it? Does flashrom utility support such kind of configurations or does it simply searching for the flash on CS0? Probably some of you have some ideas on enabling SPI_CS1 or even some useful links etc. Unfortunately the official Intel ICH8M documentation looks kind of complicated and no so clear to me. I'll of course digg into it but any help, hints or advices are highly appreciated! Thanks in advance, xborodax.

2 1

#5: Winbond W25Q128 for ICH
by flashrom 18 Sep '12

18 Sep '12

#5: Winbond W25Q128 for ICH ----------------------------------+--------------------------- Reporter: rheneus.paul@… | Owner: hailfinger Type: defect | Status: new Priority: critical | Milestone: Component: flashrom | Version: Keywords: | Dependencies: Patch Status: there is no patch | ----------------------------------+--------------------------- I could not use flashrom 0.9.3 -r1205 to detect Winbond W25Q128 to program BIOS. Attached the read log Just by adding WINBOND_NEX_W25Q128 0x4018 in flashchips.c for W25Q128, similar to W25Q64 throws run Opcode 0x3 error for read. Attached Verbose log of read -- Ticket URL: <http://www.flashrom.org/trac/flashrom/ticket/5> flashrom <http://www.flashrom.org/>

1 2

Add support for unlock and write to Atmel AT26F040
by tim＠buttersideup.com 17 Sep '12

17 Sep '12

Add support for unlock and write to Atmel AT26F040 SPI 512k chips. Tested using a bus pirate only. I'm unavailble for a couple of weeks imminently, but will reply on return if pos... Cheers, Tim. ~# flashrom -c AT26F004 -p buspirate_spi:dev=/dev/ttyUSB0 -Vw rr620WDA-read-rom-image flashrom v0.9.3-r1349 on Linux 2.6.32-5-686 (i686), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1088M loops per second, 10 myus = 10 us, 100 myus = 95 us, 1000 myus = 945 us, 10000 myus = 9495 us, 4 myus = 5 us, OK. Initializing buspirate_spi programmer SPI speed is 8MHz Raw bitbang mode version 1 Raw SPI mode version 1 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x400 Chip status register is 1c Found chip "Atmel AT26F004" (512 kB, SPI) on buspirate_spi. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Some block protection in effect, disabling All write protection disabled! Reading old flash chip contents... Erasing and writing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x000fff:EW, 0x001000-0x001fff:W, 0x002000-0x002fff:S, 0x003000-0x003fff:S, 0x004000-0x004fff:S, 0x005000-0x005fff:S, 0x006000-0x006fff:S, 0x007000-0x007fff:S, 0x008000-0x008fff:S, 0x009000-0x009fff:S, 0x00a000-0x00afff:S, 0x00b000-0x00bfff:S, 0x00c000-0x00cfff:W, 0x00d000-0x00dfff:S, 0x00e000-0x00efff:S, 0x00f000-0x00ffff:S, 0x010000-0x010fff:EW, 0x011000-0x011fff:EW, 0x012000-0x012fff:EW, 0x013000-0x013fff:EW, 0x014000-0x014fff:EW, 0x015000-0x015fff:W, 0x016000-0x016fff:W, 0x017000-0x017fff:S, 0x018000-0x018fff:S, 0x019000-0x019fff:S, 0x01a000-0x01afff:S, 0x01b000-0x01bfff:S, 0x01c000-0x01cfff:S, 0x01d000-0x01dfff:S, 0x01e000-0x01efff:S, 0x01f000-0x01ffff:S, 0x020000-0x020fff:EW, 0x021000-0x021fff:W, 0x022000-0x022fff:W, 0x023000-0x023fff:W, 0x024000-0x024fff:W, 0x025000-0x025fff:W, 0x026000-0x026fff:W, 0x027000-0x027fff:W, 0x028000-0x028fff:W, 0x029000-0x029fff:W, 0x02a000-0x02aff f:W, 0x02b000-0x02bfff:W, 0x02c000-0x02cfff:W, 0x02d000-0x02dfff:W, 0x02e000-0x02efff:W, 0x02f000-0x02ffff:W, 0x030000-0x030fff:W, 0x031000-0x031fff:W, 0x032000-0x032fff:W, 0x033000-0x033fff:W, 0x034000-0x034fff:W, 0x035000-0x035fff:W, 0x036000-0x036fff:W, 0x037000-0x037fff:W, 0x038000-0x038fff:W, 0x039000-0x039fff:W, 0x03a000-0x03afff:W, 0x03b000-0x03bfff:W, 0x03c000-0x03cfff:W, 0x03d000-0x03dfff:S, 0x03e000-0x03efff:S, 0x03f000-0x03ffff:S, 0x040000-0x040fff:S, 0x041000-0x041fff:S, 0x042000-0x042fff:S, 0x043000-0x043fff:S, 0x044000-0x044fff:S, 0x045000-0x045fff:S, 0x046000-0x046fff:S, 0x047000-0x047fff:S, 0x048000-0x048fff:S, 0x049000-0x049fff:S, 0x04a000-0x04afff:S, 0x04b000-0x04bfff:S, 0x04c000-0x04cfff:S, 0x04d000-0x04dfff:S, 0x04e000-0x04efff:S, 0x04f000-0x04ffff:S, 0x050000-0x050fff:S, 0x051000-0x051fff:S, 0x052000-0x052fff:S, 0x053000-0x053fff:S, 0x054000-0x054fff:S, 0x055000-0x055fff:S, 0x056000-0x056fff:S, 0x057000-0x057fff:S, 0x058000-0x058fff:S, 0x059000-0x059fff: S, 0x05a000-0x05afff:S, 0x05b000-0x05bfff:W, 0x05c000-0x05cfff:W, 0x05d000-0x05dfff:S, 0x05e000-0x05efff:S, 0x05f000-0x05ffff:S, 0x060000-0x060fff:S, 0x061000-0x061fff:S, 0x062000-0x062fff:S, 0x063000-0x063fff:S, 0x064000-0x064fff:S, 0x065000-0x065fff:S, 0x066000-0x066fff:S, 0x067000-0x067fff:S, 0x068000-0x068fff:S, 0x069000-0x069fff:S, 0x06a000-0x06afff:S, 0x06b000-0x06bfff:S, 0x06c000-0x06cfff:S, 0x06d000-0x06dfff:S, 0x06e000-0x06efff:S, 0x06f000-0x06ffff:S, 0x070000-0x070fff:S, 0x071000-0x071fff:S, 0x072000-0x072fff:S, 0x073000-0x073fff:S, 0x074000-0x074fff:S, 0x075000-0x075fff:S, 0x076000-0x076fff:S, 0x077000-0x077fff:S, 0x078000-0x078fff:S, 0x079000-0x079fff:S, 0x07a000-0x07afff:S, 0x07b000-0x07bfff:S, 0x07c000-0x07cfff:S, 0x07d000-0x07dfff:S, 0x07e000-0x07efff:S, 0x07f000-0x07ffff:S Done. Verifying flash... VERIFIED. Raw bitbang mode version 1 Bus Pirate shutdown completed. Signed-off-by: Tim Small <tim(a)seoss.co.uk> Index: at25.c =================================================================== --- at25.c (revision 1349) +++ at25.c (working copy) @@ -215,6 +215,8 @@ /* spi_disable_blockprotect_at25df is not really the right way to do * this, but the side effects of said function work here as well. */ + /* FIXME? This does a global unlock, but at25f don't have this command? + */ return spi_disable_blockprotect_at25df(flash); } @@ -285,3 +287,71 @@ } return 0; } + + +int spi_disable_blockprotect_at26f040(struct flashchip *flash) +{ + uint8_t status; + uint32_t i; + int result; + + /* See Page 19 * + * http://www.atmel.com/dyn/resources/prod_documents/doc3588.pdf */ + + /* Write Protect Pin status: 0 == cannot set SPRL to 0 (unlocked) */ + const uint8_t stat_bit_WPP = (1 << 4); + + /* Software Protection Status: 00 == all sectors unprotected */ + const uint8_t stat_bit_SWP = (3 << 2); + + /* Sector Protection registers locked: 0 == unlocked. * + * Cannot be set to 0 if WPP is 1 (hardware lock). */ + const uint8_t stat_bit_SPRL = (1 << 7); + + /* Page 6 */ + const uint8_t at26f004_unprotect_sector = 0x39; + + status = spi_read_status_register(); + /* If block protection is disabled, OK to go ahead, stop here. */ + if ((status & stat_bit_SWP) == 0) + return 0; + + msg_cdbg("Some block protection in effect, disabling\n"); + if (status & stat_bit_SPRL) { + msg_cdbg("Need to disable Sector Protection Register Lock\n"); + if ((status & stat_bit_WPP) == 0) { + msg_cerr("The chips write-protect pin is being " + "asserted (driven low) by external hardware." + "\nWriting is impossible :-(.\n"); + return 1; + } + /* All bits except bit 7 (SPRL) are readonly. */ + /* Unlock sector protection registers. */ + result = spi_write_status_register(flash, status & ~stat_bit_SPRL); + if (result) { + msg_cerr("spi_write_status_register failed\n"); + return result; + } + + } + /* Call unprotect sector on each sector. We need to give an address */ + /* within each sector, and the smallest sector is 8KB. */ + for (i = 0; i < 0x80000; i += 0x1000) { + const unsigned char cmd[4] = { at26f004_unprotect_sector, + (i >> 16) & 0xff, + (i >> 8) & 0xff, + i & 0xff}; + /* set the chip's "WEL" write latch - WREN (Write Enable) */ + spi_write_enable(); + spi_send_command(sizeof(cmd), 0, cmd, NULL); + } + status = spi_read_status_register(); + if ((status & stat_bit_SWP) != 0) { + msg_cerr("Block protection could not be disabled!\n"); + return 1; + } else { + msg_cerr("All write protection disabled!\n"); + } + + return 0; +} Index: spi25.c =================================================================== --- spi25.c (revision 1349) +++ spi25.c (working copy) @@ -1210,3 +1210,94 @@ return 0; } + + +/* This is for Atmel chips only (AT26F004, AT26DF161A etc.) - the 25F004 only + * does either this mode, or byte-at-a-time. */ +int spi_at26_write_sequential(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + /* ref http://www.atmel.com/dyn/resources/prod_documents/doc3588.pdf + * page 9 etc. */ + const int AT26_SEQ_BYTE_WRITE_OUTSIZE = 5; + const int AT26_SEQ_BYTE_WRITE_CONT_OUTSIZE = 2; + const int AT26_SEQ_BYTE_WRITE_CMD = 0xaf; + uint32_t pos = start; + int result; + unsigned char cmd[4] = { + AT26_SEQ_BYTE_WRITE_CMD + }; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = AT26_SEQ_BYTE_WRITE_OUTSIZE, + .writearr = (const unsigned char[]){ + AT26_SEQ_BYTE_WRITE_CMD, + (start >> 16) & 0xff, + (start >> 8) & 0xff, + (start & 0xff), + buf[0] + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + switch (spi_programmer->type) { +#if CONFIG_INTERNAL == 1 +#if defined(__i386__) || defined(__x86_64__) + case SPI_CONTROLLER_IT87XX: + case SPI_CONTROLLER_WBSIO: + msg_perr("%s: impossible with this SPI controller," + " degrading to byte program\n", __func__); + return spi_chip_write_1(flash, buf, start, len); +#endif +#endif + default: + break; + } + + cmds[1].writearr = (const unsigned char[]){ + 0xAF, + (pos >> 16) & 0xff, + (pos >> 8) & 0xff, + (pos & 0xff), + buf[pos - start] + }; + + + result = spi_send_multicommand(cmds); + if (result) { + msg_cerr("%s failed during start command execution\n", + __func__); + /* FIXME: Should we send WRDI here as well to make sure the chip + * is not in seuquential wirte mode? + */ + return result; + } + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + programmer_delay(5); + + pos ++; + + while (pos < start + len) { + cmd[1] = buf[pos++ - start]; + spi_send_command(AT26_SEQ_BYTE_WRITE_CONT_OUTSIZE, 0, cmd, NULL); + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + programmer_delay(5); + } + + /* Use WRDI to exit sequential write mode. This needs to be done before + * issuing any other non-sequential-byte-write commands. + */ + spi_write_disable(); + + return 0; +} Index: flashchips.c =================================================================== --- flashchips.c (revision 1349) +++ flashchips.c (working copy) @@ -1883,6 +1883,7 @@ }, .printlock = spi_prettyprint_status_register_atmel_at26df081a, .unlock = spi_disable_blockprotect, + /* Should support spi_at26_write_sequential too, but it's untested */ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, @@ -1914,6 +1915,7 @@ .model_id = ATMEL_AT26F004, .total_size = 512, .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -1936,7 +1938,9 @@ .block_erase = spi_block_erase_c7, } }, - .write = NULL /* Incompatible Page write */, + .unlock = spi_disable_blockprotect_at26f040, + /* also supports spi_chip_write_1, but nothing else */ + .write = spi_at26_write_sequential, .read = spi_chip_read, .voltage = {2700, 3600}, }, Index: chipdrivers.h =================================================================== --- chipdrivers.h (revision 1349) +++ chipdrivers.h (working copy) @@ -55,6 +55,7 @@ int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); +int spi_at26_write_sequential(struct flashchip *flash, uint8_t *buf, int start, int len); /* a25.c */ int spi_prettyprint_status_register_amic_a25l05p(struct flashchip *flash); @@ -74,6 +75,7 @@ int spi_disable_blockprotect_at25f(struct flashchip *flash); int spi_disable_blockprotect_at25fs010(struct flashchip *flash); int spi_disable_blockprotect_at25fs040(struct flashchip *flash); +int spi_disable_blockprotect_at26f040(struct flashchip *flash); /* 82802ab.c */ uint8_t wait_82802ab(struct flashchip *flash);

3 4

Flashing M/B Bios (Asus P5LD2-VM) goes wrong
by Emil Sirbu 07 Sep '12

07 Sep '12

Hello, I have an ASUS P5LD2-VM, and I try to update bios, first with flashrom v0.9.2-r1028 ( http://paste.flashrom.org/view.php?id=489 ) then with 0.9.3 ( http://paste.flashrom.org/view.php?id=490 also, the ROM is at http://paste.flashrom.org/uploads/491.bin ) but: Writing flash chip... Erasing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x000fff, 0x001000-0x001fff, 0x002000-0x002fff, 0x003000-0xff, 0x004000-0x004fff, 0x005000-0x005fff, ERASE FAILED at 0x00005760! Expected=0xff, Read=0x50, failed byte count from 0x00005000-0x00005fff: 0x87a ERASE FAILED! Can you help whit this? I'm carco on freenode/#flashrom channel Thank you, Emil Sirbu

3 4

Gembird-PCI-VIA VT6421A-W39V040C
by Alexey 05 Sep '12

05 Sep '12

Hi! I'm going to flash Gembird PCI 3SATA+1IDE controller's BIOS, there is W39V040C. I found an excellent professionaly modified ROM for this device. I will try to do it on board of ASUS P4P800E-DELUX. Just let me know, is it possible in the moment or I have to wait for a new version of flashrom.exe? This device have unfriendly relations to Radeon X1600 AGP, on board of ASRock P4i45E MB, so I found only new modified ROM of PCI controller can help. Waiting for Your answer, Alexey.

2 4

[PATCH] Hack libpci not to exit(1) during init if PCI does not work
by Carl-Daniel Hailfinger 05 Sep '12

05 Sep '12

This patch is for testing only, and not for immediate merge. libpci unhelpfully calls exit(1) instead of reporting an error if init fails. Fortunately, that part of libpci has not changed since the year 2000, so we can use a really evil hack to avoid that. We supply an alternative error printing function (which does not exit(1)) and this function detects which error is happening and hacks internal libpci structures in a way that avoids a later segfault due to NULL pointer dereference. We MUST absolutely make sure that pci_init() in libpci will not change or this hack will explode spectacularly. Once we decide that this hack is the way to go, notifying the libpci maintainer is essential. Apply this patch, then compile flashrom with make CONFIG_DUMMY=no CONFIG_INTERNAL=o CONFIG_SERPROG=no CONFIG_RAYER_SPI=no CONFIG_NIC3COM=no CONFIG_GFXNVIDIA=no CONFIG_SATASII=no CONFIG_FT2232_SPI=no CONFIG_DRKAISER=no CONFIG_NICREALTEK=no CONFIG_NICINTEL_SPI=no CONFIG_BUSPIRATE_SPI=no CONFIG_OGP_SPI=no CONFIG_SATAMV=no CONFIG_NICINTEL=yes To check if the hack works, run "flashrom -V" and respond to this mail with the output. You should get a message near the end which says that programmer initialization failed. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-libpci_hack_avoid_exit1_during_init/pcidev.c =================================================================== --- flashrom-libpci_hack_avoid_exit1_during_init/pcidev.c (Revision 1362) +++ flashrom-libpci_hack_avoid_exit1_during_init/pcidev.c (Arbeitskopie) @@ -21,6 +21,8 @@ #include <stdlib.h> #include <string.h> +#include <stdio.h> +#include <stdarg.h> #include "flash.h" #include "programmer.h" @@ -188,6 +190,58 @@ return 0; } +/* Ugliest hack ever in flashrom! Should work for all libpci versions released + * in the year 2000 or later. Checked to make sense until at least version + * 3.1.8-test1. + */ +static void fake_libpci_method_init(struct pci_access *foo) +{ + msg_pinfo("Working around another pcilib crash\n"); + return; +} + +static struct { + char *name; /* name in all libpci versions */ + char *dummy1; /* Only present in some libpci versions */ + void *dummy2; + void (*init1)(struct pci_access *); /* init in older versions */ + void (*init2)(struct pci_access *); /* init in newer versions */ + void *dummy3; + void *dummy4; + void *dummy5; + void *dummy6; + void *dummy7; + void *dummy8; + void *dummy9; + void *dummy10; +} fake_libpci_methods = { + .name = "None", + .init1 = &fake_libpci_method_init, + .init2 = &fake_libpci_method_init, +}; + +static int pci_init_failed = 0; + +static void my_libpci_generic_error(char *msg, ...) +{ + va_list ap; + + msg_pinfo("pcilib: "); + va_start(ap, msg); + vprintf(msg, ap); + va_end(ap); + msg_pinfo("\n"); + if (!strcmp(msg, "Cannot find any working access method.")) { + /* Workaround for crash, very ugly. */ + msg_pinfo("Working around pcilib crash\n"); + pacc->methods = (void *)&fake_libpci_methods; + pci_init_failed = 1; + } else { + /* Any error in libpci would result in exit(1) by default. */ + exit(1); + } +} + uintptr_t pcidev_init(int bar, const struct pcidev_status *devs) { struct pci_dev *dev; @@ -198,7 +252,14 @@ uintptr_t addr = 0, curaddr = 0; pacc = pci_alloc(); /* Get the pci_access structure */ + pacc->error = &my_libpci_generic_error; pci_init(pacc); /* Initialize the PCI library */ + /* pci_init returns void, so we have to hack it. */ + if (pci_init_failed) { + /* Yes, technically we would have to free stuff... */ + return 1; + } + pci_scan_bus(pacc); /* We want to get the list of devices */ pci_filter_init(pacc, &filter); -- http://www.hailfinger.org/

4 7

[PATCH] Fix flashrom -L
by Carl-Daniel Hailfinger 26 Aug '12

26 Aug '12

flashrom -L output did not contain a list of programmers nor were all programmers listed. Fix it. (Well, mostly. Some programmers have no devices listed. And formatting on 80 column screens is totally broken for the flash chip list.) Wiki output is unchanged, and will need separate fixups. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> New output from flashrom -L follows: flashrom v0.9.2-r1196 on Linux 2.6.22.19-0.2-default (i686), built with libpci 2.2.6, LLVM Clang 2.8 (trunk 108130), little endian flashrom is free software, get the source code at http://www.flashrom.org Supported flash chips (total: 261): Vendor Device Tested Known Size/KB: Type: OK Broken (P = PROBE, R = READ, E = ERASE, W = WRITE) AMD Am29F010A/B P R E W 128 Parallel AMD Am29F002(N)BB 256 Parallel AMD Am29F002(N)BT 256 Parallel AMD Am29F016D 2048 Parallel AMD Am29F040B 512 Parallel AMD Am29F080B 1024 Parallel AMD Am29LV040B P R E W 512 Parallel AMD Am29LV081B 1024 Parallel AMIC A25L05PT 64 SPI AMIC A25L05PU 64 SPI AMIC A25L10PT 128 SPI AMIC A25L10PU 128 SPI AMIC A25L20PT 256 SPI AMIC A25L20PU 256 SPI AMIC A25L40PT P R W 512 SPI AMIC A25L40PU P R W 512 SPI AMIC A25L80P P R E W 1024 SPI AMIC A25L16PT 2048 SPI AMIC A25L16PU P R W 2048 SPI AMIC A25L512 64 SPI AMIC A25L010 128 SPI AMIC A25L020 256 SPI AMIC A25L040 512 SPI AMIC A25L080 1024 SPI AMIC A25L016 2048 SPI AMIC A25L032 4096 SPI AMIC A25LQ032 4096 SPI AMIC A29002B 256 Parallel AMIC A29002T P R W 256 Parallel AMIC A29040B 512 Parallel AMIC A49LF040A P R E W 512 LPC Atmel AT25DF021 256 SPI Atmel AT25DF041A 512 SPI Atmel AT25DF081 1024 SPI Atmel AT25DF081A 1024 SPI Atmel AT25DF161 2048 SPI Atmel AT25DF321 P R E W 4096 SPI Atmel AT25DF321A 4096 SPI Atmel AT25DF641 8192 SPI Atmel AT25DQ161 2048 SPI Atmel AT25F512B 64 SPI Atmel AT25FS010 128 SPI Atmel AT25FS040 512 SPI Atmel AT26DF041 512 SPI Atmel AT26DF081A P R 1024 SPI Atmel AT26DF161 2048 SPI Atmel AT26DF161A 2048 SPI Atmel AT26F004 512 SPI Atmel AT29C512 64 Parallel Atmel AT29C010A P R E W 128 Parallel Atmel AT29C020 256 Parallel Atmel AT29C040A 512 Parallel Atmel AT45CS1282 R 16896 SPI Atmel AT45DB011D R 128 SPI Atmel AT45DB021D R 256 SPI Atmel AT45DB041D R 512 SPI Atmel AT45DB081D R 1024 SPI Atmel AT45DB161D R 2048 SPI Atmel AT45DB321C R 4224 SPI Atmel AT45DB321D R 4096 SPI Atmel AT45DB642D R 8192 SPI Atmel AT49BV512 64 Parallel Atmel AT49F020 P R E W 256 Parallel Atmel AT49F002(N) 256 Parallel Atmel AT49F002(N)T P R W 256 Parallel Bright BM29F040 P R 512 Parallel EMST F49B002UA 256 Parallel EMST F25L008A 1024 SPI Eon EN25B05 64 SPI Eon EN25B05T 64 SPI Eon EN25B10 128 SPI Eon EN25B10T 128 SPI Eon EN25B20 256 SPI Eon EN25B20T 256 SPI Eon EN25B40 512 SPI Eon EN25B40T 512 SPI Eon EN25B80 1024 SPI Eon EN25B80T 1024 SPI Eon EN25B16 2048 SPI Eon EN25B16T 2048 SPI Eon EN25B32 4096 SPI Eon EN25B32T 4096 SPI Eon EN25B64 8192 SPI Eon EN25B64T 8192 SPI Eon EN25D16 2048 SPI Eon EN25F05 64 SPI Eon EN25F10 128 SPI Eon EN25F20 256 SPI Eon EN25F40 P 512 SPI Eon EN25F80 P R E W 1024 SPI Eon EN25F16 2048 SPI Eon EN25F32 4096 SPI Eon EN29F010 P R E W 128 Parallel Eon EN29F002(A)(N)B P R W 256 Parallel Eon EN29F002(A)(N)T P R W 256 Parallel Fujitsu MBM29F004BC 512 Parallel Fujitsu MBM29F004TC 512 Parallel Fujitsu MBM29F400BC W 512 Parallel Fujitsu MBM29F400TC 512 Parallel Hyundai HY29F002T P R E W 256 Parallel Hyundai HY29F002B 256 Parallel Hyundai HY29F040A 512 Parallel Intel 28F001BN/BX-B 128 Parallel Intel 28F001BN/BX-T 128 Parallel Intel 28F002BC/BL/BV/BX-T P R E W 256 Parallel Intel 28F008S3/S5/SC 512 Parallel Intel 28F004B5/BE/BV/BX-B 512 Parallel Intel 28F004B5/BE/BV/BX-T 512 Parallel Intel 28F400BV/BX/CE/CV-B 512 Parallel Intel 28F400BV/BX/CE/CV-T 512 Parallel Intel 82802AB P R 512 FWH Intel 82802AC P R 1024 FWH Macronix MX25L512 64 SPI Macronix MX25L1005 128 SPI Macronix MX25L2005 256 SPI Macronix MX25L4005 P R W 512 SPI Macronix MX25L8005 P R E W 1024 SPI Macronix MX25L1605 P R W 2048 SPI Macronix MX25L1635D 2048 SPI Macronix MX25L1635E 2048 SPI Macronix MX25L3205 P R W 4096 SPI Macronix MX25L3235D 4096 SPI Macronix MX25L6405 P 8192 SPI Macronix MX25L12805 16384 SPI Macronix MX29F001B 128 Parallel Macronix MX29F001T 128 Parallel Macronix MX29F002B 256 Parallel Macronix MX29F002T P R W 256 Parallel Macronix MX29F040 512 Parallel Macronix MX29LV040 512 Parallel MoselVitelic V29C51000B 64 Parallel MoselVitelic V29C51000T 64 Parallel MoselVitelic V29C51400B 512 Parallel MoselVitelic V29C51400T 512 Parallel MoselVitelic V29LC51000 64 Parallel MoselVitelic V29LC51001 128 Parallel MoselVitelic V29LC51002 256 Parallel Numonyx M25PE10 128 SPI Numonyx M25PE20 256 SPI Numonyx M25PE40 512 SPI Numonyx M25PE80 P R E W 1024 SPI Numonyx M25PE16 2048 SPI PMC Pm25LV010 128 SPI PMC Pm25LV016B 2048 SPI PMC Pm25LV020 256 SPI PMC Pm25LV040 512 SPI PMC Pm25LV080B 1024 SPI PMC Pm25LV512 64 SPI PMC Pm29F002T P R E W 256 Parallel PMC Pm29F002B 256 Parallel PMC Pm39LV010 P R E W 128 Parallel PMC Pm39LV020 256 Parallel PMC Pm39LV040 512 Parallel PMC Pm49FL002 P R E W 256 LPC,FWH PMC Pm49FL004 P R E W 512 LPC,FWH Sanyo LF25FW203A 2048 SPI Sharp LHF00L04 1024 FWH Spansion S25FL008A P R E W 1024 SPI Spansion S25FL016A P R W 2048 SPI SST SST25VF016B P R E W 2048 SPI SST SST25VF032B P R E W 4096 SPI SST SST25VF064C P R E W 8192 SPI SST SST25VF040.REMS P R 512 SPI SST SST25VF040B 512 SPI SST SST25LF040A.RES P 512 SPI SST SST25VF040B.REMS P R 512 SPI SST SST25VF080B P R E W 1024 SPI SST SST28SF040A 512 Parallel SST SST29EE010 P R W 128 Parallel SST SST29LE010 128 Parallel SST SST29EE020A P R E W 256 Parallel SST SST29LE020 P R E W 256 Parallel SST SST39SF512 64 Parallel SST SST39SF010A P R W 128 Parallel SST SST39SF020A P R E W 256 Parallel SST SST39SF040 P R E W 512 Parallel SST SST39VF512 P R E W 64 Parallel SST SST39VF010 P R E W 128 Parallel SST SST39VF020 256 Parallel SST SST39VF040 512 Parallel SST SST39VF080 1024 Parallel SST SST49LF002A/B P R E W 256 FWH SST SST49LF003A/B P R 384 FWH SST SST49LF004A/B P R E W 512 FWH SST SST49LF004C 512 FWH SST SST49LF008A P R E W 1024 FWH SST SST49LF008C 1024 FWH SST SST49LF016C P R W 2048 FWH SST SST49LF020 P R E W 256 LPC SST SST49LF020A P R E W 256 LPC SST SST49LF040 P R E W 512 LPC SST SST49LF040B P R E W 512 LPC SST SST49LF080A P R E W 1024 LPC SST SST49LF160C P R E W 2048 LPC ST M25P05-A 64 SPI ST M25P05.RES 64 SPI ST M25P10-A P R E W 128 SPI ST M25P10.RES 128 SPI ST M25P20 256 SPI ST M25P40 P R W 512 SPI ST M25P40-old 512 SPI ST M25P80 P R W 1024 SPI ST M25P16 P R W 2048 SPI ST M25P32 P R W 4096 SPI ST M25P64 8192 SPI ST M25P128 16384 SPI ST M25PX32 P R E W 4096 SPI ST M25PX64 P R E W 8192 SPI ST M29F002B 256 Parallel ST M29F002T/NT 256 Parallel ST M29F040B 512 Parallel ST M29F400BB W 512 Parallel ST M29F400BT 512 Parallel ST M29W010B 128 Parallel ST M29W040B 512 Parallel ST M29W512B P R E W 64 Parallel ST M50FLW040A 512 LPC,FWH ST M50FLW040B 512 LPC,FWH ST M50FLW080A P R E W 1024 LPC,FWH ST M50FLW080B 1024 LPC,FWH ST M50FW002 256 FWH ST M50FW016 2048 FWH ST M50FW040 P R 512 FWH ST M50FW080 P R 1024 FWH ST M50LPW116 2048 LPC SyncMOS/MoselVitelic {F,S,V}29C51001B 128 Parallel SyncMOS/MoselVitelic {F,S,V}29C51001T 128 Parallel SyncMOS/MoselVitelic {F,S,V}29C51002B 256 Parallel SyncMOS/MoselVitelic {F,S,V}29C51002T P R E W 256 Parallel SyncMOS/MoselVitelic {F,S,V}29C51004B 512 Parallel SyncMOS/MoselVitelic {F,S,V}29C51004T 512 Parallel SyncMOS/MoselVitelic {S,V}29C31004B 512 Parallel SyncMOS/MoselVitelic {S,V}29C31004T 512 Parallel TI TMS29F002RB 256 Parallel TI TMS29F002RT 256 Parallel Winbond W25Q80 P R E W 1024 SPI Winbond W25Q16 2048 SPI Winbond W25Q32 P R E W 4096 SPI Winbond W25Q64 P R W 8192 SPI Winbond W25x10 128 SPI Winbond W25x20 256 SPI Winbond W25x40 P R E W 512 SPI Winbond W25x80 P R E W 1024 SPI Winbond W25x16 P R E W 2048 SPI Winbond W25x32 P 4096 SPI Winbond W25x64 8192 SPI Winbond W29C010(M)/W29C011A/W29EE011/W29EE012 P R W 128 Parallel Winbond W29C020(C)/W29C022 P R E W 256 Parallel Winbond W29C040/P 512 Parallel Winbond W29C010(M)/W29C011A/W29EE011/W29EE012 P R E W 128 Parallel Winbond W39V040A P R W 512 LPC Winbond W39V040(F)B P R E W 512 LPC Winbond W39V040(F)C 512 LPC Winbond W39V040FA P R E W 512 FWH Winbond W39V080A 1024 LPC Winbond W49F002U/N P R E W 256 Parallel Winbond W49F020 P 256 Parallel Winbond W49V002A P R E W 256 LPC Winbond W49V002FA P R W 256 FWH Winbond W39V080FA P R E W 1024 FWH Winbond W39V080FA (dual mode) 512 FWH Supported programmers: internal, dummy, nic3com, nicrealtek, nicsmc1211, nicnatsemi, gfxnvidia, drkaiser, satasii, atahpt, it87spi, ft2232_spi, serprog, buspirate_spi, dediprog, rayer_spi, nicintel_spi Supported devices for the internal programmer: Supported chipsets (total: 152): Vendor: Chipset: PCI IDs: ALi M1533 10b9:1533 AMD AMD-768 1022:7440 AMD AMD8111 1022:7468 AMD CS5530(A) 1078:0100 AMD CS5536 1022:2080 AMD CS5536 1022:2090 AMD Elan SC520 1022:3000 AMD SB600 1002:438d AMD SB700/SB710/SB750 1002:439d AMD SC1100 100b:0510 (untested) ATI SB400 1002:4377 Broadcom OSB4 1166:0200 Broadcom HT-1000 1166:0205 Intel 3400 Desktop 8086:3b00 (untested) Intel 3400 Mobile 8086:3b01 (untested) Intel P55 8086:3b02 (untested) Intel PM55 8086:3b03 (untested) Intel H55 8086:3b06 (untested) Intel QM57 8086:3b07 Intel H57 8086:3b08 (untested) Intel HM55 8086:3b09 (untested) Intel Q57 8086:3b0a (untested) Intel HM57 8086:3b0b (untested) Intel 3400 Mobile SFF 8086:3b0d (untested) Intel B55 8086:3b0e (untested) Intel QS57 8086:3b0f (untested) Intel 3400 8086:3b12 (untested) Intel 3420 8086:3b14 (untested) Intel 3450 8086:3b16 (untested) Intel B55 8086:3b1e (untested) Intel 440MX 8086:7198 Intel 6300ESB 8086:25a1 Intel 631xESB/632xESB/3100 8086:2670 Intel EP80579 8086:5031 Intel ICH0 8086:2420 Intel ICH10 8086:3a18 Intel ICH10D 8086:3a1a Intel ICH10DO 8086:3a14 Intel ICH10R 8086:3a16 Intel ICH2 8086:2440 Intel ICH2-M 8086:244c Intel ICH3-M 8086:248c Intel ICH3-S 8086:2480 Intel ICH4/ICH4-L 8086:24c0 Intel ICH4-M 8086:24cc Intel ICH5/ICH5R 8086:24d0 Intel ICH6/ICH6R 8086:2640 Intel ICH6-M 8086:2641 Intel ICH7DH 8086:27b0 Intel ICH7/ICH7R 8086:27b8 Intel ICH7M 8086:27b9 Intel ICH7MDH 8086:27bd Intel NM10 8086:27bc Intel ICH 8086:2410 Intel ICH8DH 8086:2812 Intel ICH8DO 8086:2814 Intel ICH8/ICH8R 8086:2810 Intel ICH8M 8086:2815 Intel ICH8M-E 8086:2811 Intel ICH9 8086:2918 Intel ICH9DH 8086:2912 Intel ICH9DO 8086:2914 Intel ICH9M 8086:2919 Intel ICH9M-E 8086:2917 Intel ICH9R 8086:2916 Intel ICH9 Engineering Sample 8086:2910 Intel MPIIX 8086:1234 (untested) Intel PIIX3 8086:7000 Intel PIIX4/4E/4M 8086:7110 Intel PIIX 8086:122e Intel Poulsbo 8086:8119 NVIDIA nForce4/MCP4 10de:0030 NVIDIA CK804 10de:0050 NVIDIA CK804 10de:0051 NVIDIA NForce2 10de:0060 NVIDIA NForce3 10de:00e0 NVIDIA CK804 10de:00d3 NVIDIA MCP51 10de:0260 (untested) NVIDIA MCP51 10de:0261 (untested) NVIDIA MCP51 10de:0262 (untested) NVIDIA MCP51 10de:0263 (untested) NVIDIA MCP55 10de:0360 NVIDIA MCP55 10de:0362 NVIDIA MCP55 10de:0363 NVIDIA MCP55 10de:0364 NVIDIA MCP55 10de:0365 NVIDIA MCP55 10de:0366 NVIDIA MCP55 10de:0367 NVIDIA MCP61 10de:03e0 (untested) NVIDIA MCP61 10de:03e1 (untested) NVIDIA MCP61 10de:03e2 (untested) NVIDIA MCP61 10de:03e3 (untested) NVIDIA MCP65 10de:0440 (untested) NVIDIA MCP65 10de:0441 (untested) NVIDIA MCP65 10de:0442 (untested) NVIDIA MCP65 10de:0443 (untested) NVIDIA MCP67 10de:0548 NVIDIA MCP78S 10de:075c (untested) NVIDIA MCP78S 10de:075d (untested) NVIDIA MCP73 10de:07d7 (untested) NVIDIA MCP79 10de:0aac (untested) NVIDIA MCP79 10de:0aad (untested) NVIDIA MCP79 10de:0aae (untested) NVIDIA MCP79 10de:0aaf (untested) SiS 85C496+497 1039:0496 (untested) SiS 501/5101/5501 1039:0406 (untested) SiS 5511 1039:5511 (untested) SiS 5596 1039:5596 (untested) SiS 5571 1039:5571 (untested) SiS 5591/5592 1039:5591 (untested) SiS 5597/5598/5581/5120 1039:5597 (untested) SiS 530 1039:0530 (untested) SiS 600 1039:5600 (untested) SiS 620 1039:0620 (untested) SiS 540 1039:0540 (untested) SiS 630 1039:0630 (untested) SiS 635 1039:0635 (untested) SiS 640 1039:0640 (untested) SiS 645 1039:0645 (untested) SiS 645DX 1039:0646 (untested) SiS 648 1039:0648 (untested) SiS 650 1039:0650 (untested) SiS 651 1039:0651 (untested) SiS 655 1039:0655 (untested) SiS 661 1039:0661 SiS 730 1039:0730 (untested) SiS 733 1039:0733 (untested) SiS 735 1039:0735 SiS 740 1039:0740 (untested) SiS 741 1039:0741 SiS 745 1039:0745 SiS 746 1039:0746 (untested) SiS 748 1039:0748 (untested) SiS 755 1039:0755 (untested) VIA VT82C585VPX 1106:0585 (untested) VIA VT82C595 1106:0595 (untested) VIA VT82C597 1106:0597 (untested) VIA VT82C69x 1106:0691 (untested) VIA VT8601/VT8601A 1106:0601 (untested) VIA VT8601T 1106:8601 (untested) VIA CX700 1106:8324 VIA VT8231 1106:8231 (untested) VIA VT8233 1106:3074 (untested) VIA VT8233A 1106:3147 VIA VT8235 1106:3177 VIA VT8237 1106:3227 VIA VT8237A 1106:3337 VIA VT8237S 1106:3372 VIA VX800 1106:8353 VIA VT82C596 1106:0596 VIA VT82C586A/B 1106:0586 VIA VT82C686A/B 1106:0686 (untested) Known boards (good: 259, bad: 18): Vendor: Board: Status: Required option: A-Trend ATC-6220 OK abit AN-M2 OK (autodetected) abit AX8 OK abit BM6 OK (autodetected) abit Fatal1ty F-I90HD OK abit IC7 OK (autodetected) abit IP35 OK (autodetected) abit IP35 Pro OK (autodetected) abit IS-10 BAD abit KN8 Ultra OK (autodetected) abit NF-M2 nView OK (autodetected) abit NF7-S OK (autodetected) abit VA6 OK (autodetected) abit VT6X4 OK -m abit:vt6x4 Acorp 6A815EPD OK (autodetected) Advantech PCM-5820 OK agami Aruma OK -m AGAMI:ARUMA Albatron PM266A Pro OK (autodetected) AOpen vKM400Am-S OK Artec Group DBE61 OK -m artecgroup:dbe61 Artec Group DBE62 OK -m artecgroup:dbe62 ASI MB-5BLMP OK ASRock 775i65G OK (autodetected) ASRock 939A785GMH/128M OK ASRock A330GC OK ASRock A770CrossFire OK ASRock ALiveNF6G-DVI OK ASRock K7S41 OK (autodetected) ASRock K7VT4A+ BAD ASRock K8S8X OK ASRock M3A790GXH/128M OK ASRock P4i65GV OK (autodetected) ASUS A7N8X Deluxe OK ASUS A7N8X-E Deluxe OK ASUS A7V133 OK ASUS A7V333 OK (autodetected) ASUS A7V400-MX OK ASUS A7V600-X OK (autodetected) ASUS A7V8X OK (autodetected) ASUS A7V8X-MX OK ASUS A7V8X-MX SE OK (autodetected) ASUS A7V8X-X OK (autodetected) ASUS A8Jm OK (autodetected) ASUS A8N OK (autodetected) ASUS A8N-E OK ASUS A8N-LA (Nagami-GL8E) OK (autodetected) ASUS A8N-SLI OK ASUS A8N-SLI Premium OK ASUS A8N-VM CSM OK (autodetected) ASUS A8NE-FM/S OK ASUS A8V Deluxe OK ASUS A8V-E Deluxe OK ASUS A8V-E SE OK ASUS K8V OK ASUS K8V SE Deluxe OK ASUS K8V-X SE OK ASUS M2A-MX OK ASUS M2A-VM OK ASUS M2N32-SLI Deluxe OK ASUS M2N-E OK ASUS M2N-SLI Deluxe OK ASUS M2NBP-VM CSM OK (autodetected) ASUS M2NPV-VM OK ASUS M2V OK ASUS M2V-MX OK (autodetected) ASUS M3A76-CM OK ASUS M3A78-EM OK ASUS M4A785TD-M EVO OK ASUS M4A79T Deluxe OK ASUS M4A87TD/USB3 OK ASUS MEW-AM BAD ASUS MEW-VM BAD ASUS P2B OK ASUS P2B-D OK ASUS P2B-DS OK ASUS P2B-F OK ASUS P2B-N OK (autodetected) ASUS P2E-M OK ASUS P2L97-S OK ASUS P3B-F BAD ASUS P4B266 OK (autodetected) ASUS P4B266-LM OK (autodetected) ASUS P4B533-E OK (autodetected) ASUS P4C800-E Deluxe OK (autodetected) ASUS P4P800 OK (autodetected) ASUS P4P800-E Deluxe OK (autodetected) ASUS P4SC-E OK (autodetected) ASUS P4SD-LA OK (autodetected) ASUS P4S800-MX OK (autodetected) ASUS P5A OK -m asus:p5a ASUS P5B OK ASUS P5B-Deluxe OK ASUS P5BV-M BAD ASUS P5GC-MX/1333 OK ASUS P5GDC Deluxe OK (autodetected) ASUS P5KC OK ASUS P5L-MX OK ASUS P5GD1 Pro OK (autodetected) ASUS P5ND2-SLI Deluxe OK (autodetected) ASUS P5PE-VM OK (autodetected) ASUS P6T SE OK ASUS P6T Deluxe OK ASUS P6T Deluxe V2 OK ASUS Z8NA-D6C OK BCOM WinNET100 OK Biostar M6TBA BAD Biostar M7NCD Pro OK Biostar P4M80-M4 OK Biostar TA780G M2+ OK Boser HS-6637 BAD Congatec conga-X852 OK Dell OptiPlex GX1 OK (autodetected) Dell PowerEdge 1850 OK (autodetected) DFI 855GME-MGF BAD DFI Blood-Iron P35 T2RL OK Elitegroup GeForce6100SM-M OK Elitegroup K7S5A OK Elitegroup K7S6A OK Elitegroup K7VTA3 OK (autodetected) Elitegroup P6IWP-Fe OK Elitegroup P6VAP-A+ OK Elitegroup RS485M-M OK Emerson ATCA-7360 OK EPoX EP-8K5A2 OK (autodetected) EPoX EP-8RDA3+ OK (autodetected) EPoX EP-BX3 OK -m epox:ep-bx3 FIC VA-502 BAD Foxconn A6VMX OK Fujitsu-Siemens ESPRIMO P5915 OK GIGABYTE GA-2761GXDK OK GIGABYTE GA-6BXC OK GIGABYTE GA-6BXDU OK GIGABYTE GA-6IEM OK (autodetected) GIGABYTE GA-6ZMA OK GIGABYTE GA-MA785GMT-UD2H OK GIGABYTE GA-770TA-UD3 OK GIGABYTE GA-7DXR OK GIGABYTE GA-7VT600 OK GIGABYTE GA-7ZM OK (autodetected) GIGABYTE GA-8IRML OK (autodetected) GIGABYTE GA-8PE667 Ultra 2 OK (autodetected) GIGABYTE GA-965P-DS4 OK GIGABYTE GA-EP35-DS3L OK GIGABYTE GA-EX58-UD4P OK GIGABYTE GA-K8N-SLI OK (autodetected) GIGABYTE GA-K8N51GMF-9 OK (autodetected) GIGABYTE GA-M57SLI-S4 OK GIGABYTE GA-M61P-S3 OK GIGABYTE GA-MA69VM-S2 OK GIGABYTE GA-MA74GM-S2H (rev. 3.0) OK GIGABYTE GA-MA770T-UD3P OK GIGABYTE GA-MA78G-DS3H OK GIGABYTE GA-MA78GM-S2H OK GIGABYTE GA-MA78GPM-DS2H OK GIGABYTE GA-MA790FX-DQ6 OK GIGABYTE GA-MA790GP-DS4H OK HP ProLiant DL145 G3 OK -m hp:dl145_g3 HP ProLiant DL165 G6 OK -m hp:dl165_g6 HP Puffer2-UL8E OK (autodetected) HP Vectra VL400 OK (autodetected) HP Vectra VL420 SFF OK (autodetected) HP xw9400 OK (autodetected) IBASE MB899 OK -m ibase:mb899 IBM x3455 OK (autodetected) IEI PICOe-9452 OK Intel D201GLY OK (autodetected) Intel EP80759 OK Intel Foxhollow OK Intel Greencity OK Intel SE440BX-2 BAD (autodetected) IWILL DK8-HTX OK -m iwill:dk8_htx Jetway J7F4K1G5D-PB OK Kontron 986LCD-M OK -m kontron:986lcd-m Lex CV700A OK Mitac 6513WU OK (autodetected) MSI MS-6153 OK MSI MS-6156 OK MSI MS-6163 (MS-6163 Pro) OK (autodetected) MSI MS-6178 BAD MSI MS-6330 (K7T Turbo) OK MSI MS-6561 (745 Ultra) OK (autodetected) MSI MS-6570 (K7N2) OK MSI MS-6577 (Xenon) OK (autodetected) MSI MS-6590 (KT4 Ultra) OK (autodetected) MSI MS-6702E (K8T Neo2-F) OK (autodetected) MSI MS-6712 (KT4V) OK (autodetected) MSI MS-6787 (P4MAM-V/P4MAM-L) OK -m msi:ms6787 MSI MS-7005 (651M-L) OK (autodetected) MSI MS-7025 (K8N Neo2 Platinum) OK (autodetected) MSI MS-7046 OK (autodetected) MSI MS-7061 (KM4M-V/KM4AM-V) OK (autodetected) MSI MS-7065 OK MSI MS-7135 (K8N Neo3) OK -m msi:k8n-neo3 MSI MS-7168 (Orion) OK MSI MS-7207 (K8NGM2-L) OK (autodetected) MSI MS-7211 (PM8M3-V) OK MSI MS-7236 (945PL Neo3) OK MSI MS-7253 (K9VGM-V) OK MSI MS-7255 (P4M890M) OK MSI MS-7260, (K9N Neo) BAD MSI MS-7312 (K9MM-V) OK MSI MS-7345 (P35 Neo2-FIR) OK MSI MS-7368 (K9AG Neo2-Digital) OK MSI MS-7376 (K9A2 Platinum) OK MSI MS-7642 (890GXM-G65) OK NEC PowerMate 2000 OK Nokia IP530 OK (autodetected) PC Engines Alix.1c OK PC Engines Alix.2c2 OK PC Engines Alix.2c3 OK PC Engines Alix.3c3 OK PC Engines Alix.3d3 OK PC Engines WRAP.2E OK Portwell PEB-4700VLA OK RCA RM4100 OK Samsung Polaris 32 OK (autodetected) Shuttle AK31 OK -m shuttle:ak31 Shuttle AK38N OK (autodetected) Shuttle AV11V30 OK Shuttle FD37 OK Shuttle FN25 OK (autodetected) Shuttle X50/X50(B) OK Soyo SY-5VD BAD Soyo SY-6BA+ III OK Soyo SY-7VCA OK (autodetected) Sun Blade x6250 OK Sun Fire x4150 BAD Sun Fire x4200 BAD Sun Fire x4540 BAD Sun Fire x4600 BAD Supermicro H8QC8 OK Supermicro X8DTT-F OK T-Online S-100 OK Tekram P6Pro-A5 OK (autodetected) Termtek TK-3370 (Rev:2.5B) OK (autodetected) Thomson IP1000 OK TriGem Lomita OK Tyan S5375-1U (Tempest i5100X) OK Tyan S1846 (Tsunami ATX) OK Tyan S2466 (Tiger MPX) OK Tyan S2498 (Tomcat K7M) OK (autodetected) Tyan S2881 (Thunder K8SR) OK Tyan S2882 (Thunder K8S Pro) OK Tyan S2882-D (Thunder K8SD Pro) OK Tyan S2891 (Thunder K8SRE) OK Tyan S2892 (Thunder K8SE) OK Tyan S2895 (Thunder K8WE) OK Tyan S2915 (Thunder n6650W) OK Tyan S2915-E (Thunder n6650W) OK Tyan S2933 (Thunder n3600S) OK Tyan S3095 (Tomcat i945GM) OK Tyan S3992 (Thunder h2000M) OK Tyan S5180 (Toledo i965R) OK Tyan S5191 (Toledo i3000R) OK Tyan S5197 (Toledo i3010W) OK Tyan S5211 (Toledo i3210W) OK Tyan S5211-1U (Toledo i3200R) OK Tyan S5220 (Toledo q35T) OK Tyan S5375 (Tempest i5100X) OK Tyan S5376 (Tempest i5100W) OK Tyan S5377 (Tempest i5100T) OK Tyan S5382 (Tempest i5000PW) OK Tyan S5397 (Tempest i5400PW) OK VIA EPIA M/MII/... OK (autodetected) VIA EPIA SP OK VIA EPIA-CN OK VIA EPIA EK OK (autodetected) VIA EPIA-EX15000G OK VIA EPIA-LN OK VIA EPIA-M700 OK VIA EPIA-N/NL OK (autodetected) VIA EPIA-NX15000G OK VIA NAB74X0 OK VIA pc2500e OK VIA PC3500G OK VIA VB700X OK ZOTAC ZBOX HD-ID11 OK Known laptops (good: 2, bad: 7): Vendor: Board: Status: Required option: Acer Aspire 1520 OK Acer Aspire One BAD ASUS Eee PC 701 4G BAD Dell Latitude CPi A366XT BAD HP/Compaq nx9005 BAD HP/Compaq nx9010 BAD IBM/Lenovo Thinkpad T40p BAD IBM/Lenovo 240 BAD Lenovo 3000 V100 TF05Cxx OK Supported devices for the dummy programmer: Supported devices for the nic3com programmer: PCI devices: 3COM 3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX [10b7:9055] 3COM 3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4 [10b7:9001] (untested) 3COM 3C90xB: PCI 10BASE-T (TPO) [10b7:9004] 3COM 3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO) [10b7:9005] (untested) 3COM 3C90xB: PCI 10BASE-T/10BASE2 (TPC) [10b7:9006] (untested) 3COM 3C90xB: PCI 10BASE-FL [10b7:900a] (untested) 3COM 3C90xB: PCI 10BASE-FX [10b7:905a] (untested) 3COM 3C905B: Cyclone 10/100/BNC [10b7:9058] 3COM 3C905C: EtherLink 10/100 PCI (TX) [10b7:9200] 3COM 3C980C: EtherLink Server 10/100 PCI (TX) [10b7:9805] (untested) Supported devices for the nicrealtek programmer: PCI devices: Realtek RTL8139/8139C/8139C+ [10ec:8139] Supported devices for the nicsmc1211 programmer: PCI devices: SMC2 1211TX [1113:1211] Supported devices for the nicnatsemi programmer: PCI devices: National Semiconductor DP83815/DP83816 [100b:20] (untested) National Semiconductor DP83820 [100b:22] (untested) Supported devices for the gfxnvidia programmer: PCI devices: NVIDIA Mutara V08 [NV2] [10de:10] (untested) NVIDIA RIVA 128 [10de:18] (untested) NVIDIA RIVA TNT [10de:20] (untested) NVIDIA RIVA TNT2/TNT2 Pro [10de:28] (untested) NVIDIA RIVA TNT2 Ultra [10de:29] (untested) NVIDIA Vanta/Vanta LT [10de:2c] (untested) NVIDIA RIVA TNT2 Model 64/Model 64 Pro [10de:2d] NVIDIA Aladdin TNT2 [10de:a0] (untested) NVIDIA GeForce 256 [10de:100] (untested) NVIDIA GeForce DDR [10de:101] (untested) NVIDIA Quadro [10de:103] (untested) NVIDIA GeForce2 MX [10de:110] (untested) NVIDIA GeForce2 MX [10de:111] (untested) NVIDIA GeForce2 GO [10de:112] (untested) NVIDIA Quadro2 MXR [10de:113] (untested) NVIDIA GeForce2 GTS/Pro [10de:150] (untested) NVIDIA GeForce2 GTS [10de:151] (untested) NVIDIA GeForce2 Ultra [10de:152] (untested) NVIDIA Quadro2 Pro [10de:153] (untested) NVIDIA GeForce 3 nFX [10de:200] (untested) NVIDIA GeForce 3 nFX [10de:201] (untested) NVIDIA GeForce 3 nFX Ultra [10de:202] (untested) NVIDIA Quadro 3 DDC [10de:203] (untested) Supported devices for the drkaiser programmer: PCI devices: Dr. Kaiser PC-Waechter (Actel FPGA) [1803:5057] Supported devices for the satasii programmer: PCI devices: Silicon Image PCI0680 Ultra ATA-133 Host Ctrl [1095:680] Silicon Image SiI 3112 [SATALink/SATARaid] SATA Ctrl [1095:3112] Silicon Image SiI 3114 [SATALink/SATARaid] SATA Ctrl [1095:3114] Silicon Image SiI 3124 PCI-X SATA Ctrl [1095:3124] Silicon Image SiI 3132 SATA Raid II Ctrl [1095:3132] Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl [1095:3512] Supported devices for the atahpt programmer: PCI devices: Highpoint HPT366/368/370/370A/372/372N [1103:04] (untested) Highpoint HPT372A/372N [1103:05] (untested) Highpoint HPT302/302N [1103:06] (untested) Supported devices for the ft2232_spi programmer: USB devices: FTDI FT2232H [0403:6010] FTDI FT4232H [0403:6011] Amontec JTAGkey [0403:cff8] Supported devices for the serprog programmer: Supported devices for the buspirate_spi programmer: Supported devices for the dediprog programmer: Supported devices for the rayer_spi programmer: Supported devices for the nicintel_spi programmer: PCI devices: Intel 82571EB Gigabit Ethernet Controller [8086:105e] Intel 82541PI Gigabit Ethernet Controller [8086:107c] Intel 82572EI Gigabit Ethernet Controller [8086:10b9] Patch: Index: flashrom-list_supported_programmers/flash.h =================================================================== --- flashrom-list_supported_programmers/flash.h (Revision 1196) +++ flashrom-list_supported_programmers/flash.h (Arbeitskopie) @@ -200,6 +200,7 @@ char *strcat_realloc(char *dest, const char *src); void print_version(void); void print_banner(void); +void list_programmers_linebreak(int startcol, int cols, int paren); int selfcheck(void); int doit(struct flashchip *flash, int force, char *filename, int read_it, int write_it, int erase_it, int verify_it); Index: flashrom-list_supported_programmers/pcidev.c =================================================================== --- flashrom-list_supported_programmers/pcidev.c (Revision 1196) +++ flashrom-list_supported_programmers/pcidev.c (Arbeitskopie) @@ -132,6 +132,7 @@ { int i; + msg_pinfo("PCI devices:\n"); for (i = 0; devs[i].vendor_name != NULL; i++) { msg_pinfo("%s %s [%02x:%02x]%s\n", devs[i].vendor_name, devs[i].device_name, devs[i].vendor_id, Index: flashrom-list_supported_programmers/cli_classic.c =================================================================== --- flashrom-list_supported_programmers/cli_classic.c (Revision 1196) +++ flashrom-list_supported_programmers/cli_classic.c (Arbeitskopie) @@ -33,11 +33,6 @@ static void cli_classic_usage(const char *name) { - const char *pname; - int pnamelen; - int remaining = 0; - enum programmer p; - printf("Usage: flashrom [-n] [-V] [-f] [-h|-R|-L|" #if CONFIG_PRINT_WIKI == 1 "-z|" @@ -83,32 +78,9 @@ "in wiki syntax\n" #endif " -p | --programmer <name>[:<param>] specify the programmer " - "device"); + "device\n"); - for (p = 0; p < PROGRAMMER_INVALID; p++) { - pname = programmer_table[p].name; - pnamelen = strlen(pname); - if (remaining - pnamelen - 2 < 0) { - printf("\n "); - remaining = 43; - } else { - printf(" "); - remaining--; - } - if (p == 0) { - printf("("); - remaining--; - } - printf("%s", pname); - remaining -= pnamelen; - if (p < PROGRAMMER_INVALID - 1) { - printf(","); - remaining--; - } else { - printf(")\n"); - } - } - + list_programmers_linebreak(37, 80, 1); printf("\nYou can specify one of -h, -R, -L, " #if CONFIG_PRINT_WIKI == 1 "-z, " Index: flashrom-list_supported_programmers/atahpt.c =================================================================== --- flashrom-list_supported_programmers/atahpt.c (Revision 1196) +++ flashrom-list_supported_programmers/atahpt.c (Arbeitskopie) @@ -30,7 +30,7 @@ #define PCI_VENDOR_ID_HPT 0x1103 -struct pcidev_status ata_hpt[] = { +const struct pcidev_status ata_hpt[] = { {0x1103, 0x0004, NT, "Highpoint", "HPT366/368/370/370A/372/372N"}, {0x1103, 0x0005, NT, "Highpoint", "HPT372A/372N"}, {0x1103, 0x0006, NT, "Highpoint", "HPT302/302N"}, Index: flashrom-list_supported_programmers/ft2232_spi.c =================================================================== --- flashrom-list_supported_programmers/ft2232_spi.c (Revision 1196) +++ flashrom-list_supported_programmers/ft2232_spi.c (Arbeitskopie) @@ -346,6 +346,7 @@ { int i; + msg_pinfo("USB devices:\n"); for (i = 0; devs[i].vendor_name != NULL; i++) { msg_pinfo("%s %s [%04x:%04x]%s\n", devs[i].vendor_name, devs[i].device_name, devs[i].vendor_id, Index: flashrom-list_supported_programmers/flashrom.c =================================================================== --- flashrom-list_supported_programmers/flashrom.c (Revision 1196) +++ flashrom-list_supported_programmers/flashrom.c (Arbeitskopie) @@ -1332,6 +1332,46 @@ msg_ginfo("\n"); } +void list_programmers_linebreak(int startcol, int cols, int paren) +{ + const char *pname; + int pnamelen; + int remaining = 0; + int firstline = 1; + enum programmer p; + + for (p = 0; p < PROGRAMMER_INVALID; p++) { + pname = programmer_table[p].name; + pnamelen = strlen(pname); + if (remaining - pnamelen - 2 < 0) { + if (firstline) + firstline = 0; + else + printf("\n"); + for (int i = 0; i < startcol; i++) + printf(" "); + remaining = cols - startcol; + } else { + printf(" "); + remaining--; + } + if (paren && (p == 0)) { + printf("("); + remaining--; + } + printf("%s", pname); + remaining -= pnamelen; + if (p < PROGRAMMER_INVALID - 1) { + printf(","); + remaining--; + } else { + if (paren) + printf(")"); + printf("\n"); + } + } +} + void print_sysinfo(void) { #if HAVE_UTSNAME == 1 Index: flashrom-list_supported_programmers/print.c =================================================================== --- flashrom-list_supported_programmers/print.c (Revision 1196) +++ flashrom-list_supported_programmers/print.c (Arbeitskopie) @@ -223,50 +223,90 @@ void print_supported(void) { - print_supported_chips(); + print_supported_chips(); + + printf("\nSupported programmers:\n"); + list_programmers_linebreak(0, 80, 0); #if CONFIG_INTERNAL == 1 - print_supported_chipsets(); - print_supported_boards_helper(boards_known, "boards"); - print_supported_boards_helper(laptops_known, "laptops"); + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_INTERNAL].name); + print_supported_chipsets(); + print_supported_boards_helper(boards_known, "boards"); + print_supported_boards_helper(laptops_known, "laptops"); #endif -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1 - printf("\nSupported PCI devices flashrom can use " - "as programmer:\n\n"); +#if CONFIG_DUMMY == 1 + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_DUMMY].name); + /* FIXME */ #endif #if CONFIG_NIC3COM == 1 - print_supported_pcidevs(nics_3com); + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_NIC3COM].name); + print_supported_pcidevs(nics_3com); #endif #if CONFIG_NICREALTEK == 1 - print_supported_pcidevs(nics_realtek); - print_supported_pcidevs(nics_realteksmc1211); + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_NICREALTEK].name); + print_supported_pcidevs(nics_realtek); + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_NICREALTEK2].name); + print_supported_pcidevs(nics_realteksmc1211); #endif #if CONFIG_NICNATSEMI == 1 - print_supported_pcidevs(nics_natsemi); + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_NICNATSEMI].name); + print_supported_pcidevs(nics_natsemi); #endif #if CONFIG_GFXNVIDIA == 1 - print_supported_pcidevs(gfx_nvidia); + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_GFXNVIDIA].name); + print_supported_pcidevs(gfx_nvidia); #endif #if CONFIG_DRKAISER == 1 - print_supported_pcidevs(drkaiser_pcidev); + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_DRKAISER].name); + print_supported_pcidevs(drkaiser_pcidev); #endif #if CONFIG_SATASII == 1 - print_supported_pcidevs(satas_sii); + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_SATASII].name); + print_supported_pcidevs(satas_sii); #endif #if CONFIG_ATAHPT == 1 - print_supported_pcidevs(ata_hpt); + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_ATAHPT].name); + print_supported_pcidevs(ata_hpt); #endif -#if CONFIG_NICINTEL_SPI == 1 - print_supported_pcidevs(nics_intel_spi); +#if CONFIG_FT2232_SPI == 1 + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_FT2232_SPI].name); + print_supported_usbdevs(devs_ft2232spi); #endif - -#if CONFIG_FT2232_SPI+CONFIG_DEDIPROG >= 1 - printf("\nSupported USB devices flashrom can use " - "as programmer:\n\n"); +#if CONFIG_SERPROG == 1 + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_SERPROG].name); + /* FIXME */ #endif - -#if CONFIG_FT2232_SPI == 1 - print_supported_usbdevs(devs_ft2232spi); +#if CONFIG_BUSPIRATE_SPI == 1 + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_BUSPIRATE_SPI].name); + /* FIXME */ #endif +#if CONFIG_DEDIPROG == 1 + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_DEDIPROG].name); + /* FIXME */ +#endif +#if CONFIG_RAYER_SPI == 1 + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_RAYER_SPI].name); + /* FIXME */ +#endif +#if CONFIG_NICINTEL_SPI == 1 + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_NICINTEL_SPI].name); + print_supported_pcidevs(nics_intel_spi); +#endif } #if CONFIG_INTERNAL == 1 -- http://www.hailfinger.org/

4 8

Re: [flashrom] [PATCH 6/8] use getpagesize() to determine physmap's length in nicintel_spi.c
by Carl-Daniel Hailfinger 26 Aug '12

26 Aug '12

Am 15.03.2011 16:29 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner<stefan.tauner(a)student.tuwien.ac.at> > Right, this is a really good idea. Could you patch physmap instead to round down the requested address and round up the end of the range? Then we could just request the amount we need without having to care in each programmer driver about page size. I think somewhere in flashrom we even have rounding code for physmap, it just needs to be moved from a driver to the generic physmap. Your code looks solid. > --- > nicintel_spi.c | 7 +++++-- > 1 files changed, 5 insertions(+), 2 deletions(-) > > diff --git a/nicintel_spi.c b/nicintel_spi.c > index 5a6e04d..811ed6e 100644 > --- a/nicintel_spi.c > +++ b/nicintel_spi.c > @@ -26,11 +26,14 @@ > */ > > #include<stdlib.h> > +#include<unistd.h> > #include "flash.h" > #include "programmer.h" > > #define PCI_VENDOR_ID_INTEL 0x8086 > > +#define MEMMAP_SIZE getpagesize() > + > #define EECD 0x10 > #define FLA 0x1c > > @@ -148,7 +151,7 @@ int nicintel_spi_init(void) > io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_intel_spi); > > nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", > - io_base_addr, 4096); > + io_base_addr, MEMMAP_SIZE); > tmp = pci_mmio_readl(nicintel_spibar + EECD); > tmp&= ~FLASH_WRITES_DISABLED; > tmp |= FLASH_WRITES_ENABLED; > @@ -173,7 +176,7 @@ int nicintel_spi_shutdown(void) > tmp |= FLASH_WRITES_DISABLED; > pci_mmio_writel(tmp, nicintel_spibar + EECD); > > - physunmap(nicintel_spibar, 4096); > + physunmap(nicintel_spibar, MEMMAP_SIZE); > pci_cleanup(pacc); > release_io_perms(); > > Regards, Carl-Daniel -- http://www.hailfinger.org/

2 8

[PATCH 1/1] Simplify hwaccess.c
by Peter Lemenkov 26 Aug '12

26 Aug '12

This file is saturated with superfluous ifdefs arranged into several nested levels. This in turn adds additional complexity to process of adding another architecture. I re-arranged all ifdef blocks and killed duplicated function definitions. Also I added define(__amd64) to the list of x86-arches. Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- hwaccess.c | 85 +++++++++++++++++++++-------------------------------------- 1 files changed, 30 insertions(+), 55 deletions(-) diff --git a/hwaccess.c b/hwaccess.c index 3a61e60..4e87642 100644 --- a/hwaccess.c +++ b/hwaccess.c @@ -29,30 +29,47 @@ #endif #include "flash.h" +#if !( defined(__i386__) || \ + defined(__x86_64__) || defined(__amd64) || \ + defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) || \ + defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)) +#error Unknown architecture +#endif + #if defined(__i386__) || defined(__x86_64__) +#if defined(__FreeBSD__) || defined(__DragonFly__) +int io_fd; +#endif +#endif -/* sync primitive is not needed because x86 uses uncached accesses - * which have a strongly ordered memory model. - */ static inline void sync_primitive(void) { -} - -#if defined(__FreeBSD__) || defined(__DragonFly__) -int io_fd; +/* sync primitive is needed only on PowerPC because + * x86 uses uncached accesses which have a strongly ordered memory model + * /dev/mem on MIPS uses uncached accesses in mode 2 which has a strongly ordered memory model. + */ +#if defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + /* Prevent reordering and/or merging of reads/writes to hardware. + * Such reordering and/or merging would break device accesses which + * depend on the exact access order. + */ + asm("eieio" : : : "memory"); #endif +} void get_io_perms(void) { +/* PCI port I/O is not yet implemented on PowerPC or MIPS. */ +#if defined(__i386__) || defined(__x86_64__) || defined(__amd64) #if defined(__DJGPP__) /* We have full permissions by default. */ return; #else -#if defined (__sun) && (defined(__i386) || defined(__amd64)) +#if defined (__sun) if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { #elif defined(__FreeBSD__) || defined (__DragonFly__) if ((io_fd = open("/dev/io", O_RDWR)) < 0) { -#else +#else if (iopl(3) != 0) { #endif msg_perr("ERROR: Could not get I/O privileges (%s).\n" @@ -65,60 +82,18 @@ void get_io_perms(void) exit(1); } #endif +#endif } void release_io_perms(void) { +/* PCI port I/O is not yet implemented on PowerPC or MIPS. */ +#if defined(__i386__) || defined(__x86_64__) || defined(__amd64) #if defined(__FreeBSD__) || defined(__DragonFly__) close(io_fd); #endif -} - -#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) - -static inline void sync_primitive(void) -{ - /* Prevent reordering and/or merging of reads/writes to hardware. - * Such reordering and/or merging would break device accesses which - * depend on the exact access order. - */ - asm("eieio" : : : "memory"); -} - -/* PCI port I/O is not yet implemented on PowerPC. */ -void get_io_perms(void) -{ -} - -/* PCI port I/O is not yet implemented on PowerPC. */ -void release_io_perms(void) -{ -} - -#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) - -/* sync primitive is not needed because /dev/mem on MIPS uses uncached accesses - * in mode 2 which has a strongly ordered memory model. - */ -static inline void sync_primitive(void) -{ -} - -/* PCI port I/O is not yet implemented on MIPS. */ -void get_io_perms(void) -{ -} - -/* PCI port I/O is not yet implemented on MIPS. */ -void release_io_perms(void) -{ -} - -#else - -#error Unknown architecture - #endif +} void mmio_writeb(uint8_t val, void *addr) { -- 1.7.2.3

2 1

Re: [flashrom] [PATCH 5/7] warn if SMM BIOS Write Protection is detected in BIOS_CNTL
by Stefan Reinauer 25 Aug '12

25 Aug '12

On 5/23/11 4:23 PM, Stefan Tauner wrote: > Signed-off-by: Stefan Tauner<stefan.tauner(a)student.tuwien.ac.at> > --- > chipset_enable.c | 12 +++++++++++- > 1 files changed, 11 insertions(+), 1 deletions(-) > > diff --git a/chipset_enable.c b/chipset_enable.c > index 83b49ad..339c6bb 100644 > --- a/chipset_enable.c > +++ b/chipset_enable.c > @@ -264,8 +264,18 @@ static int enable_flash_ich(struct pci_dev *dev, const char *name, > (old& (1<< 0)) ? "en" : "dis"); > msg_pdbg("BIOS_CNTL is 0x%x\n", old); > > - new = old | 1; > + /* > + * Quote from the 6 Series datasheet: > + * "5: SMM BIOS Write Protect Disable (SMM_BWP) > + * 1 = BIOS region SMM protection is enabled. > + * The BIOS Region is not writable unless all processors are in SMM." > + * In earlier chipsets this bit is reserved. */ > + if (old& (5<< 1)) { > + msg_pinfo("WARNING: BIOS region SMM protection is enabled!\n"); > + return -1; You might still be successful doing the write, in case the SMM handler does not enforce the protection, so maybe you should just print a warning but not return here? > + } > > + new = old | 1; > if (new == old) > return 0; >

2 5

rtl8169 support - Final
by Jon Shadow 25 Aug '12

25 Aug '12

Fixed a few things. Still need someone to test it. Signed-off-by: Sergey Lichack <shadowpilot34(a)gmail.com>

4 3

[PATCH] board enable for DFI AD77
by Tadas Slotkus 25 Aug '12

25 Aug '12

Hello, Thank you people on the IRC for helping with assembler :) Happy Easter!

3 5

[PATCH] Make satasii driver more robust
by David Borg 24 Aug '12

24 Aug '12

Sorry, forgot to CC.the list. Updated patch to apply cleanly against latest revision (1151) and changed the string as pointed out by Rudolf Marek. Regards, David >-----BEGIN PGP SIGNED MESSAGE----- >Hash: SHA1 > >Hi thanks for doing that. > >Carl-Daniel Hailfinger wrote: >> Make the satasii driver more robust. >> >> Untested. >> >> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2...(a)gmx.net> >> >> Index: flashrom-satasii_robust/satasii.c >> =================================================================== >> --- flashrom-satasii_robust/satasii.c (Revision 1005) >> +++ flashrom-satasii_robust/satasii.c (Arbeitskopie) >> @@ -44,6 +44,7 @@ >> { >> uint32_t addr; >> uint16_t reg_offset; >> + uint32_t tmp; >> >> get_io_perms(); >> >> @@ -59,12 +60,19 @@ >> reg_offset = 0x50; >> } >> >> - sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset; >> + sii_bar = physmap("SATA SiI registers", addr, 0x100) + reg_offset; >> >> /* Check if ROM cycle are OK. */ >> if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26)))) >> msg_pinfo("Warning: Flash seems unconnected.\n"); >> >> + msg_pdbg("Using BAR5 access method.\n"); >> + tmp = pci_read_long(pcidev_dev, 0x40) & (1 << 1); >> + msg_pdbg("BAR5 Indirect Access is %snabled\n", tmp ? "en" : "dis"); >> + /* This bit has contradicting definitions in the 3512 datasheet. */ > >this looks strange you get dissnabled or ensabled ;) > >> + tmp = pci_read_long(pcidev_dev, 0x88) & (1 << 16); >> + msg_pdbg("BAR5 Access is %snabled\n", tmp ? "en" : "dis"); > >This Reg is EN_66 in other controllers so I guess it just this and not the >BA5_EN. It looks like it is driven by strap resistor only anyway. > >Interesting would be to test if BA5_EN is not enabled if you can access it >through indirect access through C0/C4 regs. > >Thanks, >Rudolf > > >> + >> buses_supported = CHIP_BUSTYPE_PARALLEL; >> >> return 0; >> @@ -81,6 +89,7 @@ >> void satasii_chip_writeb(uint8_t val, chipaddr addr) >> { >> uint32_t ctrl_reg, data_reg; >> + int i = 0; >> >> while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; >> >> @@ -92,12 +101,19 @@ >> mmio_writel(data_reg, (sii_bar + 4)); >> mmio_writel(ctrl_reg, sii_bar); >> >> - while (mmio_readl(sii_bar) & (1 << 25)) ; >> + while (mmio_readl(sii_bar) & (1 << 25)) { >> + if (++i > 10000) { >> + msg_perr("%s: control reg stuck at %08x, aborting\n", >> + __func__, mmio_readl(sii_bar)); >> + break; >> + } >> + } >> } >> >> uint8_t satasii_chip_readb(const chipaddr addr) >> { >> uint32_t ctrl_reg; >> + int i = 0; >> >> while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; >> >> @@ -107,7 +123,13 @@ >> >> mmio_writel(ctrl_reg, sii_bar); >> >> - while (mmio_readl(sii_bar) & (1 << 25)) ; >> + while (mmio_readl(sii_bar) & (1 << 25)) { >> + if (++i > 10000) { >> + msg_perr("%s: control reg stuck at %08x, aborting\n", >> + __func__, mmio_readl(sii_bar)); >> + break; >> + } >> + } >> >> return (mmio_readl(sii_bar + 4)) & 0xff; >> } >> >> >-----BEGIN PGP SIGNATURE----- >Version: GnuPG v1.4.10 (GNU/Linux) >Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org > >iEYEARECAAYFAkv4VwUACgkQ3J9wPJqZRNU4BQCfYmc1fp2kmy5SjQHjirrsKP82 >enkAoKQLbvmaCGs6/qNfawamobV7RayX >=7NEj >-----END PGP SIGNATURE----- > -- David Borg

2 1

New flash chips, AT49F010 and CAT28F512
by Andrew Morgan 13 Aug '12

13 Aug '12

AT49F010 patch is basically a copy of the existing AT49F020 code, but with half the size and the correct ID. The log was from a write of random data, after the chip already contained different random data. I did separate read, erase, write tests before but this log seems to show that PREW all work. CAT28F512 I have successfully probed and read data from, but erase fails. Could be because it needs 12v VPP. The CAT28F512 I have is soldered on to a NIC. I haven't investigated if VPP is connected at all yet. Thought I'd include the patch as-is anyway. Both patches: Signed-off-by: Andrew Morgan <ziltro(a)ziltro.com> -- Andrew.

3 10

[patch] board enable for ASUS P4P800-X (with erasing/writing SST SST49LF003A/B)
by Idwer Vollering 13 Aug '12

13 Aug '12

Enable writing/erasing on the ASUS P4P800-X, tested by mindcat on IRC. This board enable is inspired by the board enable for the ASUS P4P800-VM. As a bonus, testin the erasing/writing functionality on the SST SST49LF003A/B chip is now known to work. Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- Before (r1205/v0.9.3): Write report: http://paste.flashrom.org/view.php?id=465 Write report: http://paste.flashrom.org/view.php?id=466 After (r1285): Erase report: http://paste.flashrom.org/view.php?id=467

3 7

[PATCH] Bus Pirate buffer management revamp
by Carl-Daniel Hailfinger 08 Jun '12

08 Jun '12

Use separate functions for managing the Bus Pirate command/data buffer. Open-coding the buffer management was the first step, now the goal is to make it readable. This is the buffer management part of "Re: [flashrom] [PATCH] Make Bus Pirate init more robust, speed up flashing" The buffer management of the Bus Pirate driver has been revamped to use grow-only buffers with a reasonable initial default size so realloc() will not have to be called in normal operation. A side effect is the ability to switch to a static buffer without major hassle. Handle OOM gracefully. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-buspirate_buffermanagement/flash.h =================================================================== --- flashrom-buspirate_buffermanagement/flash.h (Revision 1184) +++ flashrom-buspirate_buffermanagement/flash.h (Arbeitskopie) @@ -35,6 +35,9 @@ #define ERROR_PTR ((void*)-1) +/* Error codes */ +#define OOM_ERROR -100 + typedef unsigned long chipaddr; int register_shutdown(void (*function) (void *data), void *data); Index: flashrom-buspirate_buffermanagement/buspirate_spi.c =================================================================== --- flashrom-buspirate_buffermanagement/buspirate_spi.c (Revision 1184) +++ flashrom-buspirate_buffermanagement/buspirate_spi.c (Arbeitskopie) @@ -46,6 +46,55 @@ #define sp_flush_incoming(...) 0 #endif +static unsigned char *bp_commbuf = NULL; +static int bp_commbufsize = 0; + +static int buspirate_commbuf_resize(int bufsize) +{ + unsigned char *tmpbuf; + + /* Never shrink. realloc() calls are expensive. */ + if (bufsize <= bp_commbufsize) + return 0; + + tmpbuf = realloc(bp_commbuf, bufsize); + if (!tmpbuf) { + /* This is debatable. Do we really want to free the existing + * buffer or do we want to keep it around, especially if memory + * is already tight? + */ + free(bp_commbuf); + bp_commbuf = NULL; + bp_commbufsize = 0; + msg_perr("Out of memory!\n"); + return OOM_ERROR; + } + + bp_commbuf = tmpbuf; + bp_commbufsize = bufsize; + return 0; +} + +static int buspirate_commbuf_init(int bufsize) +{ + bp_commbuf = malloc(bufsize); + if (!bp_commbuf) { + bp_commbufsize = 0; + msg_perr("Out of memory!\n"); + return OOM_ERROR; + } + + bp_commbufsize = bufsize; + return 0; +} + +static void buspirate_commbuf_shutdown(void) +{ + free(bp_commbuf); + bp_commbuf = NULL; + bp_commbufsize = 0; +} + static int buspirate_sendrecv(unsigned char *buf, unsigned int writecnt, unsigned int readcnt) { int i, ret = 0; @@ -231,6 +280,10 @@ return 1; } + /* Sensible default buffer size. */ + if (buspirate_commbuf_init(16 + 3)) + return OOM_ERROR; + buses_supported = CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_BUSPIRATE; @@ -267,6 +320,9 @@ ret = serialport_shutdown(); if (ret) return ret; + + buspirate_commbuf_shutdown(); + msg_pdbg("Bus Pirate shutdown completed.\n"); return 0; @@ -275,55 +331,51 @@ int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - static unsigned char *buf = NULL; int i = 0, ret = 0; if (writecnt > 16 || readcnt > 16 || (readcnt + writecnt) > 16) return SPI_INVALID_LENGTH; /* 3 bytes extra for CS#, len, CS#. */ - buf = realloc(buf, writecnt + readcnt + 3); - if (!buf) { - msg_perr("Out of memory!\n"); - exit(1); // -1 - } + if (buspirate_commbuf_resize(writecnt + readcnt + 3)) + return OOM_ERROR; /* Assert CS# */ - buf[i++] = 0x02; + bp_commbuf[i++] = 0x02; - buf[i++] = 0x10 | (writecnt + readcnt - 1); - memcpy(buf + i, writearr, writecnt); + bp_commbuf[i++] = 0x10 | (writecnt + readcnt - 1); + memcpy(bp_commbuf + i, writearr, writecnt); i += writecnt; - memset(buf + i, 0, readcnt); + memset(bp_commbuf + i, 0, readcnt); i += readcnt; /* De-assert CS# */ - buf[i++] = 0x03; + bp_commbuf[i++] = 0x03; - ret = buspirate_sendrecv(buf, i, i); + ret = buspirate_sendrecv(bp_commbuf, i, i); if (ret) { msg_perr("Bus Pirate communication error!\n"); return SPI_GENERIC_ERROR; } - if (buf[0] != 0x01) { + if (bp_commbuf[0] != 0x01) { msg_perr("Protocol error while lowering CS#!\n"); return SPI_GENERIC_ERROR; } - if (buf[1] != 0x01) { + if (bp_commbuf[1] != 0x01) { msg_perr("Protocol error while reading/writing SPI!\n"); return SPI_GENERIC_ERROR; } - if (buf[i - 1] != 0x01) { + if (bp_commbuf[i - 1] != 0x01) { msg_perr("Protocol error while raising CS#!\n"); return SPI_GENERIC_ERROR; } /* Skip CS#, length, writearr. */ - memcpy(readarr, buf + 2 + writecnt, readcnt); + memcpy(readarr, bp_commbuf + 2 + writecnt, readcnt); return ret; } -- http://www.hailfinger.org/

2 5

Re: [flashrom] [PATCH] Remove sharplhf00l04.c
by Carl-Daniel Hailfinger 15 May '12

15 May '12

Am 20.06.2011 01:13 schrieb Michael Karcher: > The currently unreferenced function in sharplhf00l04.c does a standard > FWH block protection reset (writes 0 to the protection register) and a > standard FWH block erase. > > The locking blocks of the FWH block lock cover 128KB areas, and thats > the only thing page_size is used for in the functions referenced in the > LHF00L04 entry. > My datasheet talks about 8 kB sectors and 64 kB blocks in "Figure 3. Memory Map", but "Table 8. FWH Flash Registers Configuration Map" only mentions registers for the 8 kB sectors in the top 64 kB block explicitly. "Table 8" also mentions "XX002H Whole Block Lock Register" as generic placeholder, and AFAICS those two X mean you have one block lock register for each of the 15 bottom 64 kB blocks and one for each of the 8 top 8 kB sectors. That also means the 82802ab unlocking as is can't be used. I was unable to find any 128 kB reference in my datasheet, so I'm going to Nack that part. > Finally, this adds a comment that there are non-volatile (flash memory) > lock bits for 8 sectors in the last 64KB. They are write-only and clearable > at once. Readback seems unsupported. > I have a slightly different interpretation of the datasheet (see above), so I'm not sure how to proceed. > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > Killing sharplhf00l04.c is a good thing, though, so that part is Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

3 3

[PATCH] Add logfile support to flashrom
by Carl-Daniel Hailfinger 08 May '12

08 May '12

Add log file support to flashrom. The log file will always contain all verbose messages even if the user doesn't specify -V. If the user specifies -VV, SPEW messages will be logged as well. Proof of concept, comments welcome. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-logfile/flash.h =================================================================== --- flashrom-logfile/flash.h (Revision 1326) +++ flashrom-logfile/flash.h (Arbeitskopie) @@ -229,6 +229,8 @@ #define ERROR_NONFATAL 0x100 /* cli_output.c */ +int open_logfile(char *filename); +int msg_log(const char *fmt, ...); /* Let gcc and clang check for correct printf-style format strings. */ int print(int type, const char *fmt, ...) __attribute__((format(printf, 2, 3))); #define MSG_ERROR 0 Index: flashrom-logfile/cli_output.c =================================================================== --- flashrom-logfile/cli_output.c (Revision 1326) +++ flashrom-logfile/cli_output.c (Arbeitskopie) @@ -2,6 +2,7 @@ * This file is part of the flashrom project. * * Copyright (C) 2009 Sean Nelson <audiohacked(a)gmail.com> + * Copyright (C) 2011 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,30 +23,70 @@ #include <stdarg.h> #include "flash.h" -int print(int type, const char *fmt, ...) +static FILE *logfile = NULL; + +int open_logfile(char *filename) { + if (!filename) { + msg_gerr("No filename specified.\n"); + return 1; + } + if ((logfile = fopen(filename, "w")) == NULL) { + perror(filename); + return 1; + } + return 0; +} + +int msg_log(const char *fmt, ...) +{ va_list ap; int ret; - FILE *output_type; + if (!logfile) + return -1; + va_start(ap, fmt); + ret = vfprintf(logfile, fmt, ap); + va_end(ap); + return ret; +} + +int print(int type, const char *fmt, ...) +{ + va_list ap; + int ret = 0; + int want_screen = 1; + int want_file = 1; + FILE *output_type = stdout; + switch (type) { case MSG_ERROR: output_type = stderr; break; case MSG_BARF: - if (verbose < 2) - return 0; + if (verbose < 2) { + want_screen = 0; + want_file = 0; + } + break; case MSG_DEBUG: if (verbose < 1) - return 0; + want_screen = 0; + break; case MSG_INFO: default: - output_type = stdout; break; } - va_start(ap, fmt); - ret = vfprintf(output_type, fmt, ap); - va_end(ap); + if (want_screen) { + va_start(ap, fmt); + ret = vfprintf(output_type, fmt, ap); + va_end(ap); + } + if (want_file && logfile) { + va_start(ap, fmt); + ret = vfprintf(logfile, fmt, ap); + va_end(ap); + } return ret; } Index: flashrom-logfile/cli_classic.c =================================================================== --- flashrom-logfile/cli_classic.c (Revision 1326) +++ flashrom-logfile/cli_classic.c (Arbeitskopie) @@ -38,7 +38,8 @@ "-z|" #endif "-E|-r <file>|-w <file>|-v <file>]\n" - " [-c <chipname>] [-m [<vendor>:]<part>] [-l <file>]\n" + " [-c <chipname>] [-m [<vendor>:]<part>] [-l <file>] " + "[-o <file>]\n" " [-i <image>] [-p <programmername>[:<parameters>]]\n\n"); printf("Please note that the command line interface for flashrom has " @@ -72,6 +73,7 @@ "<file>\n" " -i | --image <name> only flash image <name> " "from flash layout\n" + " -o | --output <name> log to file <name>\n" " -L | --list-supported print supported devices\n" #if CONFIG_PRINT_WIKI == 1 " -z | --list-supported-wiki print supported devices " @@ -118,7 +120,7 @@ int operation_specified = 0; int i; - static const char optstring[] = "r:Rw:v:nVEfc:m:l:i:p:Lzh"; + static const char optstring[] = "r:Rw:v:nVEfc:m:l:i:p:Lzho:"; static const struct option long_options[] = { {"read", 1, NULL, 'r'}, {"write", 1, NULL, 'w'}, @@ -136,6 +138,7 @@ {"programmer", 1, NULL, 'p'}, {"help", 0, NULL, 'h'}, {"version", 0, NULL, 'R'}, + {"output", 1, NULL, 'o'}, {NULL, 0, NULL, 0} }; @@ -307,14 +310,17 @@ cli_classic_usage(argv[0]); exit(0); break; + case 'o': + tempstr = strdup(optarg); + if (open_logfile(tempstr)) + cli_classic_abort_usage(); + break; default: cli_classic_abort_usage(); break; } } - /* FIXME: Print the actions flashrom will take. */ - if (list_supported) { print_supported(); exit(0); @@ -355,6 +361,10 @@ flash = NULL; } + /* FIXME: Print the actions flashrom will take. */ + /* For the log. FIXME: Print this only to the log file. */ + print_version(); + /* FIXME: Delay calibration should happen in programmer code. */ myusec_calibrate_delay(); -- http://www.hailfinger.org/

5 13

[PATCH] Add Winbond SuperI/O detection
by Carl-Daniel Hailfinger 06 May '12

06 May '12

Add Winbond Super I/O detection and hook it up to the generic Super I/O detection framework. Incomplete and untested, but at least it shouldn't break anything. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-winbond_superio_detect/flash.h =================================================================== --- flashrom-winbond_superio_detect/flash.h (Revision 1064) +++ flashrom-winbond_superio_detect/flash.h (Arbeitskopie) @@ -350,6 +350,7 @@ /* board_enable.c */ void w836xx_ext_enter(uint16_t port); void w836xx_ext_leave(uint16_t port); +struct superio probe_superio_winbond(void); uint8_t sio_read(uint16_t port, uint8_t reg); void sio_write(uint16_t port, uint8_t reg, uint8_t data); void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); @@ -388,7 +389,8 @@ }; extern struct superio superio; #define SUPERIO_VENDOR_NONE 0x0 -#define SUPERIO_VENDOR_ITE 0x1 +#define SUPERIO_VENDOR_WINBOND 0x1 +#define SUPERIO_VENDOR_ITE 0x2 struct pci_dev *pci_dev_find_filter(struct pci_filter filter); struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class); struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); Index: flashrom-winbond_superio_detect/internal.c =================================================================== --- flashrom-winbond_superio_detect/internal.c (Revision 1064) +++ flashrom-winbond_superio_detect/internal.c (Arbeitskopie) @@ -104,12 +104,14 @@ void probe_superio(void) { - superio = probe_superio_ite(); + superio = probe_superio_winbond(); #if 0 - /* Winbond Super I/O code is not yet available. */ + /* ITE probe causes SMSC LPC47N217 to power off the serial UART. */ if (superio.vendor == SUPERIO_VENDOR_NONE) - superio = probe_superio_winbond(); + superio = probe_superio_smsc(); #endif + if (superio.vendor == SUPERIO_VENDOR_NONE) + superio = probe_superio_ite(); } #endif Index: flashrom-winbond_superio_detect/board_enable.c =================================================================== --- flashrom-winbond_superio_detect/board_enable.c (Revision 1064) +++ flashrom-winbond_superio_detect/board_enable.c (Arbeitskopie) @@ -229,22 +229,59 @@ address, but takes no effort to make sure the chip is really a Winbond Super I/O */ -static const struct winbond_chip * winbond_superio_detect(uint16_t base) +uint8_t probe_id_winbond(uint16_t port) { uint8_t chipid; + + w836xx_ext_enter(port); + chipid = sio_read(port, 0x20); + w836xx_ext_leave(port); + + return chipid; +} + +#define WINBOND_SUPERIO_PORT1 0x2e +#define WINBOND_SUPERIO_PORT2 0x4e + +struct superio probe_superio_winbond(void) +{ + struct superio ret = {}; + uint16_t winbond_ports[] = {WINBOND_SUPERIO_PORT1, WINBOND_SUPERIO_PORT2, 0}; + uint16_t *i = winbond_ports; + + ret.vendor = SUPERIO_VENDOR_WINBOND; + for (; *i; i++) { + ret.port = *i; + ret.model = probe_id_winbond(ret.port); + switch (ret.model) { + case WINBOND_W83627HF_ID: + case WINBOND_W83627EHF_ID: + case WINBOND_W83627THF_ID: + msg_pinfo("Found Winbond Super I/O, id %02hx\n", + ret.model); + return ret; + } + } + + /* No good ID found. */ + ret.vendor = SUPERIO_VENDOR_NONE; + ret.port = 0; + ret.model = 0; + return ret; +} + +static const struct winbond_chip *winbond_superio_chipdef(void) +{ const struct winbond_chip * chip = NULL; int i; - w836xx_ext_enter(base); - chipid = sio_read(base, 0x20); for (i = 0; i < ARRAY_SIZE(winbond_chips); i++) - if (winbond_chips[i].device_id == chipid) + if (winbond_chips[i].device_id == superio.model) { chip = &winbond_chips[i]; break; } - w836xx_ext_leave(base); return chip; } @@ -259,7 +296,7 @@ int port = pin / 10; int bit = pin % 10; - chip = winbond_superio_detect(base); + chip = winbond_superio_chipdef(); if (!chip) { msg_perr("\nERROR: No supported Winbond Super I/O found\n"); return -1; -- http://www.hailfinger.org/

2 7

[PATCH] W83697xx superio flash enable
by David Borg 05 May '12

05 May '12

Adds a function to enable the flash interface on w83697xx superio's. Still needs to be hooked up to the superio detection framework though. Signed-off-by: David Borg <borg.db(a)gmail.com>

2 1

ASUS OPLX-M results (no flash device found)
by Ville Skyttä 17 Feb '12

17 Feb '12

Hello, I tried out flashrom on a ASUS OPLX-M motherboard, and it didn't find a flash device. I found some info by googling (that I cannot verify) that the OPLX-M would be an OEM (or something) version of the ASUS MEL-M; I suppose this particular board originally came with a Fujitsu/Siemens PC. http://support.asus.com/download/download.aspx?modelname=MEL-M&SLanguage=en…

3 4

Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by Carl-Daniel Hailfinger 09 Feb '12

09 Feb '12

Hi Mike, On 23.02.2010 05:45, Spangler, Mike T wrote: > I can probe with a continuity tester, but would need to know specific > pin locations to try. Do you have any generic info on doing this? Yes (well, I'd have to write up something), but the solution mentioned by Michael is way easier, so I'll wait until Michael has diagnosed the GPIO settings from the flashrom run on factory BIOS. Regards, Carl-Daniel -- "I do consider assignment statements and pointer variables to be among computer science's most valuable treasures." -- Donald E. Knuth

2 1

[PATCH] dummy programmer: blacklist SPI commands
by Carl-Daniel Hailfinger 07 Feb '12

07 Feb '12

Add optional SPI command blacklisting to the flash chip emulator in the dummy programmer. Usage: flashrom -p dummy:spi_blacklist=hexstring If hexstring is 0302, flashrom will blacklist command 0x03 (READ) and command 0x02 (WRITE). The hexstring can have up to 521 bytes (256 commands) length, and must not start with 0x. TODO: Should 0x at the beginning of hexstring be tolerated? Very useful for testing corner cases if you don't own a locked down Intel chipset and want to simulate such a thing. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-emulate_spi_flashchip_command_blacklist/dummyflasher.c =================================================================== --- flashrom-emulate_spi_flashchip_command_blacklist/dummyflasher.c (Revision 1224) +++ flashrom-emulate_spi_flashchip_command_blacklist/dummyflasher.c (Arbeitskopie) @@ -19,6 +19,7 @@ #include <string.h> #include <stdlib.h> +#include <stdio.h> #include <ctype.h> #include "flash.h" #include "chipdrivers.h" @@ -56,6 +57,8 @@ static int emu_jedec_be_d8_size = 0; static int emu_jedec_ce_60_size = 0; static int emu_jedec_ce_c7_size = 0; +unsigned char spi_blacklist[256]; +int spi_blacklist_size = 0; #endif #endif @@ -71,6 +74,7 @@ { char *bustext = NULL; char *tmp = NULL; + int i; #if EMULATE_CHIP struct stat image_stat; #endif @@ -116,6 +120,31 @@ } } + tmp = extract_programmer_param("spi_blacklist"); + if (tmp) { + i = strlen(tmp); + if (i % 2) { + msg_perr("Invalid SPI command blacklist\n"); + free(tmp); + return 1; + } + tolower_string(tmp); + if (strspn(tmp, "0123456789abcdef") != i) { + msg_perr("Invalid SPI command blacklist\n"); + free(tmp); + return 1; + } + spi_blacklist_size = i / 2; + for (i = 0; i < spi_blacklist_size; i++) { + sscanf(tmp, "%2hhx", &spi_blacklist[i]); + } + msg_pdbg("SPI blacklist is "); + for (i = 0; i < spi_blacklist_size; i++) + msg_pdbg("%02x ", spi_blacklist[i]); + msg_pdbg(", size %i\n", spi_blacklist_size); + } + free(tmp); + #if EMULATE_CHIP tmp = extract_programmer_param("emulate"); if (!tmp) { @@ -285,7 +314,7 @@ static int emulate_spi_chip_response(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - int offs; + int offs, i; static int aai_offs; static int aai_active = 0; @@ -293,7 +322,16 @@ msg_perr("No command sent to the chip!\n"); return 1; } - /* TODO: Implement command blacklists here. */ + for (i = 0; i < spi_blacklist_size; i++) { + if (writearr[0] == spi_blacklist[i]) { + msg_perr("Refusing blacklisted SPI command 0x%02x\n", + spi_blacklist[i]); + /* FIXME: Do we want a separate return code for + * command unavailable? + */ + return 1; + } + } switch (writearr[0]) { case JEDEC_RES: if (emu_chip != EMULATE_ST_M25P10_RES) -- http://www.hailfinger.org/

3 7

AMD SB7xx/SB8xx w/IMC: enable specs
by Joshua Roys 03 Jan '12

03 Jan '12

Hello all, The specific board this is for is the Supermicro H8DGT. Attached is only the specification, which is not guaranteed to be correct. Use with care. Also, after using this, you may want to turn off and unplug the computer for a few minutes to restore the correct operational state. The AMD SB700/710/750 Register Reference Guide (#43009) was used as a reference. Thanks, Josh

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[PATCH] Implement unknown Dediprog commands
by Carl-Daniel Hailfinger 19 Dec '11

19 Dec '11

Secret knowledge is cool, but public knowledge is better. Implement all Dediprog commands found in USB traces, even if their purpose is not yet known. Annotate unknown commands with info about the call sequence they are embedded in and the firmware version of the log. Add a new shutdown command for firmware 5.x. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-dediprog_unknown_commands/dediprog.c =================================================================== --- flashrom-dediprog_unknown_commands/dediprog.c (Revision 1232) +++ flashrom-dediprog_unknown_commands/dediprog.c (Arbeitskopie) @@ -27,6 +27,7 @@ #define DEFAULT_TIMEOUT 3000 static usb_dev_handle *dediprog_handle; +static int dediprog_firmwareversion; #if 0 /* Might be useful for other pieces of code as well. */ @@ -228,6 +229,7 @@ fw[1], fw[2]); return 1; } + dediprog_firmwareversion = fw[0]; return 0; } @@ -253,6 +255,32 @@ return 0; } +#if 0 +/* Something. + * Present in eng_detect_blink.log with firmware 3.1.8 + * Always preceded by Command Receive Device String + */ +static int dediprog_command_b(void) +{ + int ret; + char buf[0x3]; + + memset(buf, 0, sizeof(buf)); + ret = usb_control_msg(dediprog_handle, 0xc3, 0x7, 0x0, 0xef00, buf, 0x3, DEFAULT_TIMEOUT); + if (ret < 0) { + msg_perr("Command B failed (%s)!\n", usb_strerror()); + return 1; + } + if ((ret != 0x3) || (buf[0] != 0xff) || (buf[1] != 0xff) || + (buf[2] != 0xff)) { + msg_perr("Unexpected response to Command B!\n"); + return 1; + } + + return 0; +} +#endif + /* Command C is only sent after dediprog_check_devicestring, but not after every * invocation of dediprog_check_devicestring. It is only sent after the first * dediprog_command_a(); dediprog_check_devicestring() sequence in each session. @@ -264,7 +292,7 @@ ret = usb_control_msg(dediprog_handle, 0x42, 0x4, 0x0, 0x0, NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { - msg_perr("Unexpected response to Command C!\n"); + msg_perr("Command C failed (%s)!\n", usb_strerror()); return 1; } return 0; @@ -274,6 +302,7 @@ /* Very strange. Seems to be a programmer keepalive or somesuch. * Wait unsuccessfully for timeout ms to read one byte. * Is usually called after setting voltage to 0. + * Present in all logs with Firmware 2.1.1 and 3.1.8 */ static int dediprog_command_f(int timeout) { @@ -282,14 +311,90 @@ memset(buf, 0, sizeof(buf)); ret = usb_control_msg(dediprog_handle, 0xc2, 0x11, 0xff, 0xff, buf, 0x1, timeout); + /* This check is most probably wrong. Command F always causes a timeout + * in the logs, so we should check for timeout instead of checking for + * success. + */ + if (ret != 0x1) { + msg_perr("Command F failed (%s)!\n", usb_strerror()); + return 1; + } + return 0; +} + +/* Start/stop blinking? + * Present in eng_detect_blink.log with firmware 3.1.8 + * Preceded by Command J + */ +static int dediprog_command_g(void) +{ + int ret; + + ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, 0x03, NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { - msg_perr("Unexpected response to Command F!\n"); + msg_perr("Command G failed (%s)!\n", usb_strerror()); return 1; } return 0; } + +/* Something. + * Present in all logs with firmware 5.1.5 + * Always preceded by Command Receive Device String + * Always followed by Command Set SPI Voltage nonzero + */ +static int dediprog_command_h(void) +{ + int ret; + + ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, 0x05, NULL, 0x0, DEFAULT_TIMEOUT); + if (ret != 0x0) { + msg_perr("Command H failed (%s)!\n", usb_strerror()); + return 1; + } + return 0; +} #endif +/* Shutdown for firmware 5.x? + * Present in all logs with firmware 5.1.5 + * Often preceded by a SPI operation (Command Read SPI Bulk or Receive SPI) + * Always followed by Command Set SPI Voltage 0x0000 + */ +static int dediprog_command_i(void) +{ + int ret; + + ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, 0x06, NULL, 0x0, DEFAULT_TIMEOUT); + if (ret != 0x0) { + msg_perr("Command I failed (%s)!\n", usb_strerror()); + return 1; + } + return 0; +} + +#if 0 +/* Start/stop blinking? + * Present in all logs with firmware 5.1.5 + * Always preceded by Command Receive Device String on 5.1.5 + * Always followed by Command Set SPI Voltage nonzero on 5.1.5 + * Present in eng_detect_blink.log with firmware 3.1.8 + * Preceded by Command B in eng_detect_blink.log + * Followed by Command G in eng_detect_blink.log + */ +static int dediprog_command_j(void) +{ + int ret; + + ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, 0x07, NULL, 0x0, DEFAULT_TIMEOUT); + if (ret != 0x0) { + msg_perr("Command J failed (%s)!\n", usb_strerror()); + return 1; + } + return 0; +} +#endif + static int parse_voltage(char *voltage) { char *tmp = NULL; @@ -445,9 +550,11 @@ /* URB 136 is just URB 9. */ /* URB 137 is just URB 11. */ - /* Command I is probably Start Bulk Read. Data is u16 blockcount, u16 blocksize. */ - /* Command J is probably Start Bulk Write. Data is u16 blockcount, u16 blocksize. */ - /* Bulk transfer sizes for Command I/J are always 512 bytes, rest is filled with 0xff. */ + /* Command Start Bulk Read. Data is u16 blockcount, u16 blocksize. */ + /* Command Start Bulk Write. Data is u16 blockcount, u16 blocksize. */ + /* Bulk transfer sizes for Command Start Bulk Read/Write are always + * 512 bytes, rest is filled with 0xff. + */ return 0; } @@ -457,6 +564,10 @@ { msg_pspew("%s\n", __func__); + /* Shutdown on firmware 5.x */ + if (dediprog_firmwareversion == 5) + if (dediprog_command_i()) + return 1; /* URB 28. Command Set SPI Voltage to 0. */ if (dediprog_set_spi_voltage(0x0)) return 1; -- http://www.hailfinger.org/

2 2

[PATCH] Register Parallel/LPC/FWH programmers
by Carl-Daniel Hailfinger 09 Nov '11

09 Nov '11

Register Parallel/LPC/FWH programmers the same way SPI programmers are registered. This patch is not yet 100% clean (80 column limit violations etc.), but the general idea should be clear. We need something like this patch to handle programmers with multiple flash chips (e.g. LPC/FWH chips mapped to different regions on mainboards). TODO: - Should register_par_programmer(...) be called before or after setting max_rom_decode.*? - Is there a better name for register_par_programmer? - Should max_rom_decode.* be part of the registration? - Should map_flash_region/unmap_flash_region be part of the registration? Please check that all programmers have a register_par_programmer call unless the chip_* functions were noop. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-register_par_programmer/drkaiser.c =================================================================== --- flashrom-register_par_programmer/drkaiser.c (Revision 1325) +++ flashrom-register_par_programmer/drkaiser.c (Arbeitskopie) @@ -37,6 +37,17 @@ static uint8_t *drkaiser_bar; +static const struct par_programmer par_programmer_drkaiser = { + .chip_readb = drkaiser_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = drkaiser_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + int drkaiser_init(void) { uint32_t addr; @@ -53,7 +64,8 @@ drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory", addr, 128 * 1024); - buses_supported = CHIP_BUSTYPE_PARALLEL; + register_par_programmer(&par_programmer_drkaiser, CHIP_BUSTYPE_PARALLEL); + max_rom_decode.parallel = 131072; return 0; } Index: flashrom-register_par_programmer/it87spi.c =================================================================== --- flashrom-register_par_programmer/it87spi.c (Revision 1325) +++ flashrom-register_par_programmer/it87spi.c (Arbeitskopie) @@ -193,7 +193,7 @@ free(portpos); exit_conf_mode_ite(port); it8716f_flashport = flashport; - if (buses_supported & CHIP_BUSTYPE_SPI) + if (internal_buses_supported & CHIP_BUSTYPE_SPI) msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); /* FIXME: Add the SPI bus or replace the other buses with it? */ register_spi_programmer(&spi_programmer_it87xx); Index: flashrom-register_par_programmer/gfxnvidia.c =================================================================== --- flashrom-register_par_programmer/gfxnvidia.c (Revision 1325) +++ flashrom-register_par_programmer/gfxnvidia.c (Arbeitskopie) @@ -60,6 +60,17 @@ {}, }; +static const struct par_programmer par_programmer_gfxnvidia = { + .chip_readb = gfxnvidia_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = gfxnvidia_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + int gfxnvidia_init(void) { uint32_t reg32; @@ -78,7 +89,7 @@ nvidia_bar = physmap("NVIDIA", io_base_addr, 16 * 1024 * 1024); - buses_supported = CHIP_BUSTYPE_PARALLEL; + register_par_programmer(&par_programmer_gfxnvidia, CHIP_BUSTYPE_PARALLEL); /* Write/erase doesn't work. */ programmer_may_write = 0; Index: flashrom-register_par_programmer/nicrealtek.c =================================================================== --- flashrom-register_par_programmer/nicrealtek.c (Revision 1325) +++ flashrom-register_par_programmer/nicrealtek.c (Arbeitskopie) @@ -36,13 +36,24 @@ {}, }; +static const struct par_programmer par_programmer_nicrealtek = { + .chip_readb = nicrealtek_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicrealtek_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + int nicrealtek_init(void) { get_io_perms(); io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek); - buses_supported = CHIP_BUSTYPE_PARALLEL; + register_par_programmer(&par_programmer_nicrealtek, CHIP_BUSTYPE_PARALLEL); return 0; } Index: flashrom-register_par_programmer/serprog.c =================================================================== --- flashrom-register_par_programmer/serprog.c (Revision 1325) +++ flashrom-register_par_programmer/serprog.c (Arbeitskopie) @@ -295,6 +295,19 @@ return 0; } +static const struct par_programmer par_programmer_serprog = { + .chip_readb = serprog_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = serprog_chip_readn, + .chip_writeb = serprog_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + +enum chipbustype serprog_buses_supported = CHIP_BUSTYPE_NONE; + int serprog_init(void) { uint16_t iface; @@ -454,7 +467,7 @@ msg_perr("Warning: NAK to query supported buses\n"); c = CHIP_BUSTYPE_NONSPI; /* A reasonable default for now. */ } - buses_supported = c; + serprog_buses_supported = c; if (sp_docommand(S_CMD_O_INIT, 0, NULL, 0, NULL)) { msg_perr("Error: NAK to initialize operation buffer\n"); @@ -490,6 +503,8 @@ sp_max_read_n = 0; } + register_par_programmer(&par_programmer_serprog, serprog_buses_supported); + sp_prev_was_write = 0; sp_streamed_transmit_ops = 0; sp_streamed_transmit_bytes = 0; Index: flashrom-register_par_programmer/satamv.c =================================================================== --- flashrom-register_par_programmer/satamv.c (Revision 1325) +++ flashrom-register_par_programmer/satamv.c (Arbeitskopie) @@ -40,6 +40,17 @@ #define PCI_BAR2_CONTROL 0x00c08 #define GPIO_PORT_CONTROL 0x104f0 +static const struct par_programmer par_programmer_satamv = { + .chip_readb = satamv_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = satamv_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + /* * Random notes: * FCE# Flash Chip Enable @@ -125,7 +136,7 @@ mv_iobar = tmp & 0xffff; msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar); - buses_supported = CHIP_BUSTYPE_PARALLEL; + register_par_programmer(&par_programmer_satamv, CHIP_BUSTYPE_PARALLEL); /* 512 kByte with two 8-bit latches, and * 4 MByte with additional 3-bit latch. */ Index: flashrom-register_par_programmer/dummyflasher.c =================================================================== --- flashrom-register_par_programmer/dummyflasher.c (Revision 1325) +++ flashrom-register_par_programmer/dummyflasher.c (Arbeitskopie) @@ -73,6 +73,20 @@ .read = default_spi_read, .write_256 = dummy_spi_write_256, }; + +static const struct par_programmer par_programmer_dummy = { + .chip_readb = dummy_chip_readb, + .chip_readw = dummy_chip_readw, + .chip_readl = dummy_chip_readl, + .chip_readn = dummy_chip_readn, + .chip_writeb = dummy_chip_writeb, + .chip_writew = dummy_chip_writew, + .chip_writel = dummy_chip_writel, + .chip_writen = dummy_chip_writen, +}; + +enum chipbustype dummy_buses_supported = CHIP_BUSTYPE_NONE; + int dummy_init(void) { char *bustext = NULL; @@ -90,24 +104,31 @@ /* Convert the parameters to lowercase. */ tolower_string(bustext); - buses_supported = CHIP_BUSTYPE_NONE; + dummy_buses_supported = CHIP_BUSTYPE_NONE; if (strstr(bustext, "parallel")) { - buses_supported |= CHIP_BUSTYPE_PARALLEL; + dummy_buses_supported |= CHIP_BUSTYPE_PARALLEL; msg_pdbg("Enabling support for %s flash.\n", "parallel"); } if (strstr(bustext, "lpc")) { - buses_supported |= CHIP_BUSTYPE_LPC; + dummy_buses_supported |= CHIP_BUSTYPE_LPC; msg_pdbg("Enabling support for %s flash.\n", "LPC"); } if (strstr(bustext, "fwh")) { - buses_supported |= CHIP_BUSTYPE_FWH; + dummy_buses_supported |= CHIP_BUSTYPE_FWH; msg_pdbg("Enabling support for %s flash.\n", "FWH"); } + if (dummy_buses_supported & (CHIP_BUSTYPE_PARALLEL | CHIP_BUSTYPE_LPC | + CHIP_BUSTYPE_FWH)) + register_par_programmer(&par_programmer_dummy, + dummy_buses_supported & + (CHIP_BUSTYPE_PARALLEL | + CHIP_BUSTYPE_LPC | + CHIP_BUSTYPE_FWH)); if (strstr(bustext, "spi")) { register_spi_programmer(&spi_programmer_dummyflasher); msg_pdbg("Enabling support for %s flash.\n", "SPI"); } - if (buses_supported == CHIP_BUSTYPE_NONE) + if (dummy_buses_supported == CHIP_BUSTYPE_NONE) msg_pdbg("Support for all flash bus types disabled.\n"); free(bustext); Index: flashrom-register_par_programmer/internal.c =================================================================== --- flashrom-register_par_programmer/internal.c (Revision 1325) +++ flashrom-register_par_programmer/internal.c (Arbeitskopie) @@ -127,6 +127,19 @@ int is_laptop = 0; int laptop_ok = 0; +static const struct par_programmer par_programmer_internal = { + .chip_readb = internal_chip_readb, + .chip_readw = internal_chip_readw, + .chip_readl = internal_chip_readl, + .chip_readn = internal_chip_readn, + .chip_writeb = internal_chip_writeb, + .chip_writew = internal_chip_writew, + .chip_writel = internal_chip_writel, + .chip_writen = fallback_chip_writen, +}; + +enum chipbustype internal_buses_supported = CHIP_BUSTYPE_NONE; + int internal_init(void) { #if __FLASHROM_LITTLE_ENDIAN__ @@ -180,9 +193,10 @@ get_io_perms(); /* Default to Parallel/LPC/FWH flash devices. If a known host controller - * is found, the init routine sets the buses_supported bitfield. + * is found, the host controller init routine sets the + * internal_buses_supported bitfield. */ - buses_supported = CHIP_BUSTYPE_NONSPI; + internal_buses_supported = CHIP_BUSTYPE_NONSPI; /* Initialize PCI access for flash enables */ pacc = pci_alloc(); /* Get the pci_access structure */ @@ -267,6 +281,11 @@ * Besides that, we don't check the board enable return code either. */ #if defined(__i386__) || defined(__x86_64__) || defined (__mips) + register_par_programmer(&par_programmer_internal, internal_buses_supported); + /* FIXME: Move this message out of chipset_enable.c. */ + msg_pinfo("This chipset supports the following protocols: %s.\n", + flashbuses_to_text(buses_supported)); + return 0; #else msg_perr("Your platform is not supported yet for the internal " Index: flashrom-register_par_programmer/nicnatsemi.c =================================================================== --- flashrom-register_par_programmer/nicnatsemi.c (Revision 1325) +++ flashrom-register_par_programmer/nicnatsemi.c (Arbeitskopie) @@ -35,13 +35,24 @@ {}, }; +static const struct par_programmer par_programmer_nicnatsemi = { + .chip_readb = nicnatsemi_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicnatsemi_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + int nicnatsemi_init(void) { get_io_perms(); io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_natsemi); - buses_supported = CHIP_BUSTYPE_PARALLEL; + register_par_programmer(&par_programmer_nicnatsemi, CHIP_BUSTYPE_PARALLEL); /* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15 * in another. My NIC has MA16 connected to A16 on the boot ROM socket Index: flashrom-register_par_programmer/it85spi.c =================================================================== --- flashrom-register_par_programmer/it85spi.c (Revision 1325) +++ flashrom-register_par_programmer/it85spi.c (Arbeitskopie) @@ -254,7 +254,11 @@ INDIRECT_A3(shm_io_base, (base >> 24)); #endif #ifdef LPC_MEMORY - base = (chipaddr)programmer_map_flash_region("it85 communication", + /* WTF?!? FIXME: This should use physmap instead. And it should + * automatically block accessing that region for anything else. + * Major TODO here, and it will be a lot of work. + */ + base = (chipaddr)physmap("it85 communication", 0xFFFFF000, 0x1000); msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, (unsigned int)base); @@ -282,16 +286,17 @@ { int ret; - if (!(buses_supported & CHIP_BUSTYPE_FWH)) { + if (!(internal_buses_supported & CHIP_BUSTYPE_FWH)) { msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__); return 1; } ret = it85xx_spi_common_init(s); msg_pdbg("FWH: %s():%d ret=%d\n", __func__, __LINE__, ret); if (!ret) { - msg_pdbg("%s():%d buses_supported=0x%x\n", __func__, __LINE__, - buses_supported); - if (buses_supported & CHIP_BUSTYPE_FWH) + msg_pdbg("%s():%d internal_buses_supported=0x%x\n", __func__, __LINE__, + internal_buses_supported); + /* FIXME: We check for FWH, but claim SPI override? WTF? */ + if (internal_buses_supported & CHIP_BUSTYPE_FWH) msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n"); /* Really leave FWH enabled? */ /* Set this as spi controller. */ Index: flashrom-register_par_programmer/atahpt.c =================================================================== --- flashrom-register_par_programmer/atahpt.c (Revision 1325) +++ flashrom-register_par_programmer/atahpt.c (Arbeitskopie) @@ -38,6 +38,17 @@ {}, }; +static const struct par_programmer par_programmer_atahpt = { + .chip_readb = atahpt_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = atahpt_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + int atahpt_init(void) { uint32_t reg32; @@ -51,7 +62,7 @@ reg32 |= (1 << 24); rpci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32); - buses_supported = CHIP_BUSTYPE_PARALLEL; + register_par_programmer(&par_programmer_atahpt, CHIP_BUSTYPE_PARALLEL); return 0; } Index: flashrom-register_par_programmer/nic3com.c =================================================================== --- flashrom-register_par_programmer/nic3com.c (Revision 1325) +++ flashrom-register_par_programmer/nic3com.c (Arbeitskopie) @@ -55,6 +55,17 @@ {}, }; +static const struct par_programmer par_programmer_nic3com = { + .chip_readb = nic3com_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nic3com_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + int nic3com_init(void) { get_io_perms(); @@ -81,8 +92,8 @@ */ OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS); - buses_supported = CHIP_BUSTYPE_PARALLEL; max_rom_decode.parallel = 128 * 1024; + register_par_programmer(&par_programmer_nic3com, CHIP_BUSTYPE_PARALLEL); return 0; } Index: flashrom-register_par_programmer/satasii.c =================================================================== --- flashrom-register_par_programmer/satasii.c (Revision 1325) +++ flashrom-register_par_programmer/satasii.c (Arbeitskopie) @@ -40,6 +40,17 @@ {}, }; +static const struct par_programmer par_programmer_satasii = { + .chip_readb = satasii_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = satasii_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + int satasii_init(void) { uint32_t addr; @@ -65,7 +76,7 @@ if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26)))) msg_pinfo("Warning: Flash seems unconnected.\n"); - buses_supported = CHIP_BUSTYPE_PARALLEL; + register_par_programmer(&par_programmer_satasii, CHIP_BUSTYPE_PARALLEL); return 0; } Index: flashrom-register_par_programmer/nicintel.c =================================================================== --- flashrom-register_par_programmer/nicintel.c (Revision 1325) +++ flashrom-register_par_programmer/nicintel.c (Arbeitskopie) @@ -41,6 +41,17 @@ #define CSR_FCR 0x0c +static const struct par_programmer par_programmer_nicintel = { + .chip_readb = nicintel_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = nicintel_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + int nicintel_init(void) { uintptr_t addr; @@ -78,9 +89,8 @@ */ pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR); - buses_supported = CHIP_BUSTYPE_PARALLEL; - max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE; + register_par_programmer(&par_programmer_nicintel, CHIP_BUSTYPE_PARALLEL); return 0; Index: flashrom-register_par_programmer/chipset_enable.c =================================================================== --- flashrom-register_par_programmer/chipset_enable.c (Revision 1325) +++ flashrom-register_par_programmer/chipset_enable.c (Arbeitskopie) @@ -208,7 +208,7 @@ uint16_t old, new; uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */ - buses_supported = CHIP_BUSTYPE_PARALLEL; + internal_buses_supported = CHIP_BUSTYPE_PARALLEL; old = pci_read_word(dev, xbcs); @@ -286,7 +286,7 @@ * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and * FB_DEC_EN2. */ - buses_supported = CHIP_BUSTYPE_FWH; + internal_buses_supported = CHIP_BUSTYPE_FWH; return enable_flash_ich(dev, name, 0x4e); } @@ -383,9 +383,9 @@ msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh); /* If we're called by enable_flash_ich_dc_spi, it will override - * buses_supported anyway. + * internal_buses_supported anyway. */ - buses_supported = CHIP_BUSTYPE_FWH; + internal_buses_supported = CHIP_BUSTYPE_FWH; return enable_flash_ich(dev, name, 0xdc); } @@ -405,7 +405,7 @@ if (new != old) rpci_write_byte(dev, 0xd9, new); - buses_supported = CHIP_BUSTYPE_FWH; + internal_buses_supported = CHIP_BUSTYPE_FWH; return 0; } @@ -458,7 +458,7 @@ * on ICH7 when the southbridge is strapped to LPC */ - buses_supported = CHIP_BUSTYPE_FWH; + internal_buses_supported = CHIP_BUSTYPE_FWH; if (ich_generation == 7) { if(bbs == ICH_STRAP_LPC) { /* No further SPI initialization required */ @@ -466,7 +466,7 @@ } else /* Disable LPC/FWH if strapped to PCI or SPI */ - buses_supported = 0; + internal_buses_supported = 0; } /* this adds CHIP_BUSTYPE_SPI */ @@ -557,7 +557,7 @@ #define CS5530_ENABLE_SA2320 (1 << 2) #define CS5530_ENABLE_SA20 (1 << 6) - buses_supported = CHIP_BUSTYPE_PARALLEL; + internal_buses_supported = CHIP_BUSTYPE_PARALLEL; /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB. * FIXME: Should we really touch the low mapping below 1 MB? Flashrom @@ -707,7 +707,7 @@ (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff)); } - buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; + internal_buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; ret = sb600_probe_spi(dev); @@ -793,7 +793,7 @@ { uint8_t tmp; - buses_supported = CHIP_BUSTYPE_PARALLEL; + internal_buses_supported = CHIP_BUSTYPE_PARALLEL; tmp = INB(0xc06); tmp |= 0x1; @@ -893,7 +893,7 @@ switch ((val >> 5) & 0x3) { case 0x0: ret = enable_flash_mcp55(dev, name); - buses_supported = CHIP_BUSTYPE_LPC; + internal_buses_supported = CHIP_BUSTYPE_LPC; msg_pdbg("Flash bus type is LPC\n"); break; case 0x2: @@ -901,14 +901,14 @@ /* SPI is added in mcp6x_spi_init if it works. * Do we really want to disable LPC in this case? */ - buses_supported = CHIP_BUSTYPE_NONE; + internal_buses_supported = CHIP_BUSTYPE_NONE; msg_pdbg("Flash bus type is SPI\n"); msg_perr("SPI on this chipset is WIP. Write is unsupported!\n"); programmer_may_write = 0; break; default: /* Should not happen. */ - buses_supported = CHIP_BUSTYPE_NONE; + internal_buses_supported = CHIP_BUSTYPE_NONE; msg_pdbg("Flash bus type is unknown (none)\n"); msg_pinfo("Something went wrong with bus type detection.\n"); goto out_msg; @@ -1215,8 +1215,5 @@ msg_pinfo("PROBLEMS, continuing anyway\n"); } - msg_pinfo("This chipset supports the following protocols: %s.\n", - flashbuses_to_text(buses_supported)); - return ret; } Index: flashrom-register_par_programmer/programmer.c =================================================================== --- flashrom-register_par_programmer/programmer.c (Revision 1325) +++ flashrom-register_par_programmer/programmer.c (Arbeitskopie) @@ -19,7 +19,21 @@ */ #include "flash.h" +#include "programmer.h" +static const struct par_programmer par_programmer_none = { + .chip_readb = noop_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = noop_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + +const struct par_programmer *par_programmer = &par_programmer_none; + /* No-op shutdown() for programmers which don't need special handling */ int noop_shutdown(void) { @@ -96,3 +110,9 @@ buf[i] = chip_readb(addr + i); return; } + +void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses) +{ + par_programmer = pgm; + buses_supported |= buses; +} Index: flashrom-register_par_programmer/flashrom.c =================================================================== --- flashrom-register_par_programmer/flashrom.c (Revision 1325) +++ flashrom-register_par_programmer/flashrom.c (Arbeitskopie) @@ -132,14 +132,6 @@ .shutdown = internal_shutdown, .map_flash_region = physmap, .unmap_flash_region = physunmap, - .chip_readb = internal_chip_readb, - .chip_readw = internal_chip_readw, - .chip_readl = internal_chip_readl, - .chip_readn = internal_chip_readn, - .chip_writeb = internal_chip_writeb, - .chip_writew = internal_chip_writew, - .chip_writel = internal_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -151,14 +143,6 @@ .shutdown = dummy_shutdown, .map_flash_region = dummy_map, .unmap_flash_region = dummy_unmap, - .chip_readb = dummy_chip_readb, - .chip_readw = dummy_chip_readw, - .chip_readl = dummy_chip_readl, - .chip_readn = dummy_chip_readn, - .chip_writeb = dummy_chip_writeb, - .chip_writew = dummy_chip_writew, - .chip_writel = dummy_chip_writel, - .chip_writen = dummy_chip_writen, .delay = internal_delay, }, #endif @@ -170,14 +154,6 @@ .shutdown = nic3com_shutdown, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = nic3com_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nic3com_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -191,14 +167,6 @@ .shutdown = nicrealtek_shutdown, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = nicrealtek_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nicrealtek_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -210,14 +178,6 @@ .shutdown = nicnatsemi_shutdown, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = nicnatsemi_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nicnatsemi_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -229,14 +189,6 @@ .shutdown = gfxnvidia_shutdown, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = gfxnvidia_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = gfxnvidia_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -248,14 +200,6 @@ .shutdown = drkaiser_shutdown, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = drkaiser_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = drkaiser_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -267,14 +211,6 @@ .shutdown = satasii_shutdown, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = satasii_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = satasii_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -286,14 +222,6 @@ .shutdown = atahpt_shutdown, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = atahpt_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = atahpt_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -305,14 +233,6 @@ .shutdown = noop_shutdown, /* Missing shutdown */ .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -324,14 +244,6 @@ .shutdown = serprog_shutdown, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = serprog_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = serprog_chip_readn, - .chip_writeb = serprog_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = serprog_delay, }, #endif @@ -343,14 +255,6 @@ .shutdown = buspirate_spi_shutdown, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -362,14 +266,6 @@ .shutdown = dediprog_shutdown, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -381,14 +277,6 @@ .shutdown = noop_shutdown, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -400,14 +288,6 @@ .shutdown = nicintel_shutdown, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = nicintel_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nicintel_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -419,14 +299,6 @@ .shutdown = nicintel_spi_shutdown, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -438,14 +310,6 @@ .shutdown = ogp_spi_shutdown, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = noop_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = noop_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -457,14 +321,6 @@ .shutdown = satamv_shutdown, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, - .chip_readb = satamv_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = satamv_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, .delay = internal_delay, }, #endif @@ -566,42 +422,42 @@ void chip_writeb(uint8_t val, chipaddr addr) { - programmer_table[programmer].chip_writeb(val, addr); + par_programmer->chip_writeb(val, addr); } void chip_writew(uint16_t val, chipaddr addr) { - programmer_table[programmer].chip_writew(val, addr); + par_programmer->chip_writew(val, addr); } void chip_writel(uint32_t val, chipaddr addr) { - programmer_table[programmer].chip_writel(val, addr); + par_programmer->chip_writel(val, addr); } void chip_writen(uint8_t *buf, chipaddr addr, size_t len) { - programmer_table[programmer].chip_writen(buf, addr, len); + par_programmer->chip_writen(buf, addr, len); } uint8_t chip_readb(const chipaddr addr) { - return programmer_table[programmer].chip_readb(addr); + return par_programmer->chip_readb(addr); } uint16_t chip_readw(const chipaddr addr) { - return programmer_table[programmer].chip_readw(addr); + return par_programmer->chip_readw(addr); } uint32_t chip_readl(const chipaddr addr) { - return programmer_table[programmer].chip_readl(addr); + return par_programmer->chip_readl(addr); } void chip_readn(uint8_t *buf, chipaddr addr, size_t len) { - programmer_table[programmer].chip_readn(buf, addr, len); + par_programmer->chip_readn(buf, addr, len); } void programmer_delay(int usecs) Index: flashrom-register_par_programmer/programmer.h =================================================================== --- flashrom-register_par_programmer/programmer.h (Revision 1325) +++ flashrom-register_par_programmer/programmer.h (Arbeitskopie) @@ -95,14 +95,6 @@ size_t len); void (*unmap_flash_region) (void *virt_addr, size_t len); - void (*chip_writeb) (uint8_t val, chipaddr addr); - void (*chip_writew) (uint16_t val, chipaddr addr); - void (*chip_writel) (uint32_t val, chipaddr addr); - void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len); - uint8_t (*chip_readb) (const chipaddr addr); - uint16_t (*chip_readw) (const chipaddr addr); - uint32_t (*chip_readl) (const chipaddr addr); - void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len); void (*delay) (int usecs); }; @@ -302,6 +294,7 @@ extern int force_boardmismatch; void probe_superio(void); int register_superio(struct superio s); +extern enum chipbustype internal_buses_supported; int internal_init(void); int internal_shutdown(void); void internal_chip_writeb(uint8_t val, chipaddr addr); @@ -357,6 +350,18 @@ uint16_t fallback_chip_readw(const chipaddr addr); uint32_t fallback_chip_readl(const chipaddr addr); void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); +struct par_programmer { + void (*chip_writeb) (uint8_t val, chipaddr addr); + void (*chip_writew) (uint16_t val, chipaddr addr); + void (*chip_writel) (uint32_t val, chipaddr addr); + void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len); + uint8_t (*chip_readb) (const chipaddr addr); + uint16_t (*chip_readw) (const chipaddr addr); + uint32_t (*chip_readl) (const chipaddr addr); + void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len); +}; +extern const struct par_programmer *par_programmer; +void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses); /* dummyflasher.c */ #if CONFIG_DUMMY == 1 Index: flashrom-register_par_programmer/board_enable.c =================================================================== --- flashrom-register_par_programmer/board_enable.c (Revision 1325) +++ flashrom-register_par_programmer/board_enable.c (Arbeitskopie) @@ -424,7 +424,7 @@ /* Check if at least one flash segment is enabled. */ if (tmp & 0xf0) { /* The IT8705F will respond to LPC cycles and translate them. */ - buses_supported = CHIP_BUSTYPE_PARALLEL; + internal_buses_supported = CHIP_BUSTYPE_PARALLEL; /* Flash ROM I/F Writes Enable */ tmp |= 0x04; msg_pdbg("Enabling IT8705F flash ROM interface write.\n"); -- http://www.hailfinger.org/

3 6

[PATCH] Fintek SPI driver, based off it87spi
by Sean Nelson 22 Oct '11

22 Oct '11

I've been extremely busy with preparing for the US Air Force, which I leave for Basic on November 2nd. But... Fintek SPI Flashrom Driver: * based off of it87spi.c * untested * should be good for F71882 and F71889 Signed-off-by: Sean Nelson <audiohacked(a)gmail.com>

2 3

Success report flashrom v0.9.1-r946 on motherboard ASUS M4A89GTD PRO
by Christian Kropfreiter 20 Oct '11

20 Oct '11

2 2

Re: [flashrom] [PATCH 6/8] ichspi: add prettyprinting for PR registers
by Stefan Tauner 17 Sep '11

17 Sep '11

On Sat, 20 Aug 2011 12:39:46 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > + if (rwperms != 0x3) > + msg_pdbg(")\n0x%08x-0x%08x is %s\n", (ICH_FREG_BASE(pr) << 12), > + (ICH_FREG_LIMIT(pr) << 12) | 0x0fff, > + access_names[rwperms]); this is wrong. i have rebased these patches onto hwseq and forgot that the FREG macros have changed (no more shifting needed). depending on what gets acked when, i will fix this one way or another... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

Re: [flashrom] [PATCH] revamp the warning of failing to set BIOS write enable in enable_flash_ich
by Stefan Tauner 14 Sep '11

14 Sep '11

and if we are at it... shouldn't we tell the user, that writes will most probably fail in cases where we could not enable bios writes? e.g. the dell optiplex in the "It is hard to report a bug...."-thread: BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x2 tried to set 0xdc to 0x3 on ICH8/ICH8R failed (WARNING ONLY) as far as i understand this, an SMI is triggered and in this case the SMM prohibits us from setting the BIOS WE bit, but this may not be always the case. is there a way around it? i don't know enough about SMM to be sure if that's correct. in any case we won't be able to erase/write if the WE bit is not set and we should indicate this clearly to the user imho. what do you think? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

3 6

patch to add support for Xilinx parallel III/DLC5 programmer cable
by Jakab Peter 12 Sep '11

12 Sep '11

Hi list, I modified the rayer spi programmer source to be used with a Xilinx parallel III (also called DLC5) programmer cable. It's a trivial change of parallel port pins, but I did not know how the support for this cable should be included into the source code. Copying the same code to a separate file may not be a good idea. --- flashrom/rayer_spi.c 2010-09-18 19:48:27.000000000 +0200 +++ ../flashrom/rayer_spi.c 2010-09-18 02:12:59.000000000 +0200 @@ -37,11 +37,11 @@ * independent and are bitshift values, not real pin numbers. */ /* Pins for master->slave direction */ -#define SPI_CS_PIN 5 -#define SPI_SCK_PIN 6 -#define SPI_MOSI_PIN 7 +#define SPI_CS_PIN 2 +#define SPI_SCK_PIN 1 +#define SPI_MOSI_PIN 0 /* Pins for slave->master direction */ -#define SPI_MISO_PIN 6 +#define SPI_MISO_PIN 4 static int lpt_iobase; Thank you for working on this software, with access to the source code I was able to program my w25q64 flash chip. -- Peter JAKAB http://jap.hu/

3 3

SuperMicro X8STi
by Marek Zakrzewski 10 Sep '11

10 Sep '11

flashrom -Vw flashrom v0.9.3-r1205 on Linux 2.6.38.2-xxxx-std-ipv6-64 (x86_64), built with libpci 2.2.3, GCC 4.1.2 20080704 (Red Hat 4.1.2-48), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1528M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 999 us, 10000 myus = 10028 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. dmidecode execution unsucessfull - continuing without DMI info Found chipset "Intel ICH10R", enabling flash write... chipset PCI ID is 8086:3a16, 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x4 0x7fffffff/0x7fffffff FWH IDSEL: 0x5 0x7fffffff/0x7fffffff FWH IDSEL: 0x6 0x7fffffff/0x7fffffff FWH IDSEL: 0x7 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: enabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x3 Root Complex Register Block address = 0xfed1c000 GCS = 0x465: BIOS Interface Lock-Down: enabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x2008 (HSFS) FLOCKDN 0, FDV 0, FDOPSS 1, SCIP 0, BERASE 1, AEL 0, FCERR 0, FDONE 0 0x50: 0x00000202 (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x02, BRRA 0x02 0x54: 0x00001fff (FREG0: Flash Descriptor) Flash Descriptor region is unused. 0x58: 0x00001fff (FREG1: BIOS) BIOS region is unused. 0x5C: 0x00001fff (FREG2: Management Engine) Management Engine region is unused. 0x60: 0x00001fff (FREG3: Gigabit Ethernet) Gigabit Ethernet region is unused. 0x64: 0x00001fff (FREG4: Platform Data) Platform Data region is unused. 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0x007f1004 (SSFS, SSFC) 0x94: 0x5006 (PREOP) 0x96: 0x463b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0xc79f0190 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xB0: 0x00000000 (FDOC) Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH,SPI. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for AMIC A25L05PT, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L05PU, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L10PT, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L10PU, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L20PT, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L20PU, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L80P, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L16PT, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L16PU, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L080, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L016, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25L032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A25LQ032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25DQ161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for Bright BM29F040, 512 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for EMST F25L008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon EN29F010, 128 KB: skipped. Probing for Eon EN29F002(A)(N)B, 256 KB: skipped. Probing for Eon EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Hyundai HY29F040A, 512 KB: skipped. Probing for Intel 28F001BN/BX-B, 128 KB: skipped. Probing for Intel 28F001BN/BX-T, 128 KB: skipped. Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: skipped. Probing for Intel 28F008S3/S5/SC, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L1635E, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found chip "Macronix MX25L3205" (4096 KB, SPI) at physical address 0xffc00000. Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29F040, 512 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for MoselVitelic V29C51000B, 64 KB: skipped. Probing for MoselVitelic V29C51000T, 64 KB: skipped. Probing for MoselVitelic V29C51400B, 512 KB: skipped. Probing for MoselVitelic V29C51400T, 512 KB: skipped. Probing for MoselVitelic V29LC51000, 64 KB: skipped. Probing for MoselVitelic V29LC51001, 128 KB: skipped. Probing for MoselVitelic V29LC51002, 256 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xff, id2 0xd7, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25VF064C, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 0x15 Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST25LF040A.RES, 512 KB: program_opcodes: preop=5006 optype=462b opmenu=05ab0302c79f0190 on-the-fly OPCODE (0xAB) re-programmed, op-pos=2 probe_spi_res2: id1 0x15, id2 0x15 Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 0x15 Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xff, id2 0xd7, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25PX32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M25PX64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BB, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0xff, id2 0xd7, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25Q64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W29C020(C)/W29C022, 256 KB: skipped. Probing for Winbond W29C040/P, 512 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040(F)B, 512 KB: skipped. Probing for Winbond W39V040(F)C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U/N, 256 KB: skipped. Probing for Winbond W49F020, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xff, id2 0xd7, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Eon unknown Eon SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Macronix unknown Macronix SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Generic unknown SPI chip (RDID), 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 0xc2, id2 0x15 === This flash part has status UNTESTED for operations: ERASE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash before programming... Erasing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x000fff, program_opcodes: preop=5006 optype=463b opmenu=05200302c79f0190 on-the-fly OPCODE (0x20) re-programmed, op-pos=2 0x001000-0x001fff, 0x002000-0x002fff, 0x003000-0x003fff, 0x004000-0x004fff, 0x005000-0x005fff, 0x006000-0x006fff, 0x007000-0x007fff, 0x008000-0x008fff, 0x009000-0x009fff, 0x00a000-0x00afff, 0x00b000-0x00bfff, 0x00c000-0x00cfff, 0x00d000-0x00dfff, 0x00e000-0x00efff, 0x00f000-0x00ffff, 0x010000-0x010fff, 0x011000-0x011fff, 0x012000-0x012fff, 0x013000-0x013fff, 0x014000-0x014fff, 0x015000-0x015fff, 0x016000-0x016fff, 0x017000-0x017fff, 0x018000-0x018fff, 0x019000-0x019fff, 0x01a000-0x01afff, 0x01b000-0x01bfff, 0x01c000-0x01cfff, 0x01d000-0x01dfff, 0x01e000-0x01efff, 0x01f000-0x01ffff, 0x020000-0x020fff, 0x021000-0x021fff, 0x022000-0x022fff, 0x023000-0x023fff, 0x024000-0x024fff, 0x025000-0x025fff, 0x026000-0x026fff, 0x027000-0x027fff, 0x028000-0x028fff, 0x029000-0x029fff, 0x02a000-0x02afff, 0x02b000-0x02bfff, 0x02c000-0x02cfff, 0x02d000-0x02dfff, 0x02e000-0x02efff, 0x02f000-0x02ffff, 0x030000-0x030fff, 0x031000-0x031fff, 0x032000-0x032fff, 0x033000-0x033fff, 0x034000-0x034fff, 0x035000-0x035fff, 0x036000-0x036fff, 0x037000-0x037fff, 0x038000-0x038fff, 0x039000-0x039fff, 0x03a000-0x03afff, 0x03b000-0x03bfff, 0x03c000-0x03cfff, 0x03d000-0x03dfff, 0x03e000-0x03efff, 0x03f000-0x03ffff, 0x040000-0x040fff, 0x041000-0x041fff, 0x042000-0x042fff, 0x043000-0x043fff, 0x044000-0x044fff, 0x045000-0x045fff, 0x046000-0x046fff, 0x047000-0x047fff, 0x048000-0x048fff, 0x049000-0x049fff, 0x04a000-0x04afff, 0x04b000-0x04bfff, 0x04c000-0x04cfff, 0x04d000-0x04dfff, 0x04e000-0x04efff, 0x04f000-0x04ffff, 0x050000-0x050fff, 0x051000-0x051fff, 0x052000-0x052fff, 0x053000-0x053fff, 0x054000-0x054fff, 0x055000-0x055fff, 0x056000-0x056fff, 0x057000-0x057fff, 0x058000-0x058fff, 0x059000-0x059fff, 0x05a000-0x05afff, 0x05b000-0x05bfff, 0x05c000-0x05cfff, 0x05d000-0x05dfff, 0x05e000-0x05efff, 0x05f000-0x05ffff, 0x060000-0x060fff, 0x061000-0x061fff, 0x062000-0x062fff, 0x063000-0x063fff, 0x064000-0x064fff, 0x065000-0x065fff, 0x066000-0x066fff, 0x067000-0x067fff, 0x068000-0x068fff, 0x069000-0x069fff, 0x06a000-0x06afff, 0x06b000-0x06bfff, 0x06c000-0x06cfff, 0x06d000-0x06dfff, 0x06e000-0x06efff, 0x06f000-0x06ffff, 0x070000-0x070fff, 0x071000-0x071fff, 0x072000-0x072fff, 0x073000-0x073fff, 0x074000-0x074fff, 0x075000-0x075fff, 0x076000-0x076fff, 0x077000-0x077fff, 0x078000-0x078fff, 0x079000-0x079fff, 0x07a000-0x07afff, 0x07b000-0x07bfff, 0x07c000-0x07cfff, 0x07d000-0x07dfff, 0x07e000-0x07efff, 0x07f000-0x07ffff, 0x080000-0x080fff, 0x081000-0x081fff, 0x082000-0x082fff, 0x083000-0x083fff, 0x084000-0x084fff, 0x085000-0x085fff, 0x086000-0x086fff, 0x087000-0x087fff, 0x088000-0x088fff, 0x089000-0x089fff, 0x08a000-0x08afff, 0x08b000-0x08bfff, 0x08c000-0x08cfff, 0x08d000-0x08dfff, 0x08e000-0x08efff, 0x08f000-0x08ffff, 0x090000-0x090fff, 0x091000-0x091fff, 0x092000-0x092fff, 0x093000-0x093fff, 0x094000-0x094fff, 0x095000-0x095fff, 0x096000-0x096fff, 0x097000-0x097fff, 0x098000-0x098fff, 0x099000-0x099fff, 0x09a000-0x09afff, 0x09b000-0x09bfff, 0x09c000-0x09cfff, 0x09d000-0x09dfff, 0x09e000-0x09efff, 0x09f000-0x09ffff, 0x0a0000-0x0a0fff, 0x0a1000-0x0a1fff, 0x0a2000-0x0a2fff, 0x0a3000-0x0a3fff, 0x0a4000-0x0a4fff, 0x0a5000-0x0a5fff, 0x0a6000-0x0a6fff, 0x0a7000-0x0a7fff, 0x0a8000-0x0a8fff, 0x0a9000-0x0a9fff, 0x0aa000-0x0aafff, 0x0ab000-0x0abfff, 0x0ac000-0x0acfff, 0x0ad000-0x0adfff, 0x0ae000-0x0aefff, 0x0af000-0x0affff, 0x0b0000-0x0b0fff, 0x0b1000-0x0b1fff, 0x0b2000-0x0b2fff, 0x0b3000-0x0b3fff, 0x0b4000-0x0b4fff, 0x0b5000-0x0b5fff, 0x0b6000-0x0b6fff, 0x0b7000-0x0b7fff, 0x0b8000-0x0b8fff, 0x0b9000-0x0b9fff, 0x0ba000-0x0bafff, 0x0bb000-0x0bbfff, 0x0bc000-0x0bcfff, 0x0bd000-0x0bdfff, 0x0be000-0x0befff, 0x0bf000-0x0bffff, 0x0c0000-0x0c0fff, 0x0c1000-0x0c1fff, 0x0c2000-0x0c2fff, 0x0c3000-0x0c3fff, 0x0c4000-0x0c4fff, 0x0c5000-0x0c5fff, 0x0c6000-0x0c6fff, 0x0c7000-0x0c7fff, 0x0c8000-0x0c8fff, 0x0c9000-0x0c9fff, 0x0ca000-0x0cafff, 0x0cb000-0x0cbfff, 0x0cc000-0x0ccfff, 0x0cd000-0x0cdfff, 0x0ce000-0x0cefff, 0x0cf000-0x0cffff, 0x0d0000-0x0d0fff, 0x0d1000-0x0d1fff, 0x0d2000-0x0d2fff, 0x0d3000-0x0d3fff, 0x0d4000-0x0d4fff, 0x0d5000-0x0d5fff, 0x0d6000-0x0d6fff, 0x0d7000-0x0d7fff, 0x0d8000-0x0d8fff, 0x0d9000-0x0d9fff, 0x0da000-0x0dafff, 0x0db000-0x0dbfff, 0x0dc000-0x0dcfff, 0x0dd000-0x0ddfff, 0x0de000-0x0defff, 0x0df000-0x0dffff, 0x0e0000-0x0e0fff, 0x0e1000-0x0e1fff, 0x0e2000-0x0e2fff, 0x0e3000-0x0e3fff, 0x0e4000-0x0e4fff, 0x0e5000-0x0e5fff, 0x0e6000-0x0e6fff, 0x0e7000-0x0e7fff, 0x0e8000-0x0e8fff, 0x0e9000-0x0e9fff, 0x0ea000-0x0eafff, 0x0eb000-0x0ebfff, 0x0ec000-0x0ecfff, 0x0ed000-0x0edfff, 0x0ee000-0x0eefff, 0x0ef000-0x0effff, 0x0f0000-0x0f0fff, 0x0f1000-0x0f1fff, 0x0f2000-0x0f2fff, 0x0f3000-0x0f3fff, 0x0f4000-0x0f4fff, 0x0f5000-0x0f5fff, 0x0f6000-0x0f6fff, 0x0f7000-0x0f7fff, 0x0f8000-0x0f8fff, 0x0f9000-0x0f9fff, 0x0fa000-0x0fafff, 0x0fb000-0x0fbfff, 0x0fc000-0x0fcfff, 0x0fd000-0x0fdfff, 0x0fe000-0x0fefff, 0x0ff000-0x0fffff, 0x100000-0x100fff, 0x101000-0x101fff, 0x102000-0x102fff, 0x103000-0x103fff, 0x104000-0x104fff, 0x105000-0x105fff, 0x106000-0x106fff, 0x107000-0x107fff, 0x108000-0x108fff, 0x109000-0x109fff, 0x10a000-0x10afff, 0x10b000-0x10bfff, 0x10c000-0x10cfff, 0x10d000-0x10dfff, 0x10e000-0x10efff, 0x10f000-0x10ffff, 0x110000-0x110fff, 0x111000-0x111fff, 0x112000-0x112fff, 0x113000-0x113fff, 0x114000-0x114fff, 0x115000-0x115fff, 0x116000-0x116fff, 0x117000-0x117fff, 0x118000-0x118fff, 0x119000-0x119fff, 0x11a000-0x11afff, 0x11b000-0x11bfff, 0x11c000-0x11cfff, 0x11d000-0x11dfff, 0x11e000-0x11efff, 0x11f000-0x11ffff, 0x120000-0x120fff, 0x121000-0x121fff, 0x122000-0x122fff, 0x123000-0x123fff, 0x124000-0x124fff, 0x125000-0x125fff, 0x126000-0x126fff, 0x127000-0x127fff, 0x128000-0x128fff, 0x129000-0x129fff, 0x12a000-0x12afff, 0x12b000-0x12bfff, 0x12c000-0x12cfff, 0x12d000-0x12dfff, 0x12e000-0x12efff, 0x12f000-0x12ffff, 0x130000-0x130fff, 0x131000-0x131fff, 0x132000-0x132fff, 0x133000-0x133fff, 0x134000-0x134fff, 0x135000-0x135fff, 0x136000-0x136fff, 0x137000-0x137fff, 0x138000-0x138fff, 0x139000-0x139fff, 0x13a000-0x13afff, 0x13b000-0x13bfff, 0x13c000-0x13cfff, 0x13d000-0x13dfff, 0x13e000-0x13efff, 0x13f000-0x13ffff, 0x140000-0x140fff, 0x141000-0x141fff, 0x142000-0x142fff, 0x143000-0x143fff, 0x144000-0x144fff, 0x145000-0x145fff, 0x146000-0x146fff, 0x147000-0x147fff, 0x148000-0x148fff, 0x149000-0x149fff, 0x14a000-0x14afff, 0x14b000-0x14bfff, 0x14c000-0x14cfff, 0x14d000-0x14dfff, 0x14e000-0x14efff, 0x14f000-0x14ffff, 0x150000-0x150fff, 0x151000-0x151fff, 0x152000-0x152fff, 0x153000-0x153fff, 0x154000-0x154fff, 0x155000-0x155fff, 0x156000-0x156fff, 0x157000-0x157fff, 0x158000-0x158fff, 0x159000-0x159fff, 0x15a000-0x15afff, 0x15b000-0x15bfff, 0x15c000-0x15cfff, 0x15d000-0x15dfff, 0x15e000-0x15efff, 0x15f000-0x15ffff, 0x160000-0x160fff, 0x161000-0x161fff, 0x162000-0x162fff, 0x163000-0x163fff, 0x164000-0x164fff, 0x165000-0x165fff, 0x166000-0x166fff, 0x167000-0x167fff, 0x168000-0x168fff, 0x169000-0x169fff, 0x16a000-0x16afff, 0x16b000-0x16bfff, 0x16c000-0x16cfff, 0x16d000-0x16dfff, 0x16e000-0x16efff, 0x16f000-0x16ffff, 0x170000-0x170fff, 0x171000-0x171fff, 0x172000-0x172fff, 0x173000-0x173fff, 0x174000-0x174fff, 0x175000-0x175fff, 0x176000-0x176fff, 0x177000-0x177fff, 0x178000-0x178fff, 0x179000-0x179fff, 0x17a000-0x17afff, 0x17b000-0x17bfff, 0x17c000-0x17cfff, 0x17d000-0x17dfff, 0x17e000-0x17efff, 0x17f000-0x17ffff, 0x180000-0x180fff, 0x181000-0x181fff, 0x182000-0x182fff, 0x183000-0x183fff, 0x184000-0x184fff, 0x185000-0x185fff, 0x186000-0x186fff, 0x187000-0x187fff, 0x188000-0x188fff, 0x189000-0x189fff, 0x18a000-0x18afff, 0x18b000-0x18bfff, 0x18c000-0x18cfff, 0x18d000-0x18dfff, 0x18e000-0x18efff, 0x18f000-0x18ffff, 0x190000-0x190fff, 0x191000-0x191fff, 0x192000-0x192fff, 0x193000-0x193fff, 0x194000-0x194fff, 0x195000-0x195fff, 0x196000-0x196fff, 0x197000-0x197fff, 0x198000-0x198fff, 0x199000-0x199fff, 0x19a000-0x19afff, 0x19b000-0x19bfff, 0x19c000-0x19cfff, 0x19d000-0x19dfff, 0x19e000-0x19efff, 0x19f000-0x19ffff, 0x1a0000-0x1a0fff, 0x1a1000-0x1a1fff, 0x1a2000-0x1a2fff, 0x1a3000-0x1a3fff, 0x1a4000-0x1a4fff, 0x1a5000-0x1a5fff, 0x1a6000-0x1a6fff, 0x1a7000-0x1a7fff, 0x1a8000-0x1a8fff, 0x1a9000-0x1a9fff, 0x1aa000-0x1aafff, 0x1ab000-0x1abfff, 0x1ac000-0x1acfff, 0x1ad000-0x1adfff, 0x1ae000-0x1aefff, 0x1af000-0x1affff, 0x1b0000-0x1b0fff, 0x1b1000-0x1b1fff, 0x1b2000-0x1b2fff, 0x1b3000-0x1b3fff, 0x1b4000-0x1b4fff, 0x1b5000-0x1b5fff, 0x1b6000-0x1b6fff, 0x1b7000-0x1b7fff, 0x1b8000-0x1b8fff, 0x1b9000-0x1b9fff, 0x1ba000-0x1bafff, 0x1bb000-0x1bbfff, 0x1bc000-0x1bcfff, 0x1bd000-0x1bdfff, 0x1be000-0x1befff, 0x1bf000-0x1bffff, 0x1c0000-0x1c0fff, 0x1c1000-0x1c1fff, 0x1c2000-0x1c2fff, 0x1c3000-0x1c3fff, 0x1c4000-0x1c4fff, 0x1c5000-0x1c5fff, 0x1c6000-0x1c6fff, 0x1c7000-0x1c7fff, 0x1c8000-0x1c8fff, 0x1c9000-0x1c9fff, 0x1ca000-0x1cafff, 0x1cb000-0x1cbfff, 0x1cc000-0x1ccfff, 0x1cd000-0x1cdfff, 0x1ce000-0x1cefff, 0x1cf000-0x1cffff, 0x1d0000-0x1d0fff, 0x1d1000-0x1d1fff, 0x1d2000-0x1d2fff, 0x1d3000-0x1d3fff, 0x1d4000-0x1d4fff, 0x1d5000-0x1d5fff, 0x1d6000-0x1d6fff, 0x1d7000-0x1d7fff, 0x1d8000-0x1d8fff, 0x1d9000-0x1d9fff, 0x1da000-0x1dafff, 0x1db000-0x1dbfff, 0x1dc000-0x1dcfff, 0x1dd000-0x1ddfff, 0x1de000-0x1defff, 0x1df000-0x1dffff, 0x1e0000-0x1e0fff, 0x1e1000-0x1e1fff, 0x1e2000-0x1e2fff, 0x1e3000-0x1e3fff, 0x1e4000-0x1e4fff, 0x1e5000-0x1e5fff, 0x1e6000-0x1e6fff, 0x1e7000-0x1e7fff, 0x1e8000-0x1e8fff, 0x1e9000-0x1e9fff, 0x1ea000-0x1eafff, 0x1eb000-0x1ebfff, 0x1ec000-0x1ecfff, 0x1ed000-0x1edfff, 0x1ee000-0x1eefff, 0x1ef000-0x1effff, 0x1f0000-0x1f0fff, 0x1f1000-0x1f1fff, 0x1f2000-0x1f2fff, 0x1f3000-0x1f3fff, 0x1f4000-0x1f4fff, 0x1f5000-0x1f5fff, 0x1f6000-0x1f6fff, 0x1f7000-0x1f7fff, 0x1f8000-0x1f8fff, 0x1f9000-0x1f9fff, 0x1fa000-0x1fafff, 0x1fb000-0x1fbfff, 0x1fc000-0x1fcfff, 0x1fd000-0x1fdfff, 0x1fe000-0x1fefff, 0x1ff000-0x1fffff, 0x200000-0x200fff, 0x201000-0x201fff, 0x202000-0x202fff, 0x203000-0x203fff, 0x204000-0x204fff, 0x205000-0x205fff, 0x206000-0x206fff, 0x207000-0x207fff, 0x208000-0x208fff, 0x209000-0x209fff, 0x20a000-0x20afff, 0x20b000-0x20bfff, 0x20c000-0x20cfff, 0x20d000-0x20dfff, 0x20e000-0x20efff, 0x20f000-0x20ffff, 0x210000-0x210fff, 0x211000-0x211fff, 0x212000-0x212fff, 0x213000-0x213fff, 0x214000-0x214fff, 0x215000-0x215fff, 0x216000-0x216fff, 0x217000-0x217fff, 0x218000-0x218fff, 0x219000-0x219fff, 0x21a000-0x21afff, 0x21b000-0x21bfff, 0x21c000-0x21cfff, 0x21d000-0x21dfff, 0x21e000-0x21efff, 0x21f000-0x21ffff, 0x220000-0x220fff, 0x221000-0x221fff, 0x222000-0x222fff, 0x223000-0x223fff, 0x224000-0x224fff, 0x225000-0x225fff, 0x226000-0x226fff, 0x227000-0x227fff, 0x228000-0x228fff, 0x229000-0x229fff, 0x22a000-0x22afff, 0x22b000-0x22bfff, 0x22c000-0x22cfff, 0x22d000-0x22dfff, 0x22e000-0x22efff, 0x22f000-0x22ffff, 0x230000-0x230fff, 0x231000-0x231fff, 0x232000-0x232fff, 0x233000-0x233fff, 0x234000-0x234fff, 0x235000-0x235fff, 0x236000-0x236fff, 0x237000-0x237fff, 0x238000-0x238fff, 0x239000-0x239fff, 0x23a000-0x23afff, 0x23b000-0x23bfff, 0x23c000-0x23cfff, 0x23d000-0x23dfff, 0x23e000-0x23efff, 0x23f000-0x23ffff, 0x240000-0x240fff, 0x241000-0x241fff, 0x242000-0x242fff, 0x243000-0x243fff, 0x244000-0x244fff, 0x245000-0x245fff, 0x246000-0x246fff, 0x247000-0x247fff, 0x248000-0x248fff, 0x249000-0x249fff, 0x24a000-0x24afff, 0x24b000-0x24bfff, 0x24c000-0x24cfff, 0x24d000-0x24dfff, 0x24e000-0x24efff, 0x24f000-0x24ffff, 0x250000-0x250fff, 0x251000-0x251fff, 0x252000-0x252fff, 0x253000-0x253fff, 0x254000-0x254fff, 0x255000-0x255fff, 0x256000-0x256fff, 0x257000-0x257fff, 0x258000-0x258fff, 0x259000-0x259fff, 0x25a000-0x25afff, 0x25b000-0x25bfff, 0x25c000-0x25cfff, 0x25d000-0x25dfff, 0x25e000-0x25efff, 0x25f000-0x25ffff, 0x260000-0x260fff, 0x261000-0x261fff, 0x262000-0x262fff, 0x263000-0x263fff, 0x264000-0x264fff, 0x265000-0x265fff, 0x266000-0x266fff, 0x267000-0x267fff, 0x268000-0x268fff, 0x269000-0x269fff, 0x26a000-0x26afff, 0x26b000-0x26bfff, 0x26c000-0x26cfff, 0x26d000-0x26dfff, 0x26e000-0x26efff, 0x26f000-0x26ffff, 0x270000-0x270fff, 0x271000-0x271fff, 0x272000-0x272fff, 0x273000-0x273fff, 0x274000-0x274fff, 0x275000-0x275fff, 0x276000-0x276fff, 0x277000-0x277fff, 0x278000-0x278fff, 0x279000-0x279fff, 0x27a000-0x27afff, 0x27b000-0x27bfff, 0x27c000-0x27cfff, 0x27d000-0x27dfff, 0x27e000-0x27efff, 0x27f000-0x27ffff, 0x280000-0x280fff, 0x281000-0x281fff, 0x282000-0x282fff, 0x283000-0x283fff, 0x284000-0x284fff, 0x285000-0x285fff, 0x286000-0x286fff, 0x287000-0x287fff, 0x288000-0x288fff, 0x289000-0x289fff, 0x28a000-0x28afff, 0x28b000-0x28bfff, 0x28c000-0x28cfff, 0x28d000-0x28dfff, 0x28e000-0x28efff, 0x28f000-0x28ffff, 0x290000-0x290fff, 0x291000-0x291fff, 0x292000-0x292fff, 0x293000-0x293fff, 0x294000-0x294fff, 0x295000-0x295fff, 0x296000-0x296fff, 0x297000-0x297fff, 0x298000-0x298fff, 0x299000-0x299fff, 0x29a000-0x29afff, 0x29b000-0x29bfff, 0x29c000-0x29cfff, 0x29d000-0x29dfff, 0x29e000-0x29efff, 0x29f000-0x29ffff, 0x2a0000-0x2a0fff, 0x2a1000-0x2a1fff, 0x2a2000-0x2a2fff, 0x2a3000-0x2a3fff, 0x2a4000-0x2a4fff, 0x2a5000-0x2a5fff, 0x2a6000-0x2a6fff, 0x2a7000-0x2a7fff, 0x2a8000-0x2a8fff, 0x2a9000-0x2a9fff, 0x2aa000-0x2aafff, 0x2ab000-0x2abfff, 0x2ac000-0x2acfff, 0x2ad000-0x2adfff, 0x2ae000-0x2aefff, 0x2af000-0x2affff, 0x2b0000-0x2b0fff, 0x2b1000-0x2b1fff, 0x2b2000-0x2b2fff, 0x2b3000-0x2b3fff, 0x2b4000-0x2b4fff, 0x2b5000-0x2b5fff, 0x2b6000-0x2b6fff, 0x2b7000-0x2b7fff, 0x2b8000-0x2b8fff, 0x2b9000-0x2b9fff, 0x2ba000-0x2bafff, 0x2bb000-0x2bbfff, 0x2bc000-0x2bcfff, 0x2bd000-0x2bdfff, 0x2be000-0x2befff, 0x2bf000-0x2bffff, 0x2c0000-0x2c0fff, 0x2c1000-0x2c1fff, 0x2c2000-0x2c2fff, 0x2c3000-0x2c3fff, 0x2c4000-0x2c4fff, 0x2c5000-0x2c5fff, 0x2c6000-0x2c6fff, 0x2c7000-0x2c7fff, 0x2c8000-0x2c8fff, 0x2c9000-0x2c9fff, 0x2ca000-0x2cafff, 0x2cb000-0x2cbfff, 0x2cc000-0x2ccfff, 0x2cd000-0x2cdfff, 0x2ce000-0x2cefff, 0x2cf000-0x2cffff, 0x2d0000-0x2d0fff, 0x2d1000-0x2d1fff, 0x2d2000-0x2d2fff, 0x2d3000-0x2d3fff, 0x2d4000-0x2d4fff, 0x2d5000-0x2d5fff, 0x2d6000-0x2d6fff, 0x2d7000-0x2d7fff, 0x2d8000-0x2d8fff, 0x2d9000-0x2d9fff, 0x2da000-0x2dafff, 0x2db000-0x2dbfff, 0x2dc000-0x2dcfff, 0x2dd000-0x2ddfff, 0x2de000-0x2defff, 0x2df000-0x2dffff, 0x2e0000-0x2e0fff, 0x2e1000-0x2e1fff, 0x2e2000-0x2e2fff, 0x2e3000-0x2e3fff, 0x2e4000-0x2e4fff, 0x2e5000-0x2e5fff, 0x2e6000-0x2e6fff, 0x2e7000-0x2e7fff, 0x2e8000-0x2e8fff, 0x2e9000-0x2e9fff, 0x2ea000-0x2eafff, 0x2eb000-0x2ebfff, 0x2ec000-0x2ecfff, 0x2ed000-0x2edfff, 0x2ee000-0x2eefff, 0x2ef000-0x2effff, 0x2f0000-0x2f0fff, 0x2f1000-0x2f1fff, 0x2f2000-0x2f2fff, 0x2f3000-0x2f3fff, 0x2f4000-0x2f4fff, 0x2f5000-0x2f5fff, 0x2f6000-0x2f6fff, 0x2f7000-0x2f7fff, 0x2f8000-0x2f8fff, 0x2f9000-0x2f9fff, 0x2fa000-0x2fafff, 0x2fb000-0x2fbfff, 0x2fc000-0x2fcfff, 0x2fd000-0x2fdfff, 0x2fe000-0x2fefff, 0x2ff000-0x2fffff, 0x300000-0x300fff, 0x301000-0x301fff, 0x302000-0x302fff, 0x303000-0x303fff, 0x304000-0x304fff, 0x305000-0x305fff, 0x306000-0x306fff, 0x307000-0x307fff, 0x308000-0x308fff, 0x309000-0x309fff, 0x30a000-0x30afff, 0x30b000-0x30bfff, 0x30c000-0x30cfff, 0x30d000-0x30dfff, 0x30e000-0x30efff, 0x30f000-0x30ffff, 0x310000-0x310fff, 0x311000-0x311fff, 0x312000-0x312fff, 0x313000-0x313fff, 0x314000-0x314fff, 0x315000-0x315fff, 0x316000-0x316fff, 0x317000-0x317fff, 0x318000-0x318fff, 0x319000-0x319fff, 0x31a000-0x31afff, 0x31b000-0x31bfff, 0x31c000-0x31cfff, 0x31d000-0x31dfff, 0x31e000-0x31efff, 0x31f000-0x31ffff, 0x320000-0x320fff, 0x321000-0x321fff, 0x322000-0x322fff, 0x323000-0x323fff, 0x324000-0x324fff, 0x325000-0x325fff, 0x326000-0x326fff, 0x327000-0x327fff, 0x328000-0x328fff, 0x329000-0x329fff, 0x32a000-0x32afff, 0x32b000-0x32bfff, 0x32c000-0x32cfff, 0x32d000-0x32dfff, 0x32e000-0x32efff, 0x32f000-0x32ffff, 0x330000-0x330fff, 0x331000-0x331fff, 0x332000-0x332fff, 0x333000-0x333fff, 0x334000-0x334fff, 0x335000-0x335fff, 0x336000-0x336fff, 0x337000-0x337fff, 0x338000-0x338fff, 0x339000-0x339fff, 0x33a000-0x33afff, 0x33b000-0x33bfff, 0x33c000-0x33cfff, 0x33d000-0x33dfff, 0x33e000-0x33efff, 0x33f000-0x33ffff, 0x340000-0x340fff, 0x341000-0x341fff, 0x342000-0x342fff, 0x343000-0x343fff, 0x344000-0x344fff, 0x345000-0x345fff, 0x346000-0x346fff, 0x347000-0x347fff, 0x348000-0x348fff, 0x349000-0x349fff, 0x34a000-0x34afff, 0x34b000-0x34bfff, 0x34c000-0x34cfff, 0x34d000-0x34dfff, 0x34e000-0x34efff, 0x34f000-0x34ffff, 0x350000-0x350fff, 0x351000-0x351fff, 0x352000-0x352fff, 0x353000-0x353fff, 0x354000-0x354fff, 0x355000-0x355fff, 0x356000-0x356fff, 0x357000-0x357fff, 0x358000-0x358fff, 0x359000-0x359fff, 0x35a000-0x35afff, 0x35b000-0x35bfff, 0x35c000-0x35cfff, 0x35d000-0x35dfff, 0x35e000-0x35efff, 0x35f000-0x35ffff, 0x360000-0x360fff, 0x361000-0x361fff, 0x362000-0x362fff, 0x363000-0x363fff, 0x364000-0x364fff, 0x365000-0x365fff, 0x366000-0x366fff, 0x367000-0x367fff, 0x368000-0x368fff, 0x369000-0x369fff, 0x36a000-0x36afff, 0x36b000-0x36bfff, 0x36c000-0x36cfff, 0x36d000-0x36dfff, 0x36e000-0x36efff, 0x36f000-0x36ffff, 0x370000-0x370fff, 0x371000-0x371fff, 0x372000-0x372fff, 0x373000-0x373fff, 0x374000-0x374fff, 0x375000-0x375fff, 0x376000-0x376fff, 0x377000-0x377fff, 0x378000-0x378fff, 0x379000-0x379fff, 0x37a000-0x37afff, 0x37b000-0x37bfff, 0x37c000-0x37cfff, 0x37d000-0x37dfff, 0x37e000-0x37efff, 0x37f000-0x37ffff, 0x380000-0x380fff, 0x381000-0x381fff, 0x382000-0x382fff, 0x383000-0x383fff, 0x384000-0x384fff, 0x385000-0x385fff, 0x386000-0x386fff, 0x387000-0x387fff, 0x388000-0x388fff, 0x389000-0x389fff, 0x38a000-0x38afff, 0x38b000-0x38bfff, 0x38c000-0x38cfff, 0x38d000-0x38dfff, 0x38e000-0x38efff, 0x38f000-0x38ffff, 0x390000-0x390fff, 0x391000-0x391fff, 0x392000-0x392fff, 0x393000-0x393fff, 0x394000-0x394fff, 0x395000-0x395fff, 0x396000-0x396fff, 0x397000-0x397fff, 0x398000-0x398fff, 0x399000-0x399fff, 0x39a000-0x39afff, 0x39b000-0x39bfff, 0x39c000-0x39cfff, 0x39d000-0x39dfff, 0x39e000-0x39efff, 0x39f000-0x39ffff, 0x3a0000-0x3a0fff, 0x3a1000-0x3a1fff, 0x3a2000-0x3a2fff, 0x3a3000-0x3a3fff, 0x3a4000-0x3a4fff, 0x3a5000-0x3a5fff, 0x3a6000-0x3a6fff, 0x3a7000-0x3a7fff, 0x3a8000-0x3a8fff, 0x3a9000-0x3a9fff, 0x3aa000-0x3aafff, 0x3ab000-0x3abfff, 0x3ac000-0x3acfff, 0x3ad000-0x3adfff, 0x3ae000-0x3aefff, 0x3af000-0x3affff, 0x3b0000-0x3b0fff, 0x3b1000-0x3b1fff, 0x3b2000-0x3b2fff, 0x3b3000-0x3b3fff, 0x3b4000-0x3b4fff, 0x3b5000-0x3b5fff, 0x3b6000-0x3b6fff, 0x3b7000-0x3b7fff, 0x3b8000-0x3b8fff, 0x3b9000-0x3b9fff, 0x3ba000-0x3bafff, 0x3bb000-0x3bbfff, 0x3bc000-0x3bcfff, 0x3bd000-0x3bdfff, 0x3be000-0x3befff, 0x3bf000-0x3bffff, 0x3c0000-0x3c0fff, 0x3c1000-0x3c1fff, 0x3c2000-0x3c2fff, 0x3c3000-0x3c3fff, 0x3c4000-0x3c4fff, 0x3c5000-0x3c5fff, 0x3c6000-0x3c6fff, 0x3c7000-0x3c7fff, 0x3c8000-0x3c8fff, 0x3c9000-0x3c9fff, 0x3ca000-0x3cafff, 0x3cb000-0x3cbfff, 0x3cc000-0x3ccfff, 0x3cd000-0x3cdfff, 0x3ce000-0x3cefff, 0x3cf000-0x3cffff, 0x3d0000-0x3d0fff, 0x3d1000-0x3d1fff, 0x3d2000-0x3d2fff, 0x3d3000-0x3d3fff, 0x3d4000-0x3d4fff, 0x3d5000-0x3d5fff, 0x3d6000-0x3d6fff, 0x3d7000-0x3d7fff, 0x3d8000-0x3d8fff, 0x3d9000-0x3d9fff, 0x3da000-0x3dafff, 0x3db000-0x3dbfff, 0x3dc000-0x3dcfff, 0x3dd000-0x3ddfff, 0x3de000-0x3defff, 0x3df000-0x3dffff, 0x3e0000-0x3e0fff, 0x3e1000-0x3e1fff, 0x3e2000-0x3e2fff, 0x3e3000-0x3e3fff, 0x3e4000-0x3e4fff, 0x3e5000-0x3e5fff, 0x3e6000-0x3e6fff, 0x3e7000-0x3e7fff, 0x3e8000-0x3e8fff, 0x3e9000-0x3e9fff, 0x3ea000-0x3eafff, 0x3eb000-0x3ebfff, 0x3ec000-0x3ecfff, 0x3ed000-0x3edfff, 0x3ee000-0x3eefff, 0x3ef000-0x3effff, 0x3f0000-0x3f0fff, 0x3f1000-0x3f1fff, 0x3f2000-0x3f2fff, 0x3f3000-0x3f3fff, 0x3f4000-0x3f4fff, 0x3f5000-0x3f5fff, 0x3f6000-0x3f6fff, 0x3f7000-0x3f7fff, 0x3f8000-0x3f8fff, 0x3f9000-0x3f9fff, 0x3fa000-0x3fafff, 0x3fb000-0x3fbfff, 0x3fc000-0x3fcfff, 0x3fd000-0x3fdfff, 0x3fe000-0x3fefff, 0x3ff000-0x3fffff, SUCCESS. done. Programming flash... done. COMPLETE. Verifying flash... VERIFIED.

2 7

Re: [flashrom] Atmel AT49LH002 support missing
by Mattias Mattsson 08 Sep '11

08 Sep '11

On Fri, Jul 15, 2011 at 02:34:07PM -0300, Marcos Felipe Rasia de Mello wrote: > 2011/7/15 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at>: > > > > jup, this one is not supported yet. > > the datasheet can for example be found here: > > http://www.datasheetcatalog.org/datasheet/atmel/doc3377.pdf > > it supports LPC and FWH so it may share some characteristics with the > > Pm49FL002. patches are welcome ;) > > Thank you for the information. Unfortunately I won't stay much time > with this board to test it, in case someone add support for the chip. Please test the attached patch and post a verbose (-V) log. Thanks, -mattias

4 3

[PATCH] Add Linux SPI support
by Sven Schnelle 07 Sep '11

07 Sep '11

Hi List, this patch adds support for the Linux SPI subsystem. See http://www.kernel.org/doc/Documentation/spi/spidev for a short introduction. Usage is as follows: flashrom -p linux_spi:dev=/dev/spidevX.Y where X is the bus number, and Y device. It accepts an optional parameter 'speed' which allows to set the SPI CLK speed in KHz. I'm using a AVR32 Board (http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4102) to program my ThinkPad X60, but it should work on every Linux system. Signed-off-by: Sven Schnelle <svens(a)stackframe.org>

3 6

[PATCH] Mark the GIGABYTE GA-8I945GZME-RH / SST25LF040A.RES as supported
by Uwe Hermann 07 Sep '11

07 Sep '11

Hi, see patch. Not sure if I should mark the SST25VF040.REMS as supported too? The code worked too, but it's not the correct chip, of course. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

1 1

[PATCH 1/1] Introduce ERROR_FATAL in chipset enables
by Tadas Slotkus 06 Sep '11

06 Sep '11

Currently we are continuing even if chipset enable has failed. Some chipset enables do exits, so to kill those exits I have prepared one sneaky check :) Errors are negative there, so I have chosen this constant. Signed-off-by: Tadas Slotkus <devtadas(a)gmail.com> --- chipset_enable.c | 4 ++++ flash.h | 3 ++- internal.c | 3 ++- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 687682a..f6c5d81 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1289,6 +1289,10 @@ int chipset_flash_enable(void) msg_pinfo("OK.\n"); else if (ret == ERROR_NONFATAL) msg_pinfo("PROBLEMS, continuing anyway\n"); + else if (ret == ERROR_FATAL) { + msg_perr("FATAL ERROR!\n") + return ret; + } } s = flashbuses_to_text(buses_supported); diff --git a/flash.h b/flash.h index 3d47a16..7386ecb 100644 --- a/flash.h +++ b/flash.h @@ -224,8 +224,9 @@ int write_buf_to_file(unsigned char *buf, unsigned long size, const char *filena #define OK 0 #define NT 1 /* Not tested */ -/* Something happened that shouldn't happen, but we can go on */ +/* Something happened that shouldn't happen, but we can go on, or not */ #define ERROR_NONFATAL 0x100 +#define ERROR_FATAL -0xEE /* cli_output.c */ /* Let gcc and clang check for correct printf-style format strings. */ diff --git a/internal.c b/internal.c index 846cf1e..46836b7 100644 --- a/internal.c +++ b/internal.c @@ -268,7 +268,8 @@ int internal_init(void) if (ret == -2) { msg_perr("WARNING: No chipset found. Flash detection " "will most likely fail.\n"); - } + } else if (ret == ERROR_FATAL) + return ret; #if defined(__i386__) || defined(__x86_64__) /* Probe unconditionally for IT87* LPC->SPI translation and for -- 1.7.6

3 9

[PATCH] Kill exit() calls in cli_classic
by Tadas Slotkus 03 Sep '11

03 Sep '11

exit() calls are very bad. GUI's and payload don't like it, so remove it for easier flashrom usage across projects. P.S. currently return values are the same as vere to exit calls, so if you have a clue what these should be please tell it now. Signed-off-by: Tadas Slotkus <devtadas(a)gmail.com> --- cli_classic.c | 55 ++++++++++++++++++++++++++----------------------------- 1 files changed, 26 insertions(+), 29 deletions(-) diff --git a/cli_classic.c b/cli_classic.c index c6fb379..43b435f 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -93,7 +93,6 @@ static void cli_classic_usage(const char *name) static void cli_classic_abort_usage(void) { printf("Please run \"flashrom --help\" for usage info.\n"); - exit(1); } int main(int argc, char *argv[]) @@ -142,7 +141,7 @@ int main(int argc, char *argv[]) print_banner(); if (selfcheck()) - exit(1); + return 1; setbuf(stdout, NULL); /* FIXME: Delay all operation_specified checks until after command @@ -155,7 +154,7 @@ int main(int argc, char *argv[]) if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } filename = strdup(optarg); read_it = 1; @@ -164,7 +163,7 @@ int main(int argc, char *argv[]) if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } filename = strdup(optarg); write_it = 1; @@ -174,12 +173,12 @@ int main(int argc, char *argv[]) if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } if (dont_verify_it) { fprintf(stderr, "--verify and --noverify are" "mutually exclusive. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } filename = strdup(optarg); verify_it = 1; @@ -188,7 +187,7 @@ int main(int argc, char *argv[]) if (verify_it) { fprintf(stderr, "--verify and --noverify are" "mutually exclusive. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } dont_verify_it = 1; break; @@ -202,7 +201,7 @@ int main(int argc, char *argv[]) if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } erase_it = 1; break; @@ -214,7 +213,7 @@ int main(int argc, char *argv[]) fprintf(stderr, "Error: Internal programmer support " "was not compiled in and --mainboard only\n" "applies to the internal programmer. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; #endif break; case 'f': @@ -222,8 +221,9 @@ int main(int argc, char *argv[]) break; case 'l': tempstr = strdup(optarg); - if (read_romlayout(tempstr)) - cli_classic_abort_usage(); + if (read_romlayout(tempstr)) { + cli_classic_abort_usage(); return 1; + } break; case 'i': /* FIXME: -l has to be specified before -i. */ @@ -232,14 +232,14 @@ int main(int argc, char *argv[]) fprintf(stderr, "Error: image %s not found in " "layout file or -i specified before " "-l\n", tempstr); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } break; case 'L': if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } list_supported = 1; break; @@ -248,13 +248,13 @@ int main(int argc, char *argv[]) if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } list_supported_wiki = 1; #else fprintf(stderr, "Error: Wiki output was not compiled " "in. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; #endif break; case 'p': @@ -286,7 +286,7 @@ int main(int argc, char *argv[]) if (programmer == PROGRAMMER_INVALID) { fprintf(stderr, "Error: Unknown programmer " "%s.\n", optarg); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } break; case 'R': @@ -294,41 +294,38 @@ int main(int argc, char *argv[]) if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } - exit(0); - break; + return 0; case 'h': if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } cli_classic_usage(argv[0]); - exit(0); - break; + return 0; default: - cli_classic_abort_usage(); - break; + cli_classic_abort_usage(); return 1; } } if (optind < argc) { fprintf(stderr, "Error: Extra parameter found.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } /* FIXME: Print the actions flashrom will take. */ if (list_supported) { print_supported(); - exit(0); + return 0; } #if CONFIG_PRINT_WIKI == 1 if (list_supported_wiki) { print_supported_wiki(); - exit(0); + return 0; } #endif @@ -336,7 +333,7 @@ int main(int argc, char *argv[]) if ((programmer != PROGRAMMER_INTERNAL) && (lb_part || lb_vendor)) { fprintf(stderr, "Error: --mainboard requires the internal " "programmer. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } #endif @@ -349,7 +346,7 @@ int main(int argc, char *argv[]) chip_to_probe); printf("Run flashrom -L to view the hardware supported " "in this flashrom version.\n"); - exit(1); + return 1; } /* Clean up after the check. */ flash = NULL; -- 1.7.6

2 2

Re: [flashrom] [PATCH] Make the laptop warning less scary if unsure
by Stefan Tauner 03 Sep '11

03 Sep '11

On Thu, 25 Aug 2011 14:56:56 +0200 Idwer Vollering <vidwer(a)gmail.com> wrote: > 2011/8/20 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at>: > > Telling the user to use "force_I_want_a_brick" if it is not even a > > laptop, is a bit over-the-top. Introduce a new laptop parameter > > "this_is_not_a_laptop" that allows to force operation, but only if > > the detection is not sure. > > > > --- > > > > complicates the whole thing a bit. could do without the extra > > variable and new part of the if condition, if we allow the > > this_is_not_a_laptop parameter to always work, not only if the > > laptop detection is uncertain. it will be undocumented and only > > visible to the user together with the warning anyway... > > I was curious whether the currently present overriding parameter works > in combination with the parameter in this patch, and it does: $ sudo > ./flashrom -V -p internal:laptop=force_I_want_a_brick -p > internal:laptop=this_is_not_a_laptop > flashrom v0.9.4-r1418 on FreeBSD 9.0-BETA1 (i386), built with libpci > 3.1.7, GCC 4.2.2 20070831 prerelease [FreeBSD], little endian > (etcetera) > > Do you think this behaviour is desired? > the force_I_want_a_brick will override the other one (which is then neither used nor checked). i think that is ok... this is already way too sophisticated imho. :) but thanks for pointing it out, i have not thought about it yet. do you think this is a problem? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 4

[PATCH] Make all programmer/CLI options case-insensitive
by Uwe Hermann 02 Sep '11

02 Sep '11

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

3 4

Re: [flashrom] SuperMicro X8DTU-6TF+: flashrom -Vr failed
by Stefan Tauner 02 Sep '11

02 Sep '11

On Fri, 12 Aug 2011 15:16:16 -0500 Scott Silverman <ssilverman(a)simplexinvestments.com> wrote: > # ./flashrom -Vr ../current.bios > flashrom v0.9.4-r1412 on Linux 2.6.29.6-sxtickless (x86_64), built with > libpci 3.1.7, GCC 4.1.2 20080704 (Red Hat 4.1.2-50), little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OS timer resolution is 1 usecs, 1523M loops per > second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 998 us, 10000 myus = > 9990 us, 4 myus = 4 us, OK. > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "Supermicro" > DMI string system-product-name: "X8DTU-6+" > DMI string system-version: "1234567890" > DMI string baseboard-manufacturer: "Supermicro" > DMI string baseboard-product-name: "X8DTU-6+" > DMI string baseboard-version: "2.01" > DMI string chassis-type: "Main Server Chassis" > Found chipset "Intel ICH10R" with PCI ID 8086:3a16. Enabling flash write... > 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x4 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x5 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x6 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x7 > 0x7fffffff/0x7fffffff FWH decode enabled > 0x7fffffff/0x7fffffff FWH decode enabled > 0x7fffffff/0x7fffffff FWH decode enabled > 0x7fffffff/0x7fffffff FWH decode enabled > 0x7fffffff/0x7fffffff FWH decode enabled > 0x7fffffff/0x7fffffff FWH decode enabled > 0x7fffffff/0x7fffffff FWH decode enabled > 0x7fffffff/0x7fffffff FWH decode enabled > 0x7fffffff/0x7fffffff FWH decode disabled > 0x7fffffff/0x7fffffff FWH decode disabled > 0x7fffffff/0x7fffffff FWH decode disabled > 0x7fffffff/0x7fffffff FWH decode disabled > Maximum FWH chip size: 0x100000 bytes > BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 > > Root Complex Register Block address = 0xfed1c000 > GCS = 0x460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) > Top Swap : not enabled > SPIBAR = 0xfed1c000 + 0x3800 > 0x04: 0x6008 (HSFS) > HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 > 0x06: 0x0000 (HSFC) > HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 > 0x08: 0x00002000 (FADDR) > 0x50: 0x00001a1b (FRAP) > BMWAG 0x00, BMRAG 0x00, BRWA 0x1a, BRRA 0x1b > 0x54: 0x00010000 (FREG0: Flash Descriptor) > 0x00000000-0x00001fff is read-only > 0x58: 0x03ff0200 (FREG1: BIOS) > 0x00200000-0x003fffff is read-write > 0x5C: 0x01ff0002 (FREG2: Management Engine) > 0x00002000-0x001fffff is locked > 0x60: 0x00001fff (FREG3: Gigabit Ethernet) > Gigabit Ethernet region is unused. > 0x64: 0x00001fff (FREG4: Platform Data) > Platform Data region is unused. > 0x74: 0x00000000 (PR0) > 0x78: 0x00000000 (PR1) > 0x7C: 0x00000000 (PR2) > 0x80: 0x00000000 (PR3) > 0x84: 0x00000000 (PR4) > 0x90: 0x04 (SSFS) > SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 > 0x91: 0x000000 (SSFC) > SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=0 > 0x94: 0x3906 (PREOP) > 0x96: 0xd43b (OPTYPE) > 0x98: 0x05200302 (OPMENU) > 0x9C: 0x3906019f (OPMENU+4) > 0xA0: 0x00000000 (BBAR) > 0xD0: 0x00000000 (FPB) > Programming OPCODES... > program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 > done > preop0=0x06, preop1=0x50 > op[0]=0x02, 3, 0 > op[1]=0x03, 2, 0 > op[2]=0xd8, 3, 0 > op[3]=0x05, 0, 0 > op[4]=0x90, 2, 0 > op[5]=0x01, 1, 0 > op[6]=0x9f, 0, 0 > op[7]=0xc7, 1, 0 > > SPI Read Configuration: prefetching disabled, caching enabled, OK. > This chipset supports the following protocols: FWH, SPI. > […] > Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 > 0x4701 > Chip status register is 10 > Found Atmel flash chip "AT25DF321A" (4096 kB, SPI) at physical address > 0xffc00000. > Ignoring security lockdown (if present) > Ignoring status register byte 2 > Chip status register is 10 > Chip status register: Sector Protection Register Lock (SRPL) is not set > Chip status register: Bit 6 is not set > Chip status register: Erase/Program Error (EPE) is not set > Chip status register: WP# pin (WPP) is not asserted > Chip status register: Software Protection Status (SWP): no sectors are > protected > Chip status register: Write Enable Latch (WEL) is not set > Chip status register: Write In Progress (WIP/BUSY) is not set > […] > === > This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE > The test status of this chip may have been updated in the latest development > version of flashrom. If you are running the latest development version, > please email a report to flashrom(a)flashrom.org if any of the above > operations > work correctly for you with this flash part. Please include the flashrom > output with the additional -V option for all operations you tested (-V, -Vr, > -Vw, -VE), and mention which mainboard or programmer you tested. > Please mention your board in the subject line. Thanks for your help! > Ignoring security lockdown (if present) > Reading flash... Transaction error! > SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 > SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=0 > Running OPCODE 0x03 failed at address 0x002000 (payload length was 64). > Read operation failed! > FAILED. > Restoring MMIO space at 0x7fe44a3648a0 > Restoring MMIO space at 0x7fe44a36489c > Restoring MMIO space at 0x7fe44a364898 > Restoring MMIO space at 0x7fe44a364896 > Restoring MMIO space at 0x7fe44a364894 > Restoring PCI config space for 00:1f:0 reg 0xdc Hello Scott, Thanks for your report! I have marked the flash chip as being detectable and will commit that later. The transaction error is expected, because the region is locked: > 0x5C: 0x01ff0002 (FREG2: Management Engine) > 0x00002000-0x001fffff is locked we are working on that but dont expect it to be working soon. i'll add the board to our list of (un)supported boards. you could try to update the bios region only with the help of a layout file, but i would not recommend it at all(!). the ME region contains the firmware for an embedded controller on your board and the (new) BIOS might not be compatible with the old firmware. this could lead to a bricked board that requires an external flash programmer and possibly even desoldering the flash chip to fix it... please use the vendor tools instead, sorry. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 2

[PATCH] Add a bunch of new/tested stuff and various small changes 7
by Stefan Tauner 31 Aug '11

31 Aug '11

- add Asus Crosshair IV Extreme to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-August/007640.html - add P7H55-M LX to the list of supported boards although flashrom works correctly, it is marked as not ok, because flashing the vendor image will break the LAN interface. - add GA-X58A-UD7 to the list of supported boards http://paste.flashrom.org/view.php?id=739 - add Asus P4P800-VM to print.c (has a working board enable) - add Asus K8V-X to print.c reported by florz http://paste.flashrom.org/view.php?id=742 - add Intel D865GLC to print.c reported by jmd on IRC http://paste.flashrom.org/view.php?id=775 - add ECS P4M800PRO-M (V1.0A) to the list of supported boards reported by dweg on IRC (hot flashed a SST49LF040B, original was W39V040B) - add X8DTU-6TF+ to print.c (needs ME unlocking) http://www.flashrom.org/pipermail/flashrom/2011-August/007553.html - add Shuttle FH67 (used in the SH67H3 barebone) to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-August/007749.html - add Tyan S2912 to the list of supported boards reported by erlan on IRC - add Zotac GeForce 8200 to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-August/007612.html - mark AT25DF321A as TEST_OK_PROBE http://www.flashrom.org/pipermail/flashrom/2011-August/007553.html - mark 28F001BN/BX-T as TEST_OK_PR http://www.flashrom.org/pipermail/flashrom/2011-July/007208.html - rename MX29F002 http://patchwork.coreboot.org/patch/2794/ - mark SST39SF040 as fully tested reported by Florian 'florz' Zumbiehl http://paste.flashrom.org/view.php?id=742 - mark SST49LF040B as fully tested reported by dweg on IRC and later by Armin on the ml: http://www.flashrom.org/pipermail/flashrom/2011-August/007764.html - mark H55 chipset as OK http://www.flashrom.org/pipermail/flashrom/2011-July/007432.html - mark H67 chipset as OK http://www.flashrom.org/pipermail/flashrom/2011-August/007749.html - add preliminary X79 (patsburg) PCI IDs 0x1d40 was reported already as working (not archived in our pipermail?) - mark "82557/8/9/0/1 Ethernet Pro 100" in nicintel.c as working http://www.flashrom.org/pipermail/flashrom/2011-August/007480.html - rename some chips that had gratuitous "probing" suffixes: - SST25VF010.REMS - SST25VF040.REMS - M25P05.RES - M25P10.RES - remove unneeded nicintel_spi-related function declarations in programmer.h - typos and whitespace fixes - fix Asus P4P800-E Deluxe detection The original board enable was added before DMI matching and used the IDs of a Promise controller as secondary PCI ID set. The controller could be disabled in the BIOS which would make the board not match. This patch uses the SMBUS controller instead and adds a DMI pattern. This was Tested-by: Michael Schneider <vdrportal_midas at gmx dot de> - add "Sealed-case PC" to the list of chassis type (as indicating "not a laptop") This is Acked-by: Idwer Vollering <vidwer(a)gmail.com> the fix for the typo unusued -> unused is Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier(a)gmail.com> everything else is Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- I think this is (more than) big enough to be committed. If no one vetoes i will commit it friday evening. board_enable.c | 2 +- chipset_enable.c | 12 +++++++----- dmi.c | 1 + flashchips.c | 24 ++++++++++++------------ flashchips.h | 8 ++++---- nicintel.c | 2 +- print.c | 11 +++++++++++ programmer.h | 3 --- 8 files changed, 37 insertions(+), 26 deletions(-) diff --git a/board_enable.c b/board_enable.c index 72f4cfe..896ab40 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2018,7 +2018,7 @@ const struct board_pciid_enable board_pciid_enables[] = { {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, P3, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise}, {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, P3, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, P3, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise}, - {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D3, 0x1043, 0x80A6, "^P4P800-E$", NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80A5, 0x8086, 0x24d0, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise}, {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e}, {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise}, diff --git a/chipset_enable.c b/chipset_enable.c index 336ad2e..ce00324 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -327,7 +327,7 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) } if (fwh_idsel & 0xffff000000000000ULL) { msg_perr("Error: fwh_idsel= specified, but value had " - "unusued bits set.\n"); + "unused bits set.\n"); goto idsel_garbage_out; } fwh_idsel_old = pci_read_long(dev, 0xd0); @@ -341,7 +341,7 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) /* FIXME: Decode settings are not changed. */ } else if (idsel) { msg_perr("Error: fwh_idsel= specified, but no value given.\n"); -idsel_garbage_out: +idsel_garbage_out: free(idsel); /* FIXME: Return failure here once internal_init() starts * to care about the return value of the chipset enable. @@ -846,7 +846,7 @@ static int enable_flash_ck804(struct pci_dev *dev, const char *name) if (new != old) { rpci_write_byte(dev, 0x88, new); if (pci_read_byte(dev, 0x88) != new) { - msg_pinfo("Setting register to set 0x%x to 0x%x on %s " + msg_pinfo("Setting register to 0x%x to 0x%x on %s " "failed (WARNING ONLY).\n", 0x88, new, name); } } @@ -1196,7 +1196,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x1c46, NT, "Intel", "P67", enable_flash_pch6}, {0x8086, 0x1c47, NT, "Intel", "UM67", enable_flash_pch6}, {0x8086, 0x1c49, NT, "Intel", "HM65", enable_flash_pch6}, - {0x8086, 0x1c4a, NT, "Intel", "H67", enable_flash_pch6}, + {0x8086, 0x1c4a, OK, "Intel", "H67", enable_flash_pch6}, {0x8086, 0x1c4b, NT, "Intel", "HM67", enable_flash_pch6}, {0x8086, 0x1c4c, NT, "Intel", "Q65", enable_flash_pch6}, {0x8086, 0x1c4d, NT, "Intel", "QS67", enable_flash_pch6}, @@ -1207,6 +1207,8 @@ const struct penable chipset_enables[] = { {0x8086, 0x1c54, NT, "Intel", "C204", enable_flash_pch6}, {0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_pch6}, {0x8086, 0x1c5c, NT, "Intel", "H61", enable_flash_pch6}, + {0x8086, 0x1d40, OK, "Intel", "X79", enable_flash_ich10}, /* FIXME: when datasheet is available */ + {0x8086, 0x1d41, NT, "Intel", "X79", enable_flash_ich10}, /* FIXME: when datasheet is available */ {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e}, {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e}, {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e}, @@ -1249,7 +1251,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_pch5}, {0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_pch5}, {0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_pch5}, - {0x8086, 0x3b06, NT, "Intel", "H55", enable_flash_pch5}, + {0x8086, 0x3b06, OK, "Intel", "H55", enable_flash_pch5}, {0x8086, 0x3b07, OK, "Intel", "QM57", enable_flash_pch5}, {0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_pch5}, {0x8086, 0x3b09, NT, "Intel", "HM55", enable_flash_pch5}, diff --git a/dmi.c b/dmi.c index 8f78376..5f64b94 100644 --- a/dmi.c +++ b/dmi.c @@ -81,6 +81,7 @@ static const struct { {0x0e, 1, "Sub Notebook"}, {0x11, 0, "Main Server Chassis"}, {0x17, 0, "Rack Mount Chassis"}, + {0x18, 0, "Sealed-case PC"}, /* used by Supermicro (X8SIE) */ }; #define DMI_COMMAND_LEN_MAX 260 diff --git a/flashchips.c b/flashchips.c index 7e7f47d..5ee8210 100644 --- a/flashchips.c +++ b/flashchips.c @@ -1544,7 +1544,7 @@ const struct flashchip flashchips[] = { .total_size = 4096, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PROBE, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -3768,13 +3768,13 @@ const struct flashchip flashchips[] = { .model_id = INTEL_28F001T, .total_size = 128, .page_size = 128 * 1024, /* 112k + 2x4k + 8k */ - .tested = TEST_UNTESTED, + .tested = TEST_OK_PR, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ .block_erasers = { { - .eraseblocks = { + .eraseblocks = { {112 * 1024, 1}, {4 * 1024, 2}, {8 * 1024, 1}, @@ -4488,7 +4488,7 @@ const struct flashchip flashchips[] = { { .vendor = "Macronix", - .name = "MX29F002B", + .name = "MX29F002(N)B", .bustype = BUS_PARALLEL, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX29F002B, @@ -4520,7 +4520,7 @@ const struct flashchip flashchips[] = { { .vendor = "Macronix", - .name = "MX29F002T", + .name = "MX29F002(N)T", .bustype = BUS_PARALLEL, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX29F002T, @@ -5637,7 +5637,7 @@ const struct flashchip flashchips[] = { { .vendor = "SST", - .name = "SST25VF010.REMS", + .name = "SST25VF010", .bustype = BUS_SPI, .manufacture_id = SST_ID, .model_id = SST_SST25VF010_REMS, @@ -5775,7 +5775,7 @@ const struct flashchip flashchips[] = { { .vendor = "SST", - .name = "SST25VF040.REMS", + .name = "SST25VF040", .bustype = BUS_SPI, .manufacture_id = SST_ID, .model_id = SST_SST25VF040_REMS, @@ -6125,7 +6125,7 @@ const struct flashchip flashchips[] = { .total_size = 512, .page_size = 4096, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, /* 150 ns */ .block_erasers = @@ -6610,7 +6610,7 @@ const struct flashchip flashchips[] = { .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_EITHER_RESET | FEATURE_REGISTERMAP, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, /* 150ns */ .block_erasers = @@ -6729,7 +6729,7 @@ const struct flashchip flashchips[] = { */ { .vendor = "ST", - .name = "M25P05.RES", + .name = "M25P05", .bustype = BUS_SPI, .manufacture_id = 0, /* Not used. */ .model_id = ST_M25P05_RES, @@ -6784,7 +6784,7 @@ const struct flashchip flashchips[] = { /* The ST M25P10 has the same problem as the M25P05. */ { .vendor = "ST", - .name = "M25P10.RES", + .name = "M25P10", .bustype = BUS_SPI, .manufacture_id = 0, /* Not used. */ .model_id = ST_M25P10_RES, @@ -6837,7 +6837,7 @@ const struct flashchip flashchips[] = { }, { - .vendor = "ST", + .vendor = "ST", /* Numonyx */ .name = "M25P40", .bustype = BUS_SPI, .manufacture_id = ST_ID, diff --git a/flashchips.h b/flashchips.h index ff49d31..e8b46ad 100644 --- a/flashchips.h +++ b/flashchips.h @@ -369,8 +369,8 @@ #define MACRONIX_MX25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */ #define MACRONIX_MX29F001B 0x19 #define MACRONIX_MX29F001T 0x18 -#define MACRONIX_MX29F002B 0x34 /* Same as MX29F002NB */ -#define MACRONIX_MX29F002T 0xB0 /* Same as MX29F002NT */ +#define MACRONIX_MX29F002B 0x34 /* Same as MX29F002NB; N has reset pin n/c. */ +#define MACRONIX_MX29F002T 0xB0 /* Same as MX29F002NT; N has reset pin n/c. */ #define MACRONIX_MX29F004B 0x46 #define MACRONIX_MX29F004T 0x45 #define MACRONIX_MX29F022T 0x36 /* Same as MX29F022NT */ @@ -474,7 +474,7 @@ #define SST_SST25VF040_REMS 0x44 /* REMS or RES opcode, same as SST25LF040A */ #define SST_SST25VF040B 0x258D #define SST_SST25VF040B_REMS 0x8D /* REMS or RES opcode */ -#define SST_SST25VF080_REMS 0x80 /* REMS or RES opcode */ +#define SST_SST25VF080_REMS 0x80 /* REMS or RES opcode, same as SST25LF080A */ #define SST_SST25VF080B 0x258E #define SST_SST25VF080B_REMS 0x8E /* REMS or RES opcode */ #define SST_SST25VF016B 0x2541 @@ -526,7 +526,7 @@ * ST25P chips are SPI, first byte of device ID is memory type, second * byte of device ID is related to log(bitsize) at least for some chips. */ -#define ST_ID 0x20 /* ST / SGS/Thomson */ +#define ST_ID 0x20 /* ST / SGS/Thomson / Numonyx (later acquired by Micron) */ #define ST_M25P05A 0x2010 #define ST_M25P05_RES 0x10 /* Same code as M25P10. */ #define ST_M25P10A 0x2011 diff --git a/nicintel.c b/nicintel.c index 5410523..f94cbc9 100644 --- a/nicintel.c +++ b/nicintel.c @@ -28,7 +28,7 @@ uint8_t *nicintel_control_bar; const struct pcidev_status nics_intel[] = { {PCI_VENDOR_ID_INTEL, 0x1209, NT, "Intel", "8255xER/82551IT Fast Ethernet Controller"}, - {PCI_VENDOR_ID_INTEL, 0x1229, NT, "Intel", "82557/8/9/0/1 Ethernet Pro 100"}, + {PCI_VENDOR_ID_INTEL, 0x1229, OK, "Intel", "82557/8/9/0/1 Ethernet Pro 100"}, {}, }; diff --git a/print.c b/print.c index f0bd477..66eb144 100644 --- a/print.c +++ b/print.c @@ -431,9 +431,11 @@ const struct board_info boards_known[] = { B("ASUS", "A8V Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=tvpdgPNCPaABZRVU", NULL), B("ASUS", "A8V-E Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=hQBPIJWEZnnGAZEh", NULL), B("ASUS", "A8V-E SE", 1, "http://www.asus.com/product.aspx?P_ID=VMfiJJRYTHM4gXIi", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html"), + B("ASUS", "Crosshair IV Extreme", 1, "http://www.asus.com/product.aspx?P_ID=lt1ShF6xEn3rlLe7", NULL), B("ASUS", "E35M1-I DELUXE", 1, "http://www.asus.com/product.aspx?P_ID=9BmKhMwWCwqyl1lz", NULL), B("ASUS", "K8V", 1, "http://www.asus.com/product.aspx?P_ID=fG2KZOWF7v6MRFRm", NULL), B("ASUS", "K8V SE Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=65HeDI8XM1u6Uy6o", NULL), + B("ASUS", "K8V-X", 1, NULL, NULL), B("ASUS", "K8V-X SE", 1, "http://www.asus.com/product.aspx?P_ID=lzDXlbBVHkdckHVr", NULL), B("ASUS", "M2A-MX", 1, "http://www.asus.com/product.aspx?P_ID=BmaOnPewi1JgltOZ", NULL), B("ASUS", "M2A-VM", 1, "http://www.asus.com/product.aspx?P_ID=St3pWpym8xXpROQS", "See http://www.coreboot.org/pipermail/coreboot/2007-September/025281.html"), @@ -469,6 +471,7 @@ const struct board_info boards_known[] = { B("ASUS", "P4C800-E Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=cFuVCr9bXXCckmcK", NULL), B("ASUS", "P4P800", 1, "http://www.asus.com/product.aspx?P_ID=DYt1Et9MlBChqzLb", NULL), B("ASUS", "P4P800-E Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=INIJUvLlif7LHp3g", NULL), + B("ASUS", "P4P800-VM", 1, NULL, NULL), B("ASUS", "P4SC-E", 1, "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock478/p4sc-e/", "Part of ASUS Terminator P4 533 barebone system"), B("ASUS", "P4SD-LA", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00022505", NULL), B("ASUS", "P4S533-X", 1, "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock478/p4s533-x/", NULL), @@ -496,6 +499,7 @@ const struct board_info boards_known[] = { B("ASUS", "P6T Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=vXixf82co6Q5v0BZ", NULL), B("ASUS", "P6T Deluxe V2", 1, "http://www.asus.com/product.aspx?P_ID=iRlP8RG9han6saZx", NULL), B("ASUS", "P7H57D-V EVO", 1, "http://www.asus.com/Motherboards/Intel_Socket_1156/P7H57DV_EVO/", NULL), + B("ASUS", "P7H55-M LX", 0, NULL, "flashrom works correctly, but GbE LAN is nonworking (probably due to a missing/bogus MAC address; see http://www.flashrom.org/pipermail/flashrom/2011-July/007432.html and http://ubuntuforums.org/showthread.php?t=1534389 for a possible workaround)"), B("ASUS", "Z8NA-D6C", 1, "http://www.asus.com/product.aspx?P_ID=k81cpN8uEB01BpQ6", NULL), B("BCOM", "WinNET100", 1, "http://www.coreboot.org/BCOM_WINNET100", "Used in the IGEL-316 thin client."), B("Biostar", "M6TBA", 0, "ftp://ftp.biostar-usa.com/manuals/M6TBA/", "No public report found. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>. May work now."), @@ -512,6 +516,7 @@ const struct board_info boards_known[] = { B("Elitegroup", "K7S5A", 1, "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=279&…", NULL), B("Elitegroup", "K7S6A", 1, "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=77&C…", NULL), B("Elitegroup", "K7VTA3", 1, "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=264&…", NULL), + B("Elitegroup", "P4M800PRO-M (V1.0A)", 1, "http://www.ecs.com.tw/ECSWebSite_2007/Products/ProductsDetail.aspx?Category…", NULL), B("Elitegroup", "P6IWP-Fe", 1, "http://www.ecs.com.tw/ECSWebSite_2007/Products/ProductsDetail.aspx?Category…", NULL), B("Elitegroup", "P6VAP-A+", 1, "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=117&…", NULL), B("Elitegroup", "RS485M-M", 1, "http://www.ecs.com.tw/ECSWebSite_2007/Products/ProductsDetail.aspx?Category…", NULL), @@ -567,6 +572,7 @@ const struct board_info boards_known[] = { B("GIGABYTE", "GA-MA790GP-DS4H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2887", NULL), B("GIGABYTE", "GA-MA790XT-UD4P (rev. 1.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3010", NULL), B("GIGABYTE", "GA-P55A-UD4 (rev. 1.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3436", NULL), + B("GIGABYTE", "GA-X58A-UD7 (rev. 2.0)", 1, NULL, NULL), B("HP", "e-Vectra P2706T", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?lang=en&cc=us&pro…", NULL), B("HP", "ProLiant DL145 G3", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c008…", NULL), B("HP", "ProLiant DL165 G6", 1, "http://h10010.www1.hp.com/wwpc/us/en/sm/WF05a/15351-15351-3328412-241644-33…", NULL), @@ -579,6 +585,7 @@ const struct board_info boards_known[] = { B("IBM", "x3455", 1, "http://www-03.ibm.com/systems/x/hardware/rack/x3455/index.html", NULL), B("IEI", "PICOe-9452", 1, "http://www.ieiworld.com/product_groups/industrial/content.aspx?keyword=WSB&…", NULL), B("Intel", "D201GLY", 1, "http://www.intel.com/support/motherboards/desktop/d201gly/index.htm", NULL), + B("Intel", "D865GLC", 0, NULL, "ICH5 with BIOS lock enable, see http://paste.flashrom.org/view.php?id=775"), B("Intel", "DG45ID", 0, "http://www.intel.com/products/desktop/motherboards/dg45id/dg45id-overview.h…", "Probing works (Winbond W25x32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME is locked."), B("Intel", "EP80759", 1, NULL, NULL), B("Intel", "Foxhollow", 1, NULL, "Intel reference board."), @@ -647,6 +654,7 @@ const struct board_info boards_known[] = { B("Shuttle", "AK38N", 1, "http://eu.shuttle.com/en/desktopdefault.aspx/tabid-36/558_read-9889/", NULL), B("Shuttle", "AV11V30", 1, NULL, NULL), B("Shuttle", "FD37", 1, "http://www.shuttle.eu/products/discontinued/barebones/sd37p2/", NULL), + B("Shuttle", "FH67", 1, "http://www.shuttle.eu/products/mini-pc/sh67h3/specification/", NULL), B("Shuttle", "FN25", 1, "http://www.shuttle.eu/products/discontinued/barebones/sn25p/?0=", NULL), B("Shuttle", "X50/X50(B)", 1, "http://au.shuttle.com/product_detail_spec.jsp?PI=1241", NULL), B("Soyo", "SY-5VD", 0, "http://www.soyo.com/content/Downloads/163/&c=80&p=464&l=English", "No public report found. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>. May work now."), @@ -664,6 +672,7 @@ const struct board_info boards_known[] = { B("Supermicro", "X8DT3", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DT3.cfm", NULL), B("Supermicro", "X8DTH-6F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTH-6F.cfm", NULL), B("Supermicro", "X8DTT-F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTT-F.cfm", NULL), + B("Supermicro", "X8DTU-6TF+", 0, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTU_.cfm?TYP=SAS&…", "Probing works (Atmel AT25DF321A, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked."), B("Supermicro", "X8DTU-F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTU-F.cfm", NULL), B("Supermicro", "X8SIE(-F)", 0, "http://www.supermicro.com/products/motherboard/Xeon3000/3400/X8SIE.cfm?IPMI…", "Requires unlocking the ME although the registers are set up correctly by the descriptor/BIOS already (tested with swseq and hwseq)."), B("Supermicro", "X8STi", 1, "http://www.supermicro.com/products/motherboard/Xeon3000/X58/X8STi.cfm", NULL), @@ -683,6 +692,7 @@ const struct board_info boards_known[] = { B("Tyan", "S2891 (Thunder K8SRE)", 1, "http://www.tyan.com/product_board_detail.aspx?pid=144", NULL), B("Tyan", "S2892 (Thunder K8SE)", 1, "http://www.tyan.com/product_board_detail.aspx?pid=145", NULL), B("Tyan", "S2895 (Thunder K8WE)", 1, "http://www.tyan.com/archive/products/html/thunderk8we.html", NULL), + B("Tyan", "S2912 (Thunder n3600R)", 1, "http://www.tyan.com/product_board_detail.aspx?pid=157", NULL), B("Tyan", "S2915 (Thunder n6650W)", 1, "http://tyan.com/product_board_detail.aspx?pid=163", NULL), B("Tyan", "S2915-E (Thunder n6650W)", 1, "http://tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=541&SKU=600000041", NULL), B("Tyan", "S2933 (Thunder n3600S)", 1, "http://tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=478&SKU=600000063", NULL), @@ -712,6 +722,7 @@ const struct board_info boards_known[] = { B("VIA", "pc2500e", 1, "http://www.via.com.tw/en/initiatives/empowered/pc2500_mainboard/index.jsp", NULL), B("VIA", "PC3500G", 1, "http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp", NULL), B("VIA", "VB700X", 1, "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…", NULL), + B("ZOTAC", "GeForce 8200", 1, "http://pden.zotac.com/index.php?page=shop.product_details&product_id=129&ca…", NULL), B("ZOTAC", "ZBOX HD-ID11", 1, "http://pdde.zotac.com/index.php?page=shop.product_details&product_id=240&ca…", NULL), #endif diff --git a/programmer.h b/programmer.h index 6a28dbe..70f3c09 100644 --- a/programmer.h +++ b/programmer.h @@ -424,9 +424,6 @@ extern const struct pcidev_status nics_intel[]; /* nicintel_spi.c */ #if CONFIG_NICINTEL_SPI == 1 int nicintel_spi_init(void); -int nicintel_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -void nicintel_spi_chip_writeb(uint8_t val, chipaddr addr); extern const struct pcidev_status nics_intel_spi[]; #endif -- 1.7.1

1 0

Tested writing vendor bios on asus m2n-e
by Armin Preiml 31 Aug '11

31 Aug '11

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Hello flashrom team I've tested writing the latest vendor bios (5001) on the asus m2n-e board. The log is attached. best regards - -- Armin Preiml Student of Computer Science -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iF4EAREIAAYFAk5egjcACgkQxbiSTpmfomFoHwD/T53aesUpjjiCkv6usPYD7PEa Gef+JILXJm3LGqmDBB4A/RFUaOFSYLKA3VhubY+9dJXsF6ocHk6smjh9fwZh/VJl =XN9F -----END PGP SIGNATURE-----

2 1

[PATCH] Revert parts of r1397
by Carl-Daniel Hailfinger 31 Aug '11

31 Aug '11

Hi, the whitespace and coding-style fixes in r1397 changed a few places which should have been left untouched or changed differently for various reasons: - Mixing uninitialized and initialized local variables leads to confusion. - ft2232_spi error cases should have gotten some error handling, and that's the reason the curly braces were there. - Depending on whom you ask about the C99 standard, a comma after the last element of an array initializer will cause another empty array element to be allocated, and that increases array size by 1 and may break some code which assumes certain fields to be nonzero. - Sometimes the introduced linebreaks look worse than before. - Fixing typos/wording in some places would have been nice given that those places were touched anyway. - If we insist on spelling "ASUS" all uppercase because the vendor said so, we have to spell "LPC Bridge" with an uppercase B because the datasheet said so. - #if/#else/#endif are sometimes hard to follow, and a comment at the #endif can improve readability a lot. Comments welcome. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-revert_r1397_partially/it87spi.c =================================================================== --- flashrom-revert_r1397_partially/it87spi.c (Revision 1402) +++ flashrom-revert_r1397_partially/it87spi.c (Arbeitskopie) @@ -203,7 +203,8 @@ int init_superio_ite(void) { - int i, ret = 0; + int i; + int ret = 0; for (i = 0; i < superio_count; i++) { if (superios[i].vendor != SUPERIO_VENDOR_ITE) Index: flashrom-revert_r1397_partially/cli_classic.c =================================================================== --- flashrom-revert_r1397_partially/cli_classic.c (Revision 1402) +++ flashrom-revert_r1397_partially/cli_classic.c (Arbeitskopie) @@ -104,13 +104,14 @@ struct flashchip flashes[3]; struct flashchip *fill_flash; const char *name; - int startchip = 0, chipcount = 0, namelen, opt, option_index = 0; - int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; - int dont_verify_it = 0, list_supported = 0, force = 0; + int namelen, opt, i; + int startchip = 0, chipcount = 0, option_index = 0, force = 0; #if CONFIG_PRINT_WIKI == 1 int list_supported_wiki = 0; #endif - int operation_specified = 0, i, ret = 0; + int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; + int dont_verify_it = 0, list_supported = 0, operation_specified = 0; + int ret = 0; static const char optstring[] = "r:Rw:v:nVEfc:m:l:i:p:Lzh"; static const struct option long_options[] = { Index: flashrom-revert_r1397_partially/dmi.c =================================================================== --- flashrom-revert_r1397_partially/dmi.c (Revision 1402) +++ flashrom-revert_r1397_partially/dmi.c (Arbeitskopie) @@ -196,7 +196,8 @@ */ static int dmi_compare(const char *value, const char *pattern) { - int anchored = 0, patternlen; + int anchored = 0; + int patternlen; msg_pspew("matching %s against %s\n", value, pattern); /* The empty string is part of all strings! */ Index: flashrom-revert_r1397_partially/dediprog.c =================================================================== --- flashrom-revert_r1397_partially/dediprog.c (Revision 1402) +++ flashrom-revert_r1397_partially/dediprog.c (Arbeitskopie) @@ -496,7 +496,8 @@ static int parse_voltage(char *voltage) { char *tmp = NULL; - int i, millivolt, fraction = 0; + int i; + int millivolt = 0, fraction = 0; if (!voltage || !strlen(voltage)) { msg_perr("Empty voltage= specified.\n"); @@ -574,7 +575,8 @@ { struct usb_device *dev; char *voltage; - int millivolt = 3500, ret; + int millivolt = 3500; + int ret; msg_pspew("%s\n", __func__); Index: flashrom-revert_r1397_partially/it85spi.c =================================================================== --- flashrom-revert_r1397_partially/it85spi.c (Revision 1402) +++ flashrom-revert_r1397_partially/it85spi.c (Arbeitskopie) @@ -84,15 +84,15 @@ static int it85xx_scratch_rom_reenter = 0; /* This function will poll the keyboard status register until either - * an expected value shows up, or - * timeout reaches. + * an expected value shows up, or the timeout is reached. + * timeout is in usec. * - * Returns: 0 -- the expected value has shown. - * 1 -- timeout reached. + * Returns: 0 -- the expected value showed up. + * 1 -- timeout. */ static int wait_for(const unsigned int mask, const unsigned int expected_value, - const int timeout /* in usec */, const char *error_message, - const char *function_name, const int lineno) + const int timeout, const char * error_message, + const char * function_name, const int lineno) { int time_passed; @@ -317,8 +317,9 @@ int i; it85xx_enter_scratch_rom(); - /* exit scratch ROM ONLY when programmer shuts down. Otherwise, the - * temporary flash state may halt EC. */ + /* Exit scratch ROM ONLY when programmer shuts down. Otherwise, the + * temporary flash state may halt the EC. + */ #ifdef LPC_IO INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); Index: flashrom-revert_r1397_partially/buspirate_spi.c =================================================================== --- flashrom-revert_r1397_partially/buspirate_spi.c (Revision 1402) +++ flashrom-revert_r1397_partially/buspirate_spi.c (Arbeitskopie) @@ -109,7 +109,7 @@ {"2.6M", 0x5}, {"4M", 0x6}, {"8M", 0x7}, - {NULL, 0x0}, + {NULL, 0x0} }; static int buspirate_spi_shutdown(void *data) @@ -150,9 +150,11 @@ int buspirate_spi_init(void) { unsigned char buf[512]; - int ret = 0, i, spispeed = 0x7; char *dev = NULL; char *speed = NULL; + int spispeed = 0x7; + int ret = 0; + int i; dev = extract_programmer_param("dev"); if (!dev || !strlen(dev)) { Index: flashrom-revert_r1397_partially/physmap.c =================================================================== --- flashrom-revert_r1397_partially/physmap.c (Revision 1402) +++ flashrom-revert_r1397_partially/physmap.c (Arbeitskopie) @@ -76,7 +76,7 @@ mi.address = phys_addr; mi.size = len; - ret = __dpmi_physical_address_mapping (&mi); + ret = __dpmi_physical_address_mapping(&mi); if (ret != 0) return ERROR_PTR; Index: flashrom-revert_r1397_partially/ft2232_spi.c =================================================================== --- flashrom-revert_r1397_partially/ft2232_spi.c (Revision 1402) +++ flashrom-revert_r1397_partially/ft2232_spi.c (Arbeitskopie) @@ -246,17 +246,21 @@ ftdic->error_str); } - if (ftdi_usb_reset(ftdic) < 0) + if (ftdi_usb_reset(ftdic) < 0) { msg_perr("Unable to reset FTDI device\n"); + } - if (ftdi_set_latency_timer(ftdic, 2) < 0) + if (ftdi_set_latency_timer(ftdic, 2) < 0) { msg_perr("Unable to set latency timer\n"); + } - if (ftdi_write_data_set_chunksize(ftdic, 256)) + if (ftdi_write_data_set_chunksize(ftdic, 256)) { msg_perr("Unable to set chunk size\n"); + } - if (ftdi_set_bitmode(ftdic, 0x00, BITMODE_BITBANG_SPI) < 0) + if (ftdi_set_bitmode(ftdic, 0x00, BITMODE_BITBANG_SPI) < 0) { msg_perr("Unable to set bitmode to SPI\n"); + } if (clock_5x) { msg_pdbg("Disable divide-by-5 front stage\n"); @@ -323,7 +327,8 @@ struct ftdi_context *ftdic = &ftdic_context; static unsigned char *buf = NULL; /* failed is special. We use bitwise ops, but it is essentially bool. */ - int i = 0, ret = 0, failed = 0, bufsize; + int i = 0, ret = 0, failed = 0; + int bufsize; static int oldbufsize = 0; if (writecnt > 65536 || readcnt > 65536) Index: flashrom-revert_r1397_partially/chipset_enable.c =================================================================== --- flashrom-revert_r1397_partially/chipset_enable.c (Revision 1402) +++ flashrom-revert_r1397_partially/chipset_enable.c (Arbeitskopie) @@ -309,8 +309,9 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) { uint32_t fwh_conf; + int i, tmp; char *idsel = NULL; - int i, tmp, max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0; + int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0; int contiguous = 1; idsel = extract_programmer_param("fwh_idsel"); @@ -1028,8 +1029,8 @@ flashbase = parx << 12; } } else { - msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. " - "Assuming flash at 4G\n"); + msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. Assuming " + "flash at 4G.\n"); } /* 4. Clean up */ Index: flashrom-revert_r1397_partially/flashrom.c =================================================================== --- flashrom-revert_r1397_partially/flashrom.c (Revision 1402) +++ flashrom-revert_r1397_partially/flashrom.c (Arbeitskopie) @@ -600,8 +600,7 @@ size_t size = flash->total_size * 1024; /* Flash registers live 4 MByte below the flash. */ /* FIXME: This is incorrect for nonstandard flashbase. */ - flash->virtual_registers = (chipaddr)programmer_map_flash_region( - "flash chip registers", (0xFFFFFFFF - 0x400000 - size + 1), size); + flash->virtual_registers = (chipaddr)programmer_map_flash_region("flash chip registers", (0xFFFFFFFF - 0x400000 - size + 1), size); } int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len) @@ -753,8 +752,9 @@ int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, const char *message) { - int i, ret = 0, failcount = 0; + int i; uint8_t *readbuf = malloc(len); + int ret = 0, failcount = 0; if (!len) goto out_free; @@ -832,7 +832,8 @@ */ int need_erase(uint8_t *have, uint8_t *want, int len, enum write_granularity gran) { - int result = 0, i, j, limit; + int result = 0; + int i, j, limit; switch (gran) { case write_gran_1bit: @@ -898,7 +899,8 @@ static int get_next_write(uint8_t *have, uint8_t *want, int len, int *first_start, enum write_granularity gran) { - int need_write = 0, rel_start = 0, first_len = 0, i, limit, stride; + int need_write = 0, rel_start = 0, first_len = 0; + int i, limit, stride; switch (gran) { case write_gran_1bit: @@ -1326,7 +1328,8 @@ */ static int selfcheck_eraseblocks(const struct flashchip *flash) { - int i, j, k, ret = 0; + int i, j, k; + int ret = 0; for (k = 0; k < NUM_ERASEFUNCTIONS; k++) { unsigned int done = 0; @@ -1451,7 +1454,8 @@ void *param1, void *param2) { int i, j; - unsigned int start = 0, len; + unsigned int start = 0; + unsigned int len; struct block_eraser eraser = flash->block_erasers[erasefunction]; for (i = 0; i < NUM_ERASEREGIONS; i++) { @@ -1603,8 +1607,10 @@ void list_programmers_linebreak(int startcol, int cols, int paren) { const char *pname; - int pnamelen, remaining = 0, firstline = 1, i; + int pnamelen; + int remaining = 0, firstline = 1; enum programmer p; + int i; for (p = 0; p < PROGRAMMER_INVALID; p++) { pname = programmer_table[p].name; @@ -1737,7 +1743,7 @@ msg_gerr("Known laptops table does not exist!\n"); ret = 1; } -#endif +#endif // CONFIG_INTERNAL == 1 return ret; } Index: flashrom-revert_r1397_partially/board_enable.c =================================================================== --- flashrom-revert_r1397_partially/board_enable.c (Revision 1402) +++ flashrom-revert_r1397_partially/board_enable.c (Arbeitskopie) @@ -179,7 +179,7 @@ static const struct winbond_port w83627hf[3] = { UNIMPLEMENTED_PORT, {w83627hf_port2_mux, 0x08, 0, 0xF0}, - UNIMPLEMENTED_PORT, + UNIMPLEMENTED_PORT }; static const struct winbond_mux w83627ehf_port2_mux[8] = { @@ -190,7 +190,7 @@ {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */ {0x2A, 0x01, 0x01}, {0x2A, 0x01, 0x01}, - {0x2A, 0x01, 0x01}, + {0x2A, 0x01, 0x01} }; static const struct winbond_port w83627ehf[6] = { @@ -199,7 +199,7 @@ UNIMPLEMENTED_PORT, UNIMPLEMENTED_PORT, UNIMPLEMENTED_PORT, - UNIMPLEMENTED_PORT, + UNIMPLEMENTED_PORT }; static const struct winbond_mux w83627thf_port4_mux[8] = { @@ -210,7 +210,7 @@ {0x2D, 0x10, 0x10}, /* or PWROK */ {0x2D, 0x20, 0x20}, /* or suspend LED */ {0x2D, 0x40, 0x40}, /* or panel switch input */ - {0x2D, 0x80, 0x80}, /* or panel switch output */ + {0x2D, 0x80, 0x80} /* or panel switch output */ }; static const struct winbond_port w83627thf[5] = { @@ -218,7 +218,7 @@ UNIMPLEMENTED_PORT, /* GPIO2 */ UNIMPLEMENTED_PORT, /* GPIO3 */ {w83627thf_port4_mux, 0x09, 1, 0xF4}, - UNIMPLEMENTED_PORT, /* GPIO5 */ + UNIMPLEMENTED_PORT /* GPIO5 */ }; static const struct winbond_chip winbond_chips[] = { @@ -812,7 +812,7 @@ { struct pci_dev *dev; - dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA bridge. */ + dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */ if (!dev) { msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n"); return -1; @@ -860,7 +860,7 @@ return -1; } - /* First, check the ISA bridge */ + /* First, check the ISA Bridge */ dev = pci_dev_find_vendorclass(0x10DE, 0x0601); switch (dev->device_id) { case 0x0030: /* CK804 */ @@ -1101,7 +1101,7 @@ struct pci_dev *dev; uint32_t reg; - dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus controller */ + dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus Controller */ if (!dev) { msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n"); return -1; @@ -1128,8 +1128,8 @@ struct pci_dev *dev; uint32_t tmp, base; - /* GPPO {0,8,27,28,30} are always available */ - static const uint32_t nonmuxed_gpos = 0x58000101; + /* GPO{0,8,27,28,30} are always available. */ + static const uint32_t nonmuxed_gpos = 0x58000101; static const struct {unsigned int reg, mask, value; } piix4_gpo[] = { {0}, @@ -1178,10 +1178,9 @@ } if ((((1 << gpo) & nonmuxed_gpos) == 0) && - (pci_read_word(dev, piix4_gpo[gpo].reg) - & piix4_gpo[gpo].mask) != piix4_gpo[gpo].value) { - msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", - gpo); + ((pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) != + piix4_gpo[gpo].value)) { + msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo); return -1; } @@ -1317,7 +1316,7 @@ /* libpci before version 2.2.4 does not store class info. */ device_class = pci_read_word(dev, PCI_CLASS_DEVICE); if ((dev->vendor_id == 0x8086) && - (device_class == 0x0601)) { /* ISA bridge */ + (device_class == 0x0601)) { /* ISA Bridge */ /* Is this device in our list? */ for (i = 0; intel_ich_gpio_table[i].id; i++) if (dev->device_id == intel_ich_gpio_table[i].id) @@ -1329,7 +1328,7 @@ } if (!dev) { - msg_perr("\nERROR: No known Intel LPC bridge found.\n"); + msg_perr("\nERROR: No Known Intel LPC Bridge found.\n"); return -1; } @@ -1349,12 +1348,12 @@ allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01; if (!allowed) { - msg_perr("\nERROR: This Intel LPC bridge does not allow" - " setting GPIO%02d\n", gpio); + msg_perr("\nERROR: This Intel LPC Bridge does not allow" + " setting GPIO%02d\n", gpio); return -1; } - msg_pdbg("\nIntel ICH LPC bridge: %sing GPIO%02d.\n", + msg_pdbg("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n", raise ? "Rais" : "Dropp", gpio); if (gpio < 32) { @@ -1373,7 +1372,7 @@ if (dev->device_id > 0x2800) { tmp = INL(base); if (!(tmp & (1 << gpio))) { - msg_perr("\nERROR: This Intel LPC bridge" + msg_perr("\nERROR: This Intel LPC Bridge" " does not allow setting GPIO%02d\n", gpio); return -1; @@ -1405,7 +1404,7 @@ if (dev->device_id > 0x2800) { tmp = INL(base + 30); if (!(tmp & (1 << gpio))) { - msg_perr("\nERROR: This Intel LPC bridge" + msg_perr("\nERROR: This Intel LPC Bridge" " does not allow setting GPIO%02d\n", gpio + 32); return -1; @@ -1434,7 +1433,7 @@ tmp = INL(base + 40); if (!(tmp & (1 << gpio))) { - msg_perr("\nERROR: This Intel LPC bridge does " + msg_perr("\nERROR: This Intel LPC Bridge does " "not allow setting GPIO%02d\n", gpio + 64); return -1; } @@ -2091,8 +2090,8 @@ * Match boards on coreboot table gathered vendor and part name. * Require main PCI IDs to match too as extra safety. */ -static const struct board_pciid_enable *board_match_coreboot_name( - const char *vendor, const char *part) +static const struct board_pciid_enable *board_match_coreboot_name(const char *vendor, + const char *part) { const struct board_pciid_enable *board = board_pciid_enables; const struct board_pciid_enable *partmatch = NULL; @@ -2144,8 +2143,7 @@ * Match boards on PCI IDs and subsystem IDs. * Second set of IDs can be main only or missing completely. */ -const static struct board_pciid_enable *board_match_pci_card_ids( - enum board_match_phase phase) +const static struct board_pciid_enable *board_match_pci_card_ids(enum board_match_phase phase) { const struct board_pciid_enable *board = board_pciid_enables; -- http://www.hailfinger.org/

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[commit] r1424 - trunk
by repository service 31 Aug '11

31 Aug '11

Author: hailfinger Date: Wed Aug 31 18:19:50 2011 New Revision: 1424 URL: http://flashrom.org/trac/flashrom/changeset/1424 Log: Shorten some board enable related function names Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/flashrom.c trunk/print.c trunk/print_wiki.c trunk/programmer.h Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sat Aug 27 23:19:56 2011 (r1423) +++ trunk/board_enable.c Wed Aug 31 18:19:50 2011 (r1424) @@ -1974,7 +1974,7 @@ */ /* Please keep this list alphabetically ordered by vendor/board name. */ -const struct board_pciid_enable board_pciid_enables[] = { +const struct board_match board_matches[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */ #if defined(__i386__) || defined(__x86_64__) @@ -2102,11 +2102,11 @@ * Match boards on coreboot table gathered vendor and part name. * Require main PCI IDs to match too as extra safety. */ -static const struct board_pciid_enable *board_match_coreboot_name( - const char *vendor, const char *part) +static const struct board_match *board_match_cbname(const char *vendor, + const char *part) { - const struct board_pciid_enable *board = board_pciid_enables; - const struct board_pciid_enable *partmatch = NULL; + const struct board_match *board = board_matches; + const struct board_match *partmatch = NULL; for (; board->vendor_name; board++) { if (vendor && (!board->lb_vendor @@ -2153,12 +2153,11 @@ /* * Match boards on PCI IDs and subsystem IDs. - * Second set of IDs can be main only or missing completely. + * Second set of IDs can be either main+subsystem IDs, main IDs or no IDs. */ -const static struct board_pciid_enable *board_match_pci_card_ids( - enum board_match_phase phase) +const static struct board_match *board_match_pci_ids(enum board_match_phase phase) { - const struct board_pciid_enable *board = board_pciid_enables; + const struct board_match *board = board_matches; for (; board->vendor_name; board++) { if ((!board->first_card_vendor || !board->first_card_device) && @@ -2204,7 +2203,7 @@ return NULL; } -static int unsafe_board_handler(const struct board_pciid_enable *board) +static int unsafe_board_handler(const struct board_match *board) { if (!board) return 1; @@ -2231,9 +2230,9 @@ /* FIXME: Should this be identical to board_flash_enable? */ static int board_handle_phase(enum board_match_phase phase) { - const struct board_pciid_enable *board = NULL; + const struct board_match *board = NULL; - board = board_match_pci_card_ids(phase); + board = board_match_pci_ids(phase); if (unsafe_board_handler(board)) board = NULL; @@ -2262,14 +2261,14 @@ int board_flash_enable(const char *vendor, const char *part) { - const struct board_pciid_enable *board = NULL; + const struct board_match *board = NULL; int ret = 0; if (part) - board = board_match_coreboot_name(vendor, part); + board = board_match_cbname(vendor, part); if (!board) - board = board_match_pci_card_ids(P3); + board = board_match_pci_ids(P3); if (unsafe_board_handler(board)) board = NULL; Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sat Aug 27 23:19:56 2011 (r1423) +++ trunk/flashrom.c Wed Aug 31 18:19:50 2011 (r1424) @@ -1731,7 +1731,7 @@ msg_gerr("Chipset enables table does not exist!\n"); ret = 1; } - if (board_pciid_enables == NULL) { + if (board_matches == NULL) { msg_gerr("Board enables table does not exist!\n"); ret = 1; } Modified: trunk/print.c ============================================================================== --- trunk/print.c Sat Aug 27 23:19:56 2011 (r1423) +++ trunk/print.c Wed Aug 31 18:19:50 2011 (r1424) @@ -203,7 +203,7 @@ const char *devicetype) { int i, boardcount_good = 0, boardcount_bad = 0; - const struct board_pciid_enable *e = board_pciid_enables; + const struct board_match *e = board_matches; const struct board_info *b = boards; int maxvendorlen = strlen("Vendor") + 1; int maxboardlen = strlen("Board") + 1; @@ -241,7 +241,7 @@ msg_ginfo(" "); msg_ginfo((b->working) ? "OK " : "BAD "); - for (e = board_pciid_enables; e->vendor_name != NULL; e++) { + for (e = board_matches; e->vendor_name != NULL; e++) { if (strcmp(e->vendor_name, b->vendor) || strcmp(e->board_name, b->name)) continue; Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Sat Aug 27 23:19:56 2011 (r1423) +++ trunk/print_wiki.c Wed Aug 31 18:19:50 2011 (r1424) @@ -125,7 +125,7 @@ int num_notes = 0; char *notes = calloc(1, 1); char tmp[900 + 1]; - const struct board_pciid_enable *b = board_pciid_enables; + const struct board_match *b = board_matches; for (i = 0; boards[i].vendor != NULL; i++) { if (boards[i].working) Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sat Aug 27 23:19:56 2011 (r1423) +++ trunk/programmer.h Wed Aug 31 18:19:50 2011 (r1424) @@ -158,7 +158,7 @@ P3 }; -struct board_pciid_enable { +struct board_match { /* Any device, but make it sensible, like the ISA bridge. */ uint16_t first_vendor; uint16_t first_device; @@ -190,7 +190,7 @@ int (*enable) (void); /* May be NULL. */ }; -extern const struct board_pciid_enable board_pciid_enables[]; +extern const struct board_match board_matches[]; struct board_info { const char *vendor;

1 0

[PATCH] add SPI interface support for Tunnel Creek chipset
by Feldschmid, Ingo 30 Aug '11

30 Aug '11

The Intel Tunnel Creek chipset supports both an SPI and an LPC bus. Set chipset table entry for Tunnel Creek to new function "enable_flash_tunnelcreek", which will read the hardware straps and return support for the bus that has been used for booting. This function uses "ich_init_spi" with ich_generation set to 7 for initializing the SPI bus if necessary. SPI functionality tested on actual hardware (see attached file flashrom.log), Tunnel Creek LPC interface not tested yet (missing hardware for that). Signed-off-by: Ingo Feldschmid <ifel(a)msc-ge.com> <<tunnelcreek.patch>> <<flashrom.log>> Es gelten unsere Allgemeinen Leistungsbedingungen die unter http://www.msc-ge.com/alb abrufbar sind. Our standard terms and conditions apply which are available under http://www.msc-ge.com/alb . MSC Vertriebs GmbH Sitz der Gesellschaft: Industriestrasse 16, 76297 Stutensee Handelsregister: Mannheim, HRB Nr. 10 3631 Geschaftsfuhrung: Manfred Schwarztrauber, Lothar Kummerlin, Rudiger Kuhn, Silvano Geissler Umsatzsteuer ID Nr.: DE 143 585 507 WEEE Reg. Nr. : DE 31011852 Gleichmann & Co. Electronics GmbH Sitz der Gesellschaft: Schraderstrasse 44, 67227 Frankenthal Handelsregister: Ludwigshafen, HRB Nr. 21305 Geschaftsfuhrung: Manfred Schwarztrauber, Thomas Klein Umsatzsteuer ID Nr. : DE 148 421 329 WEEE Reg. Nr.: DE 72277043 Diese E-Mail enthalt vertrauliche und/ oder rechtlich geschutzte Informationen. Wenn Sie nicht der beabsichtigte Empfanger sind, informieren Sie bitte sofort den Absender und loschen Sie diese E-Mail. The information contained in this message is confidential and/ or protected by law. If you are not the intended recipient, please contact the sender and delete this message.

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Re: [flashrom] alix2d13, AMD CS5536: problem report with v0.9.2-r1141
by Paul Menzel 30 Aug '11

30 Aug '11

Dear Bill, thank you for report. Am Montag, den 29.08.2011, 14:36 -0700 schrieb Bill Larson: > Here is the message I get when running flashrom. > > root@voyage:~# flashrom > flashrom v0.9.2-r1141 on Linux 2.6.33.7-rt29-voyage (i586), built with libpci 3. > 1.7, GCC 4.4.5 20100728 (prerelease), little endian > flashrom is free software, get the source code at http://www.flashrom.org Please try a newer version like 0.9.4 or directly from SVN [1]. > Calibrating delay loop... OK. > No coreboot table found. > sh: dmidecode: not found > dmidecode execution unsucessfull - continuing without DMI info > Found chipset "AMD CS5536", enabling flash write... OK. > WARNING: unexpected second chipset match: "AMD CS5536" > ignoring, please report lspci and board URL to flashrom(a)flashrom.org! > This chipset supports the following protocols: Non-SPI. > Found chip "AMIC A49LF040A" (512 KB, LPC) at physical address 0xfff80000. > No operations were specified. > > I'm running it on a PC Engines alix2d13 board. > > http://pcengines.ch/alix2d13.htm > > And the lspci results > > 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host > Bridge (rev 33) > 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX A > ES Security Block > 00:09.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) > > 00:0a.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) > > 00:0b.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) > > 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (r > ev 03) > 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE > (rev 01) > 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OH > C (rev 02) > 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EH > C (rev 02) Please turn off line wrapping when inserting stuff. Thanks, Paul [1] http://flashrom.org/Downloads

1 0

problem report
by Bill Larson 29 Aug '11

29 Aug '11

Here is the message I get when running flashrom. root@voyage:~# flashrom flashrom v0.9.2-r1141 on Linux 2.6.33.7-rt29-voyage (i586), built with libpci 3. 1.7, GCC 4.4.5 20100728 (prerelease), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. No coreboot table found. sh: dmidecode: not found dmidecode execution unsucessfull - continuing without DMI info Found chipset "AMD CS5536", enabling flash write... OK. WARNING: unexpected second chipset match: "AMD CS5536" ignoring, please report lspci and board URL to flashrom(a)flashrom.org! This chipset supports the following protocols: Non-SPI. Found chip "AMIC A49LF040A" (512 KB, LPC) at physical address 0xfff80000. No operations were specified. I'm running it on a PC Engines alix2d13 board. http://pcengines.ch/alix2d13.htm And the lspci results 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 33) 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX A ES Security Block 00:09.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) 00:0a.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) 00:0b.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (r ev 03) 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01) 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OH C (rev 02) 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EH C (rev 02)

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Re: [flashrom] report for Intel QM67 | Winbond W25Q64 - layout patches
by Stefan Tauner 29 Aug '11

29 Aug '11

On Fri, 26 Aug 2011 11:25:27 +0200 "Frei, Thomas (GE Germany)" <Thomas.Frei(a)ge.com> wrote: > Hi, > > Now I loaded the Revision 1421 from SVN repository, patched it and tried to compile - nope :-( > > Output of GCC: > ---snip--- > Checking for a C compiler... found. > ARCH is "x86" > Checking for libpci headers... found. > Checking if libpci is present and sufficient... yes. > Checking for FTDI support... not found. > Checking for utsname support... found. > cc -MMD -Os -Wall -Wshadow -Werror -D'CONFIG_INTERNAL=1' -D'CONFIG_SERPROG=1' -D'CONFIG_RAYER_SPI=1' -D'CONFIG_BITBANG_SPI=1' -D'CONFIG_NIC3COM=1' -D'CONFIG_GFXNVIDIA=1' -D'CONFIG_SATASII=1' -D'CONFIG_DUMMY=1' -D'CONFIG_DRKAISER=1' -D'CONFIG_NICREALTEK=1' -D'CONFIG_NICINTEL=1' -D'CONFIG_NICINTEL_SPI=1' -D'CONFIG_OGP_SPI=1' -D'CONFIG_BUSPIRATE_SPI=1' -D'CONFIG_SATAMV=1' -D'NEED_PCI=1' -D'HAVE_UTSNAME=1' -D'FLASHROM_VERSION="0.9.4-r1421"' -o layout.o -c layout.c > layout.c:43:20: error: expected â€˜=â€™, â€˜,â€™, â€˜;â€™, â€˜asmâ€™ or â€˜__attribute__â€™ before â€˜rom_entriesâ€™ > layout.c: In function â€˜read_romlayoutâ€™: > layout.c:161:50: error: â€˜rom_entriesâ€™ undeclared (first use in this function) > layout.c:161:50: note: each undeclared identifier is reported only once for each function it appears in > layout.c: At top level: > layout.c:214:12: error: static declaration of â€˜find_romentryâ€™ follows non-static declaration > flash.h:256:5: note: previous declaration of â€˜find_romentryâ€™ was here > layout.c: In function â€˜find_romentryâ€™: > layout.c:230:15: error: â€˜rom_entriesâ€™ undeclared (first use in this function) > layout.c: At top level: > layout.c:279:13: error: expected â€˜=â€™, â€˜,â€™, â€˜;â€™, â€˜asmâ€™ or â€˜__attribute__â€™ before â€˜*â€™ token > layout.c:309:47: error: expected â€˜)â€™ before â€˜*â€™ token > layout.c: In function â€˜build_new_imageâ€™: > layout.c:355:2: error: â€˜romlayout_tâ€™ undeclared (first use in this function) > layout.c:355:15: error: â€˜entryâ€™ undeclared (first use in this function) > cc1: warnings being treated as errors > layout.c:368:3: error: implicit declaration of function â€˜get_next_included_romentryâ€™ > layout.c:381:3: error: implicit declaration of function â€˜read_content_from_fileâ€™ > make: *** [layout.o] Error 1 > ---snip--- > ??? > > Please help. > hello the output was probably mangled in the mail transfer, but besides that it certainly does not look as it should either. i have tried to reproduce the behavior by checking out r1421 and applying the patches i have sent you. after each application of a patch i have run make clean; make and got no errors whatsoever. please assure that you have a clean checkout of r1421 without any remains of previous trials etc. and that the patches apply cleanly. if they dont, you have either started with the wrong sources or something is broken. in that case please tell us the exact command sequence (and the outputs respectively) that leads to the error. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] flashrom works with H67 Chip
by Stefan Tauner 29 Aug '11

29 Aug '11

On Sat, 27 Aug 2011 23:39:18 -0500 Dr Lawrence M Fox <drfox(a)chicagovet.net> wrote: > carlina@FOXBOX:~/Downloads/DOS$ sudo flashrom -w SH67H000.114 > flashrom v0.9.4-r1395 on Linux 2.6.38-11-generic (x86_64), built with libpci > 3.1.7, GCC 4.5.2, little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > Found chipset "Intel H67". > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom(a)flashrom.org including a > verbose (-V) log. Thank you! > Enabling flash write... OK. > This chipset supports the following protocols: FWH, SPI. > Found Winbond flash chip "W25Q32" (4096 kB, SPI) at physical address > 0xffc00000. > Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. > Reading old flash chip contents... done. > Erasing and writing flash chip... Erase/write done. > Verifying flash... VERIFIED. Hello, Thanks for your report! I have marked the chipset as tested and will commit that later. > carlina@FOXBOX:~/Downloads/DOS$ sudo flashrom -V -w SH67H000.114 > flashrom v0.9.4-r1395 on Linux 2.6.38-11-generic (x86_64), built with libpci > 3.1.7, GCC 4.5.2, little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OS timer resolution is 1 usecs, 3360M loops per > second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 991 us, 10000 myus = > 9922 us, 4 myus = 4 us, OK. > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "Shuttle" > DMI string system-product-name: "SH67H3" > DMI string system-version: "1.0" > DMI string baseboard-manufacturer: "Shuttle" > DMI string baseboard-product-name: "FH67" > DMI string baseboard-version: "1.0" > DMI string chassis-type: "Desktop" I have also added your mainboard (FH67) used in your barebone to our list of supported boards, thank you. > Found ITE Super I/O, ID 0x8772 on port 0x2e > Found chipset "Intel H67" with PCI ID 8086:1c4a. > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom(a)flashrom.org including a > verbose (-V) log. Thank you! > Enabling flash write... > […] > Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 > 0x4016 > Chip status register is 00 > Found Winbond flash chip "W25Q32" (4096 kB, SPI) at physical address > 0xffc00000. > […] > Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xef, > id2 0x15 > Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. > Reading old flash chip contents... done. > Erasing and writing flash chip... Trying erase function 0... > 0x000000-0x000fff:S, 0x001000-0x001fff:S, 0x002000-0x002fff:S, > […] > 0x3ff000-0x3fffff:S all those :S tokens indicate that the erase+write cycle for this block was skipped, because the content of the flash chip was equal to the file. this is of course expected because you have written the same file just before. i just mention it because this makes this log less informative. writing it in verbose mode the first time, would have been better for us. not a big deal though at all. > Erase/write done. > Verifying flash... VERIFIED. > Restoring MMIO space at 0x7f3670ff48a0 > Restoring MMIO space at 0x7f3670ff489c > Restoring MMIO space at 0x7f3670ff4898 > Restoring MMIO space at 0x7f3670ff4896 > Restoring MMIO space at 0x7f3670ff4894 > Restoring PCI config space for 00:1f:0 reg 0xdc -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Testing nicintel with SB82558B
by Andrew Morgan 28 Aug '11

28 Aug '11

Probe and read work. Erase fails and write requires erase to test. The problems could be to do with the (soldered) flash chip requiring VPP to write. I haven't tested the hardware any further yet, but I thought you might like this log to show that it does work this much. :) I have two of these cards, this one has a soldered flash chip, the other has a socket. I haven't tested the socketed one yet... -- Andrew.

2 1

flashrom works with H67 Chip
by Dr Lawrence M Fox 28 Aug '11

28 Aug '11

carlina@FOXBOX:~/Downloads/DOS$ sudo flashrom -w SH67H000.114 flashrom v0.9.4-r1395 on Linux 2.6.38-11-generic (x86_64), built with libpci 3.1.7, GCC 4.5.2, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel H67". This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... OK. This chipset supports the following protocols: FWH, SPI. Found Winbond flash chip "W25Q32" (4096 kB, SPI) at physical address 0xffc00000. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. carlina@FOXBOX:~/Downloads/DOS$ sudo flashrom -V -w SH67H000.114 flashrom v0.9.4-r1395 on Linux 2.6.38-11-generic (x86_64), built with libpci 3.1.7, GCC 4.5.2, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 3360M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 991 us, 10000 myus = 9922 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Shuttle" DMI string system-product-name: "SH67H3" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "Shuttle" DMI string baseboard-product-name: "FH67" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8772 on port 0x2e Found chipset "Intel H67" with PCI ID 8086:1c4a. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 Root Complex Register Block address = 0xfed1c000 GCS = 0xc00: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x3 (LPC) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x6008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x003fffc0 (FADDR) 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 (FREG0: Flash Descriptor) 0x00000000-0x00000fff is read-write 0x58: 0x03ff0200 (FREG1: BIOS) 0x00200000-0x003fffff is read-write 0x5C: 0x01ff0001 (FREG2: Management Engine) 0x00001000-0x001fffff is read-write 0x60: 0x00000fff (FREG3: Gigabit Ethernet) Gigabit Ethernet region is unused. 0x64: 0x00000fff (FREG4: Platform Data) Platform Data region is unused. 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0x84 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf87f10 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=0 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x0000019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xD0: 0x00000000 (FPB) Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done preop0=0x06, preop1=0x50 op[0]=0x02, 3, 0 op[1]=0x03, 2, 0 op[2]=0xd8, 3, 0 op[3]=0x05, 0, 0 op[4]=0x90, 2, 0 op[5]=0x01, 1, 0 op[6]=0x9f, 0, 0 op[7]=0xc7, 1, 0 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. Super I/O ID 0x8772 is not on the list of flash capable controllers. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x61, id2 0x12, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x24, id2 0x22, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x61, id2 0x12, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25LF040A.RES, 512 kB: program_opcodes: preop=5006 optype=462b opmenu=05ab0302c79f0190 on-the-fly OPCODE (0xAB) re-programmed, op-pos=2 probe_spi_res2: id1 0x15, id2 0x15 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x24, id2 0x22, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x61, id2 0x12, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x61, id2 0x12, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x61, id2 0x12, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x61, id2 0x12, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x24, id2 0x22, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x61, id2 0x12, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Chip status register is 00 Found Winbond flash chip "W25Q32" (4096 kB, SPI) at physical address 0xffc00000. Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x24, id2 0x22, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x61, id2 0x12, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xef, id2 0x15 Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:S, 0x001000-0x001fff:S, 0x002000-0x002fff:S, 0x003000-0x003fff:S, 0x004000-0x004fff:S, 0x005000-0x005fff:S, 0x006000-0x006fff:S, 0x007000-0x007fff:S, 0x008000-0x008fff:S, 0x009000-0x009fff:S, 0x00a000-0x00afff:S, 0x00b000-0x00bfff:S, 0x00c000-0x00cfff:S, 0x00d000-0x00dfff:S, 0x00e000-0x00efff:S, 0x00f000-0x00ffff:S, 0x010000-0x010fff:S, 0x011000-0x011fff:S, 0x012000-0x012fff:S, 0x013000-0x013fff:S, 0x014000-0x014fff:S, 0x015000-0x015fff:S, 0x016000-0x016fff:S, 0x017000-0x017fff:S, 0x018000-0x018fff:S, 0x019000-0x019fff:S, 0x01a000-0x01afff:S, 0x01b000-0x01bfff:S, 0x01c000-0x01cfff:S, 0x01d000-0x01dfff:S, 0x01e000-0x01efff:S, 0x01f000-0x01ffff:S, 0x020000-0x020fff:S, 0x021000-0x021fff:S, 0x022000-0x022fff:S, 0x023000-0x023fff:S, 0x024000-0x024fff:S, 0x025000-0x025fff:S, 0x026000-0x026fff:S, 0x027000-0x027fff:S, 0x028000-0x028fff:S, 0x029000-0x029fff:S, 0x02a000-0x02afff:S, 0x02b000-0x02bfff:S, 0x02c000-0x02cfff:S, 0x02d000-0x02dfff:S, 0x02e000-0x02efff:S, 0x02f000-0x02ffff:S, 0x030000-0x030fff:S, 0x031000-0x031fff:S, 0x032000-0x032fff:S, 0x033000-0x033fff:S, 0x034000-0x034fff:S, 0x035000-0x035fff:S, 0x036000-0x036fff:S, 0x037000-0x037fff:S, 0x038000-0x038fff:S, 0x039000-0x039fff:S, 0x03a000-0x03afff:S, 0x03b000-0x03bfff:S, 0x03c000-0x03cfff:S, 0x03d000-0x03dfff:S, 0x03e000-0x03efff:S, 0x03f000-0x03ffff:S, 0x040000-0x040fff:S, 0x041000-0x041fff:S, 0x042000-0x042fff:S, 0x043000-0x043fff:S, 0x044000-0x044fff:S, 0x045000-0x045fff:S, 0x046000-0x046fff:S, 0x047000-0x047fff:S, 0x048000-0x048fff:S, 0x049000-0x049fff:S, 0x04a000-0x04afff:S, 0x04b000-0x04bfff:S, 0x04c000-0x04cfff:S, 0x04d000-0x04dfff:S, 0x04e000-0x04efff:S, 0x04f000-0x04ffff:S, 0x050000-0x050fff:S, 0x051000-0x051fff:S, 0x052000-0x052fff:S, 0x053000-0x053fff:S, 0x054000-0x054fff:S, 0x055000-0x055fff:S, 0x056000-0x056fff:S, 0x057000-0x057fff:S, 0x058000-0x058fff:S, 0x059000-0x059fff:S, 0x05a000-0x05afff:S, 0x05b000-0x05bfff:S, 0x05c000-0x05cfff:S, 0x05d000-0x05dfff:S, 0x05e000-0x05efff:S, 0x05f000-0x05ffff:S, 0x060000-0x060fff:S, 0x061000-0x061fff:S, 0x062000-0x062fff:S, 0x063000-0x063fff:S, 0x064000-0x064fff:S, 0x065000-0x065fff:S, 0x066000-0x066fff:S, 0x067000-0x067fff:S, 0x068000-0x068fff:S, 0x069000-0x069fff:S, 0x06a000-0x06afff:S, 0x06b000-0x06bfff:S, 0x06c000-0x06cfff:S, 0x06d000-0x06dfff:S, 0x06e000-0x06efff:S, 0x06f000-0x06ffff:S, 0x070000-0x070fff:S, 0x071000-0x071fff:S, 0x072000-0x072fff:S, 0x073000-0x073fff:S, 0x074000-0x074fff:S, 0x075000-0x075fff:S, 0x076000-0x076fff:S, 0x077000-0x077fff:S, 0x078000-0x078fff:S, 0x079000-0x079fff:S, 0x07a000-0x07afff:S, 0x07b000-0x07bfff:S, 0x07c000-0x07cfff:S, 0x07d000-0x07dfff:S, 0x07e000-0x07efff:S, 0x07f000-0x07ffff:S, 0x080000-0x080fff:S, 0x081000-0x081fff:S, 0x082000-0x082fff:S, 0x083000-0x083fff:S, 0x084000-0x084fff:S, 0x085000-0x085fff:S, 0x086000-0x086fff:S, 0x087000-0x087fff:S, 0x088000-0x088fff:S, 0x089000-0x089fff:S, 0x08a000-0x08afff:S, 0x08b000-0x08bfff:S, 0x08c000-0x08cfff:S, 0x08d000-0x08dfff:S, 0x08e000-0x08efff:S, 0x08f000-0x08ffff:S, 0x090000-0x090fff:S, 0x091000-0x091fff:S, 0x092000-0x092fff:S, 0x093000-0x093fff:S, 0x094000-0x094fff:S, 0x095000-0x095fff:S, 0x096000-0x096fff:S, 0x097000-0x097fff:S, 0x098000-0x098fff:S, 0x099000-0x099fff:S, 0x09a000-0x09afff:S, 0x09b000-0x09bfff:S, 0x09c000-0x09cfff:S, 0x09d000-0x09dfff:S, 0x09e000-0x09efff:S, 0x09f000-0x09ffff:S, 0x0a0000-0x0a0fff:S, 0x0a1000-0x0a1fff:S, 0x0a2000-0x0a2fff:S, 0x0a3000-0x0a3fff:S, 0x0a4000-0x0a4fff:S, 0x0a5000-0x0a5fff:S, 0x0a6000-0x0a6fff:S, 0x0a7000-0x0a7fff:S, 0x0a8000-0x0a8fff:S, 0x0a9000-0x0a9fff:S, 0x0aa000-0x0aafff:S, 0x0ab000-0x0abfff:S, 0x0ac000-0x0acfff:S, 0x0ad000-0x0adfff:S, 0x0ae000-0x0aefff:S, 0x0af000-0x0affff:S, 0x0b0000-0x0b0fff:S, 0x0b1000-0x0b1fff:S, 0x0b2000-0x0b2fff:S, 0x0b3000-0x0b3fff:S, 0x0b4000-0x0b4fff:S, 0x0b5000-0x0b5fff:S, 0x0b6000-0x0b6fff:S, 0x0b7000-0x0b7fff:S, 0x0b8000-0x0b8fff:S, 0x0b9000-0x0b9fff:S, 0x0ba000-0x0bafff:S, 0x0bb000-0x0bbfff:S, 0x0bc000-0x0bcfff:S, 0x0bd000-0x0bdfff:S, 0x0be000-0x0befff:S, 0x0bf000-0x0bffff:S, 0x0c0000-0x0c0fff:S, 0x0c1000-0x0c1fff:S, 0x0c2000-0x0c2fff:S, 0x0c3000-0x0c3fff:S, 0x0c4000-0x0c4fff:S, 0x0c5000-0x0c5fff:S, 0x0c6000-0x0c6fff:S, 0x0c7000-0x0c7fff:S, 0x0c8000-0x0c8fff:S, 0x0c9000-0x0c9fff:S, 0x0ca000-0x0cafff:S, 0x0cb000-0x0cbfff:S, 0x0cc000-0x0ccfff:S, 0x0cd000-0x0cdfff:S, 0x0ce000-0x0cefff:S, 0x0cf000-0x0cffff:S, 0x0d0000-0x0d0fff:S, 0x0d1000-0x0d1fff:S, 0x0d2000-0x0d2fff:S, 0x0d3000-0x0d3fff:S, 0x0d4000-0x0d4fff:S, 0x0d5000-0x0d5fff:S, 0x0d6000-0x0d6fff:S, 0x0d7000-0x0d7fff:S, 0x0d8000-0x0d8fff:S, 0x0d9000-0x0d9fff:S, 0x0da000-0x0dafff:S, 0x0db000-0x0dbfff:S, 0x0dc000-0x0dcfff:S, 0x0dd000-0x0ddfff:S, 0x0de000-0x0defff:S, 0x0df000-0x0dffff:S, 0x0e0000-0x0e0fff:S, 0x0e1000-0x0e1fff:S, 0x0e2000-0x0e2fff:S, 0x0e3000-0x0e3fff:S, 0x0e4000-0x0e4fff:S, 0x0e5000-0x0e5fff:S, 0x0e6000-0x0e6fff:S, 0x0e7000-0x0e7fff:S, 0x0e8000-0x0e8fff:S, 0x0e9000-0x0e9fff:S, 0x0ea000-0x0eafff:S, 0x0eb000-0x0ebfff:S, 0x0ec000-0x0ecfff:S, 0x0ed000-0x0edfff:S, 0x0ee000-0x0eefff:S, 0x0ef000-0x0effff:S, 0x0f0000-0x0f0fff:S, 0x0f1000-0x0f1fff:S, 0x0f2000-0x0f2fff:S, 0x0f3000-0x0f3fff:S, 0x0f4000-0x0f4fff:S, 0x0f5000-0x0f5fff:S, 0x0f6000-0x0f6fff:S, 0x0f7000-0x0f7fff:S, 0x0f8000-0x0f8fff:S, 0x0f9000-0x0f9fff:S, 0x0fa000-0x0fafff:S, 0x0fb000-0x0fbfff:S, 0x0fc000-0x0fcfff:S, 0x0fd000-0x0fdfff:S, 0x0fe000-0x0fefff:S, 0x0ff000-0x0fffff:S, 0x100000-0x100fff:S, 0x101000-0x101fff:S, 0x102000-0x102fff:S, 0x103000-0x103fff:S, 0x104000-0x104fff:S, 0x105000-0x105fff:S, 0x106000-0x106fff:S, 0x107000-0x107fff:S, 0x108000-0x108fff:S, 0x109000-0x109fff:S, 0x10a000-0x10afff:S, 0x10b000-0x10bfff:S, 0x10c000-0x10cfff:S, 0x10d000-0x10dfff:S, 0x10e000-0x10efff:S, 0x10f000-0x10ffff:S, 0x110000-0x110fff:S, 0x111000-0x111fff:S, 0x112000-0x112fff:S, 0x113000-0x113fff:S, 0x114000-0x114fff:S, 0x115000-0x115fff:S, 0x116000-0x116fff:S, 0x117000-0x117fff:S, 0x118000-0x118fff:S, 0x119000-0x119fff:S, 0x11a000-0x11afff:S, 0x11b000-0x11bfff:S, 0x11c000-0x11cfff:S, 0x11d000-0x11dfff:S, 0x11e000-0x11efff:S, 0x11f000-0x11ffff:S, 0x120000-0x120fff:S, 0x121000-0x121fff:S, 0x122000-0x122fff:S, 0x123000-0x123fff:S, 0x124000-0x124fff:S, 0x125000-0x125fff:S, 0x126000-0x126fff:S, 0x127000-0x127fff:S, 0x128000-0x128fff:S, 0x129000-0x129fff:S, 0x12a000-0x12afff:S, 0x12b000-0x12bfff:S, 0x12c000-0x12cfff:S, 0x12d000-0x12dfff:S, 0x12e000-0x12efff:S, 0x12f000-0x12ffff:S, 0x130000-0x130fff:S, 0x131000-0x131fff:S, 0x132000-0x132fff:S, 0x133000-0x133fff:S, 0x134000-0x134fff:S, 0x135000-0x135fff:S, 0x136000-0x136fff:S, 0x137000-0x137fff:S, 0x138000-0x138fff:S, 0x139000-0x139fff:S, 0x13a000-0x13afff:S, 0x13b000-0x13bfff:S, 0x13c000-0x13cfff:S, 0x13d000-0x13dfff:S, 0x13e000-0x13efff:S, 0x13f000-0x13ffff:S, 0x140000-0x140fff:S, 0x141000-0x141fff:S, 0x142000-0x142fff:S, 0x143000-0x143fff:S, 0x144000-0x144fff:S, 0x145000-0x145fff:S, 0x146000-0x146fff:S, 0x147000-0x147fff:S, 0x148000-0x148fff:S, 0x149000-0x149fff:S, 0x14a000-0x14afff:S, 0x14b000-0x14bfff:S, 0x14c000-0x14cfff:S, 0x14d000-0x14dfff:S, 0x14e000-0x14efff:S, 0x14f000-0x14ffff:S, 0x150000-0x150fff:S, 0x151000-0x151fff:S, 0x152000-0x152fff:S, 0x153000-0x153fff:S, 0x154000-0x154fff:S, 0x155000-0x155fff:S, 0x156000-0x156fff:S, 0x157000-0x157fff:S, 0x158000-0x158fff:S, 0x159000-0x159fff:S, 0x15a000-0x15afff:S, 0x15b000-0x15bfff:S, 0x15c000-0x15cfff:S, 0x15d000-0x15dfff:S, 0x15e000-0x15efff:S, 0x15f000-0x15ffff:S, 0x160000-0x160fff:S, 0x161000-0x161fff:S, 0x162000-0x162fff:S, 0x163000-0x163fff:S, 0x164000-0x164fff:S, 0x165000-0x165fff:S, 0x166000-0x166fff:S, 0x167000-0x167fff:S, 0x168000-0x168fff:S, 0x169000-0x169fff:S, 0x16a000-0x16afff:S, 0x16b000-0x16bfff:S, 0x16c000-0x16cfff:S, 0x16d000-0x16dfff:S, 0x16e000-0x16efff:S, 0x16f000-0x16ffff:S, 0x170000-0x170fff:S, 0x171000-0x171fff:S, 0x172000-0x172fff:S, 0x173000-0x173fff:S, 0x174000-0x174fff:S, 0x175000-0x175fff:S, 0x176000-0x176fff:S, 0x177000-0x177fff:S, 0x178000-0x178fff:S, 0x179000-0x179fff:S, 0x17a000-0x17afff:S, 0x17b000-0x17bfff:S, 0x17c000-0x17cfff:S, 0x17d000-0x17dfff:S, 0x17e000-0x17efff:S, 0x17f000-0x17ffff:S, 0x180000-0x180fff:S, 0x181000-0x181fff:S, 0x182000-0x182fff:S, 0x183000-0x183fff:S, 0x184000-0x184fff:S, 0x185000-0x185fff:S, 0x186000-0x186fff:S, 0x187000-0x187fff:S, 0x188000-0x188fff:S, 0x189000-0x189fff:S, 0x18a000-0x18afff:S, 0x18b000-0x18bfff:S, 0x18c000-0x18cfff:S, 0x18d000-0x18dfff:S, 0x18e000-0x18efff:S, 0x18f000-0x18ffff:S, 0x190000-0x190fff:S, 0x191000-0x191fff:S, 0x192000-0x192fff:S, 0x193000-0x193fff:S, 0x194000-0x194fff:S, 0x195000-0x195fff:S, 0x196000-0x196fff:S, 0x197000-0x197fff:S, 0x198000-0x198fff:S, 0x199000-0x199fff:S, 0x19a000-0x19afff:S, 0x19b000-0x19bfff:S, 0x19c000-0x19cfff:S, 0x19d000-0x19dfff:S, 0x19e000-0x19efff:S, 0x19f000-0x19ffff:S, 0x1a0000-0x1a0fff:S, 0x1a1000-0x1a1fff:S, 0x1a2000-0x1a2fff:S, 0x1a3000-0x1a3fff:S, 0x1a4000-0x1a4fff:S, 0x1a5000-0x1a5fff:S, 0x1a6000-0x1a6fff:S, 0x1a7000-0x1a7fff:S, 0x1a8000-0x1a8fff:S, 0x1a9000-0x1a9fff:S, 0x1aa000-0x1aafff:S, 0x1ab000-0x1abfff:S, 0x1ac000-0x1acfff:S, 0x1ad000-0x1adfff:S, 0x1ae000-0x1aefff:S, 0x1af000-0x1affff:S, 0x1b0000-0x1b0fff:S, 0x1b1000-0x1b1fff:S, 0x1b2000-0x1b2fff:S, 0x1b3000-0x1b3fff:S, 0x1b4000-0x1b4fff:S, 0x1b5000-0x1b5fff:S, 0x1b6000-0x1b6fff:S, 0x1b7000-0x1b7fff:S, 0x1b8000-0x1b8fff:S, 0x1b9000-0x1b9fff:S, 0x1ba000-0x1bafff:S, 0x1bb000-0x1bbfff:S, 0x1bc000-0x1bcfff:S, 0x1bd000-0x1bdfff:S, 0x1be000-0x1befff:S, 0x1bf000-0x1bffff:S, 0x1c0000-0x1c0fff:S, 0x1c1000-0x1c1fff:S, 0x1c2000-0x1c2fff:S, 0x1c3000-0x1c3fff:S, 0x1c4000-0x1c4fff:S, 0x1c5000-0x1c5fff:S, 0x1c6000-0x1c6fff:S, 0x1c7000-0x1c7fff:S, 0x1c8000-0x1c8fff:S, 0x1c9000-0x1c9fff:S, 0x1ca000-0x1cafff:S, 0x1cb000-0x1cbfff:S, 0x1cc000-0x1ccfff:S, 0x1cd000-0x1cdfff:S, 0x1ce000-0x1cefff:S, 0x1cf000-0x1cffff:S, 0x1d0000-0x1d0fff:S, 0x1d1000-0x1d1fff:S, 0x1d2000-0x1d2fff:S, 0x1d3000-0x1d3fff:S, 0x1d4000-0x1d4fff:S, 0x1d5000-0x1d5fff:S, 0x1d6000-0x1d6fff:S, 0x1d7000-0x1d7fff:S, 0x1d8000-0x1d8fff:S, 0x1d9000-0x1d9fff:S, 0x1da000-0x1dafff:S, 0x1db000-0x1dbfff:S, 0x1dc000-0x1dcfff:S, 0x1dd000-0x1ddfff:S, 0x1de000-0x1defff:S, 0x1df000-0x1dffff:S, 0x1e0000-0x1e0fff:S, 0x1e1000-0x1e1fff:S, 0x1e2000-0x1e2fff:S, 0x1e3000-0x1e3fff:S, 0x1e4000-0x1e4fff:S, 0x1e5000-0x1e5fff:S, 0x1e6000-0x1e6fff:S, 0x1e7000-0x1e7fff:S, 0x1e8000-0x1e8fff:S, 0x1e9000-0x1e9fff:S, 0x1ea000-0x1eafff:S, 0x1eb000-0x1ebfff:S, 0x1ec000-0x1ecfff:S, 0x1ed000-0x1edfff:S, 0x1ee000-0x1eefff:S, 0x1ef000-0x1effff:S, 0x1f0000-0x1f0fff:S, 0x1f1000-0x1f1fff:S, 0x1f2000-0x1f2fff:S, 0x1f3000-0x1f3fff:S, 0x1f4000-0x1f4fff:S, 0x1f5000-0x1f5fff:S, 0x1f6000-0x1f6fff:S, 0x1f7000-0x1f7fff:S, 0x1f8000-0x1f8fff:S, 0x1f9000-0x1f9fff:S, 0x1fa000-0x1fafff:S, 0x1fb000-0x1fbfff:S, 0x1fc000-0x1fcfff:S, 0x1fd000-0x1fdfff:S, 0x1fe000-0x1fefff:S, 0x1ff000-0x1fffff:S, 0x200000-0x200fff:S, 0x201000-0x201fff:S, 0x202000-0x202fff:S, 0x203000-0x203fff:S, 0x204000-0x204fff:S, 0x205000-0x205fff:S, 0x206000-0x206fff:S, 0x207000-0x207fff:S, 0x208000-0x208fff:S, 0x209000-0x209fff:S, 0x20a000-0x20afff:S, 0x20b000-0x20bfff:S, 0x20c000-0x20cfff:S, 0x20d000-0x20dfff:S, 0x20e000-0x20efff:S, 0x20f000-0x20ffff:S, 0x210000-0x210fff:S, 0x211000-0x211fff:S, 0x212000-0x212fff:S, 0x213000-0x213fff:S, 0x214000-0x214fff:S, 0x215000-0x215fff:S, 0x216000-0x216fff:S, 0x217000-0x217fff:S, 0x218000-0x218fff:S, 0x219000-0x219fff:S, 0x21a000-0x21afff:S, 0x21b000-0x21bfff:S, 0x21c000-0x21cfff:S, 0x21d000-0x21dfff:S, 0x21e000-0x21efff:S, 0x21f000-0x21ffff:S, 0x220000-0x220fff:S, 0x221000-0x221fff:S, 0x222000-0x222fff:S, 0x223000-0x223fff:S, 0x224000-0x224fff:S, 0x225000-0x225fff:S, 0x226000-0x226fff:S, 0x227000-0x227fff:S, 0x228000-0x228fff:S, 0x229000-0x229fff:S, 0x22a000-0x22afff:S, 0x22b000-0x22bfff:S, 0x22c000-0x22cfff:S, 0x22d000-0x22dfff:S, 0x22e000-0x22efff:S, 0x22f000-0x22ffff:S, 0x230000-0x230fff:S, 0x231000-0x231fff:S, 0x232000-0x232fff:S, 0x233000-0x233fff:S, 0x234000-0x234fff:S, 0x235000-0x235fff:S, 0x236000-0x236fff:S, 0x237000-0x237fff:S, 0x238000-0x238fff:S, 0x239000-0x239fff:S, 0x23a000-0x23afff:S, 0x23b000-0x23bfff:S, 0x23c000-0x23cfff:S, 0x23d000-0x23dfff:S, 0x23e000-0x23efff:S, 0x23f000-0x23ffff:S, 0x240000-0x240fff:S, 0x241000-0x241fff:S, 0x242000-0x242fff:S, 0x243000-0x243fff:S, 0x244000-0x244fff:S, 0x245000-0x245fff:S, 0x246000-0x246fff:S, 0x247000-0x247fff:S, 0x248000-0x248fff:S, 0x249000-0x249fff:S, 0x24a000-0x24afff:S, 0x24b000-0x24bfff:S, 0x24c000-0x24cfff:S, 0x24d000-0x24dfff:S, 0x24e000-0x24efff:S, 0x24f000-0x24ffff:S, 0x250000-0x250fff:S, 0x251000-0x251fff:S, 0x252000-0x252fff:S, 0x253000-0x253fff:S, 0x254000-0x254fff:S, 0x255000-0x255fff:S, 0x256000-0x256fff:S, 0x257000-0x257fff:S, 0x258000-0x258fff:S, 0x259000-0x259fff:S, 0x25a000-0x25afff:S, 0x25b000-0x25bfff:S, 0x25c000-0x25cfff:S, 0x25d000-0x25dfff:S, 0x25e000-0x25efff:S, 0x25f000-0x25ffff:S, 0x260000-0x260fff:S, 0x261000-0x261fff:S, 0x262000-0x262fff:S, 0x263000-0x263fff:S, 0x264000-0x264fff:S, 0x265000-0x265fff:S, 0x266000-0x266fff:S, 0x267000-0x267fff:S, 0x268000-0x268fff:S, 0x269000-0x269fff:S, 0x26a000-0x26afff:S, 0x26b000-0x26bfff:S, 0x26c000-0x26cfff:S, 0x26d000-0x26dfff:S, 0x26e000-0x26efff:S, 0x26f000-0x26ffff:S, 0x270000-0x270fff:S, 0x271000-0x271fff:S, 0x272000-0x272fff:S, 0x273000-0x273fff:S, 0x274000-0x274fff:S, 0x275000-0x275fff:S, 0x276000-0x276fff:S, 0x277000-0x277fff:S, 0x278000-0x278fff:S, 0x279000-0x279fff:S, 0x27a000-0x27afff:S, 0x27b000-0x27bfff:S, 0x27c000-0x27cfff:S, 0x27d000-0x27dfff:S, 0x27e000-0x27efff:S, 0x27f000-0x27ffff:S, 0x280000-0x280fff:S, 0x281000-0x281fff:S, 0x282000-0x282fff:S, 0x283000-0x283fff:S, 0x284000-0x284fff:S, 0x285000-0x285fff:S, 0x286000-0x286fff:S, 0x287000-0x287fff:S, 0x288000-0x288fff:S, 0x289000-0x289fff:S, 0x28a000-0x28afff:S, 0x28b000-0x28bfff:S, 0x28c000-0x28cfff:S, 0x28d000-0x28dfff:S, 0x28e000-0x28efff:S, 0x28f000-0x28ffff:S, 0x290000-0x290fff:S, 0x291000-0x291fff:S, 0x292000-0x292fff:S, 0x293000-0x293fff:S, 0x294000-0x294fff:S, 0x295000-0x295fff:S, 0x296000-0x296fff:S, 0x297000-0x297fff:S, 0x298000-0x298fff:S, 0x299000-0x299fff:S, 0x29a000-0x29afff:S, 0x29b000-0x29bfff:S, 0x29c000-0x29cfff:S, 0x29d000-0x29dfff:S, 0x29e000-0x29efff:S, 0x29f000-0x29ffff:S, 0x2a0000-0x2a0fff:S, 0x2a1000-0x2a1fff:S, 0x2a2000-0x2a2fff:S, 0x2a3000-0x2a3fff:S, 0x2a4000-0x2a4fff:S, 0x2a5000-0x2a5fff:S, 0x2a6000-0x2a6fff:S, 0x2a7000-0x2a7fff:S, 0x2a8000-0x2a8fff:S, 0x2a9000-0x2a9fff:S, 0x2aa000-0x2aafff:S, 0x2ab000-0x2abfff:S, 0x2ac000-0x2acfff:S, 0x2ad000-0x2adfff:S, 0x2ae000-0x2aefff:S, 0x2af000-0x2affff:S, 0x2b0000-0x2b0fff:S, 0x2b1000-0x2b1fff:S, 0x2b2000-0x2b2fff:S, 0x2b3000-0x2b3fff:S, 0x2b4000-0x2b4fff:S, 0x2b5000-0x2b5fff:S, 0x2b6000-0x2b6fff:S, 0x2b7000-0x2b7fff:S, 0x2b8000-0x2b8fff:S, 0x2b9000-0x2b9fff:S, 0x2ba000-0x2bafff:S, 0x2bb000-0x2bbfff:S, 0x2bc000-0x2bcfff:S, 0x2bd000-0x2bdfff:S, 0x2be000-0x2befff:S, 0x2bf000-0x2bffff:S, 0x2c0000-0x2c0fff:S, 0x2c1000-0x2c1fff:S, 0x2c2000-0x2c2fff:S, 0x2c3000-0x2c3fff:S, 0x2c4000-0x2c4fff:S, 0x2c5000-0x2c5fff:S, 0x2c6000-0x2c6fff:S, 0x2c7000-0x2c7fff:S, 0x2c8000-0x2c8fff:S, 0x2c9000-0x2c9fff:S, 0x2ca000-0x2cafff:S, 0x2cb000-0x2cbfff:S, 0x2cc000-0x2ccfff:S, 0x2cd000-0x2cdfff:S, 0x2ce000-0x2cefff:S, 0x2cf000-0x2cffff:S, 0x2d0000-0x2d0fff:S, 0x2d1000-0x2d1fff:S, 0x2d2000-0x2d2fff:S, 0x2d3000-0x2d3fff:S, 0x2d4000-0x2d4fff:S, 0x2d5000-0x2d5fff:S, 0x2d6000-0x2d6fff:S, 0x2d7000-0x2d7fff:S, 0x2d8000-0x2d8fff:S, 0x2d9000-0x2d9fff:S, 0x2da000-0x2dafff:S, 0x2db000-0x2dbfff:S, 0x2dc000-0x2dcfff:S, 0x2dd000-0x2ddfff:S, 0x2de000-0x2defff:S, 0x2df000-0x2dffff:S, 0x2e0000-0x2e0fff:S, 0x2e1000-0x2e1fff:S, 0x2e2000-0x2e2fff:S, 0x2e3000-0x2e3fff:S, 0x2e4000-0x2e4fff:S, 0x2e5000-0x2e5fff:S, 0x2e6000-0x2e6fff:S, 0x2e7000-0x2e7fff:S, 0x2e8000-0x2e8fff:S, 0x2e9000-0x2e9fff:S, 0x2ea000-0x2eafff:S, 0x2eb000-0x2ebfff:S, 0x2ec000-0x2ecfff:S, 0x2ed000-0x2edfff:S, 0x2ee000-0x2eefff:S, 0x2ef000-0x2effff:S, 0x2f0000-0x2f0fff:S, 0x2f1000-0x2f1fff:S, 0x2f2000-0x2f2fff:S, 0x2f3000-0x2f3fff:S, 0x2f4000-0x2f4fff:S, 0x2f5000-0x2f5fff:S, 0x2f6000-0x2f6fff:S, 0x2f7000-0x2f7fff:S, 0x2f8000-0x2f8fff:S, 0x2f9000-0x2f9fff:S, 0x2fa000-0x2fafff:S, 0x2fb000-0x2fbfff:S, 0x2fc000-0x2fcfff:S, 0x2fd000-0x2fdfff:S, 0x2fe000-0x2fefff:S, 0x2ff000-0x2fffff:S, 0x300000-0x300fff:S, 0x301000-0x301fff:S, 0x302000-0x302fff:S, 0x303000-0x303fff:S, 0x304000-0x304fff:S, 0x305000-0x305fff:S, 0x306000-0x306fff:S, 0x307000-0x307fff:S, 0x308000-0x308fff:S, 0x309000-0x309fff:S, 0x30a000-0x30afff:S, 0x30b000-0x30bfff:S, 0x30c000-0x30cfff:S, 0x30d000-0x30dfff:S, 0x30e000-0x30efff:S, 0x30f000-0x30ffff:S, 0x310000-0x310fff:S, 0x311000-0x311fff:S, 0x312000-0x312fff:S, 0x313000-0x313fff:S, 0x314000-0x314fff:S, 0x315000-0x315fff:S, 0x316000-0x316fff:S, 0x317000-0x317fff:S, 0x318000-0x318fff:S, 0x319000-0x319fff:S, 0x31a000-0x31afff:S, 0x31b000-0x31bfff:S, 0x31c000-0x31cfff:S, 0x31d000-0x31dfff:S, 0x31e000-0x31efff:S, 0x31f000-0x31ffff:S, 0x320000-0x320fff:S, 0x321000-0x321fff:S, 0x322000-0x322fff:S, 0x323000-0x323fff:S, 0x324000-0x324fff:S, 0x325000-0x325fff:S, 0x326000-0x326fff:S, 0x327000-0x327fff:S, 0x328000-0x328fff:S, 0x329000-0x329fff:S, 0x32a000-0x32afff:S, 0x32b000-0x32bfff:S, 0x32c000-0x32cfff:S, 0x32d000-0x32dfff:S, 0x32e000-0x32efff:S, 0x32f000-0x32ffff:S, 0x330000-0x330fff:S, 0x331000-0x331fff:S, 0x332000-0x332fff:S, 0x333000-0x333fff:S, 0x334000-0x334fff:S, 0x335000-0x335fff:S, 0x336000-0x336fff:S, 0x337000-0x337fff:S, 0x338000-0x338fff:S, 0x339000-0x339fff:S, 0x33a000-0x33afff:S, 0x33b000-0x33bfff:S, 0x33c000-0x33cfff:S, 0x33d000-0x33dfff:S, 0x33e000-0x33efff:S, 0x33f000-0x33ffff:S, 0x340000-0x340fff:S, 0x341000-0x341fff:S, 0x342000-0x342fff:S, 0x343000-0x343fff:S, 0x344000-0x344fff:S, 0x345000-0x345fff:S, 0x346000-0x346fff:S, 0x347000-0x347fff:S, 0x348000-0x348fff:S, 0x349000-0x349fff:S, 0x34a000-0x34afff:S, 0x34b000-0x34bfff:S, 0x34c000-0x34cfff:S, 0x34d000-0x34dfff:S, 0x34e000-0x34efff:S, 0x34f000-0x34ffff:S, 0x350000-0x350fff:S, 0x351000-0x351fff:S, 0x352000-0x352fff:S, 0x353000-0x353fff:S, 0x354000-0x354fff:S, 0x355000-0x355fff:S, 0x356000-0x356fff:S, 0x357000-0x357fff:S, 0x358000-0x358fff:S, 0x359000-0x359fff:S, 0x35a000-0x35afff:S, 0x35b000-0x35bfff:S, 0x35c000-0x35cfff:S, 0x35d000-0x35dfff:S, 0x35e000-0x35efff:S, 0x35f000-0x35ffff:S, 0x360000-0x360fff:S, 0x361000-0x361fff:S, 0x362000-0x362fff:S, 0x363000-0x363fff:S, 0x364000-0x364fff:S, 0x365000-0x365fff:S, 0x366000-0x366fff:S, 0x367000-0x367fff:S, 0x368000-0x368fff:S, 0x369000-0x369fff:S, 0x36a000-0x36afff:S, 0x36b000-0x36bfff:S, 0x36c000-0x36cfff:S, 0x36d000-0x36dfff:S, 0x36e000-0x36efff:S, 0x36f000-0x36ffff:S, 0x370000-0x370fff:S, 0x371000-0x371fff:S, 0x372000-0x372fff:S, 0x373000-0x373fff:S, 0x374000-0x374fff:S, 0x375000-0x375fff:S, 0x376000-0x376fff:S, 0x377000-0x377fff:S, 0x378000-0x378fff:S, 0x379000-0x379fff:S, 0x37a000-0x37afff:S, 0x37b000-0x37bfff:S, 0x37c000-0x37cfff:S, 0x37d000-0x37dfff:S, 0x37e000-0x37efff:S, 0x37f000-0x37ffff:S, 0x380000-0x380fff:S, 0x381000-0x381fff:S, 0x382000-0x382fff:S, 0x383000-0x383fff:S, 0x384000-0x384fff:S, 0x385000-0x385fff:S, 0x386000-0x386fff:S, 0x387000-0x387fff:S, 0x388000-0x388fff:S, 0x389000-0x389fff:S, 0x38a000-0x38afff:S, 0x38b000-0x38bfff:S, 0x38c000-0x38cfff:S, 0x38d000-0x38dfff:S, 0x38e000-0x38efff:S, 0x38f000-0x38ffff:S, 0x390000-0x390fff:S, 0x391000-0x391fff:S, 0x392000-0x392fff:S, 0x393000-0x393fff:S, 0x394000-0x394fff:S, 0x395000-0x395fff:S, 0x396000-0x396fff:S, 0x397000-0x397fff:S, 0x398000-0x398fff:S, 0x399000-0x399fff:S, 0x39a000-0x39afff:S, 0x39b000-0x39bfff:S, 0x39c000-0x39cfff:S, 0x39d000-0x39dfff:S, 0x39e000-0x39efff:S, 0x39f000-0x39ffff:S, 0x3a0000-0x3a0fff:S, 0x3a1000-0x3a1fff:S, 0x3a2000-0x3a2fff:S, 0x3a3000-0x3a3fff:S, 0x3a4000-0x3a4fff:S, 0x3a5000-0x3a5fff:S, 0x3a6000-0x3a6fff:S, 0x3a7000-0x3a7fff:S, 0x3a8000-0x3a8fff:S, 0x3a9000-0x3a9fff:S, 0x3aa000-0x3aafff:S, 0x3ab000-0x3abfff:S, 0x3ac000-0x3acfff:S, 0x3ad000-0x3adfff:S, 0x3ae000-0x3aefff:S, 0x3af000-0x3affff:S, 0x3b0000-0x3b0fff:S, 0x3b1000-0x3b1fff:S, 0x3b2000-0x3b2fff:S, 0x3b3000-0x3b3fff:S, 0x3b4000-0x3b4fff:S, 0x3b5000-0x3b5fff:S, 0x3b6000-0x3b6fff:S, 0x3b7000-0x3b7fff:S, 0x3b8000-0x3b8fff:S, 0x3b9000-0x3b9fff:S, 0x3ba000-0x3bafff:S, 0x3bb000-0x3bbfff:S, 0x3bc000-0x3bcfff:S, 0x3bd000-0x3bdfff:S, 0x3be000-0x3befff:S, 0x3bf000-0x3bffff:S, 0x3c0000-0x3c0fff:S, 0x3c1000-0x3c1fff:S, 0x3c2000-0x3c2fff:S, 0x3c3000-0x3c3fff:S, 0x3c4000-0x3c4fff:S, 0x3c5000-0x3c5fff:S, 0x3c6000-0x3c6fff:S, 0x3c7000-0x3c7fff:S, 0x3c8000-0x3c8fff:S, 0x3c9000-0x3c9fff:S, 0x3ca000-0x3cafff:S, 0x3cb000-0x3cbfff:S, 0x3cc000-0x3ccfff:S, 0x3cd000-0x3cdfff:S, 0x3ce000-0x3cefff:S, 0x3cf000-0x3cffff:S, 0x3d0000-0x3d0fff:S, 0x3d1000-0x3d1fff:S, 0x3d2000-0x3d2fff:S, 0x3d3000-0x3d3fff:S, 0x3d4000-0x3d4fff:S, 0x3d5000-0x3d5fff:S, 0x3d6000-0x3d6fff:S, 0x3d7000-0x3d7fff:S, 0x3d8000-0x3d8fff:S, 0x3d9000-0x3d9fff:S, 0x3da000-0x3dafff:S, 0x3db000-0x3dbfff:S, 0x3dc000-0x3dcfff:S, 0x3dd000-0x3ddfff:S, 0x3de000-0x3defff:S, 0x3df000-0x3dffff:S, 0x3e0000-0x3e0fff:S, 0x3e1000-0x3e1fff:S, 0x3e2000-0x3e2fff:S, 0x3e3000-0x3e3fff:S, 0x3e4000-0x3e4fff:S, 0x3e5000-0x3e5fff:S, 0x3e6000-0x3e6fff:S, 0x3e7000-0x3e7fff:S, 0x3e8000-0x3e8fff:S, 0x3e9000-0x3e9fff:S, 0x3ea000-0x3eafff:S, 0x3eb000-0x3ebfff:S, 0x3ec000-0x3ecfff:S, 0x3ed000-0x3edfff:S, 0x3ee000-0x3eefff:S, 0x3ef000-0x3effff:S, 0x3f0000-0x3f0fff:S, 0x3f1000-0x3f1fff:S, 0x3f2000-0x3f2fff:S, 0x3f3000-0x3f3fff:S, 0x3f4000-0x3f4fff:S, 0x3f5000-0x3f5fff:S, 0x3f6000-0x3f6fff:S, 0x3f7000-0x3f7fff:S, 0x3f8000-0x3f8fff:S, 0x3f9000-0x3f9fff:S, 0x3fa000-0x3fafff:S, 0x3fb000-0x3fbfff:S, 0x3fc000-0x3fcfff:S, 0x3fd000-0x3fdfff:S, 0x3fe000-0x3fefff:S, 0x3ff000-0x3fffff:S Erase/write done. Verifying flash... VERIFIED. Restoring MMIO space at 0x7f3670ff48a0 Restoring MMIO space at 0x7f3670ff489c Restoring MMIO space at 0x7f3670ff4898 Restoring MMIO space at 0x7f3670ff4896 Restoring MMIO space at 0x7f3670ff4894 Restoring PCI config space for 00:1f:0 reg 0xdc carlina@FOXBOX:~/Downloads/DOS$ ^C -- *Lawrence M Fox, DVM DABVP* *Certified in Canine & Feline Practice* River Grove (Chicago), IL USA

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Re: [flashrom] [PATCH] Fix printing of the Boot BIOS Straps on Intel chipsets
by Uwe Hermann 27 Aug '11

27 Aug '11

On Wed, Aug 17, 2011 at 06:17:45AM +0200, Stefan Tauner wrote: > defining all those arrays is not very elegant, but i think it is at least very > readable this way. Yep, pretty good solution IMHO, I would have done the same. > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> I cross-checked the datasheets and didn't spot any errors (ICH7-10, NM10, EP*, 5/6 series). ICH6 and lower, ESB*, and 3100 series and probably others don't have GCS, thus no need to list/mention them here (which you didn't). > + case 7: > + /* EP80579 may need further changes, but this is the least > + * intrusive way to get correct BOOT Strap printing without > + * changing the rest of its code path) */ ^ Missing full stop here. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

2 1

[commit] r1423 - trunk
by repository service 27 Aug '11

27 Aug '11

Author: stefanct Date: Sat Aug 27 23:19:56 2011 New Revision: 1423 URL: http://flashrom.org/trac/flashrom/changeset/1423 Log: Fix printing of the Boot BIOS Straps on Intel chipsets The meaning of the bits involved has changed several times in the past. This patch takes these changes into account and hence fixes the output of the pretty printing of GCS on all SPI-supported Intel chipsets that are not ICH7 or NM10 (the latter were unaffected, because the defaults were correct). This patch also allows to differentiate Ibex Peak and Cougar Point chipsets from the earlier chipset series (ICH10) by adding new wrapper functions that set "ich_generation" to 11 and 12 respectively. This should not change behavior outside of enable_flash_ich_dc_spi, because the code path for ich_generation >=9 is equal. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> --- defining all those arrays is not very elegant, but i think it is at least very readable this way. improvements are welcome! reviewers should have an eye on the codepaths for ich_generation >= 9. i did not spot a problem, but it should be checked again. alternatively we could just remove the pretty printing of GCS and just output the bits involved. i would like to keep the pch differentiation anyway though, because i feel it will become handy in the future. tested on my QS57-based thinkpad (probe + partial read) Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Fri Aug 26 23:11:41 2011 (r1422) +++ trunk/chipset_enable.c Sat Aug 27 23:19:56 2011 (r1423) @@ -440,11 +440,6 @@ return 0; } -#define ICH_STRAP_RSVD 0x00 -#define ICH_STRAP_SPI 0x01 -#define ICH_STRAP_PCI 0x02 -#define ICH_STRAP_LPC 0x03 - static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) { /* Do we really need no write enable? */ @@ -458,13 +453,39 @@ uint8_t bbs, buc; uint32_t tmp, gcs; void *rcrb; + const char *const *straps_names; - /* - * TODO: These names are incorrect for EP80579. For that, the solution - * would look like the commented line below. - */ - // static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" }; - static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" }; + static const char *const straps_names_EP80579[] = { "SPI", "reserved", "reserved", "LPC" }; + static const char *const straps_names_ich7_nm10[] = { "reserved", "SPI", "PCI", "LPC" }; + static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" }; + static const char *const straps_names_pch56[] = { "LPC", "reserved", "PCI", "SPI" }; + static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" }; + + switch (ich_generation) { + case 7: + /* EP80579 may need further changes, but this is the least + * intrusive way to get correct BOOT Strap printing without + * changing the rest of its code path). */ + if (strcmp(name, "EP80579") == 0) + straps_names = straps_names_EP80579; + else + straps_names = straps_names_ich7_nm10; + break; + case 8: + case 9: + case 10: + straps_names = straps_names_ich8910; + break; + case 11: + case 12: + straps_names = straps_names_pch56; + break; + default: + msg_gerr("%s: unknown ICH generation. Please report!\n", + __func__); + straps_names = straps_names_unknown; + break; + } /* Enable Flash Writes */ ret = enable_flash_ich_dc(dev, name); @@ -481,7 +502,7 @@ msg_pdbg("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); bbs = (gcs >> 10) & 0x3; - msg_pdbg("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); + msg_pdbg("Boot BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); buc = mmio_readb(rcrb + 0x3414); msg_pdbg("Top Swap : %s\n", @@ -491,11 +512,11 @@ * time. At least not with our current code. So we prevent searching * on ICH7 when the southbridge is strapped to LPC */ - buses_supported = BUS_FWH; if (ich_generation == 7) { - if (bbs == ICH_STRAP_LPC) { - /* No further SPI initialization required */ + if (bbs == 0x03) { + /* If strapped to LPC, no further SPI initialization is + * required. */ return ret; } else { /* Disable LPC/FWH if strapped to PCI or SPI */ @@ -532,6 +553,18 @@ return enable_flash_ich_dc_spi(dev, name, 10); } +/* Ibex Peak aka. 5 series & 3400 series */ +static int enable_flash_pch5(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_dc_spi(dev, name, 11); +} + +/* Cougar Point aka. 6 series & c200 series */ +static int enable_flash_pch6(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_dc_spi(dev, name, 12); +} + static int via_no_byte_merge(struct pci_dev *dev, const char *name) { uint8_t val; @@ -1159,21 +1192,21 @@ {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, - {0x8086, 0x1c44, NT, "Intel", "Z68", enable_flash_ich10}, - {0x8086, 0x1c46, NT, "Intel", "P67", enable_flash_ich10}, - {0x8086, 0x1c47, NT, "Intel", "UM67", enable_flash_ich10}, - {0x8086, 0x1c49, NT, "Intel", "HM65", enable_flash_ich10}, - {0x8086, 0x1c4a, NT, "Intel", "H67", enable_flash_ich10}, - {0x8086, 0x1c4b, NT, "Intel", "HM67", enable_flash_ich10}, - {0x8086, 0x1c4c, NT, "Intel", "Q65", enable_flash_ich10}, - {0x8086, 0x1c4d, NT, "Intel", "QS67", enable_flash_ich10}, - {0x8086, 0x1c4e, NT, "Intel", "Q67", enable_flash_ich10}, - {0x8086, 0x1c4f, NT, "Intel", "QM67", enable_flash_ich10}, - {0x8086, 0x1c50, NT, "Intel", "B65", enable_flash_ich10}, - {0x8086, 0x1c52, NT, "Intel", "C202", enable_flash_ich10}, - {0x8086, 0x1c54, NT, "Intel", "C204", enable_flash_ich10}, - {0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_ich10}, - {0x8086, 0x1c5c, NT, "Intel", "H61", enable_flash_ich10}, + {0x8086, 0x1c44, NT, "Intel", "Z68", enable_flash_pch6}, + {0x8086, 0x1c46, NT, "Intel", "P67", enable_flash_pch6}, + {0x8086, 0x1c47, NT, "Intel", "UM67", enable_flash_pch6}, + {0x8086, 0x1c49, NT, "Intel", "HM65", enable_flash_pch6}, + {0x8086, 0x1c4a, NT, "Intel", "H67", enable_flash_pch6}, + {0x8086, 0x1c4b, NT, "Intel", "HM67", enable_flash_pch6}, + {0x8086, 0x1c4c, NT, "Intel", "Q65", enable_flash_pch6}, + {0x8086, 0x1c4d, NT, "Intel", "QS67", enable_flash_pch6}, + {0x8086, 0x1c4e, NT, "Intel", "Q67", enable_flash_pch6}, + {0x8086, 0x1c4f, NT, "Intel", "QM67", enable_flash_pch6}, + {0x8086, 0x1c50, NT, "Intel", "B65", enable_flash_pch6}, + {0x8086, 0x1c52, NT, "Intel", "C202", enable_flash_pch6}, + {0x8086, 0x1c54, NT, "Intel", "C204", enable_flash_pch6}, + {0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_pch6}, + {0x8086, 0x1c5c, NT, "Intel", "H61", enable_flash_pch6}, {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e}, {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e}, {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e}, @@ -1212,23 +1245,23 @@ {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10}, {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10}, {0x8086, 0x3a1e, NT, "Intel", "ICH10 Engineering Sample", enable_flash_ich10}, - {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_ich10}, - {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_ich10}, - {0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_ich10}, - {0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_ich10}, - {0x8086, 0x3b06, NT, "Intel", "H55", enable_flash_ich10}, - {0x8086, 0x3b07, OK, "Intel", "QM57", enable_flash_ich10}, - {0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_ich10}, - {0x8086, 0x3b09, NT, "Intel", "HM55", enable_flash_ich10}, - {0x8086, 0x3b0a, NT, "Intel", "Q57", enable_flash_ich10}, - {0x8086, 0x3b0b, NT, "Intel", "HM57", enable_flash_ich10}, - {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_ich10}, - {0x8086, 0x3b0e, NT, "Intel", "B55", enable_flash_ich10}, - {0x8086, 0x3b0f, OK, "Intel", "QS57", enable_flash_ich10}, - {0x8086, 0x3b12, NT, "Intel", "3400", enable_flash_ich10}, - {0x8086, 0x3b14, NT, "Intel", "3420", enable_flash_ich10}, - {0x8086, 0x3b16, NT, "Intel", "3450", enable_flash_ich10}, - {0x8086, 0x3b1e, NT, "Intel", "B55", enable_flash_ich10}, + {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_pch5}, + {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_pch5}, + {0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_pch5}, + {0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_pch5}, + {0x8086, 0x3b06, NT, "Intel", "H55", enable_flash_pch5}, + {0x8086, 0x3b07, OK, "Intel", "QM57", enable_flash_pch5}, + {0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_pch5}, + {0x8086, 0x3b09, NT, "Intel", "HM55", enable_flash_pch5}, + {0x8086, 0x3b0a, NT, "Intel", "Q57", enable_flash_pch5}, + {0x8086, 0x3b0b, NT, "Intel", "HM57", enable_flash_pch5}, + {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_pch5}, + {0x8086, 0x3b0e, NT, "Intel", "B55", enable_flash_pch5}, + {0x8086, 0x3b0f, OK, "Intel", "QS57", enable_flash_pch5}, + {0x8086, 0x3b12, NT, "Intel", "3400", enable_flash_pch5}, + {0x8086, 0x3b14, NT, "Intel", "3420", enable_flash_pch5}, + {0x8086, 0x3b16, NT, "Intel", "3450", enable_flash_pch5}, + {0x8086, 0x3b1e, NT, "Intel", "B55", enable_flash_pch5}, {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7}, {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},

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use flashrom for Foxconn H67MP-V
by A.P. 27 Aug '11

27 Aug '11

Good day, I want to use flashrom to flash bios on H67MP-V motherboard. Is it safe for me? $flashrom -p internal:laptop=force_I_want_a_brick -V : flashrom v0.9.4-r1395 on Linux 2.6.35-30-generic-pae (i686), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 2975M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 994 us, 10000 myus = 9947 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "To be filled by O.E.M." DMI string system-product-name: "To be filled by O.E.M." DMI string system-version: "To be filled by O.E.M." DMI string baseboard-manufacturer: "Foxconn " DMI string baseboard-product-name: "H67MP-S/-V/H67MP " DMI string baseboard-version: " " DMI string chassis-type: "" DMI chassis-type is not specific enough. Found ITE Super I/O, ID 0x8728 on port 0x2e Found chipset "Intel H67" with PCI ID 8086:1c4a. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 Root Complex Register Block address = 0xfed1c000 GCS = 0xc00: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x3 (LPC) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x6009 (HSFS) HSFS: FDONE=1, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 0x06: 0x3f00 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 (FREG0: Flash Descriptor) 0x00000000-0x00000fff is read-only 0x58: 0x03ff0200 (FREG1: BIOS) 0x00200000-0x003fffff is read-write 0x5C: 0x01ff0001 (FREG2: Management Engine) 0x00001000-0x001fffff is locked 0x60: 0x00000fff (FREG3: Gigabit Ethernet) Gigabit Ethernet region is unused. 0x64: 0x00000fff (FREG4: Platform Data) Platform Data region is unused. 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0x84 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf84140 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=1, SME=0, SCF=0 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x0000019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xD0: 0x00000000 (FPB) Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done preop0=0x06, preop1=0x50 op[0]=0x02, 3, 0 op[1]=0x03, 2, 0 op[2]=0xd8, 3, 0 op[3]=0x05, 0, 0 op[4]=0x90, 2, 0 op[5]=0x01, 1, 0 op[6]=0x9f, 0, 0 op[7]=0xc7, 1, 0 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. Super I/O ID 0x8728 is not on the list of flash capable controllers. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xaa, id2 0x89, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xaa, id2 0x89, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25LF040A.RES, 512 kB: program_opcodes: preop=5006 optype=462b opmenu=05ab0302c79f0190 on-the-fly OPCODE (0xAB) re-programmed, op-pos=2 probe_spi_res2: id1 0x15, id2 0x15 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xaa, id2 0x89, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xaa, id2 0x89, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xaa, id2 0x89, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xaa, id2 0x89, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xaa, id2 0x89, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Chip status register is 00 Found Winbond flash chip "W25Q32" (4096 kB, SPI) at physical address 0xffc00000. Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xaa, id2 0x89, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xef, id2 0x15 No operations were specified. Restoring MMIO space at 0xb78568a0 Restoring MMIO space at 0xb785689c Restoring MMIO space at 0xb7856898 Restoring MMIO space at 0xb7856896 Restoring MMIO space at 0xb7856894 Restoring PCI config space for 00:1f:0 reg 0xdc

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Re: [flashrom] [PATCH]add AMD hudson support
by Uwe Hermann 26 Aug '11

26 Aug '11

On Fri, Aug 26, 2011 at 09:56:42AM +0800, QingPei Wang wrote: > you are right, it's 0x1022. new patch attached~~~ Thanks, committed as r1422. Please let us know if the patch is tested on hardware or not though, and preferrably also post the output of "./flashrom -V", thanks! Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r1422 - trunk
by repository service 26 Aug '11

26 Aug '11

Author: uwe Date: Fri Aug 26 23:11:41 2011 New Revision: 1422 URL: http://flashrom.org/trac/flashrom/changeset/1422 Log: Add AMD Hudson chipset-enable. AMD Hudson has different vendor/device IDs than AMD SBx00, handle that properly. Signed-off-by: Wang Qing Pei <wangqingpei(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/chipset_enable.c trunk/sb600spi.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Fri Aug 26 00:54:23 2011 (r1421) +++ trunk/chipset_enable.c Fri Aug 26 23:11:41 2011 (r1422) @@ -1058,6 +1058,7 @@ {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, + {0x1022, 0x780e, OK, "AMD", "Hudson", enable_flash_sb600}, {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501}, {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496}, {0x1039, 0x0530, NT, "SiS", "530", enable_flash_sis530}, Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Fri Aug 26 00:54:23 2011 (r1421) +++ trunk/sb600spi.c Fri Aug 26 23:11:41 2011 (r1422) @@ -259,8 +259,11 @@ smbus_dev = pci_dev_find(0x1002, 0x4385); if (!smbus_dev) { - msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); - return ERROR_NONFATAL; + smbus_dev = pci_dev_find(0x1022, 0x780b); /* AMD Hudson */ + if (!smbus_dev) { + msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); + return ERROR_NONFATAL; + } } /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */

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Re: [flashrom] report for Intel QM67 | Winbond W25Q64 - layout patches
by Stefan Tauner 26 Aug '11

26 Aug '11

On Wed, 24 Aug 2011 17:00:43 +0200 "Frei, Thomas (GE Germany)" <Thomas.Frei(a)ge.com> wrote: > Hi, > > sorry, msg_gsbg2 is a typo - it is of course msg_gdbg2. > > I'm using the 0.9.4 from http://www.flashrom.org/Downloads. > > Isn't this the latest? > 0.9.4 is the latest *stable* release, but the patches floating around here usually are to be applied on the latest *development* source code. please check out the source code with subversion as described on the download page and retry. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH]add AMD hudson support
by Paul Menzel 26 Aug '11

26 Aug '11

Am Freitag, den 26.08.2011, 09:56 +0800 schrieb QingPei Wang: > you are right, it's 0x1022. new patch attached~~~ Thank you! Did you test it? Can you attach the output of `flashrom -V` as Uwe asked you to do? Thanks, Paul

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Re: [flashrom] [PATCH]add AMD hudson support
by Uwe Hermann 25 Aug '11

25 Aug '11

Hi, On Thu, Aug 25, 2011 at 11:06:12PM +0800, QingPei Wang wrote: > The HUDSON has different vendor & device id than SBx00. The ids are got > by lspci. > Signed-off-by: Wang Qing Pei <wangqingpei(a)gmail.com> Thanks for the patch, we'll merge it soonish, but please see below for some questions. > Index: chipset_enable.c > =================================================================== > --- chipset_enable.c (revision 1419) > +++ chipset_enable.c (working copy) > @@ -1052,6 +1052,7 @@ > + {0x1002, 0x780e, OK, "AMD", "HUDSON", enable_flash_sb600}, Shouldn't this be 0x1022 (AMD instead of ATI ID) here? Also, did you test the chipset-enable on real hardware? Otherwise we should probably commit this as "NT" (not tested) instead of "OK". Please post a log of "./flashrom -V" with the patch applied if you own some test hardware, thanks! Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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Re: [flashrom] flashrom on PowerPC
by Carl-Daniel Hailfinger 25 Aug '11

25 Aug '11

Hi Mattias, nice to see you're back, and even more so with a big bang announcement. Am 27.07.2011 18:20 schrieb Mattias Mattsson: > I was able to run flashrom under Linux on PPC (big endian) hardware > with two small modifications in internal.c and processor_enable.c (see > attached patch). Not sure if this is the right way to do it but it > seems to work for me. > > Note that for Apple hardware you have to use a special power on method > to make the flash chip accessible (hold power button until beep). On > some models you have to press and hold an additional button on the > machine ("programmer's button") or keyboard ("Command"). > http://support.apple.com/kb/HT2322 > http://support.apple.com/kb/DL1284 > http://support.apple.com/kb/DL1126 > > I have tested this on two pieces of Apple hardware: "Mac Mini" (model > ID: PowerMac10,1) and "Mac mini (Late 2005)" (model ID: PowerMac10,2): > http://support.apple.com/kb/ht3476 > > By taking the hardware apart I can confirm they have the following flash chips: > > PowerMac10,1: AMD Am29LV008BB-90EC > PowerMac10,2: SHARP LH28F008BJT-BTLZ1 > > Flash chips seem to be mapped top-aligned in the 4GB address space. > Looking at the Open Firmware forth code inside Apple's own firmware > updates also suggests this is the case. > > I was able to probe, read, write and erase on both machines. Read > files seem to contain valid data. > > Added support for LH28F008BJT-BTLZ1 and marked Am29LV008B as fully tested. > > Logs and patches attached. > > > Please tell me if I should test something else! > Excellent work! The LH28F008BJT patch is Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> The Am29LV008BB patch is Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Can you commit those? I think you still have commit rights with account mhm. The PPC patch itself needs more work: - We need to match the chipset/machine somehow to avoid disasters on untested machines. While that may not be 100% required, I'm wary of bricked machines on an architecture I don't own. - A chipset match where buses_supported = BUS_PARALLEL is set. - A chipset match where you check if the flash chip is accessible... comparing lspci --xxx between flash enabled and flash disabled boots might shed some light on this. Then again, maybe that setting isn't visible in PCI space and such a check is futile. - Side note: Not your fault, but we really need a way for a chipset enable function to tell internal_init that it should return an error. Maybe a special return code for a chipset enable? Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1421 - trunk
by repository service 25 Aug '11

25 Aug '11

Author: uwe Date: Fri Aug 26 00:54:23 2011 New Revision: 1421 URL: http://flashrom.org/trac/flashrom/changeset/1421 Log: Mark the AMD Am29LV008BB chip as fully tested. Thanks Mattias Mattsson <vitplister(a)gmail.com> for the report. http://www.flashrom.org/pipermail/flashrom/2011-July/007423.html Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flashchips.c Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Fri Aug 26 00:44:11 2011 (r1420) +++ trunk/flashchips.c Fri Aug 26 00:54:23 2011 (r1421) @@ -428,7 +428,7 @@ .total_size = 1024, .page_size = 64 * 1024, /* unused */ .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = TIMING_ZERO, .block_erasers =

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Re: [flashrom] flashrom on PowerPC (002-lh28f008bjt.patch)
by Stefan Tauner 25 Aug '11

25 Aug '11

On Wed, 27 Jul 2011 18:20:19 +0200 Mattias Mattsson <vitplister(a)gmail.com> wrote: > Index: 82802ab.c > =================================================================== > --- 82802ab.c (revision 1396) > +++ 82802ab.c (working copy) > @@ -208,3 +208,56 @@ > > return 0; > } > + > +int unlock_lh28f008bjt(struct flashchip *flash) > +{ > + chipaddr bios = flash->virtual_memory; > + uint8_t mcfg, bcfg, need_unlock = 0, can_unlock = 0; mixing initialized and declared-only variables is :( > + int i; > + > + /* Wait if chip is busy */ > + wait_82802ab(flash); > + > + /* Read identifier codes */ > + chip_writeb(0x90, bios); > + > + /* Read master lock-bit */ > + mcfg = chip_readb(bios + 0x3); > + msg_cdbg("master lock is "); > + if (mcfg) { > + msg_cdbg("locked!\n"); > + } else { > + msg_cdbg("unlocked!\n"); > + can_unlock = 1; > + } > + > + /* Read block lock-bits, 8 * 8 KiB + 15 * 64 KiB */ although correct, we don't use the IEC prefixes nowhere else... > + for (i = 0; i < flash->total_size * 1024; i+= (i >= (64 * 1024) ? 64 * 1024 : 8 * 1024)) { hm... line limit. looks very odd at first sight. maybe a while loop would be better? > + bcfg = chip_readb(bios + i + 2); // read block lock config /* */? not that i find this convention necessary... > + msg_cdbg("block lock at %06x is %slocked!\n", i, bcfg ? "" : "un"); > + if (bcfg) { > + need_unlock = 1; > + } > + } > + > + /* Reset chip */ > + chip_writeb(0xFF, bios); > + > + /* Unlock: clear block lock-bits, if needed */ > + if (can_unlock && need_unlock) { > + msg_cdbg("Unlock: "); > + chip_writeb(0x60, bios); > + chip_writeb(0xD0, bios); > + chip_writeb(0xFF, bios); > + wait_82802ab(flash); > + msg_cdbg("Done!\n"); > + } > + > + /* Error: master locked or a block is locked */ > + if (!can_unlock && need_unlock) { > + msg_cerr("At least one block is locked and lockdown is active!\n"); > + return -1; > + } > + > + return 0; > +} you start messages lower-case and end them with an exclamation mark very often. we usually do this for errors (or warnings) only. > Index: flashchips.c > =================================================================== > --- flashchips.c (revision 1396) > +++ flashchips.c (working copy) > @@ -5379,6 +5379,36 @@ > > { > .vendor = "Sharp", > + .name = "LH28F008BJT-BTLZ1", why the -BTLZ1 suffix? i have just looked briefly at the LH28F008BJT-BTLZ1 and LH28F008BJT-BTLZC datasheets, but they seem to be almost identical? > + .bustype = BUS_PARALLEL, > + .manufacture_id = SHARP_ID, > + .model_id = SHARP_LH28F008BJxxPB, i am not sure about those id names either, but they are not as important because they are not visible to the user. > + .total_size = 1024, > + .page_size = 64 * 1024, > + .tested = TEST_OK_PREW, > + .probe = probe_82802ab, > + .probe_timing = TIMING_ZERO, > + .block_erasers = > + { > + { > + .eraseblocks = { > + {8 * 1024, 8}, > + {64 * 1024, 15} > + }, > + .block_erase = erase_block_82802ab, > + }, { > + .eraseblocks = { {1024 * 1024, 1} }, > + .block_erase = erase_sector_49lfxxxc, > + } > + }, > + .unlock = unlock_lh28f008bjt, > + .write = write_82802ab, > + .read = read_memmapped, > + .voltage = {2700, 3600}, > + }, > + > + { > + .vendor = "Sharp", > .name = "LHF00L04", > .bustype = BUS_FWH, /* A/A Mux */ > .manufacture_id = SHARP_ID, > Index: chipdrivers.h > =================================================================== > --- chipdrivers.h (revision 1396) > +++ chipdrivers.h (working copy) > @@ -83,6 +83,7 @@ > void print_status_82802ab(uint8_t status); > int unlock_82802ab(struct flashchip *flash); > int unlock_28f004s5(struct flashchip *flash); > +int unlock_lh28f008bjt(struct flashchip *flash); > > /* jedec.c */ > uint8_t oddparity(uint8_t val); -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1420 - trunk
by repository service 25 Aug '11

25 Aug '11

Author: uwe Date: Fri Aug 26 00:44:11 2011 New Revision: 1420 URL: http://flashrom.org/trac/flashrom/changeset/1420 Log: Add support for the Sharp LH28F008BJT-BTLZ1 chip. Tested by Mattias Mattsson <vitplister(a)gmail.com> on a PowerPC box. Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/82802ab.c trunk/chipdrivers.h trunk/flashchips.c Modified: trunk/82802ab.c ============================================================================== --- trunk/82802ab.c Thu Aug 25 16:06:50 2011 (r1419) +++ trunk/82802ab.c Fri Aug 26 00:44:11 2011 (r1420) @@ -208,3 +208,58 @@ return 0; } + +int unlock_lh28f008bjt(struct flashchip *flash) +{ + chipaddr bios = flash->virtual_memory; + uint8_t mcfg, bcfg; + uint8_t need_unlock = 0, can_unlock = 0; + int i; + + /* Wait if chip is busy */ + wait_82802ab(flash); + + /* Read identifier codes */ + chip_writeb(0x90, bios); + + /* Read master lock-bit */ + mcfg = chip_readb(bios + 0x3); + msg_cdbg("master lock is "); + if (mcfg) { + msg_cdbg("locked!\n"); + } else { + msg_cdbg("unlocked!\n"); + can_unlock = 1; + } + + /* Read block lock-bits, 8 * 8 KB + 15 * 64 KB */ + for (i = 0; i < flash->total_size * 1024; + i += (i >= (64 * 1024) ? 64 * 1024 : 8 * 1024)) { + bcfg = chip_readb(bios + i + 2); /* read block lock config */ + msg_cdbg("block lock at %06x is %slocked!\n", i, + bcfg ? "" : "un"); + if (bcfg) + need_unlock = 1; + } + + /* Reset chip */ + chip_writeb(0xFF, bios); + + /* Unlock: clear block lock-bits, if needed */ + if (can_unlock && need_unlock) { + msg_cdbg("Unlock: "); + chip_writeb(0x60, bios); + chip_writeb(0xD0, bios); + chip_writeb(0xFF, bios); + wait_82802ab(flash); + msg_cdbg("Done!\n"); + } + + /* Error: master locked or a block is locked */ + if (!can_unlock && need_unlock) { + msg_cerr("At least one block is locked and lockdown is active!\n"); + return -1; + } + + return 0; +} Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Thu Aug 25 16:06:50 2011 (r1419) +++ trunk/chipdrivers.h Fri Aug 26 00:44:11 2011 (r1420) @@ -85,6 +85,7 @@ void print_status_82802ab(uint8_t status); int unlock_82802ab(struct flashchip *flash); int unlock_28f004s5(struct flashchip *flash); +int unlock_lh28f008bjt(struct flashchip *flash); /* jedec.c */ uint8_t oddparity(uint8_t val); Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Thu Aug 25 16:06:50 2011 (r1419) +++ trunk/flashchips.c Fri Aug 26 00:44:11 2011 (r1420) @@ -5379,6 +5379,36 @@ { .vendor = "Sharp", + .name = "LH28F008BJT-BTLZ1", + .bustype = BUS_PARALLEL, + .manufacture_id = SHARP_ID, + .model_id = SHARP_LH28F008BJxxPB, + .total_size = 1024, + .page_size = 64 * 1024, + .tested = TEST_OK_PREW, + .probe = probe_82802ab, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {8 * 1024, 8}, + {64 * 1024, 15} + }, + .block_erase = erase_block_82802ab, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = erase_sector_49lfxxxc, + } + }, + .unlock = unlock_lh28f008bjt, + .write = write_82802ab, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Sharp", .name = "LHF00L04", .bustype = BUS_FWH, /* A/A Mux */ .manufacture_id = SHARP_ID,

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Re: [flashrom] Coreboot failure on GA-MA78GM-S2HP Rev. 2.0 motherboard
by QingPei Wang 25 Aug '11

25 Aug '11

that may because of the dual bios method which used by gigabyte, since the slave spi chip is still on the board, the superio may(i guess)detect the CRC error for the main spi bios is changed(coreboot now). you can try to remove the slave spi flash chip. no sure if it works Best wishes Wang Qing Pei Phone: 86+018930528086 On Sat, Aug 20, 2011 at 11:26 PM, Donovan Lavinder <drmario2007(a)gmail.com>wrote: > I originally wanted EFI and other features that will allow me to use my > motherboard for few years out. So, I downloaded archived coreboot firmware > package, and I found one "baked" firmware ROM under folder MA78GM as the > motherboards under this family seems to be having the same chipsets, so I > went to burn my own coreboot in FreeDOS using flashrom. Now, it first > exclaimed that it found MXIC MX25L8005 chipset, but it tried 4-bytes RDID > and failed, however, I was able to erase the BIOS chip fine. Next, I wrote > the firmware - after it said "done", it froze - I reset it, it kept > reverting back to oh-so-annoying Award BIOS... No wonder my motherboard is > SO picky! > > Here, I wrote up on the paper: > flashrom Ver. 0.9.3 - r1205 (on Freedos boot CD - all I have had, no floppy > disk and it won't boot from USB disk.... I may try spare hard drive if > needed...) > - 4-byte RDID refusal (although erasure was successful) > Motherboard: Vendor - Gigabyte / Model - GA-MA78GM-S2HP > CPU: AMD Phenom II X940 Black Series 3.0GHz quad-core (Deneb) CPU > RAM: Crucial Ballistix DDR-II 800MHz 1GB x2 (2GB) on dual-channel memory > bus > Video card: Vendor - Gigabyte / Model - GV-R467ZL-1GI - FW Ver. - F12 / VPU > - AMD Radeon HD 4670 with 1GB 800MHz GDDR3 on 128-bit bus > * I removed my hard drive (with my personal documents and Windows XP) > during the firmware flash to ensure the data aren't touched in a way. > > I would like to know how I can get my motherboard to quit being all so > picky - otherwise any other methods known to work perfectly on the > GA-MA78GM-S2HP motherboard any of you may have up and running the coreboot > firmware. > > Thanks for your help! > > -- > "Mamma-mia, there's Koopa troopa in Mushroom Kingdom!" > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom >

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[PATCH]add AMD hudson support
by QingPei Wang 25 Aug '11

25 Aug '11

The HUDSON has different vendor & device id than SBx00. The ids are got by lspci. Signed-off-by: Wang Qing Pei <wangqingpei(a)gmail.com> Index: chipset_enable.c =================================================================== --- chipset_enable.c (revision 1419) +++ chipset_enable.c (working copy) @@ -1052,6 +1052,7 @@ {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400}, {0x1002, 0x438d, OK, "AMD", "SB600", enable_flash_sb600}, {0x1002, 0x439d, OK, "AMD", "SB700/SB710/SB750/SB850", enable_flash_sb600}, + {0x1002, 0x780e, OK, "AMD", "HUDSON", enable_flash_sb600}, {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100}, {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536}, {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536}, Index: sb600spi.c =================================================================== --- sb600spi.c (revision 1419) +++ sb600spi.c (working copy) @@ -259,8 +259,11 @@ smbus_dev = pci_dev_find(0x1002, 0x4385); if (!smbus_dev) { - msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); - return ERROR_NONFATAL; + smbus_dev = pci_dev_find(0x1022,0x780b); /*HUDSON*/ + if(!smbus_dev){ + msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); + return ERROR_NONFATAL; + } } /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ Best wishes Wang Qing Pei Phone: 86+018930528086

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Re: [flashrom] [PATCH] dmi: add "Sealed-case PC" to the list of non-laptop chassis
by Stefan Tauner 25 Aug '11

25 Aug '11

On Thu, 25 Aug 2011 14:44:22 +0200 Idwer Vollering <vidwer(a)gmail.com> wrote: > 2011/8/22 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at>: > > --- > > not sure though if all other computers with that chassis type are "in all > > likelihood not a laptop". > > This writeup looks rather convincing: > http://www.novell.com/communities/node/3519/adding-more-addon-image-files-b… > > > > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > > Acked-by: Idwer Vollering <vidwer(a)gmail.com> thanks, i am not fully convinced though, but i have added it to my tested_stuff branch for now, so others can still veto for a while :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] Add board enable for ASUS P5LP-LE
by Stefan Tauner 25 Aug '11

25 Aug '11

On Thu, 25 Aug 2011 14:19:33 +0200 Idwer Vollering <vidwer(a)gmail.com> wrote: > Acked-by: Idwer Vollering <vidwer(a)gmail.com> r1419, thanks. i have changed it a bit though: i had to rename the board names of the board enable, because the print.c code is not able to cope with multiple boards with the same name, resulting in output like: ASUS P5LP-LE OK (autodetected)(autodetected) i hope everyone can live with the result :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1419 - trunk
by repository service 25 Aug '11

25 Aug '11

Author: stefanct Date: Thu Aug 25 16:06:50 2011 New Revision: 1419 URL: http://flashrom.org/trac/flashrom/changeset/1419 Log: Add board enable for ASUS P5LP-LE Based on the REing of Michael Karcher and a good guess of Idwer Vollering. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Tested-by: Leon Zhang <leoncamel at gmail.com> http://www.coreboot.org/pipermail/flashrom/2010-August/004500.html Tested-by: medhi <nefkongo(a)hotmail.com> http://paste.flashrom.org/view.php?id=779 Acked-by: Idwer Vollering <vidwer(a)gmail.com> --- i have added the DMI match and changed the board enable and wiki comments a bit. i am not sure if this is the right way to add it, because there are so many variations, but we can change that later too. Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sat Aug 20 16:16:00 2011 (r1418) +++ trunk/board_enable.c Thu Aug 25 16:06:50 2011 (r1419) @@ -1517,6 +1517,9 @@ /* * Suited for: * - ASUS A8Jm (laptop): Intel 945 + ICH7 + * - ASUS P5LP-LE used in ... + * - HP Media Center m7270.fr Desktop PC as "Lithium-UL8E" + * - Epson Endeavor MT7700 */ static int intel_ich_gpio34_raise(void) { @@ -2024,6 +2027,8 @@ {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GD2-Premium$", NULL, NULL, P3, "ASUS", "P5GD2 Premium", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x27b8, 0x103c, 0x2a22, 0x8086, 0x2770, 0x103c, 0x2a22, "^LITHIUM$", NULL, NULL, P3, "ASUS", "P5LP-LE (Lithium-UL8E)",0, OK, intel_ich_gpio34_raise}, + {0x8086, 0x27b8, 0x1043, 0x2a22, 0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$", NULL, NULL, P3, "ASUS", "P5LP-LE (Epson OEM)", 0, OK, intel_ich_gpio34_raise}, {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sat Aug 20 16:16:00 2011 (r1418) +++ trunk/print.c Thu Aug 25 16:06:50 2011 (r1419) @@ -483,6 +483,9 @@ B("ASUS", "P5KC", 1, "http://www.asus.com/product.aspx?P_ID=fFZ8oUIGmLpwNMjj", NULL), B("ASUS", "P5L-MX", 1, "http://www.asus.com/product.aspx?P_ID=X70d3NCzH2DE9vWH", NULL), B("ASUS", "P5LD2", 0, NULL, "Untested board enable."), + B("ASUS", "P5LP-LE (Lithium-UL8E)", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00379616&tmp_task=prod…", "This is an OEM board from HP."), + B("ASUS", "P5LP-LE (Epson OEM)", 1, NULL, "This is an OEM board from Epson (e.g. Endeavor MT7700)."), + B("ASUS", "P5LP-LE", 0, NULL, "This designation is used for OEM boards from HP, Epson and maybe others. The HP names vary and not all of them have been tested yet. Please report any success or failure, thanks."), B("ASUS", "P5GD1 Pro", 1, "http://www.asus.com/product.aspx?P_ID=50M49xQh71EZOeM1", NULL), B("ASUS", "P5N-E SLI", 0, "http://www.asus.com/product.aspx?P_ID=KyHOsOKWujC2QguJ", "Needs a board enable (http://patchwork.coreboot.org/patch/3298/)."), B("ASUS", "P5N32-E SLI", 1, "http://www.asus.com/product.aspx?P_ID=vBZLIBtPzYB2bLcb", NULL),

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Re: [flashrom] [PATCH] Make the laptop warning less scary if unsure
by Idwer Vollering 25 Aug '11

25 Aug '11

2011/8/20 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at>: > Telling the user to use "force_I_want_a_brick" if it is not even a > laptop, is a bit over-the-top. Introduce a new laptop parameter > "this_is_not_a_laptop" that allows to force operation, but only if > the detection is not sure. > > --- > > complicates the whole thing a bit. could do without the extra > variable and new part of the if condition, if we allow the > this_is_not_a_laptop parameter to always work, not only if the > laptop detection is uncertain. it will be undocumented and only > visible to the user together with the warning anyway... I was curious whether the currently present overriding parameter works in combination with the parameter in this patch, and it does: $ sudo ./flashrom -V -p internal:laptop=force_I_want_a_brick -p internal:laptop=this_is_not_a_laptop flashrom v0.9.4-r1418 on FreeBSD 9.0-BETA1 (i386), built with libpci 3.1.7, GCC 4.2.2 20070831 prerelease [FreeBSD], little endian (etcetera) Do you think this behaviour is desired? > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > internal.c | 14 ++++++++------ > 1 files changed, 8 insertions(+), 6 deletions(-) > > diff --git a/internal.c b/internal.c > index 846cf1e..5ff605e 100644 > --- a/internal.c > +++ b/internal.c > @@ -139,6 +139,7 @@ int internal_init(void) > int ret = 0; > #endif > int force_laptop = 0; > + int not_a_laptop = 0; > char *arg; > > arg = extract_programmer_param("boardenable"); > @@ -170,9 +171,11 @@ int internal_init(void) > free(arg); > > arg = extract_programmer_param("laptop"); > - if (arg && !strcmp(arg,"force_I_want_a_brick")) { > + if (arg && !strcmp(arg,"force_I_want_a_brick")) > force_laptop = 1; > - } else if (arg && !strlen(arg)) { > + else if (arg && !strcmp(arg,"this_is_not_a_laptop")) > + not_a_laptop = 1; > + else if (arg && !strlen(arg)) { > msg_perr("Missing argument for laptop.\n"); > free(arg); > return 1; > @@ -237,7 +240,7 @@ int internal_init(void) > msg_perr("WARNING! You may be running flashrom on an unsupported laptop. We could\n" > "not detect this for sure because your vendor has not setup the SMBIOS\n" > "tables correctly. You can enforce execution by adding\n" > - "'-p internal:laptop=force_I_want_a_brick' to the command line, but\n" > + "'-p internal:laptop=this_is_not_a_laptop' to the command line, but\n" > "please read the following warning if you are not sure.\n\n"); > } > msg_perr("Laptops, notebooks and netbooks are difficult to support and we\n" > @@ -251,9 +254,8 @@ int internal_init(void) > "You have been warned.\n" > "========================================================================\n"); > > - if (force_laptop) { > - msg_perr("Proceeding anyway because user specified " > - "laptop=force_I_want_a_brick\n"); > + if (force_laptop || (not_a_laptop && (is_laptop != 1))) { > + msg_perr("Proceeding anyway because user forced us to.\n"); > } else { > msg_perr("Aborting.\n"); > exit(1); > -- > 1.7.1 > > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom >

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Re: [flashrom] [PATCH] dmi: add "Sealed-case PC" to the list of non-laptop chassis
by Idwer Vollering 25 Aug '11

25 Aug '11

2011/8/22 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at>: > --- > not sure though if all other computers with that chassis type are "in all > likelihood not a laptop". This writeup looks rather convincing: http://www.novell.com/communities/node/3519/adding-more-addon-image-files-b… > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Idwer Vollering <vidwer(a)gmail.com> > --- > dmi.c | 1 + > 1 files changed, 1 insertions(+), 0 deletions(-) > > diff --git a/dmi.c b/dmi.c > index 8f78376..5f64b94 100644 > --- a/dmi.c > +++ b/dmi.c > @@ -81,6 +81,7 @@ static const struct { > {0x0e, 1, "Sub Notebook"}, > {0x11, 0, "Main Server Chassis"}, > {0x17, 0, "Rack Mount Chassis"}, > + {0x18, 0, "Sealed-case PC"}, /* used by Supermicro (X8SIE) */ > }; > > #define DMI_COMMAND_LEN_MAX 260 > -- > 1.7.1 > > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom >

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Re: [flashrom] [PATCH] Add board enable for ASUS P5LP-LE
by Idwer Vollering 25 Aug '11

25 Aug '11

2011/8/25 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at>: > Based on the REing of Michael Karcher The result can be found here: http://www.coreboot.org/pipermail/flashrom/2010-August/004500.html > and a good guess of Idwer Vollering. > > Tested-by: Leon Zhang <leoncamel at gmail.com> > Tested-by: medhi Tested-by: medhi <nefkongo(a)hotmail.com> Acked-by: Idwer Vollering <vidwer(a)gmail.com> > --- > i have added the DMI match and changed the board enable and wiki comments > a bit. i am not sure if this is the right way to add it, because there are so many > variations, but we can change that later too. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > board_enable.c | 5 +++++ > print.c | 1 + > 2 files changed, 6 insertions(+), 0 deletions(-) > > diff --git a/board_enable.c b/board_enable.c > index b362b54..0f2300c 100644 > --- a/board_enable.c > +++ b/board_enable.c > @@ -1517,6 +1517,9 @@ static int intel_ich_gpio22_raise(void) > /* > * Suited for: > * - ASUS A8Jm (laptop): Intel 945 + ICH7 > + * - ASUS P5LP-LE used in ... > + * - HP Media Center m7270.fr Desktop PC as "Lithium-UL8E" > + * - Epson Endeavor MT7700 > */ > static int intel_ich_gpio34_raise(void) > { > @@ -2024,6 +2027,8 @@ const struct board_pciid_enable board_pciid_enables[] = { > {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise}, > {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GD2-Premium$", NULL, NULL, P3, "ASUS", "P5GD2 Premium", 0, OK, intel_ich_gpio21_raise}, > {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise}, > + {0x8086, 0x27b8, 0x103c, 0x2a22, 0x8086, 0x2770, 0x103c, 0x2a22, "^LITHIUM$", NULL, NULL, P3, "ASUS", "P5LP-LE", 0, OK, intel_ich_gpio34_raise}, > + {0x8086, 0x27b8, 0x1043, 0x2a22, 0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$", NULL, NULL, P3, "ASUS", "P5LP-LE", 0, OK, intel_ich_gpio34_raise}, > {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise}, > {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, > {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, > diff --git a/print.c b/print.c > index c25cb3e..42e031a 100644 > --- a/print.c > +++ b/print.c > @@ -483,6 +483,7 @@ const struct board_info boards_known[] = { > B("ASUS", "P5KC", 1, "http://www.asus.com/product.aspx?P_ID=fFZ8oUIGmLpwNMjj", NULL), > B("ASUS", "P5L-MX", 1, "http://www.asus.com/product.aspx?P_ID=X70d3NCzH2DE9vWH", NULL), > B("ASUS", "P5LD2", 0, NULL, "Untested board enable."), > + B("ASUS", "P5LP-LE", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00379616&tmp_task=prod…", "This is an OEM board from HP and Epson (Endeavor MT7700). The HP names vary and not all of them were tested."), > B("ASUS", "P5GD1 Pro", 1, "http://www.asus.com/product.aspx?P_ID=50M49xQh71EZOeM1", NULL), > B("ASUS", "P5N-E SLI", 0, "http://www.asus.com/product.aspx?P_ID=KyHOsOKWujC2QguJ", "Needs a board enable (http://patchwork.coreboot.org/patch/3298/)."), > B("ASUS", "P5N32-E SLI", 1, "http://www.asus.com/product.aspx?P_ID=vBZLIBtPzYB2bLcb", NULL), > -- > 1.7.1 > > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom >

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[PATCH] Add board enable for ASUS P5LP-LE
by Stefan Tauner 25 Aug '11

25 Aug '11

Based on the REing of Michael Karcher and a good guess of Idwer Vollering. Tested-by: Leon Zhang <leoncamel at gmail.com> Tested-by: medhi --- i have added the DMI match and changed the board enable and wiki comments a bit. i am not sure if this is the right way to add it, because there are so many variations, but we can change that later too. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- board_enable.c | 5 +++++ print.c | 1 + 2 files changed, 6 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index b362b54..0f2300c 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1517,6 +1517,9 @@ static int intel_ich_gpio22_raise(void) /* * Suited for: * - ASUS A8Jm (laptop): Intel 945 + ICH7 + * - ASUS P5LP-LE used in ... + * - HP Media Center m7270.fr Desktop PC as "Lithium-UL8E" + * - Epson Endeavor MT7700 */ static int intel_ich_gpio34_raise(void) { @@ -2024,6 +2027,8 @@ const struct board_pciid_enable board_pciid_enables[] = { {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GD2-Premium$", NULL, NULL, P3, "ASUS", "P5GD2 Premium", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x27b8, 0x103c, 0x2a22, 0x8086, 0x2770, 0x103c, 0x2a22, "^LITHIUM$", NULL, NULL, P3, "ASUS", "P5LP-LE", 0, OK, intel_ich_gpio34_raise}, + {0x8086, 0x27b8, 0x1043, 0x2a22, 0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$", NULL, NULL, P3, "ASUS", "P5LP-LE", 0, OK, intel_ich_gpio34_raise}, {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, diff --git a/print.c b/print.c index c25cb3e..42e031a 100644 --- a/print.c +++ b/print.c @@ -483,6 +483,7 @@ const struct board_info boards_known[] = { B("ASUS", "P5KC", 1, "http://www.asus.com/product.aspx?P_ID=fFZ8oUIGmLpwNMjj", NULL), B("ASUS", "P5L-MX", 1, "http://www.asus.com/product.aspx?P_ID=X70d3NCzH2DE9vWH", NULL), B("ASUS", "P5LD2", 0, NULL, "Untested board enable."), + B("ASUS", "P5LP-LE", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00379616&tmp_task=prod…", "This is an OEM board from HP and Epson (Endeavor MT7700). The HP names vary and not all of them were tested."), B("ASUS", "P5GD1 Pro", 1, "http://www.asus.com/product.aspx?P_ID=50M49xQh71EZOeM1", NULL), B("ASUS", "P5N-E SLI", 0, "http://www.asus.com/product.aspx?P_ID=KyHOsOKWujC2QguJ", "Needs a board enable (http://patchwork.coreboot.org/patch/3298/)."), B("ASUS", "P5N32-E SLI", 1, "http://www.asus.com/product.aspx?P_ID=vBZLIBtPzYB2bLcb", NULL), -- 1.7.1

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Re: [flashrom] [PATCH] Board enable for ASUS P5LP-LE
by Uwe Hermann 24 Aug '11

24 Aug '11

On Wed, Aug 18, 2010 at 06:27:15PM +0200, Michael Karcher wrote: > + * - ASUS P5LP-LE (Epson/HP OEM) OK, this one is going to be interesting. The board is made by ASUS for HP, it seems. HP calls it "Leonite" or "Leonite-GL8E". http://h10025.www1.hp.com/ewfrf/wc/document?lc=en&dlc=en&cc=us&docname=c008… But that would have been too easy. There are a bunch of other boards on the HP site which are also called P5LP-LE, but have different HP code names. From a quick glance I see at least: P5LP-LE (Leonite) P5LP-LE (Leonite2) P5LP-LE (Lithium) P5LP-LE (Limestone) P5LP-LE (Emery) Fun! I don't know how to differ between them, the dmidecode from Leon Zhang <leoncamel(a)gmail.com> said: DMI string system-manufacturer: "EPSON DIRECT CORP." DMI string system-product-name: "Endeavor MT7700" DMI string system-version: "" DMI string baseboard-manufacturer: "ASUSTek Computer INC." DMI string baseboard-product-name: "P5LP-LE" We don't know if other "P5LP-LE" might have the "Leonite" (or other) HP code name in there or not. Maybe something is printed as silkscreen on the board? An then one of these HP OEM boards is built into the Epson "Endeavor MT7700" system/PC. So it's a bit unclear which vendor/board name we should use in this case. It's probably best to mention all of them for better googling results. Attached is a slightly updated patch for review, let me know what you think. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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Failed Flashing Intel 3420 Chipset
by Shailendra Sodhi 24 Aug '11

24 Aug '11

Hi, Hi we use flashroom tool to flash our X8DTH and X8DTU Supermicro boards now when we try to flash X8SIE-F Motherboard with Intel 3420 chipset flashrom fails with error. Attached a file(s) detailing error. Please let me know if any further information required to make this work. Regards, Shailendra

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Re: [flashrom] report for Intel QM67 | Winbond W25Q64 - layout patches
by Tadas Slotkus 24 Aug '11

24 Aug '11

> I'm using the 0.9.4 from http://www.flashrom.org/Downloads. > > Isn't this the latest? For developing patches use latest svn revision.

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Re: [flashrom] report for Intel QM67 | Winbond W25Q64 - layout patches
by Stefan Tauner 24 Aug '11

24 Aug '11

On Wed, 24 Aug 2011 15:38:03 +0200 "Frei, Thomas (GE Germany)" <Thomas.Frei(a)ge.com> wrote: > Hi, > > I applied the patches 0001 - 0007, but now flashrom doesn't compile any more... :-( > > flashrom.c: In function verify_flash: > flashrom.c: 1234:3: error: implicit declaration of function msg_gsbg2 > flashrom.c: At top level: > flashrom.c: 1305:5: error: redefinition of write_buf_to_file > flashrom.c: 1281:5: note: previous definition of write_buf_to_file was here > flashrom.c: In function write_buf_to_file: > flashrom.c: 1311:2: error: implicit declaration of function write_dump_to_file > > can you please help here? > hi hm. how did you apply them? the reason i ask is because "msg_gsbg2" should have been "msg_gdbg2" (message general debug2) and it actually is in my posted patches afaics. the patches compile on my machine (on top of r1416 btw, probably other revisions too, but that's the one i compile tested with a few moments ago). which revision did you checkout/extract/fetch before applying the patches? i assume you are using one that is too old. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[RFC] unsignify flashchip and programmer structs
by Stefan Tauner 23 Aug '11

23 Aug '11

i don't like the use of generic "int" qualifiers at all, even more the unsigned version for things like absolute addresses, lengths and sizes. of course negative values make sense in return types to indicate errors and in the case a function returns the length of actually bytes written on success and negative values on errors it makes sense to keep the parameters the same type (else the parameter length might be too big to return it on success). i would also like to change the types to more accurate ones someday (uint32_t etc.) instead, but i think that is not important as signedness. i want to assure myself that no one objects changing the following things to unsigned before i create a patch (which should be straight forward, but of course i will need to change quite many lines and also check that all functions will stay correct...). please speak up now or forever hold your peace etc... :) spi_programmer: int max_data_read; int max_data_write; (start + len parameters of:) int (*read)(struct flashchip *flash, uint8_t *buf, int start, int len); int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len); (the return values just indicate success and failure with 0 and 1) struct flashchip: int total_size; (should also be converted to bytes instead of kB... i know this is on the todo already) int page_size; (start + len parameters of:) int (*write) (struct flashchip *flash, uint8_t *buf, int start, int len); int (*read) (struct flashchip *flash, uint8_t *buf, int start, int len); (again, the return value just indicates success, not bytes written) }; -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] ASUS P5N-D
by Joshua Roys 23 Aug '11

23 Aug '11

On 08/18/2011 04:17 AM, Guillaume Poirier-Morency wrote: > I've been told, after an unsuccessful flashing, to send you these > outputs about my motherboard. > > My board remained intact! > > If you are interested into enabling it and developing patches to make it > compatible, I do not mind giving you feedback. > > Regards, > > Arteymis > > Hello, Please try the attached patch on top of the latest SVN and let us know how it works (reply with the output from `flashrom -Vw [...]'). For the devs: the board enable was identical to the P5N-E SLI, so I have bundled them together. Josh

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Re: [flashrom] ASUS P5N-D
by Stefan Tauner 23 Aug '11

23 Aug '11

On Tue, 23 Aug 2011 06:13:26 -0400 Guillaume Poirier-Morency <guillaumepoiriermorency(a)gmail.com> wrote: > I have checked my bash history. You were right, I was using 9.2. > > I have then moved to the svn folder and used ./flashrom and curiously, look > at what I have got from the log file... > > The file is slightly different, but it's still showing version 9.2 > > Launching the flashrom executable without any arguments, it tells me I'm > using 9.4 > > I suppose there is version typo in the program itself. Otherwise, maybe the > patch affect the version this way. i seriously doubt that. there is only a single string containing the version in the program and only one place where this single string is printed... i would recommend uninstalling the old version anyway. in this case it was not important, but in other cases it may break stuff. > Anyway, It's really using 9.4 and it works very well! that's the important thing anyway :) i'll make the appropriate changes in our repository, thanks for testing! -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] ASUS P5N-D
by Stefan Tauner 23 Aug '11

23 Aug '11

On Tue, 23 Aug 2011 05:34:28 -0400 Guillaume Poirier-Morency <guillaumepoiriermorency(a)gmail.com> wrote: > I think there will soon be a new supported motherboard on your list! > > Here's the flashrom -Vw [...] output. nice! but what did you do exactly? the log shows version 0.9.2. did you patch that ancient version? why? could it be that you just rewrote with the old version by accident to get the verbose log? NB: the write protection remains disabled until reboot. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] report for Intel QM67 | Winbond W25Q64 ([PATCH] (not for merge) ichspi: print BFPR (BIOS Flash Primary Region Register))
by Stefan Tauner 23 Aug '11

23 Aug '11

On Tue, 23 Aug 2011 08:41:35 +0200 "Frei, Thomas (GE Germany)" <Thomas.Frei(a)ge.com> wrote: > please send me this patch - I first want to read out the flash - and if this works, I will try to write... > > I need this for production test. i have already posted my patches in the (sub)thread named "[PATCH 0/7] every layout handling feature you ever wanted to see but never cared to implement". if you are not subscribed to the list you could also fetch them from http://patchwork.coreboot.org/project/flashrom/list/ (all those with date 2011-08-19). i will mail them to you separately this time. you need at least 1-5 to be able to read. > Will this patch work without a layout file? I fnot, can you tell me how to generate it? no, it will not work without one. there is apparently no way to flash beyond the regions defined by the flash descriptor. the layout file can limit the address range accessed (to make it work). depending on how fine-grained you wanna use it you can define in the layout file ranges for each region as defined by the flash descriptor on your board (from this output of flashrom:) 0x54: 0x00000000 (FREG0: Flash Descriptor) 0x00000000-0x00000fff is read-write 0x58: 0x03ff0200 (FREG1: BIOS) 0x00200000-0x003fffff is read-write 0x5C: 0x01ff0001 (FREG2: Management Engine) 0x00001000-0x001fffff is read-write or just define one range for the whole accessible area (that would be something like 0x0 - 0x003fffff i would say) i think you will probably need to set the read_all_first variable in flashrom.c to 0 (and maybe also use the -w parameter) to be able to write without errors printed, else flashrom will try to read the whole flash before and after writing to verify its contents. i have told you already at least twice to look into our documentation. you know that this is my spare time and i am not here to do your work... if you have concrete questions about layout files or their usage we are happy to answer that, but "how do we do that?" makes me kinda angry, if it is already documented. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[carFl mem] Reduce memory buffers
by Tadas Slotkus 22 Aug '11

22 Aug '11

Hi all, Sending initial patches, which reduce memory usage for flashrom in coreboot. Look 0-9 patches. To get some laugh at my stupidity look for 10-21 :) Thanks, Tadas

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[PATCH] spi25: get rid of unneccessary line breaks (on failed probes)
by Stefan Tauner 22 Aug '11

22 Aug '11

--- not sure if this is correct for all execution paths, but it fixes the output of a probe on my thinkpad. i have looked a bit around to find examples of code that this patch would break and found none though. without this patch: Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3017 Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25LF080A, 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25VF010.REMS, 128 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3017 with this patch: Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3017 Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25LF080A, 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25VF010.REMS, 128 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3017 Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- spi25.c | 4 ---- 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/spi25.c b/spi25.c index 937ee5d..c9fe9ec 100644 --- a/spi25.c +++ b/spi25.c @@ -120,7 +120,6 @@ static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) uint32_t id2; if (spi_rdid(readarr, bytes)) { - msg_cdbg("\n"); return 0; } @@ -201,7 +200,6 @@ int probe_spi_rems(struct flashchip *flash) uint32_t id1, id2; if (spi_rems(readarr)) { - msg_cdbg("\n"); return 0; } @@ -259,7 +257,6 @@ int probe_spi_res1(struct flashchip *flash) } if (spi_res(readarr, 1)) { - msg_cdbg("\n"); return 0; } @@ -283,7 +280,6 @@ int probe_spi_res2(struct flashchip *flash) uint32_t id1, id2; if (spi_res(readarr, 2)) { - msg_cdbg("\n"); return 0; } -- 1.7.1

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[PATCH] dmi: add "Sealed-case PC" to the list of non-laptop chassis
by Stefan Tauner 22 Aug '11

22 Aug '11

--- not sure though if all other computers with that chassis type are "in all likelihood not a laptop". Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- dmi.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/dmi.c b/dmi.c index 8f78376..5f64b94 100644 --- a/dmi.c +++ b/dmi.c @@ -81,6 +81,7 @@ static const struct { {0x0e, 1, "Sub Notebook"}, {0x11, 0, "Main Server Chassis"}, {0x17, 0, "Rack Mount Chassis"}, + {0x18, 0, "Sealed-case PC"}, /* used by Supermicro (X8SIE) */ }; #define DMI_COMMAND_LEN_MAX 260 -- 1.7.1

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Re: [flashrom] flashrom accepts its command line parameters as a file name to read to
by Stefan Tauner 22 Aug '11

22 Aug '11

On Thu, 18 Aug 2011 17:57:59 +0200 Idwer Vollering <vidwer(a)gmail.com> wrote: > 2011/8/18 Christophe Poncy <cp(a)canaxis.org>: > > Hi, > > > > ... > > > # ./flashrom -r -L > > This shouldn't be allowed. hm. actually i think this is normal behavior (for getopt-using applications). one arbitrary example: grep [OPTIONS] [-e PATTERN | -f FILE] [FILE...] # grep -e -f cli_classic.c this uses "-f" as a search pattern to look for in cli_classic.c i do agree though, that it might be unexpected, especially for windows users. and even if it is expected behavior no one would miss it, if we prohibit it. > What about disallowing the creation of files that have a name listed > in cli_classic.c's optstring[] and/or long_options[] ? or prohibiting any option parameters to be started with "-" (this includes all the file names, but also: - chip names (not an issue so far) - mainboard names (ditto) - layout file names and region names (probably tolerable too) - programmer parameters (also not an issue i presume) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Update of Gigabyte GA-MA78GM-S2HP motherboard firmware switch
by Stefan Tauner 21 Aug '11

21 Aug '11

On Sun, 21 Aug 2011 08:40:54 -0600 Donovan Lavinder <drmario2007(a)gmail.com> wrote: > > here's the log: > > ;root@sysresccd /root % flashrom > ;flashrom v0.9.3-r1205 on Linux 2.6.38-std230-i586 (i686), built with libpci > 3.1. > ;7, GCC 4.4.5, little endian > ;flashrom is free software, get the source code at http://www.flashrom.org > ; > ; > ;Calibrating delay loop... OK. > ;coreboot table found at 0x6fffe000. > ;Found ITE Super I/O, ID 0x8718. > ;Found Chipset "AMD SB700/SB710/SB750", enabling flash write... OK. > ;This chipset supports the following protocols: LPC,FWH,SPI. > ;4 byte RDID not supported on this SPI controller > ;4 byte RDID not supported on this SPI controller > ;4 byte RDID not supported on this SPI controller > ;4 byte RDID not supported on this SPI controller > ;4 byte RDID not supported on this SPI controller > ;4 byte RDID not supported on this SPI controller > ;4 byte RDID not supported on this SPI controller > ;4 byte RDID not supported on this SPI controller > ;4 byte RDID not supported on this SPI controller > ;4 byte RDID not supported on this SPI controller > ;4 byte RDID not supported on this SPI controller > ; > > After that, that's it.... > a verbose one (with -V or even -VVV) please i am not familiar with the it87xx code, but i would say it hangs in the while loop at the end of it8716f_spi_send_command. it would be easy to add a timeout there, but the question is why it does hang there (now). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] MSI H55-GD65 (MS-7637) (H55, locked ME region, FLOCKDN=0(!))
by Bernd Blaauw 21 Aug '11

21 Aug '11

Op 21-8-2011 3:40, Donovan Lavinder schreef: > to use Linux Live CD mentioned in flashrom download page, as FreeDOS > have managed to brick all of the firmware image I have been trying to > flash. Fed up, I went to get the live CD, it works now. I used > SystemRescueCd distro (you need to figure out how to mount the hard > drive or jump drive to be able to have flashrom to download the firmware > ROM - for example: mount /dev/sda1 /mnt/disk0 ), so far, this distro is > quite nice to have! I thought ramdisks make fine temporary storage? No need to mount harddisk then. It seems a bit strange to claim FreeDOS (or DJGPP-compiled flashrom) ruined your flash image. I guess file hashes would give a definitive answer to what's the issue. I have to admit though that sometimes that FreeDOS kernel has had some FAT-related issues, no guarantee they're all solved. goodluck with CoreBoot as well! So far the Asrock E350 board seems best to experiment with, though I'd like the fanless/passive Asus E350 board instead.

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Re: [flashrom] Update of Gigabyte GA-MA78GM-S2HP motherboard firmware switch
by Donovan Lavinder 21 Aug '11

21 Aug '11

> here's the log: ;root@sysresccd /root % flashrom ;flashrom v0.9.3-r1205 on Linux 2.6.38-std230-i586 (i686), built with libpci 3.1. ;7, GCC 4.4.5, little endian ;flashrom is free software, get the source code at http://www.flashrom.org ; ; ;Calibrating delay loop... OK. ;coreboot table found at 0x6fffe000. ;Found ITE Super I/O, ID 0x8718. ;Found Chipset "AMD SB700/SB710/SB750", enabling flash write... OK. ;This chipset supports the following protocols: LPC,FWH,SPI. ;4 byte RDID not supported on this SPI controller ;4 byte RDID not supported on this SPI controller ;4 byte RDID not supported on this SPI controller ;4 byte RDID not supported on this SPI controller ;4 byte RDID not supported on this SPI controller ;4 byte RDID not supported on this SPI controller ;4 byte RDID not supported on this SPI controller ;4 byte RDID not supported on this SPI controller ;4 byte RDID not supported on this SPI controller ;4 byte RDID not supported on this SPI controller ;4 byte RDID not supported on this SPI controller ; After that, that's it.... On Sun, Aug 21, 2011 at 8:26 AM, Donovan Lavinder <drmario2007(a)gmail.com>wrote: > The flashrom is the only program that froze when looking for the flash > chip. I have tried cold reboot - same thing happened. That here, was a > head-scratcher since it is not even supposed to happen. Probably it could be > because the firmware unmounted itself (shouldn't happen). The whole OS ran > fine otherwise (I could close the frozen flashrom program with ease). I am > wondering how could SuperIO refuse the handshake between the flashrom - I > left it alone for a while, no change in the behavior (as far as the verbose > terminal emulator was concerned). > > > On Sun, Aug 21, 2011 at 8:05 AM, Stefan Tauner < > stefan.tauner(a)student.tuwien.ac.at> wrote: > >> On Sun, 21 Aug 2011 07:27:02 -0600 >> Donovan Lavinder <drmario2007(a)gmail.com> wrote: >> >> > That's strange. I have tried rewriting the firmware so I COULD provide >> you >> > the text file... It froze after couple complaints of 4-byte RDID not >> found >> > (it just ignored that before), and I tried just "flashrom", same thing. >> Now >> > that's a can of worm. It was 100% successful - verified and signed. Now >> I am >> > somewhat confused. I may have to wait for a while (thankfully I still >> have a >> > Windows laptop so I could write up the report on progresses of the >> firmware >> > ROM.) >> >> the 4 byte RDID warnings should not matter. the chip you have does not >> need it. it is just printed for other chips that are probed for by >> flashrom. you can use the -c <chipname> parameter to probe for the >> correct chip only. regarding the lockup i can't say much without a log, >> but that it should not happen. :) does it reliably happen while probing >> for the same chip or is it (seemingly) random? could you also please >> define "froze" precisely? is it flashrom alone or the whole OS etc? >> >> -- >> Kind regards/Mit freundlichen Grüßen, Stefan Tauner >> > > > > -- > "Mamma-mia, there's Koopa troopa in Mushroom Kingdom!" > -- "Mamma-mia, there's Koopa troopa in Mushroom Kingdom!"

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Re: [flashrom] Update of Gigabyte GA-MA78GM-S2HP motherboard firmware switch
by Stefan Tauner 21 Aug '11

21 Aug '11

On Sun, 21 Aug 2011 07:27:02 -0600 Donovan Lavinder <drmario2007(a)gmail.com> wrote: > That's strange. I have tried rewriting the firmware so I COULD provide you > the text file... It froze after couple complaints of 4-byte RDID not found > (it just ignored that before), and I tried just "flashrom", same thing. Now > that's a can of worm. It was 100% successful - verified and signed. Now I am > somewhat confused. I may have to wait for a while (thankfully I still have a > Windows laptop so I could write up the report on progresses of the firmware > ROM.) the 4 byte RDID warnings should not matter. the chip you have does not need it. it is just printed for other chips that are probed for by flashrom. you can use the -c <chipname> parameter to probe for the correct chip only. regarding the lockup i can't say much without a log, but that it should not happen. :) does it reliably happen while probing for the same chip or is it (seemingly) random? could you also please define "froze" precisely? is it flashrom alone or the whole OS etc? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Update of Gigabyte GA-MA78GM-S2HP motherboard firmware switch
by Stefan Tauner 21 Aug '11

21 Aug '11

On Sat, 20 Aug 2011 18:57:26 -0600 Donovan Lavinder <drmario2007(a)gmail.com> wrote: > After a day of struggling with bricked firmwares.... I finally ditched > FreeDOS. I went with SystemRescueCd distro and burnt coreboot precompiled > firmware under the folder /gigabyte_ma78gm/ and the firmware WORKED! But now > I am stuck with funny firmware quirks (Windows XP crashing when booting > halfway, almost to the point the video card driver is loaded, right after > "GIVEIO.SYS" driver is being loaded), even though it loaded Linux CD fine. I > guess I should try and ditch PS/2 mouse as it may probably be the cause of > strange behavior - I will be using USB mouse / keyboard as well. I am happy > with this firmware otherwise. And, the backup BIOS didn't even try to > intercept the Linux kernel in the firmware from loading. Thankfully. I will > eventually decide to recompile or "submit" the additional payloads such as > EFI and memtest86+ as those software will be needed in the future, after I > learn more of its capabilities. > > And, thanks for such a wonderful firmware! That thing's so fast! > congratulations :) this mail probably should have been sent to coreboot(a)coreboot.org though (too). btw could you provide a log of a successful flashrom write please? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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flashrom August 2011