June 2011 - flashrom - mail.coreboot.org

Re: [flashrom] [PATCH] Fix NULL pointer reference in board_flash_enable.
by Maciej Pijanka July 25, 2011

July 25, 2011

On Fri, 12 Mar 2010, Michael Karcher wrote: > Was introduced in r926. Found by Henrik Kretzschmar <henne(a)nachtwindheim.de>. > > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Imo looks sane and should be commited. Acked-by: Maciej Pijanka <maciej.pijanka(a)gmail.com> > --- > board_enable.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/board_enable.c b/board_enable.c > index aa463bc..0e89137 100644 > --- a/board_enable.c > +++ b/board_enable.c > @@ -1445,7 +1445,7 @@ int board_flash_enable(const char *vendor, const char *part) > if (!board) > board = board_match_pci_card_ids(); > > - if (board->status == NT) { > + if (board && board->status == NT) { > if (!force_boardenable) > { > printf("WARNING: Your mainboard is %s %s, but the mainboard-specific\n" > -- -- Maciej Pijanka I don't fear computers, I fear lack of them -- Isaac Asimov

2 1

Re: [flashrom] [PATCH 07/12] add ICH/PCH flash descriptor decoding
by Carl-Daniel Hailfinger July 20, 2011

July 20, 2011

Am 08.06.2011 04:55 schrieb Stefan Tauner: > based on the work of Matthias 'mazzoo' Wenzel this patch adds... > - pretty printing of those ICH/PCH flash descriptors that are cached/mapped by the chipset > (and which are therefore reachable via FDOC/FDOD registers) and > - a new tool to the util directory that is able to decode all flash descriptors stored in a flash > dump file. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > A slightly more verbose explanation would be nice. That said, I'll comment anyway so you have something to work with. > diff --git a/Makefile b/Makefile > index 6e6e2de..b61031f 100644 > --- a/Makefile > +++ b/Makefile > @@ -223,7 +223,7 @@ ifeq ($(CONFIG_INTERNAL), yes) > FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' > PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o > # FIXME: The PROGRAMMER_OBJS below should only be included on x86. > -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o > +PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o ich_descriptors.o sb600spi.o wbsio_spi.o mcp6x_spi.o > Maybe break this into multiple lines. > NEED_PCI := yes > endif > > diff --git a/ich_descriptors.c b/ich_descriptors.c > new file mode 100644 > index 0000000..0b03624 > --- /dev/null > +++ b/ich_descriptors.c > @@ -0,0 +1,453 @@ > +/* This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * authors: > + * (c) 2010 Matthias Wenzel <bios at mazzoo dot de> > + * (c) 2011 Stefan Tauner > Please use the same format as in other files, i.e. don't only use "(c)" but also add the word "Copyright". Rumor has it that even the order of "(c)" vs. "Copyright" is important for US law. No idea if that is true, but it can't hurt to do the same as everyone else. > + */ > + > +#include "ich_descriptors.h" > + > +#if defined(__i386__) || defined(__x86_64__) > + > +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP > + > +#define DESCRIPTOR_MODE_MAGIC 0x0ff0a55a > +#define msg_pdbg printf > +#include <stdio.h> > + > +struct flash_strap fisba; > +struct flash_upper_map flumap; > + > +#else > + > +#include "flash.h" /* for msg_* */ > + > +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP > + > +struct flash_descriptor fdbar = { 0 }; > +struct flash_component fcba = { {0} }; > +struct flash_region frba = { {0} }; > +struct flash_master fmba = { {0} }; > + > +uint32_t getFCBA() > Please use foo(void) for function declarations/definitions if no parameters are used. Same comment applies for all other functions of the same type. > +{ > + return (fdbar.FLMAP0 << 4) & 0x00000ff0; > +} > + > +uint32_t getFRBA() > +{ > + return (fdbar.FLMAP0 >> 12) & 0x00000ff0; > +} > + > +uint32_t getFMBA() > +{ > + return (fdbar.FLMAP1 << 4) & 0x00000ff0; > +} > + > +uint32_t getFMSBA() > +{ > + return (fdbar.FLMAP2 << 4) & 0x00000ff0; > +} > + > +uint32_t getFLREG_limit(uint32_t flreg) > +{ > + return (flreg >> 4) & 0x01fff000; > +} > + > +uint32_t getFLREG_base(uint32_t flreg) > +{ > + return (flreg << 12) & 0x01fff000; > +} > + > +uint32_t getFISBA() > +{ > + return (fdbar.FLMAP1 >> 12) & 0x00000ff0; > +} > + > +/** Returns the integer representation of the component density with index > +comp in bytes or 0 if a correct size can not be determined. */ > +int getFCBA_component_density(uint8_t comp) > +{ > + uint8_t size_enc; > + const int dec_mem[6] = { > + 512 * 1024, > + 1 * 1024 * 1024, > + 2 * 1024 * 1024, > + 4 * 1024 * 1024, > + 8 * 1024 * 1024, > + 16 * 1024 * 1024, > + }; > + > + switch(comp) { > + case 0: > + size_enc = fcba.comp1_density; > + break; > + case 1: > + if (fdbar.NC == 0) > + return 0; > + size_enc = fcba.comp2_density; > + break; > + default: > + msg_perr("Only component index 0 or 1 are supported yet.\n"); > + return 0; > + } > + if (size_enc > 5) { > + msg_perr("Density of component with index %d illegal or " > Please replace "illegal" with "invalid" everywhere. > + "unsupported. Encoded density is 0x%x.\n", > + comp, > Please kill this line break. > + size_enc); > + return 0; > + } > + return dec_mem[size_enc]; > +} > + > +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP > +uint32_t getVTBA() > +{ > + return (flumap.FLUMAP1 << 4) & 0x0ff0; > +} > +#endif > + > +const struct flash_descriptor_addresses desc_addr = { > + .FCBA = getFCBA, > + .FRBA = getFRBA, > + .FMBA = getFMBA, > + .FMSBA = getFMSBA, > + .FISBA = getFISBA, > + .FLREG_limit = getFLREG_limit, > + .FLREG_base = getFLREG_base, > +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP > + .VTBA = getVTBA, > +#endif > +}; > + > +void pretty_print_ich_descriptors() > +{ > + pretty_print_ich_descriptor_map(); > + pretty_print_ich_descriptor_component(); > + pretty_print_ich_descriptor_region(); > + pretty_print_ich_descriptor_master(); > +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP > + pretty_print_ich_descriptor_upper_map(); > + /* FIXME: detect chipset correctly */ > + pretty_print_ich_descriptor_straps(CHIPSET_SERIES_5_IBEX_PEAK); > +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP > + msg_pdbg("\n"); > +} > + > +void pretty_print_ich_descriptor_map(void) > +{ > + msg_pdbg("=== FDBAR ===\n"); > + msg_pdbg("FLVALSIG 0x%8.8x\n", fdbar.FLVALSIG); > + msg_pdbg("FLMAP0 0x%8.8x\n", fdbar.FLMAP0 ); > + msg_pdbg("FLMAP1 0x%8.8x\n", fdbar.FLMAP1 ); > + msg_pdbg("FLMAP2 0x%8.8x\n", fdbar.FLMAP2 ); > + msg_pdbg("\n"); > + msg_pdbg("--- FDBAR details ---\n"); > + msg_pdbg("0x%2.2x NR Number of Regions\n", fdbar.NR ); > + msg_pdbg("0x%8.8x FRBA Flash Region Base Address\n", desc_addr.FRBA() ); > + msg_pdbg("0x%2.2x NC Number of Components\n", fdbar.NC ); > + msg_pdbg("0x%8.8x FCBA Flash Component Base Address\n", desc_addr.FCBA() ); > + msg_pdbg("\n"); > + msg_pdbg("0x%2.2x ISL ICH Strap Length\n", fdbar.ISL ); > + msg_pdbg("0x%8.8x FISBA Flash ICH Strap Base Address\n", desc_addr.FISBA()); > + msg_pdbg("0x%2.2x NM Number of Masters\n", fdbar.NM ); > + msg_pdbg("0x%8.8x FMBA Flash Master Base Address\n", desc_addr.FMBA() ); > + msg_pdbg("\n"); > + msg_pdbg("0x%2.2x MSL MCH Strap Length\n", fdbar.MSL ); > + msg_pdbg("0x%8.8x FMSBA Flash MCH Strap Base Address\n", desc_addr.FMSBA()); > +} > + > +void pretty_print_ich_descriptor_component(void) > +{ > + const char * str_freq[8] = { > const char * const str_freq[8] = { > + "20 MHz", /* 000 */ > + "33 MHz", /* 001 */ > + "reserved/illegal", /* 010 */ > + "reserved/illegal", /* 011 */ > + "50 MHz", /* 100 */ > + "reserved/illegal", /* 101 */ > + "reserved/illegal", /* 110 */ > + "reserved/illegal" /* 111 */ > + }; > + const char * str_mem[8] = { > Same here. > + "512kB", > + "1 MB", > + "2 MB", > + "4 MB", > + "8 MB", > + "16 MB", > + "undocumented/illegal", > + "reserved/illegal" > + }; > + > + msg_pdbg("\n"); > + msg_pdbg("=== FCBA ===\n"); > + msg_pdbg("FLCOMP 0x%8.8x\n", fcba.FLCOMP); > + msg_pdbg("FLILL 0x%8.8x\n", fcba.FLILL ); > + msg_pdbg("\n"); > + msg_pdbg("--- FCBA details ---\n"); > + msg_pdbg("0x%2.2x freq_read_id %s\n", > + fcba.freq_read_id , str_freq[fcba.freq_read_id ]); > Out-of-bounds access if fcba.freq_read_id>=8 > + msg_pdbg("0x%2.2x freq_write %s\n", > + fcba.freq_write , str_freq[fcba.freq_write ]); > Same problem here. > + msg_pdbg("0x%2.2x freq_fastread %s\n", > + fcba.freq_fastread, str_freq[fcba.freq_fastread]); > And here. > + msg_pdbg("0x%2.2x fastread %ssupported\n", > + fcba.fastread, fcba.fastread ? "" : "not "); > + msg_pdbg("0x%2.2x freq_read %s\n", > + fcba.freq_read, str_freq[fcba.freq_read ]); > And here. > + msg_pdbg("0x%2.2x comp 1 density %s\n", > + fcba.comp1_density, str_mem[fcba.comp1_density]); > And here. > + if (fdbar.NC) > + msg_pdbg("0x%2.2x comp 2 density %s\n", > + fcba.comp2_density, str_mem[fcba.comp2_density]); > And here. > + else > + msg_pdbg("0x%2.2x comp 2 is not used (FLMAP0.NC=0)\n", > + fcba.comp2_density); > + msg_pdbg("\n"); > + msg_pdbg("0x%2.2x invalid instr 0\n", fcba.invalid_instr0); > + msg_pdbg("0x%2.2x invalid instr 1\n", fcba.invalid_instr1); > + msg_pdbg("0x%2.2x invalid instr 2\n", fcba.invalid_instr2); > + msg_pdbg("0x%2.2x invalid instr 3\n", fcba.invalid_instr3); > +} > + > +void pretty_print_ich_descriptor_region(void) > +{ > + msg_pdbg("\n"); > + msg_pdbg("=== FRBA ===\n"); > + msg_pdbg("FLREG0 0x%8.8x\n", frba.FLREG0); > + msg_pdbg("FLREG1 0x%8.8x\n", frba.FLREG1); > + msg_pdbg("FLREG2 0x%8.8x\n", frba.FLREG2); > + msg_pdbg("FLREG3 0x%8.8x\n", frba.FLREG3); > + msg_pdbg("\n"); > + msg_pdbg("--- FRBA details ---\n"); > + msg_pdbg("0x%8.8x region 0 limit (descr)\n", desc_addr.FLREG_limit(frba.FLREG0)); > + msg_pdbg("0x%8.8x region 0 base (descr)\n", desc_addr.FLREG_base(frba.FLREG0)); > + msg_pdbg("0x%8.8x region 1 limit ( BIOS)\n", desc_addr.FLREG_limit(frba.FLREG1)); > + msg_pdbg("0x%8.8x region 1 base ( BIOS)\n", desc_addr.FLREG_base(frba.FLREG1)); > + msg_pdbg("0x%8.8x region 2 limit ( ME )\n", desc_addr.FLREG_limit(frba.FLREG2)); > + msg_pdbg("0x%8.8x region 2 base ( ME )\n", desc_addr.FLREG_base(frba.FLREG2)); > + msg_pdbg("0x%8.8x region 3 limit ( GbE )\n", desc_addr.FLREG_limit(frba.FLREG3)); > + msg_pdbg("0x%8.8x region 3 base ( GbE )\n", desc_addr.FLREG_base(frba.FLREG3)); > +} > + > +void pretty_print_ich_descriptor_master(void) > +{ > + msg_pdbg("\n"); > + msg_pdbg("=== FMBA ===\n"); > + msg_pdbg("FLMSTR1 0x%8.8x\n", fmba.FLMSTR1); > + msg_pdbg("FLMSTR2 0x%8.8x\n", fmba.FLMSTR2); > + msg_pdbg("FLMSTR3 0x%8.8x\n", fmba.FLMSTR3); > + > + msg_pdbg("\n"); > + msg_pdbg("--- FMBA details ---\n"); > + msg_pdbg("BIOS can %s write GbE\n", fmba.BIOS_GbE_write ? " " : "NOT"); > + msg_pdbg("BIOS can %s write ME\n", fmba.BIOS_ME_write ? " " : "NOT"); > + msg_pdbg("BIOS can %s write BIOS\n", fmba.BIOS_BIOS_write ? " " : "NOT"); > + msg_pdbg("BIOS can %s write descr\n", fmba.BIOS_descr_write ? " " : "NOT"); > + msg_pdbg("BIOS can %s read GbE\n", fmba.BIOS_GbE_read ? " " : "NOT"); > + msg_pdbg("BIOS can %s read ME\n", fmba.BIOS_ME_read ? " " : "NOT"); > + msg_pdbg("BIOS can %s read BIOS\n", fmba.BIOS_BIOS_read ? " " : "NOT"); > + msg_pdbg("BIOS can %s read descr\n", fmba.BIOS_descr_read ? " " : "NOT"); > + msg_pdbg("ME can %s write GbE\n", fmba.ME_GbE_write ? " " : "NOT"); > + msg_pdbg("ME can %s write ME\n", fmba.ME_ME_write ? " " : "NOT"); > + msg_pdbg("ME can %s write BIOS\n", fmba.ME_BIOS_write ? " " : "NOT"); > + msg_pdbg("ME can %s write descr\n", fmba.ME_descr_write ? " " : "NOT"); > + msg_pdbg("ME can %s read GbE\n", fmba.ME_GbE_read ? " " : "NOT"); > + msg_pdbg("ME can %s read ME\n", fmba.ME_ME_read ? " " : "NOT"); > + msg_pdbg("ME can %s read BIOS\n", fmba.ME_BIOS_read ? " " : "NOT"); > + msg_pdbg("ME can %s read descr\n", fmba.ME_descr_read ? " " : "NOT"); > + msg_pdbg("GbE can %s write GbE\n", fmba.GbE_GbE_write ? " " : "NOT"); > + msg_pdbg("GbE can %s write ME\n", fmba.GbE_ME_write ? " " : "NOT"); > + msg_pdbg("GbE can %s write BIOS\n", fmba.GbE_BIOS_write ? " " : "NOT"); > + msg_pdbg("GbE can %s write descr\n", fmba.GbE_descr_write ? " " : "NOT"); > + msg_pdbg("GbE can %s read GbE\n", fmba.GbE_GbE_read ? " " : "NOT"); > + msg_pdbg("GbE can %s read ME\n", fmba.GbE_ME_read ? " " : "NOT"); > + msg_pdbg("GbE can %s read BIOS\n", fmba.GbE_BIOS_read ? " " : "NOT"); > + msg_pdbg("GbE can %s read descr\n", fmba.GbE_descr_read ? " " : "NOT"); > +} > + > +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP > +void pretty_print_ich_descriptor_straps_ich8(void) > +{ > + const char * str_GPIO12[4] = { > + "GPIO12", > + "LAN PHY Power Control Function (Native Output)", > + " GLAN_DOCK# (Native Input)", > Is the space before GLAN_DOCK# intentional? > + "invalid configuration", > + }; > + > + msg_pdbg("\n"); > + msg_pdbg("=== FISBA ===\n"); > + msg_pdbg("STRP0 0x%8.8x\n", fisba.ich8.STRP0); > + > + msg_pdbg("\n"); > + msg_pdbg("--- FISBA details ---\n"); > + msg_pdbg("ME SMBus addr2 0x%2.2x\n", fisba.ich8.ASD2); > + msg_pdbg("ME SMBus addr1 0x%2.2x\n", fisba.ich8.ASD); > + msg_pdbg("ME SMBus Controller is connected to %s\n", fisba.ich8.MESM2SEL ? "SMLink pins" : "SMBus pins"); > + msg_pdbg("SPI CS1 is used for %s\n", fisba.ich8.SPICS1_LANPHYPC_SEL ? "LAN PHY Power Control Function" : "SPI Chip Select"); > + msg_pdbg("GPIO12_SEL is used as %s\n", str_GPIO12[fisba.ich8.GPIO12_SEL]); > Out of bounds? > + msg_pdbg("PCIe Port 6 is used for %s\n", fisba.ich8.GLAN_PCIE_SEL ? "integrated GLAN" : "PCI Express"); > + msg_pdbg("Intel AMT SMBus Controller 1 is connected to %s\n", fisba.ich8.BMCMODE ? "SMLink" : "SMBus"); > + msg_pdbg("TCO slave is on %s. Intel AMT SMBus Controller 1 is %sabled\n", > + fisba.ich8.TCOMODE ? "SMBus" : "SMLink", fisba.ich8.TCOMODE ? "en" : "dis"); > + msg_pdbg("ME A is %sabled\n", fisba.ich8.ME_DISABLE ? "dis" : "en"); > + > + msg_pdbg("\n"); > + msg_pdbg("=== FMSBA ===\n"); > + msg_pdbg("STRP1 0x%8.8x\n", fisba.ich8.STRP1); > + > + msg_pdbg("\n"); > + msg_pdbg("--- FMSBA details ---\n"); > + msg_pdbg("ME B is %sabled\n", fisba.ich8.ME_disable_B ? "dis" : "en"); > +} > + > +void pretty_print_ich_descriptor_straps_ibex(void) > +{ > + int i; > + msg_pdbg("\n"); > + msg_pdbg("=== FPSBA ===\n"); > + for(i = 0; i <= 15; i++) > + msg_pdbg("STRP%-2d = 0x%8.8x\n", i, fisba.ibex.STRPs[i]); > +} > + > +void pretty_print_ich_descriptor_straps(enum chipset cs) > +{ > + switch (cs) { > + case CHIPSET_ICH8: > + pretty_print_ich_descriptor_straps_ich8(); > + break; > + case CHIPSET_SERIES_5_IBEX_PEAK: > + pretty_print_ich_descriptor_straps_ibex(); > + break; > + default: > + break; > + } > +} > + > +void pretty_print_ich_descriptor_upper_map(void) > +{ > + int i; > + msg_pdbg("\n"); > + msg_pdbg("=== FLUMAP ===\n"); > + msg_pdbg("FLUMAP1 0x%8.8x\n", flumap.FLUMAP1); > + > + msg_pdbg("\n"); > + msg_pdbg("--- FLUMAP details ---\n"); > + msg_pdbg("VTL 0x%8.8x\n", flumap.VTL); > + msg_pdbg("VTBA 0x%8.8x\n", desc_addr.VTBA()); > + msg_pdbg("\n"); > + > + for (i=0; i < flumap.VTL/2; i++) > + { > + msg_pdbg(" JID%d = 0x%8.8x\n", i, flumap.vscc_table[i].JID ); > Out of bounds if flumap.VTL contains garbage? > + msg_pdbg(" VSCC%d = 0x%8.8x\n", i, flumap.vscc_table[i].VSCC); > Out of bounds? > + } > +} > + > +int read_ich_descriptors_from_dump(uint32_t *dump) > +{ > + int i; > + uint8_t pch_bug_offset = 0; > + if (dump[0] != DESCRIPTOR_MODE_MAGIC) { > + if (dump[4] == DESCRIPTOR_MODE_MAGIC) > + pch_bug_offset = 4; > + else > + return -1; > + } > + > + /* map */ > + fdbar.FLVALSIG = dump[0 + pch_bug_offset]; > + fdbar.FLMAP0 = dump[1 + pch_bug_offset]; > + fdbar.FLMAP1 = dump[2 + pch_bug_offset]; > + fdbar.FLMAP2 = dump[3 + pch_bug_offset]; > Please either align with tabs or kill the alignment. If you think aligning with spaces is essential, please tell me why. > + > + /* component */ > + fcba.FLCOMP = dump[(desc_addr.FCBA() >> 2) + 0]; > + fcba.FLILL = dump[(desc_addr.FCBA() >> 2) + 1]; > + fcba.FLPB = dump[(desc_addr.FCBA() >> 2) + 2]; > Out of bounds? > + > + /* region */ > + frba.FLREG0 = dump[(desc_addr.FRBA() >> 2) + 0]; > + frba.FLREG1 = dump[(desc_addr.FRBA() >> 2) + 1]; > + frba.FLREG2 = dump[(desc_addr.FRBA() >> 2) + 2]; > + frba.FLREG3 = dump[(desc_addr.FRBA() >> 2) + 3]; > Out of bounds? > + > + /* master */ > + fmba.FLMSTR1 = dump[(desc_addr.FMBA() >> 2) + 0]; > + fmba.FLMSTR2 = dump[(desc_addr.FMBA() >> 2) + 1]; > + fmba.FLMSTR3 = dump[(desc_addr.FMBA() >> 2) + 2]; > Out of bounds? > + > + /* upper map */ > + flumap.FLUMAP1 = dump[(0x0efc >> 2) + 0]; > + > + for (i=0; i < flumap.VTL; i++) > + { > + flumap.vscc_table[i].JID = dump[(desc_addr.VTBA() >> 2) + i * 2 + 0]; > + flumap.vscc_table[i].VSCC = dump[(desc_addr.VTBA() >> 2) + i * 2 + 1]; > Out of bounds? > + } > + /* straps */ > + /* FIXME: detect chipset correctly */ > + switch (CHIPSET_SERIES_5_IBEX_PEAK) { > WTF? > + case CHIPSET_ICH8: > + fisba.ich8.STRP0 = dump[(desc_addr.FISBA() >> 2) + 0]; > + fisba.ich8.STRP1 = dump[(desc_addr.FMSBA() >> 2) + 0]; > Out of bounds? > + break; > + case CHIPSET_SERIES_5_IBEX_PEAK: > + for(i = 0; i <= 15; i++) > + fisba.ibex.STRPs[i] = dump[(desc_addr.FISBA() >> 2) + i]; > Out of bounds? > + break; > + default: > + break; > + } > + > + return 0; > +} > +#else // ICH_DESCRIPTORS_FROM_MMAP_DUMP > + > +static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) > +{ > + uint32_t control = 0; > + control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; > + control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; > + *(volatile uint32_t *) (spibar + ICH9_REG_FDOC) = control; > + return *(volatile uint32_t *)(spibar + ICH9_REG_FDOD); > +} > + > +void read_ich_descriptors_from_fdo(void *spibar) > +{ > + msg_pdbg("Reading flash descriptors " > + "mapped by the chipset via FDOC/FDOD..."); > + /* descriptor map section */ > + fdbar.FLVALSIG = read_descriptor_reg(0, 0, spibar); > + fdbar.FLMAP0 = read_descriptor_reg(0, 1, spibar); > + fdbar.FLMAP1 = read_descriptor_reg(0, 2, spibar); > + fdbar.FLMAP2 = read_descriptor_reg(0, 3, spibar); > Alignment with tabs... > + > + /* component section */ > + fcba.FLCOMP = read_descriptor_reg(1, 0, spibar); > + fcba.FLILL = read_descriptor_reg(1, 1, spibar); > + fcba.FLPB = read_descriptor_reg(1, 2, spibar); > + > + /* region section */ > + frba.FLREG0 = read_descriptor_reg(2, 0, spibar); > + frba.FLREG1 = read_descriptor_reg(2, 1, spibar); > + frba.FLREG2 = read_descriptor_reg(2, 2, spibar); > + frba.FLREG3 = read_descriptor_reg(2, 3, spibar); > + > + /* master section */ > + fmba.FLMSTR1 = read_descriptor_reg(3, 0, spibar); > + fmba.FLMSTR2 = read_descriptor_reg(3, 1, spibar); > + fmba.FLMSTR3 = read_descriptor_reg(3, 2, spibar); > + > + /* strap section and upper map */ > + /* impossible via FDOC/FDOD(?) */ > + msg_pdbg(" done\n"); > +} > + > +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP > +#endif // defined(__i386__) || defined(__x86_64__) > diff --git a/ich_descriptors.h b/ich_descriptors.h > new file mode 100644 > index 0000000..af9d0ba > --- /dev/null > +++ b/ich_descriptors.h > @@ -0,0 +1,408 @@ > +/* This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * authors: > + * (c) 2010 Matthias Wenzel <bios at mazzoo dot de> > + * (c) 2011 Stefan Tauner > + */ > + > +#include <stdint.h> > + > +#if defined(__i386__) || defined(__x86_64__) > +#ifndef __ICH_DESCRIPTORS_H__ > +#define __ICH_DESCRIPTORS_H__ 1 > + > +/* should probably be in ichspi.h */ > +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ > +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Select */ > +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) > +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ > +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) > +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ > + > +enum chipset { > + CHIPSET_ICH8, > + CHIPSET_ICH9, > + CHIPSET_ICH10, > + CHIPSET_SERIES_5_IBEX_PEAK, > + CHIPSET_SERIES_6_COUGAR_POINT, > + CHIPSET_SERIES_7_PANTHER_POINT > +}; > Are those all possible chipsets? > + > +struct flash_descriptor_addresses { > + uint32_t (*FCBA)(void); > + uint32_t (*FRBA)(void); > + uint32_t (*FMBA)(void); > + uint32_t (*FMSBA)(void); > + uint32_t (*FLREG_limit)(uint32_t flreg); > + uint32_t (*FLREG_base)(uint32_t flreg); > + uint32_t (*FISBA)(void); > +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP > + uint32_t (*VTBA)(void); > +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP > +}; > + > +struct flash_descriptor { > + uint32_t FLVALSIG; /* 0x00 */ > + union { /* 0x04 */ > + uint32_t FLMAP0; > + struct { > + uint8_t FCBA :8; > + uint8_t NC :2; > + unsigned :6; > + uint8_t FRBA :8; > + uint8_t NR :3; > + unsigned :5; > + }; > + }; > + union { /* 0x08 */ > + uint32_t FLMAP1; > + struct { > + uint8_t FMBA :8; > + uint8_t NM :3; > + unsigned :5; > + union { > + uint8_t FISBA :8; > + uint8_t FPSBA :8; > + }; > + uint8_t ISL :8; > + }; > + }; > + union { /* 0x0c */ > + uint32_t FLMAP2; > + struct { > + uint8_t FMSBA :8; > + uint8_t MSL :8; > + unsigned :16; > + }; > + }; > +}; > This won't fly. At the very least, it needs __attribute__((packed)), but even then I see pretty explosions because the bitfield ordering is implementation defined and I expect this to do the wrong thing if anyone ever runs that code on bigendian hosts (looking at a file is possible even if you don't have ICH SPI hardware). Heck, each gcc version could do something else. I might have misunderstood C99, so feel free to correct me. > + > +struct flash_component { > + union { /* 0x00 */ > + uint32_t FLCOMP; > + struct { > + uint8_t comp1_density :3; > + uint8_t comp2_density :3; > + unsigned :11; > + uint8_t freq_read :3; > + uint8_t fastread :1; > + uint8_t freq_fastread :3; > + uint8_t freq_write :3; > + uint8_t freq_read_id :3; > + unsigned :2; > + }; > + }; > + union { /* 0x04 */ > + uint32_t FLILL; > + struct { > + uint8_t invalid_instr0; > + uint8_t invalid_instr1; > + uint8_t invalid_instr2; > + uint8_t invalid_instr3; > + }; > + }; > + union { /* 0x08 */ > + uint32_t FLPB; > + struct { > + uint16_t FPBA :13; > + unsigned :19; > + }; > + }; > +}; > Same problem. > + > +struct flash_region { > + > + union { > + uint32_t FLREG0; /* Flash Descriptor */ > + struct { > + uint16_t reg0_base :13; > + unsigned :3; > + uint16_t reg0_limit :13; > + unsigned :3; > + }; > + }; > + union { > + uint32_t FLREG1; /* BIOS */ > + struct { > + uint16_t reg1_base :13; > + unsigned :3; > + uint16_t reg1_limit :13; > + unsigned :3; > + }; > + }; > + union { > + uint32_t FLREG2; /* ME */ > + struct { > + uint16_t reg2_base :13; > + unsigned :3; > + uint16_t reg2_limit :13; > + unsigned :3; > + }; > + }; > + union { > + uint32_t FLREG3; /* GbE */ > + struct { > + uint16_t reg3_base :13; > + unsigned :3; > + uint16_t reg3_limit :13; > + unsigned :3; > + }; > + }; > +} frba; > Dito. > + > +struct flash_master { > + union { > + uint32_t FLMSTR1; > + struct { > + uint16_t BIOS_req_ID :16; > + uint8_t BIOS_descr_read :1; > + uint8_t BIOS_BIOS_read :1; > + uint8_t BIOS_ME_read :1; > + uint8_t BIOS_GbE_read :1; > + uint8_t BIOS_plat_read :1; > + unsigned :3; > + uint8_t BIOS_descr_write :1; > + uint8_t BIOS_BIOS_write :1; > + uint8_t BIOS_ME_write :1; > + uint8_t BIOS_GbE_write :1; > + uint8_t BIOS_plat_write :1; > + unsigned :3; > + }; > + }; > + union { > + uint32_t FLMSTR2; > + struct { > + uint16_t ME_req_ID :16; > + uint8_t ME_descr_read :1; > + uint8_t ME_BIOS_read :1; > + uint8_t ME_ME_read :1; > + uint8_t ME_GbE_read :1; > + uint8_t ME_plat_read :1; > + unsigned :3; > + uint8_t ME_descr_write :1; > + uint8_t ME_BIOS_write :1; > + uint8_t ME_ME_write :1; > + uint8_t ME_GbE_write :1; > + uint8_t ME_plat_write :1; > + unsigned :3; > + }; > + }; > + union { > + uint32_t FLMSTR3; > + struct { > + uint16_t GbE_req_ID :16; > + uint8_t GbE_descr_read :1; > + uint8_t GbE_BIOS_read :1; > + uint8_t GbE_ME_read :1; > + uint8_t GbE_GbE_read :1; > + uint8_t GbE_plat_read :1; > + unsigned :3; > + uint8_t GbE_descr_write :1; > + uint8_t GbE_BIOS_write :1; > + uint8_t GbE_ME_write :1; > + uint8_t GbE_GbE_write :1; > + uint8_t GbE_plat_write :1; > + unsigned :3; > + }; > + }; > +}; > Dito. > + > +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP > +struct flash_strap { > + union { > + struct { > + union { > + uint32_t STRP0; > + struct { > + uint8_t ME_DISABLE :1; > + unsigned :6; > + uint8_t TCOMODE :1; > + uint8_t ASD :7; > + uint8_t BMCMODE :1; > + unsigned :3; > + uint8_t GLAN_PCIE_SEL :1; > + uint8_t GPIO12_SEL :2; > + uint8_t SPICS1_LANPHYPC_SEL :1; > + uint8_t MESM2SEL :1; > + unsigned :1; > + uint8_t ASD2 :7; > + }; > + }; > + union { > + uint32_t STRP1; > + struct { > + uint8_t ME_disable_B :1; > + unsigned :31; > + }; > + }; > + }ich8; > + union { > + uint32_t STRPs[15]; > + struct { > + union { > + uint32_t STRP0; > + struct { > + unsigned :1; > + uint8_t cs_ss2 :1; > + unsigned :5; > + uint8_t SMB_EN :1; > + uint8_t SML0_EN :1; > + uint8_t SML1_EN :1; > + uint8_t SML1FRQ :2; > + uint8_t SMB0FRQ :2; > + uint8_t SML0FRQ :2; > + unsigned :4; > + uint8_t LANPHYPC_GP12_SEL :1; > + uint8_t cs_ss1 :1; > + unsigned :2; > + uint8_t DMI_REQID_DIS :1; > + unsigned :4; > + uint8_t BBBS :2; > + unsigned :1; > + }; > + }; > + union { > + uint32_t STRP1; > + struct { > + }; > Why an empty struct? > + }; > + union { > + uint32_t STRP2; > + struct { > + }; > Dito. > + }; > + union { > + uint32_t STRP3; > + struct { > + }; > + }; > You get the point. > + union { > + uint32_t STRP4; > + struct { > + }; > + }; > + union { > + uint32_t STRP5; > + struct { > + }; > + }; > + union { > + uint32_t STRP6; > + struct { > + }; > + }; > + union { > + uint32_t STRP7; > + struct { > + }; > + }; > + union { > + uint32_t STRP8; > + struct { > + }; > + }; > + union { > + uint32_t STRP9; > + struct { > + }; > + }; > + union { > + uint32_t STRP10; > + struct { > + }; > + }; > + union { > + uint32_t STRP11; > + struct { > + }; > + }; > + union { > + uint32_t STRP12; > + struct { > + }; > + }; > + union { > + uint32_t STRP13; > + struct { > + }; > + }; > + union { > + uint32_t STRP14; > + struct { > + }; > + }; > + union { > + uint32_t STRP15; > + struct { > + }; > + }; > + }; > + }ibex; > + }; > +}; > __attribute__((packed)) > + > +struct flash_upper_map { > + union { > + uint32_t FLUMAP1; > + struct { > + uint8_t VTBA :8; > + uint8_t VTL :8; > + unsigned :16; > + }; > + }; > + struct { > + union { > + uint32_t JID; > + struct { > + uint8_t vid :8; > + uint8_t cid0 :8; > + uint8_t cid1 :8; > + unsigned :8; > + }; > + }; > + union { > + uint32_t VSCC; > + struct { > + uint8_t ubes :2; > + uint8_t uwg :1; > + uint8_t uwsr :1; > + uint8_t uwews :1; > + unsigned :3; > + uint8_t ueo :8; > + uint8_t lbes :2; > + uint8_t lwg :1; > + uint8_t lwsr :1; > + uint8_t lwews :1; > + unsigned :3; > + uint16_t leo :16; > + }; > + }; > + }vscc_table[128]; > +}; > Dito. > +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP > + > +void pretty_print_ich_descriptors(void); > + > +void pretty_print_ich_descriptor_map(void); > +void pretty_print_ich_descriptor_component(void); > +void pretty_print_ich_descriptor_region(void); > +void pretty_print_ich_descriptor_master(void); > + > +int getFCBA_component_density(uint8_t comp); > + > +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP > + > +void pretty_print_ich_descriptor_upper_map(void); > +void pretty_print_ich_descriptor_straps(enum chipset cs); > +int read_ich_descriptors_from_dump(uint32_t *dump); > + > +#else // ICH_DESCRIPTORS_FROM_MMAP_DUMP > + > +void read_ich_descriptors_from_fdo(void *spibar); > + > +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP > + > +#endif // __ICH_DESCRIPTORS_H__ > +#endif // defined(__i386__) || defined(__x86_64__) > diff --git a/ichspi.c b/ichspi.c > index 584cab4..d8df898 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -6,6 +6,7 @@ > * Copyright (C) 2008 Dominik Geyer <dominik.geyer(a)kontron.com> > * Copyright (C) 2008 coresystems GmbH <info(a)coresystems.de> > * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger > + * Copyright (C) 2011 Stefan Tauner > * > * This program is free software; you can redistribute it and/or modify > * it under the terms of the GNU General Public License as published by > @@ -41,6 +42,7 @@ > #include "chipdrivers.h" > #include "programmer.h" > #include "spi.h" > +#include "ich_descriptors.h" > > /* ICH9 controller register definition */ > #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ > @@ -1197,6 +1199,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > uint8_t old, new; > uint16_t spibar_offset, tmp2; > uint32_t tmp; > + int ichspi_desc = 0; > > switch (ich_generation) { > case 7: > @@ -1268,6 +1271,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); > ichspi_lock = 1; > } > + if (tmp2 & HSFS_FDV) > + ichspi_desc = 1; > > tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); > msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); > @@ -1316,6 +1321,11 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); > msg_pdbg("0xA0: 0x%08x (BBAR)\n", > ichspi_bbar); > + msg_pdbg("\n"); > + if (ichspi_desc) { > + read_ich_descriptors_from_fdo(ich_spibar); > + pretty_print_ich_descriptors(); > + } > ich_init_opcodes(); > break; > default: > diff --git a/util/ich_descriptors_tool/Makefile b/util/ich_descriptors_tool/Makefile > new file mode 100644 > index 0000000..9b1d096 > --- /dev/null > +++ b/util/ich_descriptors_tool/Makefile > @@ -0,0 +1,42 @@ > +CC ?= gcc > + > +PROGRAM=ich_descriptors_tool > +EXTRAINCDIRS = ../../ . > +DEPPATH = .dep > +OBJATH = .obj > +SHAREDSRC = ich_descriptors.c > +SHAREDSRCDIR = ../.. > + > +SRC = $(wildcard *.c) > + > +CFLAGS=-Wall > +CFLAGS += -MMD -MP -MF $(DEPPATH)/$((a)F).d > +# enables functions that populate the descriptor structs from plain dump arrays > +CFLAGS += -D ICH_DESCRIPTORS_FROM_MMAP_DUMP > +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) > + > +OBJ = $(OBJATH)/$(SRC:%.c=%.o) > + > +SHAREDOBJ = $(OBJATH)/$(notdir $(SHAREDSRC:%.c=%.o)) > + > +all:$(PROGRAM) > + > +$(OBJ): $(OBJATH)/%.o : %.c > + $(CC) $(CFLAGS) -o $@ -c $< > + > +# this enables us to NOT share object files with flashrom, > +# which would lead to unexpected results otherwise (w/o running make clean) > +$(SHAREDOBJ): $(OBJATH)/%.o : $(SHAREDSRCDIR)/%.c > + $(CC) $(CFLAGS) -o $@ -c $< > + > +$(PROGRAM): $(OBJ) $(SHAREDOBJ) > + $(CC) -o $(PROGRAM) $(OBJ) $(SHAREDOBJ) > + > +clean: > + rm -f $(PROGRAM) > + rm -rf $(DEPPATH) $(OBJATH) > + > +# Include the dependency files. > +-include $(shell mkdir -p $(DEPPATH) $(OBJATH) 2>/dev/null) $(wildcard $(DEPPATH)/*) > + > +.PHONY: all clean > \ No newline at end of file > A newline at the end of the file would be nice. > diff --git a/util/ich_descriptors_tool/TODO b/util/ich_descriptors_tool/TODO > new file mode 100644 > index 0000000..e3933ee > --- /dev/null > +++ b/util/ich_descriptors_tool/TODO > @@ -0,0 +1,5 @@ > +- reverse the path, as in assemble a descriptormode image from various > + blobs (BIOS, GbE, ME, OEM) and a description (xml? custom config? > + sane defaults and cmd-line switches?) > +- dump 256 OEM bytes > +- handle descriptors of various chipsets correctly > \ No newline at end of file > diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c > new file mode 100644 > index 0000000..8ce7677 > --- /dev/null > +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c > @@ -0,0 +1,226 @@ > +/* > + * dump information and binaries from BIOS images that are in descriptor mode/soft-strap > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * authors: > + * (c) 2010 Matthias Wenzel <bios at mazzoo dot de> > + * (c) 2011 Stefan Tauner > + * > + * */ > +#include <stdio.h> > +#include <stdint.h> > +#include <stdlib.h> > +#include <sys/mman.h> > +#include <sys/types.h> > +#include <sys/stat.h> > +#include <fcntl.h> > +#include <unistd.h> > +#include <string.h> > +#include <errno.h> > +#include "flash.h" > +#include "ich_descriptors.h" > + > +extern struct flash_descriptor fdbar; > +extern struct flash_component fcba; > +extern struct flash_region frba; > +extern struct flash_master fmba; > +extern struct flash_strap fisba; > +extern struct flash_upper_map flumap; > +extern struct flash_descriptor_addresses desc_addr; > + > +static int f; /* file descriptor to flash file */ > +static int fs; /* file size */ > +static uint32_t *fm; /* mmap'd file */ > + > +void dump_file_descriptor(char * fn) > +{ > + char * n = malloc(strlen(fn) + 11); > + snprintf(n, strlen(fn) + 11, "%s.descr.bin", fn); > + printf("\n"); > + printf("+++ dumping %s ... ", n); > + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); > + free(n); > + if (fh < 0) > + { > + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); > + exit(1); > + } > + > + int ret; > + ret = write(fh, &fm[frba.reg0_base >> 2], frba.reg0_limit); > + if (ret != frba.reg0_limit) > + { > + printf("FAILED.\n"); > + exit(1); > + } > + > + printf("done.\n"); > + > + close(fh); > +} > + > +void dump_file_BIOS(char * fn) > +{ > + char * n = malloc(strlen(fn) + 10); > + snprintf(n, strlen(fn) + 10, "%s.BIOS.bin", fn); > + printf("\n"); > + printf("+++ dumping %s ... ", n); > + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); > + free(n); > + if (fh < 0) > + { > + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); > + exit(1); > + } > + > + int ret; > + ret = write(fh, &fm[frba.reg1_base >> 2], frba.reg1_limit); > + if (ret != frba.reg1_limit) > + { > + printf("FAILED.\n"); > + exit(1); > + } > + > + printf("done.\n"); > + > + close(fh); > +} > + > +void dump_file_ME(char * fn) > +{ > + char * n = malloc(strlen(fn) + 8); > + snprintf(n, strlen(fn) + 8, "%s.ME.bin", fn); > + printf("\n"); > + printf("+++ dumping %s ... ", n); > + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); > + free(n); > + if (fh < 0) > + { > + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); > + exit(1); > + } > + > + int ret; > + ret = write(fh, &fm[frba.reg2_base >> 2], frba.reg2_limit); > + if (ret != frba.reg2_limit) > + { > + printf("FAILED.\n"); > + exit(1); > + } > + > + printf("done.\n"); > + > + close(fh); > +} > + > +void dump_file_GbE(char * fn) > +{ > + char * n = malloc(strlen(fn) + 9); > + snprintf(n, strlen(fn) + 9, "%s.GbE.bin", fn); > + printf("\n"); > + printf("+++ dumping %s ... ", n); > + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); > + free(n); > + if (fh < 0) > + { > + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); > + exit(1); > + } > + > + int ret; > + ret = write(fh, &fm[frba.reg3_base >> 2], frba.reg3_limit); > + if (ret != frba.reg3_limit) > + { > + printf("FAILED.\n"); > + exit(1); > + } > + > + printf("done.\n"); > + uint8_t * pMAC = (uint8_t *) &fm[frba.reg3_base >> 2]; > + printf("the MAC-address might be: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", > + pMAC[0], > + pMAC[1], > + pMAC[2], > + pMAC[3], > + pMAC[4], > + pMAC[5] > + ); > + > + close(fh); > +} > + > +void dump_files(char * n) > +{ > + printf("=== dumping section files ===\n"); > + if (frba.reg0_limit) > + dump_file_descriptor(n); > + if (frba.reg1_limit) > + dump_file_BIOS(n); > + if (frba.reg2_limit) > + dump_file_ME(n); > + if (frba.reg3_limit) > + dump_file_GbE(n); > +} > + > +void usage(char ** argv, char* error) > +{ > + printf("%s\n", error); > + printf("\n"); > + printf("usage: '%s <bios image file> [-d]'\n", argv[0]); > + printf("\n"); > + printf("\twhere <bios image file> isn't actually a BIOS image, but the SPI flash\n"); > + printf("\tcontents of the SPI connected to your intel chipset.\n"); > + printf("\tIn case that image is really in descriptor mode (a.k.a soft-strap)\n"); > + printf("\t%s will pretty print all relevant information.\n", argv[0]); > + printf("\tIf '-d' is specified as the second parameter some sections such as\n"); > + printf("\tthe real BIOS image as seen by the CPU or a GbE blob that is\n"); > + printf("\trequired to initialize your ICH GbE are also dumped to files.\n"); > + exit(1); > +} > + > +int main(int argc, char **argv) > +{ > + if (argc < 2) > + usage(argv, "Need at least one parameter"); > + f = open(argv[1], O_RDONLY); > + if (f < 0) > + usage(argv, "No such file"); > + if (argc >= 3 && (strcmp("-d", argv[2]) == 0)) > + usage(argv, "Bogus second argument"); > + > + fs = lseek(f, 0, SEEK_END); > + if (fs < 0) > + usage(argv, "Seeking to the end of the file failed"); > + > + fm = mmap(NULL, fs, PROT_READ, MAP_PRIVATE, f, 0); > + if (fm == (void *) -1) > + { > + /* fallback for stupid OSes like cygwin */ > + int ret; > + fm = malloc(fs); > + if (!fm) > + usage(argv, "Could not allocate memory"); > + lseek(f, 0, SEEK_SET); > + ret = read(f, fm, fs); > + if (ret != fs) > + usage(argv, "Seeking to the end of the file failed"); > + } > + printf("flash image is %d [0x%x] bytes\n", fs, fs); > + close(f); > + > + if(read_ich_descriptors_from_dump(fm)){ > + printf("not in descriptor mode\n"); > + exit(1); > + } > + > + pretty_print_ich_descriptors(); > + > + if (argc >= 3) > + dump_files(argv[1]); > + > + return 0; > +} > + > Regards, Carl-Daniel -- http://www.hailfinger.org/

3 4

ASUS A8N-VM CSM: FAILURE
by Bernie Innocenti July 20, 2011

July 20, 2011

Moreover, I get a segfault just after the third "ERASE FAILED!" line. Verify against the old BIOS now fails (it used to pass). I have not yet tried to reboot, but chances are good that the ROM has been trashed. -- Bernie Innocenti Systems Administrator, Free Software Foundation

2 2

MSI K9A2 Platinum OK
by Sylvain BERTRAND July 12, 2011

July 12, 2011

Hi, Successfully flashed BIOS v1.9 on this motherboard. Cheers, Sylvain BERTRAND

2 2

Re: [flashrom] Help: trouble when flashing rom
by Idwer Vollering July 9, 2011

July 9, 2011

Please use "reply to all" in the future. Thanks. 2011/4/19 Cyrille Bartholomée <cyrille(a)bartholomee.com>: > Dear Idwer, > > Just built checkout from svn. It outputs this result: Again: DO NOT REBOOT OR POWEROFF YOUR LAPTOP. > > flashrom v0.9.3-r1288 on Linux 2.6.35-28-generic (i686), built with libpci > 3.1.7, GCC 4.4.5, little endian > > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... delay loop is unreliable, trying to continue OK. > > Found chipset "Intel ICH4-M", enabling flash write... OK. > > This chipset supports the following protocols: FWH. > > Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. > > Flash image seems to be a legacy BIOS. Disabling checks. > > Erasing and writing flash chip... ERASE FAILED at 0x00016000! Expected=0xff, > Read=0xae, failed byte count from 0x00016000-0x00016fff: 0xfde > > ERASE FAILED! > > ERASE FAILED at 0x00010000! Expected=0xff, Read=0xca, failed byte count from > 0x00010000-0x0001ffff: 0xfeb2 > > ERASE FAILED! > > Segmentatiefout > > Segmentatiefout=segmentation error flashrom should NOT have segfaulted. Can you show the last lines of dmesg (dmesg | tail) ? > > Maybe this information can help you? > > Regards, > > Cyrille Bartholomée | De Damhouderestraat 20 | 2018 Antwerpen > > t. 0032 3 298 4244 | m. 0032 499 711 018 | e. cyrille(a)bartholomee.com > > Op dinsdag 19 april 2011 07:25:59 schreef Cyrille Bartholomée: > >> Dear Idwer, > >> > >> > >> First of all thank you for responding so fast and trying to help me! > >> > >> 1. Downloaded and built latest flashrom. Problem remains exactly the same >> as with previous version. > >> 2. I am using an Asus laptop model M6Ne, the exact type of board I don't >> know. > >> 3. I have run the commands you mentioned, the results are attached to this >> mail. > >> > >> If there is more information you need, please let me know. > >> > >> Again, thanks for your help. > >> > >> > >> Kind regards, > >> > >> Cyrille Bartholomée | De Damhouderestraat 20 | 2018 Antwerpen > >> t. 0032 3 298 4244 | m. 0032 499 711 018 | e. cyrille(a)bartholomee.com > >> > >> Op dinsdag 19 april 2011 00:21:28 schreef u: > >> > 2011/4/18 Cyrille Bartholomée <cyrille(a)bartholomee.com>: > >> > > Dear, > >> > > > >> > > I'm facing this problem when flashing my rom: > >> > > > >> > > flashrom v0.9.2-r1028 on Linux 2.6.35-28-generic (i686), built with >> > > libpci > >> > > 3.0.0, GCC 4.4.4, little endian > >> > > > >> > > flashrom is free software, get the source code at >> > > http://www.flashrom.org > >> > > > >> > > Calibrating delay loop... delay loop is unreliable, trying to continue >> > > OK. > >> > > > >> > > No coreboot table found. > >> > > > >> > > Found chipset "Intel ICH4-M", enabling flash write... OK. > >> > > > >> > > This chipset supports the following protocols: Non-SPI. > >> > > > >> > > Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address >> > > 0xfff80000. > >> > > > >> > > Flash image seems to be a legacy BIOS. Disabling checks. > >> > > > >> > > Writing flash chip... Erasing flash chip... ERASE FAILED at >> > > 0x00000008! > >> > > Expected=0xff, Read=0x00, failed byte count from >> > > 0x00000000-0x00000fff: > >> > > 0xfc5 > >> > > > >> > > ERASE FAILED! > >> > > > >> > > ERASE FAILED at 0x00000008! Expected=0xff, Read=0x00, failed byte >> > > count from > >> > > 0x00000000-0x0000ffff: 0xfadb > >> > > > >> > > ERASE FAILED! > >> > > > >> > > FAILED! > >> > > > >> > > ERASE FAILED! > >> > > > >> > > FAILED! > >> > > > >> > > Your flash chip is in an unknown state. > >> > > > >> > > Get help on IRC at irc.freenode.net (channel #flashrom) or > >> > > > >> > > mail flashrom(a)flashrom.org! > >> > > >> > Can you: > >> > - try a newer release (or build the latest developemt code yourself > >> > http://www.flashrom.org/Downloads#Installation_from_source) > >> > - mention the exact name of your board (including revision, if there > >> > are multiple revisions) > >> > - attach the output of 'flashrom -V', 'lspci -nnvvvxxx', 'superiotool > >> > -deV' (run all commands as root) > >> > > >> > > >> > Thanks in advance, > >> > Idwer > >> > > >> > > > >> > > >> > > ------------------------------------------------------------------------------- > >> > > > >> > > DO NOT REBOOT OR POWEROFF! > >> > > > >> > > Regards, > >> > > > >> > > Cyrille Bartholomée | De Damhouderestraat 20 | 2018 Antwerpen > >> > > > >> > > t. 0032 3 298 4244 | m. 0032 499 711 018 | e. cyrille(a)bartholomee.com > >> > > > >> > > _______________________________________________ > >> > > flashrom mailing list > >> > > flashrom(a)flashrom.org > >> > > http://www.flashrom.org/mailman/listinfo/flashrom > >> > > > >> > > >>

3 10

Re: [flashrom] [PATCH 4/8] ichspi.c: preserve reserved bits in address registers
by Carl-Daniel Hailfinger July 7, 2011

July 7, 2011

Am 28.06.2011 05:33 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Makes sense, but I worry that this might eventually break something. Do we (want to) report the inital address setting during programmer init, especially the reserved bits? Anyway, this is Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

3 2

Re: [flashrom] [Patch] NVIDIA Tegra2 SPI controller support
by Carl-Daniel Hailfinger July 7, 2011

July 7, 2011

Am 28.06.2011 01:52 schrieb David Hendricks: > This patch set makes Flashrom a bit more ARM-friendly and adds raw Tegra2 > SPI controller support. It isolates a few PCI-isms, adds some low-level > hardware access stubs, adds Tegra2 processor detection, and adds Tegra2 raw > SPI controller code. > Nice! > I've attached some logfiles for read/erase/write operations. This particular > patch set was tested using a board based off NVIDIA's Tegra2 reference board > ("Seaboard"). Earlier revisions were tested on a Seaboard. > > All three attached patches are: > Signed-off-by: David Hendricks <dhendrix(a)google.com> > > Much of the original U-Boot --> Flashrom porting work was done by Stefan > Reinauer <reinauer(a)google.com>, and the FIFO code updated / fixed up by > Louis Lo <yjlou(a)google.com>. > > A few notes: > 1. A few programmers must be disabled due to reliance on PCI. You can hack > up your Makefile or compile with "CONFIG_RAYER_SPI=no CONFIG_NIC3COM=no > CONFIG_NICREALTEK=no CONFIG_SATAMV=no". > Actually, it is a requirement for PCI port I/O space (well, the non-memmapped space specified in the PCI standard, usually accesses with in[bwl]/out[bwl] functions). We ought to detect unavailability of that at compile time, preferably in the Makefile. > 2. Due to issues with libpci, you can't use the same binary on machines with > PCI and without PCI. So for example, you can't program a SPI ROM onboard a > PCI card that is connected to your ARM SoC. > Could you explain more? IIRC some people were using flashrom on ARM (independent patch) with PCI support. Not calling any PCI functions should be enough to avoid any and all interactions between libpci and the hardware. > 4. The tegra2_spi code was originally contributed by NVIDIA to the Chromium > OS U-Boot<http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=blob;…> > branch > and was later grafted into Flashrom so we could more easily perform SPI ROM > updates from userspace. Please excuse minor style inconsistencies as we are > trying to stay reasonably close to the code checked into the U-Boot tree ;-) > Ah, that explains some of the quirks I saw. Could you explain the Tegra2 hardware a bit more? The code suggests that it is more or less a slightly intelligent bitbanging controller with a "special" programing interface. At a first glance, the following issues stick out: 1-3-isolate_pci_isms.patch This essentially declares ARM a no-PCI zone. That's OK for testing, but not for merge. What exactly is the problem with PCI probing here? Does it return errors? Does it crash or terminate the application? Does it mess with the machine in ways which might cause breakage? 2-3-add_arm_isms.patch Have you checked with an architecture guru that sync_primitive() can really be empty, not only for that arch in general, but also for accesses to a mmapped region the way flashrom does it? 3-3-add_tegra2_spi_controller.patch Not your fault, but we really need a way to detect the target architecture in the Makefile. The issues of which SPI masters to include for internal exists on all architectures. Any ideas? I experimented with uname calls in the past, but that checks the host arch, not the target arch. Grepping the preprocessor output for the compiler might be an option. echo|gcc -dM -E -|grep "whatever\|arch\|defines" Or you try this pretty straightforward solution: Create a file arch.h with these contents: #if defined (__i386__) #define __FLASHROM_ARCH__ "x86" #elif defined (__x86_64__) #define __FLASHROM_ARCH__ "x86_64" #elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) #define __FLASHROM_ARCH__ "mips" #elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) #define __FLASHROM_ARCH__ "ppc" #endif __FLASHROM_ARCH__ Then run gcc -E arch.h|grep -v ^# The result on my machine will be "x86" Side note: Such an arch.h file (with some extensions) might save us from having to check every possible arch define everywhere we need to differentiate between architectures. I will comment on the Tegra2 SPI driver later, we should get the infrastructure questions addressed first. Regards, Carl-Daniel -- http://www.hailfinger.org/

3 2

Re: [flashrom] [PATCH 3/3] add support for SFDP (JESD216)
by Carl-Daniel Hailfinger July 1, 2011

July 1, 2011

Am 24.06.2011 16:53 schrieb Stefan Tauner: > Similar to ICH Hardware Sequencing this uses a generic struct flashchip > element in flashrom.c with dummy values and a special probe function that fills the > obtained values into that generic struct. > Documentation used: > http://www.jedec.org/standards-documents/docs/jesd216 (2011-04) > W25Q32BV data sheet Revision F (2011-04-01) > EN25QH16 data sheet Revision F (2011-06-01) > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Nice feature. > --- > chipdrivers.h | 1 + > flashchips.c | 24 +++++ > flashchips.h | 1 + > flashrom.c | 28 ++++++- > spi.h | 5 + > spi25.c | 273 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > 6 files changed, 331 insertions(+), 1 deletions(-) > > diff --git a/chipdrivers.h b/chipdrivers.h > index 92ddbea..0a3df50 100644 > --- a/chipdrivers.h > +++ b/chipdrivers.h > @@ -26,6 +26,7 @@ > #define __CHIPDRIVERS_H__ 1 > > /* spi.c, should probably be in spi_chip.c */ > +int probe_spi_sfdp(struct flashchip *flash); > int probe_spi_rdid(struct flashchip *flash); > int probe_spi_rdid4(struct flashchip *flash); > int probe_spi_rems(struct flashchip *flash); > diff --git a/flashchips.c b/flashchips.c > index 865ba2f..6fbbd2c 100644 > --- a/flashchips.c > +++ b/flashchips.c > @@ -8507,6 +8507,30 @@ const struct flashchip flashchips[] = { > .write = write_jedec_1, > .read = read_memmapped, > }, > + > + { > + .vendor = "Unknown", > + .name = "SFDP device", > + .bustype = CHIP_BUSTYPE_SPI, > + .manufacture_id = GENERIC_MANUF_ID, > + .model_id = SFDP_DEVICE_ID, > + /* We present our own "report this" text hence we do not > + * want the default "This flash part has status UNTESTED..." > + * text to be printed. */ > + .tested = TEST_OK_PREW, > + .probe = probe_spi_sfdp, > + .page_size = 256, > + .write = spi_chip_write_256, > Does SFDP really specify 256-byte write capability? > + .read = spi_chip_read, > + /* FIXME: some vendor extensions define this */ > + .voltage = {}, > + /* Everything below will be set by the probing function. */ > + .total_size = 0, > + .feature_bits = 0, > + .block_erasers = {}, > + .unlock = NULL, > + .printlock = NULL, > + }, > > { > .vendor = "AMIC", > diff --git a/flashchips.h b/flashchips.h > index 3b2b94f..82333c8 100644 > --- a/flashchips.h > +++ b/flashchips.h > @@ -36,6 +36,7 @@ > > #define GENERIC_MANUF_ID 0xffff /* Check if there is a vendor ID */ > #define GENERIC_DEVICE_ID 0xffff /* Only match the vendor ID */ > +#define SFDP_DEVICE_ID 0xfffe > Just a comment, not something that needs to be changed: We probably need CFI_DEVICE_ID as well once we support CFI (which is SFDP for non-SPI flash). > > #define ALLIANCE_ID 0x52 /* Alliance Semiconductor */ > #define ALLIANCE_AS29F002B 0x34 > diff --git a/flashrom.c b/flashrom.c > index aed10aa..56af373 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -1206,7 +1206,33 @@ int probe_flash(int startchip, struct flashchip *fill_flash, int force) > * probe_flash() is the first one and thus no chip has been > * found before. > */ > - if (startchip == 0 || fill_flash->model_id != GENERIC_DEVICE_ID) > + if (startchip == 0 && fill_flash->model_id == SFDP_DEVICE_ID) { > + msg_cinfo("===\n" > + "SFDP has autodetected a flash chip which is " > + "not natively supported by flashrom yet.\n"); > + if (!check_block_erasers(flash, 0)) > + msg_cinfo("The standard operations read and " > + "verify should work, but to support " > + "erase, write and all other " > + "possible features"); > + else > + msg_cinfo("All standard operations (read, " > + "verify, erase and write) should " > + "work, but to support all possible " > + "features"); > + > + msg_cinfo(" we need to add them manually.\nYou " > + "can help us by mailing us the output of " > + "the following command to flashrom@flashrom." > + "org: \n'flashrom -VV [plus the " > + "-p/--programmer parameter (if needed)]" > + "'\nThanks for your help!\n" > + "===\n"); > + } > Should we refactor those SFDP messages into a separate function and do that for the untested chip messages as well? It would probably improve code readability here. > + > + if (startchip == 0 || > + ((fill_flash->model_id != GENERIC_DEVICE_ID) && > + (fill_flash->model_id != SFDP_DEVICE_ID))) > break; > > notfound: > diff --git a/spi.h b/spi.h > index b908603..5f07eae 100644 > --- a/spi.h > +++ b/spi.h > @@ -40,6 +40,11 @@ > #define JEDEC_REMS_OUTSIZE 0x04 > #define JEDEC_REMS_INSIZE 0x02 > > +/* Read Serial Flash Discoverable Parameters (SFDP) */ > +#define JEDEC_SFDP 0x5a > +#define JEDEC_SFDP_OUTSIZE 0x05 /* 8b op, 24b addr, 8b dummy */ > Ouch. A few SPI masters will have pretty explosions with that outsize. This reminds me... I should resend my patch which can deal with dummy bytes between write and read in a SPI command. > +/* JEDEC_SFDP_INSIZE : any length */ > + > /* Read Electronic Signature */ > #define JEDEC_RES 0xab > #define JEDEC_RES_OUTSIZE 0x04 > diff --git a/spi25.c b/spi25.c > index d3680fb..af81f19 100644 > --- a/spi25.c > +++ b/spi25.c > @@ -23,6 +23,7 @@ > */ > > #include <string.h> > +#include <stdlib.h> > #include "flash.h" > #include "flashchips.h" > #include "chipdrivers.h" > @@ -113,6 +114,278 @@ int spi_write_disable(void) > return spi_send_command(sizeof(cmd), 0, cmd, NULL); > } > > The code below is huge, and I'd argue it is for a chip family and should live in sfdp25.c (or something with a similar name). > +static int spi_sfdp(uint32_t address, uint8_t *buf, int len) > +{ > + const unsigned char cmd[JEDEC_SFDP_OUTSIZE] = { > + JEDEC_SFDP, > + (address >> 16) & 0xff, > + (address >> 8) & 0xff, > + (address >> 0) & 0xff, > + 0 > + }; > + return spi_send_command(sizeof(cmd), len, cmd, buf); > +} > + > +struct sfdp_tbl_hdr { > + uint8_t id; > + uint8_t v_minor; > + uint8_t v_major; > + uint8_t len; > + uint32_t ptp; /* 24b pointer */ > +}; > + > +struct sfdp_tbl_0 { > + uint8_t id; > + uint8_t v_minor; > + uint8_t v_major; > + uint8_t len; > + uint32_t ptp; /* 24b pointer */ > +}; > + > +static int sfdp_fill_flash(struct flashchip *f, uint8_t *buf, uint16_t len) > +{ > + uint32_t tmp32; > + uint8_t tmp8; > + uint32_t total_size; /* in bytes */ > + uint32_t bsize; > + int i, j; > + > + msg_cspew("Parsing JEDEC SFDP parameter table...\n"); > + if (len == 9 * 4) { > + msg_cerr("%s: len out of spec\n", __func__); > + return 1; > + } > + > + /* 1. double word */ > + i = 0; > + tmp32 = buf[(4 * i) + 0]; > + tmp32 |= ((unsigned int)buf[(4 * i) + 1]) << 8; > + tmp32 |= ((unsigned int)buf[(4 * i) + 2]) << 16; > + tmp32 |= ((unsigned int)buf[(4 * i) + 3]) << 24; > + > + tmp8 = (tmp32 >> 17) & 0x3; > + switch (tmp8) { > + case 0x0: > + msg_cspew(" 3-Byte only addressing.\n"); > + break; > + case 0x1: > + msg_cspew(" 3-Byte (and optionally 4-Byte) addressing.\n"); > + break; > + case 0x2: > + msg_cdbg(" 4-Byte only addressing not supported.\n"); > + return 1; > + default: > + msg_cdbg(" Required addressing mode (0x%x) not supported.\n", > + tmp8); > + return 1; > + } > + > + msg_cspew(" Writes to the status register have "); > + if (tmp32 & (1 << 3)) { > + f->unlock = spi_disable_blockprotect; > + msg_cspew("to be enabled with "); > + if (tmp32 & (1 << 4)) { > + f->feature_bits = FEATURE_WRSR_WREN; > + msg_cspew("WREN (0x06).\n"); > + } else { > + f->feature_bits = FEATURE_WRSR_EWSR; > + msg_cspew("EWSR (0x50).\n"); > + } > + } else > + msg_cspew("not to be especially enabled.\n"); > + > + /* 2. double word */ > + i = 1; > + tmp32 = buf[(4 * i) + 0]; > + tmp32 |= ((unsigned int)buf[(4 * i) + 1]) << 8; > + tmp32 |= ((unsigned int)buf[(4 * i) + 2]) << 16; > + tmp32 |= ((unsigned int)buf[(4 * i) + 3]) << 24; > + > + if (tmp32 & (1<<31)) { > + msg_cdbg(" Flash chip size >= 4 Gb/ 500 MB not supported.\n"); > + return 1; > + } > + total_size = (tmp32 & 0x7FFFFFFF) / 8; > + f->total_size = total_size / 1024; > + msg_cspew(" Flash chip size is %d kB.\n", f->total_size); > + > + i = 8; > + for(j = 0; j < 4; j++) { > + /* 8 double words from the start + 2 words for every eraser */ > + bsize = 2^(buf[(4 * i) + (2 * j)]); > + if (bsize == 0) > + continue; > + > + tmp32 = buf[(4 * i) + (2 * j) + 1]; > + switch(tmp32){ > + case 0x00: > + case 0xff: > + /* Not specified, assuming "not supported". */ > + continue; > + case 0x20: > + f->block_erasers[j].block_erase = spi_block_erase_20; > + break; > + case 0x52: > + f->block_erasers[j].block_erase = spi_block_erase_52; > + break; > + case 0x60: > + f->block_erasers[j].block_erase = spi_block_erase_60; > + break; > + case 0xc7: > + f->block_erasers[j].block_erase = spi_block_erase_c7; > + break; > + case 0xd7: > + f->block_erasers[j].block_erase = spi_block_erase_d7; > + break; > + case 0xd8: > + f->block_erasers[j].block_erase = spi_block_erase_d8; > + break; > + default: > + msg_cinfo("%s: unknown opcode (0x%02x) in SFDP table. " > + "Please report this at " > + "flashrom(a)flashrom.org\n", > + __func__, tmp32); > + continue; > + } > + f->block_erasers[j].eraseblocks[0].size = bsize; > + f->block_erasers[j].eraseblocks[0].count = total_size/bsize; > + msg_cspew(" Block eraser %d: %d x %d B with opcode 0x%02x\n", > + j, total_size/bsize, bsize, tmp32); > + } > + return 0; > +} > + > +static int sfdp_fetch_pt(uint32_t addr, uint8_t *buf, uint16_t len) > +{ > + uint16_t i; > + if (spi_sfdp(addr, buf, len)) { > + msg_cerr("Receiving SFDP parameter table failed.\n"); > + return 1; > + } > + msg_cspew(" Parameter table contents:\n"); > + for(i = 0; i < len; i++) { > + if ((i % 8) == 0) { > + msg_cspew(" 0x%03x: ", i); > + } > + msg_cspew(" 0x%02x", buf[i]); > + if ((i % 8) == 7) { > + msg_cspew("\n"); > + continue; > + } > + if ((i % 8) == 3) { > + msg_cspew(" "); > + continue; > + } > + } > + msg_cspew("\n"); > + return 0; > +} > + > +int probe_spi_sfdp(struct flashchip *flash) > +{ > + int ret = 0; > + uint8_t buf[8]; > + uint16_t tmp16; > + uint32_t tmp32; > + uint8_t nph; > + uint8_t i; > + struct sfdp_tbl_hdr *hdrs; > + uint8_t *hbuf; > + uint8_t *tbuf; > + > + if (spi_sfdp(0x0, buf, 4)) { > + msg_cerr("Receiving SFDP signature failed.\n"); > + return 0; > + } > + tmp32 = buf[0]; > + tmp32 |= ((unsigned int)buf[1]) << 8; > + tmp32 |= ((unsigned int)buf[2]) << 16; > + tmp32 |= ((unsigned int)buf[3]) << 24; > + > + msg_cspew("SFDP signature = 0x%08x (should be 0x50444653)\n", tmp32); > + if (tmp32 != 0x50444653) { > + msg_cdbg("No SFDP signature found.\n"); > + return 0; > + } > + if (spi_sfdp(0x4, buf, 3)) { > + msg_cerr("Receiving SFDP revision and number of parameter " > + "headers (NPH) failed. "); > + return 0; > + } > + msg_cspew("SFDP revision = %d.%d\n", buf[1], buf[0]); > + nph = buf[3]; > + msg_cspew("SFDP number of parameter headers (NPH) = %d (+ 1 mandatory)" > + "\n", nph); > + > + /* Fetch all parameter headers, even if we don't use them all (yet). */ > + hbuf = malloc(sizeof(struct sfdp_tbl_hdr) * (nph + 1)); > + hdrs = malloc((nph + 1) * 8); > + if (hbuf == NULL || hdrs == NULL ) { > + msg_gerr("Out of memory!\n"); > + exit(1); /* FIXME: shutdown gracefully */ > + } > + if (spi_sfdp(0x8, hbuf, (nph + 1) * 8)) { > + msg_cerr("Receiving SFDP parameter table headers failed.\n"); > + goto cleanup_hdrs; > + } > + > + i = 0; > + do{ > + hdrs[i].id = hbuf[(8 * i) + 0]; > + hdrs[i].v_minor = hbuf[(8 * i) + 1]; > + hdrs[i].v_major = hbuf[(8 * i) + 2]; > + hdrs[i].len = hbuf[(8 * i) + 3]; > + hdrs[i].ptp = hbuf[(8 * i) + 4]; > + hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 5]) << 8; > + hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 6]) << 16; > + msg_cspew("SFDP parameter table header %d:\n", i); > + msg_cspew(" ID 0x%02x, version %d.%d\n", hdrs[i].id, > + hdrs[i].v_major, hdrs[i].v_minor); > + tmp16 = hdrs[i].len * 4; > + tmp32 = hdrs[i].ptp; > + msg_cspew(" Length %d B, Parameter Table Pointer 0x%06x\n", > + tmp16, tmp32); > + > + tbuf = malloc(tmp16); > + if (tbuf == NULL) { > + msg_gerr("Out of memory!\n"); > + exit(1); /* FIXME: shutdown gracefully */ > + } > + if (sfdp_fetch_pt(tmp32, tbuf, tmp16)){ > + msg_cerr("Fetching SFDP parameter table %d failed.\n", > + i); > + free(tbuf); > + break; > + } > + if (i == 0) { /* Mandatory JEDEC SFDP parameter table */ > + if (hdrs[i].id != 0) > + msg_cdbg("ID of the mandatory JEDEC SFDP " > + "parameter table is not 0 as demanded " > + "by JESD216 (warning only).\n"); > + > + if (hdrs[i].len != (9 * 4)) { > + msg_cdbg("Length of the mandatory JEDEC SFDP " > + "parameter table is not 24 B as " > + "demanded by JESD216.\n"); > + if (hdrs[i].len == (4 * 4)) > + msg_cdbg("It seems like it is the " > + "preliminary Intel version of " > + "SFDP, which we don't support." > + "\n"); > + } else if (sfdp_fill_flash(flash, tbuf, tmp16) == 0) > + ret = 1; > + } > + > + free(tbuf); > + i++; > + } while(i <= nph); > + > +cleanup_hdrs: > + free(hdrs); > + free(hbuf); > + return ret; > +} > + > static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) > { > unsigned char readarr[4]; > Could you resend this with the comments addressed and with the squash patch merged in? I didn't review the SFDP code yet, but the right presentation makes reviewing easier. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 5

[PATCH] Autodetect target processor architecture
by Carl-Daniel Hailfinger July 1, 2011

July 1, 2011

Autodetect target processor architecture. Enable architecture dependent compilation of individual sub-drivers for the internal programmer. With this patch, you no longer have to edit the Makefile to compile the internal driver on MIPS/ARM/... TODO: arch.h is not suitable for inclusion in a .c/.h file because of its last line. Any ideas how to change that (move arch.h as "here document" into the Makefile, use other trickery like more #ifdefs)? Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-target_arch/Makefile =================================================================== --- flashrom-target_arch/Makefile (Revision 1357) +++ flashrom-target_arch/Makefile (Arbeitskopie) @@ -37,7 +37,10 @@ CFLAGS += -Werror endif -# FIXME We have to differentiate between host and target arch. +# Determine the destination processor architecture +ARCH = $(strip $(shell LC_ALL=C gcc -E arch.h|grep -v '^\#')) + +# FIXME We have to differentiate between host and target OS architecture. OS_ARCH ?= $(shell uname) ifneq ($(OS_ARCH), SunOS) STRIP_ARGS = -s @@ -222,8 +225,10 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o -# FIXME: The PROGRAMMER_OBJS below should only be included on x86. +ifeq ($(ARCH),"x86") PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +else +endif NEED_PCI := yes endif @@ -418,6 +423,9 @@ echo "found." || ( echo "not found."; \ rm -f .test.c .test$(EXEC_SUFFIX); exit 1) @rm -f .test.c .test$(EXEC_SUFFIX) + @printf "ARCH is " + @echo $(ARCH)|wc -l|grep -q ^1$ || ( echo "unknown. Aborting."; exit 1) + @printf "%s\n" '$(ARCH)' ifeq ($(CHECK_LIBPCI), yes) pciutils: compiler Index: flashrom-target_arch/arch.h =================================================================== --- flashrom-target_arch/arch.h (Revision 0) +++ flashrom-target_arch/arch.h (Revision 0) @@ -0,0 +1,31 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2011 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Header file for CPU architecture checking. + */ + +#if defined (__i386__) || defined (__x86_64__) +#define __FLASHROM_ARCH__ "x86" +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) +#define __FLASHROM_ARCH__ "mips" +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) +#define __FLASHROM_ARCH__ "ppc" +#endif +__FLASHROM_ARCH__ -- http://www.hailfinger.org/

5 9

Re: [flashrom] [PATCH 7/8] ichspi:c add support for Intel Hardware Sequencing
by Carl-Daniel Hailfinger July 1, 2011

July 1, 2011

Am 28.06.2011 05:33 schrieb Stefan Tauner: > --- a/flashchips.c > +++ b/flashchips.c > @@ -8507,7 +8507,27 @@ const struct flashchip flashchips[] = { > .write = write_jedec_1, > .read = read_memmapped, > }, > - > +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) > + { > + .vendor = "Intel", > + .name = "Hardware Sequencing", > + .bustype = CHIP_BUSTYPE_SPI, > + .manufacture_id = INTEL_ID, > + .model_id = INTEL_HWSEQ, > + .total_size = 0, > + .page_size = 256, > + .tested = TEST_OK_PREW, > + .probe = ich_hwseq_probe, > + .block_erasers = > + { > + { /* erase blocks will be set by the probing function */ > + .block_erase = ich_hwseq_block_erase, > + } > + }, > + .write = ich_hwseq_write_256, > + .read = ich_hwseq_read, > + }, > +#endif // defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) > { > .vendor = "AMIC", > .name = "unknown AMIC SPI chip", > I consider a chip called "Hardware Sequencing" to be a really evil thing. Hooking up a programmer with the help of a programmer-specific flash chip seems to be quite popular, and it was rejected each time and an alternative solution was found. That said, if probing for the real chip ID is impossible here and you only have read/write/erase primitives without any SPI access, this is essentially not a SPI bus chip, but a programmer-specific bus chip. The struct flashchip should probably look more like this: +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) + { + .vendor = "Unknown", + .name = "Abstract opaque chip", + .bustype = CHIP_BUSTYPE_ABSTRACT, + .manufacture_id = ABSTRACT_MANUF_ID, + .model_id = ABSTRACT_MODEL_ID, + .total_size = 0, + .page_size = 0, + .tested = TEST_OK_PREW, + .probe = abstract_probe, //abstract_probe points to programmer->abstract_probe which points to ich_hwseq_probe + .block_erasers = + { + { /* erase blocks will be set by the probing function */ + .block_erase = abstract_erase, // points to programmer->abstract_erase which points to ich_hwseq_block_erase + } + }, + .write = ich_hwseq_write_256, Same abstract_ game as above. + .read = ich_hwseq_read, Dito. + }, +#endif // defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) { .vendor = "AMIC", .name = "unknown AMIC SPI chip", Yes, the programmer struct would have to be extended for this, but at least that allows us to drive anything without having to care about the bus if we can't access the bus anyway. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1