flashrom April 2011

flashrom@flashrom.org

61 participants
201 discussions

Fwd: Asus L1N64WS/B
by Julian Shulika 06 Apr '11

06 Apr '11

> Hi,Stefan. Thank you for answer,see log file verbose.log 2011/4/5 Stefan Reinauer <stefan.reinauer(a)coreboot.org>: > * Julian Shulika <hercares(a)gmail.com> [110404 01:30]: >> Any news about adding support of Asus L1N64? > > Looks like the chipset should be supported. Can you attach a verbose > flashrom run log? > >

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Oops!
by Brandon Dowdy 06 Apr '11

06 Apr '11

I forgot to add the attachments! here they are.

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Re: [flashrom] [PATCH 3/6] changes macros for SSFS and SSFC bits: - introduce mask macros - add comments - change SSFS_CDS to SSFS_FDONE (abbr. used in datasheet not in SSFS but HSFS) - use those for refactoring and magic number elemination. - following patch uses them for pretty printing
by Stefan Reinauer 06 Apr '11

06 Apr '11

* Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> [110401 14:33]: > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > ichspi.c | 56 ++++++++++++++++++++++++++++++++++---------------------- > 1 files changed, 34 insertions(+), 22 deletions(-) > > diff --git a/ichspi.c b/ichspi.c > index 4e303d7..9491604 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -43,32 +43,44 @@ > #include "spi.h" > > /* ICH9 controller register definition */ > +#define ICH9_REG_FADDR 0x08 /* 32 Bits */ > +#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ > > -#define ICH9_REG_SSFS 0x90 /* 08 Bits */ > -#define SSFS_SCIP 0x00000001 > -#define SSFS_CDS 0x00000004 > -#define SSFS_FCERR 0x00000008 > -#define SSFS_AEL 0x00000010 > +#define ICH9_REG_SSFS 0x90 /* 08 Bits */ > +#define SSFS_SCIP 0x00000001 /* SPI Cycle In Progress */ > +#define SSFS_SCIP_OFF 0 > +#define SSFS_FDONE 0x00000004 /* Cycle Done Status */ > +#define SSFS_FDONE_OFF 2 > +#define SSFS_FCERR 0x00000008 /* Flash Cycle Error */ > +#define SSFS_FCERR_OFF 3 > +#define SSFS_AEL 0x00000010 /* Access Error Log */ > +#define SSFS_AEL_OFF 4 Would be nice to #define SSFS_AEL (1 << SSFS_AEL_OFF) and so on. If both are needed. It would be nicer to get rid of either.

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Re: [flashrom] [PATCH 2/6] some additional comments for ichspi.c
by Paul Menzel 06 Apr '11

06 Apr '11

Am Freitag, den 01.04.2011, 14:33 +0200 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > ichspi.c | 8 ++++++-- > 1 files changed, 6 insertions(+), 2 deletions(-) > > diff --git a/ichspi.c b/ichspi.c > index 0b9db20..4e303d7 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -62,6 +62,9 @@ > #define SSFC_SCF 0x01000000 > #define SSFC_SCF_20MHZ 0x00000000 > #define SSFC_SCF_33MHZ 0x01000000 > +/* We combine SSFS and SSFC to one lword, > + * therefore SSFC bits are off by 8. > + * This bits are reserved SSFC: 23-19,7,0; SSFS: 5-7. */ »These bits …« or »The following bits are …«. > #define SSFC_RESERVED_MASK 0xf8008100 > > #define ICH9_REG_FADDR 0x08 /* 32 Bits */ > @@ -116,7 +119,7 @@ static void *ich_spibar = NULL; > typedef struct _OPCODE { > uint8_t opcode; //This commands spi opcode > uint8_t spi_type; //This commands spi type > - uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1 > + uint8_t atomic; //Use preop: (0: none, 1: preop0 only, 2: both) Also put space a after the comment characters `//`? > } OPCODE; > > /* Suggested opcode definition: > @@ -679,7 +682,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, > > /* Assemble SSFS + SSFC */ > temp32 = REGREAD32(ICH9_REG_SSFS); > - /* keep reserved bits */ > + /* Keep reserved bits only */ > temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; > /* clear error status registers */ > temp32 |= (SSFS_CDS + SSFS_FCERR); > @@ -688,6 +691,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, > /* Use 20 MHz */ > temp32 |= SSFC_SCF_20MHZ; > > + /* Set data byte count (DBC) and data cycle bit (DS) */ I do not know if the common rule is to add full stops at the end of sentences or not. > if (datalength != 0) { > uint32_t datatemp; > temp32 |= SSFC_DS; Thanks, Paul

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Fwd: Asus L1N64WS/B
by Julian Shulika 06 Apr '11

06 Apr '11

I have Asus L1N64WS/B (SST49LF080A) and L1N64WS-Sli (Winbond W39V080APZ) motherboards. It's not supported by flashrom I attached the dmi output and an "lspci -vvnnxxx" output. ---------- Forwarded message ---------- From: Julian Shulika <hercares(a)gmail.com> Date: 2011/3/29 Subject: Re: [flashrom] Asus L1N64WS/B To: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at>

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I found another laptop. (with a link to the disassembled acpi code.)
by Brandon Dowdy 05 Apr '11

05 Apr '11

Company: Advent Laptop model: U40SI1 CPU: Intel Pentium T2370 CPU Socket: mPGA479M Northbridge: SiS 671MX Southbridge: SiS 968 Super I/O: ITE IT8512E EC: Same as Super I/O Flash chip: Winbond W25X80* Flash chip size: 1MB (1024 KB) Flash chip is supported by flashrom. Flash Type: SPI Owner: kiddyshaq34 (me) *The flash chip is according to Phlash. Disassembled ACPI code is here: http://www.decashare.com/?id=GErsWP7FN

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Re: [flashrom] [PATCH 6/6] introduce a global variable to save the maximum number of bytes in an SPI transaction supported by this programmer and use that to simplify code
by Stefan Reinauer 05 Apr '11

05 Apr '11

* Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> [110401 14:33]: > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > ichspi.c | 59 +++++++++++++++++++++++------------------------------------ > 1 files changed, 23 insertions(+), 36 deletions(-) > > diff --git a/ichspi.c b/ichspi.c > index 0ad4f20..b22cf4b 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -124,6 +124,9 @@ > /* ICH SPI configuration lock-down. May be set during chipset enabling. */ > static int ichspi_lock = 0; > > +/* Indicates maximum number of data bytes for each SPI transaction. */ > +static int ichspi_maxdata = -1; > + > uint32_t ichspi_bbar = 0; > > static void *ich_spibar = NULL; > @@ -824,57 +827,38 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, > static int run_opcode(OPCODE op, uint32_t offset, > uint8_t datalength, uint8_t * data) > { > + if (spi_controller == SPI_CONTROLLER_NONE){ curly brackets for command blocks want an additional space. Stefan

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Re: [flashrom] [PATCH 4/6] add pretty printing functions for SSFS+SSFC and the OPCODE struct and use them
by Stefan Reinauer 05 Apr '11

05 Apr '11

* Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> [110401 14:33]: > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > ichspi.c | 47 +++++++++++++++++++++++++++++++++++++++++------ > 1 files changed, 41 insertions(+), 6 deletions(-) > > diff --git a/ichspi.c b/ichspi.c > index 9491604..b24b6a0 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -242,6 +242,41 @@ static OPCODE POSSIBLE_OPCODES[] = { > > static OPCODES O_EXISTING = {}; > > +/* pretty printing functions */ > +static void pretty_print_opcodes(OPCODES *ops){ curly brakes for functions should go on a new line. Stefan

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Re: [flashrom] [PATCH 2/6] some additional comments for ichspi.c
by Stefan Reinauer 05 Apr '11

05 Apr '11

* Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> [110401 14:33]: > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > ichspi.c | 8 ++++++-- > 1 files changed, 6 insertions(+), 2 deletions(-) > > diff --git a/ichspi.c b/ichspi.c > index 0b9db20..4e303d7 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -62,6 +62,9 @@ > #define SSFC_SCF 0x01000000 > #define SSFC_SCF_20MHZ 0x00000000 > #define SSFC_SCF_33MHZ 0x01000000 > +/* We combine SSFS and SSFC to one lword, What's an lword?

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One more student would like to participate in GSoC
by Tadas Slotkus 04 Apr '11

04 Apr '11

Hello, I am a student at Kaunas University of Technology in Lithuania, studying Informatics Engineering second course and I would love to participate in GSoC. I have received some datasheets from VIA for unsupported chipsets, I would like port them. I have good soldering skills and am able to make small printed circuit boards. Some of my homemade art PCBs: http://www.papile.projektas.lt/imgs/usb/ So I have to setup a convenient flashing system for future development which would be brick unaware. I am interested in these ideas: 1) flashrom remote flashing with modified SerialICE - needs to add flashing functionality. With SerialICE we won't need RAM working, so it will help developing chipset code. After reset SerialICE flashing part will be activated with dosens of bytes receiveid through serial port, and communication with HOST system will be initiated (HOST system then will send commands for flashing). If SerialICE won't get any bytes from serial port in a few milliseconds it will let the coreboot to run. We would use flashrom's codebase for flashing protocols... 2) flashrom as payload - for such implementation we should make a config system where we would choose which flash chip(s) are needed to be included in our payload's build. The rom image might be transferred through serial port. But payload needs RAM, so this idea is in discussion list. The first idea would be the primary objective for me. What do you think? Thanks, Tadas Slotkus P.S. I have been around coreboot for some time. My earlier email in mailing-lists: mrtadis(a)gmail.com, current irc nick: mrtadis)

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flashrom April 2011