flashrom April 2011

flashrom@flashrom.org

61 participants
201 discussions

Re: [flashrom] Flashrom W39V040B
by Idwer Vollering 01 Apr '11

01 Apr '11

Please keep flashrom(a)flashrom.org in the "To:"-field, or in cc. Thanks. 2011/4/1 kay <kay.diam(a)gmail.com>: > Hi > > 2011/4/1 Idwer Vollering <vidwer(a)gmail.com> >> >> 2011/3/30 kay <kay.diam(a)gmail.com>: >> > Hi! >> >> Hi. >> >> > >> > I have tried to flash my BIOS without success. BIOS flash reading is ok, >> > but >> > writing does'nt work. Here is the commands output: >> > >> > $ flashrom -Vw 75i65G_3.30 >> > flashrom v0.9.2-r1028 on Linux 2.6.35-28-generic (x86_64), built with >> > libpci >> >> Can you retry writing with the latest development code ? >> >> See http://www.flashrom.org/Downloads#Installation_from_source for >> instructions. >> > > The results are different, but at this time I got only warning: > flashrom v0.9.3-r1205 on Linux 2.6.35-28-generic (x86_64), built with libpci > 3.1.7, GCC 4.4.5, little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > No coreboot table found. > Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. > This chipset supports the following protocols: FWH. > Disabling flash write protection for board "ASRock 775i65G"... OK. > No EEPROM/flash device found. Fooled you :) No really, this is strange because it found a flash device earlier. Can you try the code from subversion ? $ svn co svn://coreboot.org/flashrom/trunk flashrom $ cd flashrom $ make $ sudo ./flashrom -Vw /path/to/75i65G_3.30 > Note: flashrom can never write if the flash chip isn't found automatically. > >> >> > 3.0.0, GCC 4.4.4, little endian >> > flashrom is free software, get the source code at >> > http://www.flashrom.org >> > >> > Calibrating delay loop... OS timer resolution is 1 usecs, 2071M loops >> > per >> > second, 10 myus = 9 us, 100 myus = 90 us, 1000 myus = 898 us, 10000 myus >> > = >> > 8978 us, 4 myus = 3 >> > us, OK. >> > Initializing internal programmer >> > No coreboot table found. >> > DMI string system-manufacturer: "To Be Filled By O.E.M." >> > DMI string system-product-name: "To Be Filled By O.E.M." >> > DMI string system-version: "To Be Filled By O.E.M." >> > DMI string baseboard-manufacturer: " " >> > DMI string baseboard-product-name: "775i65G." >> >> The board is an ASRock 775i65G, correct ? >> > > Yep. > >> >> > DMI string baseboard-version: " " >> > DMI string chassis-type: "Desktop" >> > Found chipset "Intel ICH5/ICH5R", enabling flash write... chipset PCI ID >> > is >> > 8086:24d0, >> > BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 >> > OK. >> > This chipset supports the following protocols: Non-SPI. >> > >> > Found chip "Winbond W39V040B" (512 KB, LPC) at physical address >> > 0xfff80000. >> > Flash image seems to be a legacy BIOS. Disabling checks. >> > Writing flash chip... Erasing flash chip... Looking at blockwise erase >> > function 0... trying... 0x000000-0x00ffff, 0x010000-0x01ffff, >> > Looking at blockwise erase function 1... trying... 0x000000-0x07ffff, >> > Looking at blockwise erase function 2... not defined. Looking for >> > another >> > erase function. >> > Looking at blockwise erase function 3... not defined. Looking for >> > another >> > erase function. >> > Looking at blockwise erase function 4... not defined. Looking for >> > another >> > erase function. >> > >> > ERASE FAILED at 0x00013948! Expected=0xff, Read=0x44, failed byte count >> > from >> > 0x00010000-0x0001ffff: 0xc5f5 >> > ERASE FAILED! >> > ERASE FAILED at 0x00013948! Expected=0xff, Read=0x44, failed byte count >> > from >> > 0x00000000-0x0007ffff: 0x5cf57 >> > ERASE FAILED! >> > FAILED! >> > ERASE FAILED! >> > FAILED! >> > Your flash chip is in an unknown state. >> > Get help on IRC at irc.freenode.net (channel #flashrom) or >> > mail flashrom(a)flashrom.org! >> > >> > ------------------------------------------------------------------------------- >> > DO NOT REBOOT OR POWEROFF! >> >> Big fat warning but you have kept it cool :) >> >> > >> > I have checked the BIOS content and compared with backup - they are >> > identical, so I have reboot the PC without any problems. >> >> Okay, can you hit reply-to-all and attach the output of 'flashrom -V', >> 'lspci -nnvvvxxx', 'superiotool -deV' (run all commands as root) ? > > I have attached them. > > Have a nice day and watch out for the tricks on April fools' day )

2 3

[PATCH 6/6] introduce a global variable to save the maximum number of bytes in an SPI transaction supported by this programmer and use that to simplify code
by Stefan Tauner 01 Apr '11

01 Apr '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 59 +++++++++++++++++++++++------------------------------------ 1 files changed, 23 insertions(+), 36 deletions(-) diff --git a/ichspi.c b/ichspi.c index 0ad4f20..b22cf4b 100644 --- a/ichspi.c +++ b/ichspi.c @@ -124,6 +124,9 @@ /* ICH SPI configuration lock-down. May be set during chipset enabling. */ static int ichspi_lock = 0; +/* Indicates maximum number of data bytes for each SPI transaction. */ +static int ichspi_maxdata = -1; + uint32_t ichspi_bbar = 0; static void *ich_spibar = NULL; @@ -824,57 +827,38 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data) { + if (spi_controller == SPI_CONTROLLER_NONE){ + msg_perr("%s: unsupported chipset\n", __func__); + return -1; + } + + if (datalength > ichspi_maxdata) { + msg_perr("%s: Internal command size error for " + "opcode 0x%02x, got datalength=%i, want <=%i\n", + __func__, op.opcode, datalength, ichspi_maxdata); + return SPI_INVALID_LENGTH; + } + switch (spi_controller) { case SPI_CONTROLLER_VIA: - if (datalength > 16) { - msg_perr("%s: Internal command size error for " - "opcode 0x%02x, got datalength=%i, want <=16\n", - __func__, op.opcode, datalength); - return SPI_INVALID_LENGTH; - } - return ich7_run_opcode(op, offset, datalength, data, 16); case SPI_CONTROLLER_ICH7: - if (datalength > 64) { - msg_perr("%s: Internal command size error for " - "opcode 0x%02x, got datalength=%i, want <=16\n", - __func__, op.opcode, datalength); - return SPI_INVALID_LENGTH; - } - return ich7_run_opcode(op, offset, datalength, data, 64); + return ich7_run_opcode(op, offset, datalength, data, ichspi_maxdata); case SPI_CONTROLLER_ICH9: - if (datalength > 64) { - msg_perr("%s: Internal command size error for " - "opcode 0x%02x, got datalength=%i, want <=16\n", - __func__, op.opcode, datalength); - return SPI_INVALID_LENGTH; - } return ich9_run_opcode(op, offset, datalength, data); default: - msg_perr("%s: unsupported chipset\n", __func__); + /* If we ever get here, something really weird happened */ + return -1; } - - /* If we ever get here, something really weird happened */ - return -1; } int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) { - int maxdata = 64; - - if (spi_controller == SPI_CONTROLLER_VIA) - maxdata = 16; - - return spi_read_chunked(flash, buf, start, len, maxdata); + return spi_read_chunked(flash, buf, start, len, ichspi_maxdata); } int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) { - int maxdata = 64; - - if (spi_controller == SPI_CONTROLLER_VIA) - maxdata = 16; - - return spi_write_chunked(flash, buf, start, len, maxdata); + return spi_write_chunked(flash, buf, start, len, ichspi_maxdata); } int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, @@ -1115,6 +1099,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, break; } + ichspi_maxdata = 64; + /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset); @@ -1258,6 +1244,7 @@ int via_init_spi(struct pci_dev *dev) /* Not sure if it speaks all these bus protocols. */ buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_VIA; + ichspi_maxdata = 16; msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2)); -- 1.7.1

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[PATCH 5/6] improve output in case run_opcode fails
by Stefan Tauner 01 Apr '11

01 Apr '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 17 ++++++++++++++--- 1 files changed, 14 insertions(+), 3 deletions(-) diff --git a/ichspi.c b/ichspi.c index b24b6a0..0ad4f20 100644 --- a/ichspi.c +++ b/ichspi.c @@ -796,8 +796,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, /* FIXME make sure we do not needlessly cause transaction errors. */ temp32 = REGREAD32(ICH9_REG_SSFS); if (temp32 & SSFS_FCERR) { - msg_perr("Transaction error for opcode 0x%02x!\n", - op.opcode); + msg_perr("Transaction error!\n"); prettyprint_ich9_reg_ssfs(temp32); prettyprint_ich9_reg_ssfc(temp32); /* keep reserved bits */ @@ -974,7 +973,19 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, result = run_opcode(*opcode, addr, count, data); if (result) { - msg_pdbg("run OPCODE 0x%02x failed\n", opcode->opcode); + msg_pdbg("run OPCODE 0x%02x failed at address 0x%06x.\n", + opcode->opcode, addr); + /* Print out the data array if it contains data to write. + * Errors are detected before the received data is read back into + * the array so it won't make sense to print it then. */ + if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || + (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS))) { + msg_pspew("The data was:\n"); + uint8_t i; + for(i=0; i<count; i++){ + msg_pspew("%3d: 0x%02x\n", i, data[i]); + } + } } return result; -- 1.7.1

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[PATCH 4/6] add pretty printing functions for SSFS+SSFC and the OPCODE struct and use them
by Stefan Tauner 01 Apr '11

01 Apr '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 47 +++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 41 insertions(+), 6 deletions(-) diff --git a/ichspi.c b/ichspi.c index 9491604..b24b6a0 100644 --- a/ichspi.c +++ b/ichspi.c @@ -242,6 +242,41 @@ static OPCODE POSSIBLE_OPCODES[] = { static OPCODES O_EXISTING = {}; +/* pretty printing functions */ +static void pretty_print_opcodes(OPCODES *ops){ + if(ops == NULL) + return; + + msg_pspew("preop0=0x%02x, preop1=0x%02x\n", ops->preop[0], ops->preop[1]); + + OPCODE oc; + uint8_t i; + for (i = 0; i < 8; i++) { + oc = ops->opcode[i]; + msg_pspew("op[%d]=0x%02x, %d, %d\n", i, oc.opcode, oc.spi_type, oc.atomic); + } +} + +#define pprint_reg(reg, bit, sep) msg_pspew("%s=%d" sep, #bit, (reg##_##bit & reg##_##bit)>>reg##_##bit##_OFF) +static void prettyprint_ich9_reg_ssfs(uint32_t reg){ + msg_pspew("SSFS: "); + pprint_reg(SSFS, SCIP, ", "); + pprint_reg(SSFS, FDONE, ", "); + pprint_reg(SSFS, FCERR, ", "); + pprint_reg(SSFS, AEL, "\n"); +} + +static void prettyprint_ich9_reg_ssfc(uint32_t reg){ + msg_pspew("SSFC: "); + pprint_reg(SSFC, SCGO, ", "); + pprint_reg(SSFC, ACS, ", "); + pprint_reg(SSFC, SPOP, ", "); + pprint_reg(SSFC, COP, ", "); + pprint_reg(SSFC, DBC, ", "); + pprint_reg(SSFC, SME, ", "); + pprint_reg(SSFC, SCF, "\n"); +} + static uint8_t lookup_spi_type(uint8_t opcode) { int a; @@ -500,6 +535,7 @@ static int ich_init_opcodes(void) } else { curopcodes = curopcodes_done; msg_pdbg("done\n"); + pretty_print_opcodes(curopcodes); return 0; } } @@ -762,6 +798,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, if (temp32 & SSFS_FCERR) { msg_perr("Transaction error for opcode 0x%02x!\n", op.opcode); + prettyprint_ich9_reg_ssfs(temp32); + prettyprint_ich9_reg_ssfc(temp32); /* keep reserved bits */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; /* Clear the transaction error. */ @@ -1147,16 +1185,13 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, tmp = mmio_readl(ich_spibar + 0x90); msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); - msg_pdbg("AEL %i, ", (tmp >> 4) & 1); - msg_pdbg("FCERR %i, ", (tmp >> 3) & 1); - msg_pdbg("FDONE %i, ", (tmp >> 2) & 1); - msg_pdbg("SCIP %i\n", (tmp >> 0) & 1); + prettyprint_ich9_reg_ssfs(tmp); if (tmp & (1 << 3)) { msg_pdbg("Clearing SSFS.FCERR\n"); mmio_writeb(1 << 3, ich_spibar + 0x90); } - tmp >>= 8; - msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp); + msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp >> 8); + prettyprint_ich9_reg_ssfc(tmp); msg_pdbg("0x94: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x94)); -- 1.7.1

1 0

[PATCH 3/6] changes macros for SSFS and SSFC bits: - introduce mask macros - add comments - change SSFS_CDS to SSFS_FDONE (abbr. used in datasheet not in SSFS but HSFS) - use those for refactoring and magic number elemination. - following patch uses them for pretty printing
by Stefan Tauner 01 Apr '11

01 Apr '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 56 ++++++++++++++++++++++++++++++++++---------------------- 1 files changed, 34 insertions(+), 22 deletions(-) diff --git a/ichspi.c b/ichspi.c index 4e303d7..9491604 100644 --- a/ichspi.c +++ b/ichspi.c @@ -43,32 +43,44 @@ #include "spi.h" /* ICH9 controller register definition */ +#define ICH9_REG_FADDR 0x08 /* 32 Bits */ +#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ -#define ICH9_REG_SSFS 0x90 /* 08 Bits */ -#define SSFS_SCIP 0x00000001 -#define SSFS_CDS 0x00000004 -#define SSFS_FCERR 0x00000008 -#define SSFS_AEL 0x00000010 +#define ICH9_REG_SSFS 0x90 /* 08 Bits */ +#define SSFS_SCIP 0x00000001 /* SPI Cycle In Progress */ +#define SSFS_SCIP_OFF 0 +#define SSFS_FDONE 0x00000004 /* Cycle Done Status */ +#define SSFS_FDONE_OFF 2 +#define SSFS_FCERR 0x00000008 /* Flash Cycle Error */ +#define SSFS_FCERR_OFF 3 +#define SSFS_AEL 0x00000010 /* Access Error Log */ +#define SSFS_AEL_OFF 4 #define SSFS_RESERVED_MASK 0x000000e2 -#define ICH9_REG_SSFC 0x91 /* 24 Bits */ -#define SSFC_SCGO 0x00000200 -#define SSFC_ACS 0x00000400 -#define SSFC_SPOP 0x00000800 -#define SSFC_COP 0x00001000 -#define SSFC_DBC 0x00010000 -#define SSFC_DS 0x00400000 -#define SSFC_SME 0x00800000 -#define SSFC_SCF 0x01000000 -#define SSFC_SCF_20MHZ 0x00000000 -#define SSFC_SCF_33MHZ 0x01000000 +#define ICH9_REG_SSFC 0x91 /* 24 Bits */ +#define SSFC_SCGO 0x00000200 /* SPI Cycle Go */ +#define SSFC_SCGO_OFF (1 + 8) +#define SSFC_ACS 0x00000400 /* Atomic Cycle Sequence */ +#define SSFC_ACS_OFF (2 + 8) +#define SSFC_SPOP 0x00000800 /* Sequence Prefix Opcode Pointer */ +#define SSFC_SPOP_OFF (3 + 8) +#define SSFC_COP 0x00007000 /* Cycle Opcode Pointer */ +#define SSFC_COP_OFF (4 + 8) +#define SSFC_DBC 0x003F0000 /* Data Byte Count */ +#define SSFC_DBC_OFF (8 + 8) +#define SSFC_DS 0x00400000 /* Data Cycle */ +#define SSFC_DS_OFF (14 + 8) +#define SSFC_SME 0x00800000 /* SPI SMI# Enable */ +#define SSFC_SME_OFF (15 + 8) +#define SSFC_SCF 0x07000000 /* SPI Cycle Frequency */ +#define SSFC_SCF_OFF (16 + 8) +#define SSFC_SCF_20MHZ 0x00000000 +#define SSFC_SCF_33MHZ 0x01000000 /* We combine SSFS and SSFC to one lword, * therefore SSFC bits are off by 8. * This bits are reserved SSFC: 23-19,7,0; SSFS: 5-7. */ #define SSFC_RESERVED_MASK 0xf8008100 -#define ICH9_REG_FADDR 0x08 /* 32 Bits */ -#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ #define ICH9_REG_PREOP 0x94 /* 16 Bits */ #define ICH9_REG_OPTYPE 0x96 /* 16 Bits */ #define ICH9_REG_OPMENU 0x98 /* 64 Bits */ @@ -684,8 +696,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, temp32 = REGREAD32(ICH9_REG_SSFS); /* Keep reserved bits only */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; - /* clear error status registers */ - temp32 |= (SSFS_CDS + SSFS_FCERR); + /* Clear cycle done and cycle error status registers */ + temp32 |= (SSFS_FDONE + SSFS_FCERR); REGWRITE32(ICH9_REG_SSFS, temp32); /* Use 20 MHz */ @@ -695,7 +707,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, if (datalength != 0) { uint32_t datatemp; temp32 |= SSFC_DS; - datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8); + datatemp = (uint32_t) (((datalength - 1) << SSFC_DBC_OFF) & SSFC_DBC); temp32 |= datatemp; } @@ -735,7 +747,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, /* Wait for Cycle Done Status or Flash Cycle Error. */ timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ - while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_CDS | SSFS_FCERR)) == 0) && + while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_FDONE | SSFS_FCERR)) == 0) && --timeout) { programmer_delay(10); } -- 1.7.1

1 0

[PATCH 2/6] some additional comments for ichspi.c
by Stefan Tauner 01 Apr '11

01 Apr '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/ichspi.c b/ichspi.c index 0b9db20..4e303d7 100644 --- a/ichspi.c +++ b/ichspi.c @@ -62,6 +62,9 @@ #define SSFC_SCF 0x01000000 #define SSFC_SCF_20MHZ 0x00000000 #define SSFC_SCF_33MHZ 0x01000000 +/* We combine SSFS and SSFC to one lword, + * therefore SSFC bits are off by 8. + * This bits are reserved SSFC: 23-19,7,0; SSFS: 5-7. */ #define SSFC_RESERVED_MASK 0xf8008100 #define ICH9_REG_FADDR 0x08 /* 32 Bits */ @@ -116,7 +119,7 @@ static void *ich_spibar = NULL; typedef struct _OPCODE { uint8_t opcode; //This commands spi opcode uint8_t spi_type; //This commands spi type - uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1 + uint8_t atomic; //Use preop: (0: none, 1: preop0 only, 2: both) } OPCODE; /* Suggested opcode definition: @@ -679,7 +682,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, /* Assemble SSFS + SSFC */ temp32 = REGREAD32(ICH9_REG_SSFS); - /* keep reserved bits */ + /* Keep reserved bits only */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; /* clear error status registers */ temp32 |= (SSFS_CDS + SSFS_FCERR); @@ -688,6 +691,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, /* Use 20 MHz */ temp32 |= SSFC_SCF_20MHZ; + /* Set data byte count (DBC) and data cycle bit (DS) */ if (datalength != 0) { uint32_t datatemp; temp32 |= SSFC_DS; -- 1.7.1

1 0

[PATCH 1/6] whitespace (space to tabs mostly)
by Stefan Tauner 01 Apr '11

01 Apr '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 42 +++++++++++++++++++++--------------------- 1 files changed, 21 insertions(+), 21 deletions(-) diff --git a/ichspi.c b/ichspi.c index ed92893..0b9db20 100644 --- a/ichspi.c +++ b/ichspi.c @@ -43,8 +43,6 @@ #include "spi.h" /* ICH9 controller register definition */ -#define ICH9_REG_FADDR 0x08 /* 32 Bits */ -#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ #define ICH9_REG_SSFS 0x90 /* 08 Bits */ #define SSFS_SCIP 0x00000001 @@ -66,18 +64,20 @@ #define SSFC_SCF_33MHZ 0x01000000 #define SSFC_RESERVED_MASK 0xf8008100 -#define ICH9_REG_PREOP 0x94 /* 16 Bits */ -#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */ -#define ICH9_REG_OPMENU 0x98 /* 64 Bits */ +#define ICH9_REG_FADDR 0x08 /* 32 Bits */ +#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ +#define ICH9_REG_PREOP 0x94 /* 16 Bits */ +#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */ +#define ICH9_REG_OPMENU 0x98 /* 64 Bits */ // ICH9R SPI commands -#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 -#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 -#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2 -#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3 +#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 +#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 +#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2 +#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3 // ICH7 registers -#define ICH7_REG_SPIS 0x00 /* 16 Bits */ +#define ICH7_REG_SPIS 0x00 /* 16 Bits */ #define SPIS_SCIP 0x0001 #define SPIS_GRANT 0x0002 #define SPIS_CDS 0x0004 @@ -94,17 +94,17 @@ bit 7 is used with fast read and one shot controls CS de-assert? */ -#define ICH7_REG_SPIC 0x02 /* 16 Bits */ -#define SPIC_SCGO 0x0002 -#define SPIC_ACS 0x0004 -#define SPIC_SPOP 0x0008 -#define SPIC_DS 0x4000 - -#define ICH7_REG_SPIA 0x04 /* 32 Bits */ -#define ICH7_REG_SPID0 0x08 /* 64 Bytes */ -#define ICH7_REG_PREOP 0x54 /* 16 Bits */ -#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */ -#define ICH7_REG_OPMENU 0x58 /* 64 Bits */ +#define ICH7_REG_SPIC 0x02 /* 16 Bits */ +#define SPIC_SCGO 0x0002 +#define SPIC_ACS 0x0004 +#define SPIC_SPOP 0x0008 +#define SPIC_DS 0x4000 + +#define ICH7_REG_SPIA 0x04 /* 32 Bits */ +#define ICH7_REG_SPID0 0x08 /* 64 Bytes */ +#define ICH7_REG_PREOP 0x54 /* 16 Bits */ +#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */ +#define ICH7_REG_OPMENU 0x58 /* 64 Bits */ /* ICH SPI configuration lock-down. May be set during chipset enabling. */ static int ichspi_lock = 0; -- 1.7.1

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[PATCH 0/6] ichspi patches
by Stefan Tauner 01 Apr '11

01 Apr '11

i did most of this after my at25 patches and merged it with the changes introduced by r1281 now. this stuff is also available in my github repo: https://github.com/stefanct/flashrom/tree/dev_ichspi Stefan Tauner (6): whitespace (space to tabs mostly) some additional comments for ichspi.c changes macros for SSFS and SSFC bits: - introduce mask macros - add comments - change SSFS_CDS to SSFS_FDONE (abbr. used in datasheet not in SSFS but HSFS) - use those for refactoring and magic number elemination. - following patch uses them for pretty printing add pretty printing functions for SSFS+SSFC and the OPCODE struct and use them improve output in case run_opcode fails introduce a global variable to save the maximum number of bytes in an SPI transaction supported by this programmer and use that to simplify code ichspi.c | 225 ++++++++++++++++++++++++++++++++++++++------------------------ 1 files changed, 137 insertions(+), 88 deletions(-)

1 0

BIOS flashing success: MSI 890FXA-GD70 (MS-7640)
by Linux User #330250 01 Apr '11

01 Apr '11

Hello! Successful BIOS flashing on a MSI 890FXA-GD70 (MS-7640): http://www.msi.com/product/mb/890FXA-GD70.html I successfully flashed to BIOS version 1.70 a while ago and now to 1.80. See the MSI homepage for details, here are the BIOSes: http://www.msi.com/product/mb/890FXA-GD70.html#/?div=BIOS This is a nice link for MSI mainboard owners and Linux users: MSI-Forum: Flash your BIOS, the Linux way! [beware the dangers!!] http://forum-en.msi.com/index.php?topic=138659.0 Take a look at the text file (flashrom output) in the attatchement. Please add the MS-7640 aka MSI 890FXA-GD70 to the list of supported mainboards. Thanks, Andreas aka Linux User #330250

2 2

[patch] use PCI_VENDOR_ID_* define in all driver .c files
by Idwer Vollering 01 Apr '11

01 Apr '11

Use the appropiate vendor ID from the, present but not always used, #define. Unfortunately, some lines that currently are less than 80 characters wide will exceed that character count. board_enable and chipset_enable.c aren't touched by this patch. Signed-off-by: Idwer Vollering <vidwer(a)gmail.com>

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flashrom April 2011