flashrom December 2011

flashrom@flashrom.org

45 participants
143 discussions

Re: [flashrom] [PATCH 6/8] use getpagesize() to determine physmap's length in nicintel_spi.c
by Carl-Daniel Hailfinger 26 Aug '12

26 Aug '12

Am 15.03.2011 16:29 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner<stefan.tauner(a)student.tuwien.ac.at> > Right, this is a really good idea. Could you patch physmap instead to round down the requested address and round up the end of the range? Then we could just request the amount we need without having to care in each programmer driver about page size. I think somewhere in flashrom we even have rounding code for physmap, it just needs to be moved from a driver to the generic physmap. Your code looks solid. > --- > nicintel_spi.c | 7 +++++-- > 1 files changed, 5 insertions(+), 2 deletions(-) > > diff --git a/nicintel_spi.c b/nicintel_spi.c > index 5a6e04d..811ed6e 100644 > --- a/nicintel_spi.c > +++ b/nicintel_spi.c > @@ -26,11 +26,14 @@ > */ > > #include<stdlib.h> > +#include<unistd.h> > #include "flash.h" > #include "programmer.h" > > #define PCI_VENDOR_ID_INTEL 0x8086 > > +#define MEMMAP_SIZE getpagesize() > + > #define EECD 0x10 > #define FLA 0x1c > > @@ -148,7 +151,7 @@ int nicintel_spi_init(void) > io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_intel_spi); > > nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", > - io_base_addr, 4096); > + io_base_addr, MEMMAP_SIZE); > tmp = pci_mmio_readl(nicintel_spibar + EECD); > tmp&= ~FLASH_WRITES_DISABLED; > tmp |= FLASH_WRITES_ENABLED; > @@ -173,7 +176,7 @@ int nicintel_spi_shutdown(void) > tmp |= FLASH_WRITES_DISABLED; > pci_mmio_writel(tmp, nicintel_spibar + EECD); > > - physunmap(nicintel_spibar, 4096); > + physunmap(nicintel_spibar, MEMMAP_SIZE); > pci_cleanup(pacc); > release_io_perms(); > > Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH 1/1] Simplify hwaccess.c
by Peter Lemenkov 26 Aug '12

26 Aug '12

This file is saturated with superfluous ifdefs arranged into several nested levels. This in turn adds additional complexity to process of adding another architecture. I re-arranged all ifdef blocks and killed duplicated function definitions. Also I added define(__amd64) to the list of x86-arches. Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- hwaccess.c | 85 +++++++++++++++++++++-------------------------------------- 1 files changed, 30 insertions(+), 55 deletions(-) diff --git a/hwaccess.c b/hwaccess.c index 3a61e60..4e87642 100644 --- a/hwaccess.c +++ b/hwaccess.c @@ -29,30 +29,47 @@ #endif #include "flash.h" +#if !( defined(__i386__) || \ + defined(__x86_64__) || defined(__amd64) || \ + defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) || \ + defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)) +#error Unknown architecture +#endif + #if defined(__i386__) || defined(__x86_64__) +#if defined(__FreeBSD__) || defined(__DragonFly__) +int io_fd; +#endif +#endif -/* sync primitive is not needed because x86 uses uncached accesses - * which have a strongly ordered memory model. - */ static inline void sync_primitive(void) { -} - -#if defined(__FreeBSD__) || defined(__DragonFly__) -int io_fd; +/* sync primitive is needed only on PowerPC because + * x86 uses uncached accesses which have a strongly ordered memory model + * /dev/mem on MIPS uses uncached accesses in mode 2 which has a strongly ordered memory model. + */ +#if defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + /* Prevent reordering and/or merging of reads/writes to hardware. + * Such reordering and/or merging would break device accesses which + * depend on the exact access order. + */ + asm("eieio" : : : "memory"); #endif +} void get_io_perms(void) { +/* PCI port I/O is not yet implemented on PowerPC or MIPS. */ +#if defined(__i386__) || defined(__x86_64__) || defined(__amd64) #if defined(__DJGPP__) /* We have full permissions by default. */ return; #else -#if defined (__sun) && (defined(__i386) || defined(__amd64)) +#if defined (__sun) if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { #elif defined(__FreeBSD__) || defined (__DragonFly__) if ((io_fd = open("/dev/io", O_RDWR)) < 0) { -#else +#else if (iopl(3) != 0) { #endif msg_perr("ERROR: Could not get I/O privileges (%s).\n" @@ -65,60 +82,18 @@ void get_io_perms(void) exit(1); } #endif +#endif } void release_io_perms(void) { +/* PCI port I/O is not yet implemented on PowerPC or MIPS. */ +#if defined(__i386__) || defined(__x86_64__) || defined(__amd64) #if defined(__FreeBSD__) || defined(__DragonFly__) close(io_fd); #endif -} - -#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) - -static inline void sync_primitive(void) -{ - /* Prevent reordering and/or merging of reads/writes to hardware. - * Such reordering and/or merging would break device accesses which - * depend on the exact access order. - */ - asm("eieio" : : : "memory"); -} - -/* PCI port I/O is not yet implemented on PowerPC. */ -void get_io_perms(void) -{ -} - -/* PCI port I/O is not yet implemented on PowerPC. */ -void release_io_perms(void) -{ -} - -#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) - -/* sync primitive is not needed because /dev/mem on MIPS uses uncached accesses - * in mode 2 which has a strongly ordered memory model. - */ -static inline void sync_primitive(void) -{ -} - -/* PCI port I/O is not yet implemented on MIPS. */ -void get_io_perms(void) -{ -} - -/* PCI port I/O is not yet implemented on MIPS. */ -void release_io_perms(void) -{ -} - -#else - -#error Unknown architecture - #endif +} void mmio_writeb(uint8_t val, void *addr) { -- 1.7.2.3

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Re: [flashrom] [PATCH 5/7] warn if SMM BIOS Write Protection is detected in BIOS_CNTL
by Stefan Reinauer 26 Aug '12

26 Aug '12

On 5/23/11 4:23 PM, Stefan Tauner wrote: > Signed-off-by: Stefan Tauner<stefan.tauner(a)student.tuwien.ac.at> > --- > chipset_enable.c | 12 +++++++++++- > 1 files changed, 11 insertions(+), 1 deletions(-) > > diff --git a/chipset_enable.c b/chipset_enable.c > index 83b49ad..339c6bb 100644 > --- a/chipset_enable.c > +++ b/chipset_enable.c > @@ -264,8 +264,18 @@ static int enable_flash_ich(struct pci_dev *dev, const char *name, > (old& (1<< 0)) ? "en" : "dis"); > msg_pdbg("BIOS_CNTL is 0x%x\n", old); > > - new = old | 1; > + /* > + * Quote from the 6 Series datasheet: > + * "5: SMM BIOS Write Protect Disable (SMM_BWP) > + * 1 = BIOS region SMM protection is enabled. > + * The BIOS Region is not writable unless all processors are in SMM." > + * In earlier chipsets this bit is reserved. */ > + if (old& (5<< 1)) { > + msg_pinfo("WARNING: BIOS region SMM protection is enabled!\n"); > + return -1; You might still be successful doing the write, in case the SMM handler does not enforce the protection, so maybe you should just print a warning but not return here? > + } > > + new = old | 1; > if (new == old) > return 0; >

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rtl8169 support - Final
by Jon Shadow 25 Aug '12

25 Aug '12

Fixed a few things. Still need someone to test it. Signed-off-by: Sergey Lichack <shadowpilot34(a)gmail.com>

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[PATCH] board enable for DFI AD77
by Tadas Slotkus 25 Aug '12

25 Aug '12

Hello, Thank you people on the IRC for helping with assembler :) Happy Easter!

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[PATCH] Make satasii driver more robust
by David Borg 25 Aug '12

25 Aug '12

Sorry, forgot to CC.the list. Updated patch to apply cleanly against latest revision (1151) and changed the string as pointed out by Rudolf Marek. Regards, David >-----BEGIN PGP SIGNED MESSAGE----- >Hash: SHA1 > >Hi thanks for doing that. > >Carl-Daniel Hailfinger wrote: >> Make the satasii driver more robust. >> >> Untested. >> >> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2...(a)gmx.net> >> >> Index: flashrom-satasii_robust/satasii.c >> =================================================================== >> --- flashrom-satasii_robust/satasii.c (Revision 1005) >> +++ flashrom-satasii_robust/satasii.c (Arbeitskopie) >> @@ -44,6 +44,7 @@ >> { >> uint32_t addr; >> uint16_t reg_offset; >> + uint32_t tmp; >> >> get_io_perms(); >> >> @@ -59,12 +60,19 @@ >> reg_offset = 0x50; >> } >> >> - sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset; >> + sii_bar = physmap("SATA SiI registers", addr, 0x100) + reg_offset; >> >> /* Check if ROM cycle are OK. */ >> if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26)))) >> msg_pinfo("Warning: Flash seems unconnected.\n"); >> >> + msg_pdbg("Using BAR5 access method.\n"); >> + tmp = pci_read_long(pcidev_dev, 0x40) & (1 << 1); >> + msg_pdbg("BAR5 Indirect Access is %snabled\n", tmp ? "en" : "dis"); >> + /* This bit has contradicting definitions in the 3512 datasheet. */ > >this looks strange you get dissnabled or ensabled ;) > >> + tmp = pci_read_long(pcidev_dev, 0x88) & (1 << 16); >> + msg_pdbg("BAR5 Access is %snabled\n", tmp ? "en" : "dis"); > >This Reg is EN_66 in other controllers so I guess it just this and not the >BA5_EN. It looks like it is driven by strap resistor only anyway. > >Interesting would be to test if BA5_EN is not enabled if you can access it >through indirect access through C0/C4 regs. > >Thanks, >Rudolf > > >> + >> buses_supported = CHIP_BUSTYPE_PARALLEL; >> >> return 0; >> @@ -81,6 +89,7 @@ >> void satasii_chip_writeb(uint8_t val, chipaddr addr) >> { >> uint32_t ctrl_reg, data_reg; >> + int i = 0; >> >> while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; >> >> @@ -92,12 +101,19 @@ >> mmio_writel(data_reg, (sii_bar + 4)); >> mmio_writel(ctrl_reg, sii_bar); >> >> - while (mmio_readl(sii_bar) & (1 << 25)) ; >> + while (mmio_readl(sii_bar) & (1 << 25)) { >> + if (++i > 10000) { >> + msg_perr("%s: control reg stuck at %08x, aborting\n", >> + __func__, mmio_readl(sii_bar)); >> + break; >> + } >> + } >> } >> >> uint8_t satasii_chip_readb(const chipaddr addr) >> { >> uint32_t ctrl_reg; >> + int i = 0; >> >> while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; >> >> @@ -107,7 +123,13 @@ >> >> mmio_writel(ctrl_reg, sii_bar); >> >> - while (mmio_readl(sii_bar) & (1 << 25)) ; >> + while (mmio_readl(sii_bar) & (1 << 25)) { >> + if (++i > 10000) { >> + msg_perr("%s: control reg stuck at %08x, aborting\n", >> + __func__, mmio_readl(sii_bar)); >> + break; >> + } >> + } >> >> return (mmio_readl(sii_bar + 4)) & 0xff; >> } >> >> >-----BEGIN PGP SIGNATURE----- >Version: GnuPG v1.4.10 (GNU/Linux) >Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org > >iEYEARECAAYFAkv4VwUACgkQ3J9wPJqZRNU4BQCfYmc1fp2kmy5SjQHjirrsKP82 >enkAoKQLbvmaCGs6/qNfawamobV7RayX >=7NEj >-----END PGP SIGNATURE----- > -- David Borg

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New flash chips, AT49F010 and CAT28F512
by Andrew Morgan 14 Aug '12

14 Aug '12

AT49F010 patch is basically a copy of the existing AT49F020 code, but with half the size and the correct ID. The log was from a write of random data, after the chip already contained different random data. I did separate read, erase, write tests before but this log seems to show that PREW all work. CAT28F512 I have successfully probed and read data from, but erase fails. Could be because it needs 12v VPP. The CAT28F512 I have is soldered on to a NIC. I haven't investigated if VPP is connected at all yet. Thought I'd include the patch as-is anyway. Both patches: Signed-off-by: Andrew Morgan <ziltro(a)ziltro.com> -- Andrew.

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[patch] board enable for ASUS P4P800-X (with erasing/writing SST SST49LF003A/B)
by Idwer Vollering 13 Aug '12

13 Aug '12

Enable writing/erasing on the ASUS P4P800-X, tested by mindcat on IRC. This board enable is inspired by the board enable for the ASUS P4P800-VM. As a bonus, testin the erasing/writing functionality on the SST SST49LF003A/B chip is now known to work. Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- Before (r1205/v0.9.3): Write report: http://paste.flashrom.org/view.php?id=465 Write report: http://paste.flashrom.org/view.php?id=466 After (r1285): Erase report: http://paste.flashrom.org/view.php?id=467

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[PATCH] Bus Pirate buffer management revamp
by Carl-Daniel Hailfinger 08 Jun '12

08 Jun '12

Use separate functions for managing the Bus Pirate command/data buffer. Open-coding the buffer management was the first step, now the goal is to make it readable. This is the buffer management part of "Re: [flashrom] [PATCH] Make Bus Pirate init more robust, speed up flashing" The buffer management of the Bus Pirate driver has been revamped to use grow-only buffers with a reasonable initial default size so realloc() will not have to be called in normal operation. A side effect is the ability to switch to a static buffer without major hassle. Handle OOM gracefully. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-buspirate_buffermanagement/flash.h =================================================================== --- flashrom-buspirate_buffermanagement/flash.h (Revision 1184) +++ flashrom-buspirate_buffermanagement/flash.h (Arbeitskopie) @@ -35,6 +35,9 @@ #define ERROR_PTR ((void*)-1) +/* Error codes */ +#define OOM_ERROR -100 + typedef unsigned long chipaddr; int register_shutdown(void (*function) (void *data), void *data); Index: flashrom-buspirate_buffermanagement/buspirate_spi.c =================================================================== --- flashrom-buspirate_buffermanagement/buspirate_spi.c (Revision 1184) +++ flashrom-buspirate_buffermanagement/buspirate_spi.c (Arbeitskopie) @@ -46,6 +46,55 @@ #define sp_flush_incoming(...) 0 #endif +static unsigned char *bp_commbuf = NULL; +static int bp_commbufsize = 0; + +static int buspirate_commbuf_resize(int bufsize) +{ + unsigned char *tmpbuf; + + /* Never shrink. realloc() calls are expensive. */ + if (bufsize <= bp_commbufsize) + return 0; + + tmpbuf = realloc(bp_commbuf, bufsize); + if (!tmpbuf) { + /* This is debatable. Do we really want to free the existing + * buffer or do we want to keep it around, especially if memory + * is already tight? + */ + free(bp_commbuf); + bp_commbuf = NULL; + bp_commbufsize = 0; + msg_perr("Out of memory!\n"); + return OOM_ERROR; + } + + bp_commbuf = tmpbuf; + bp_commbufsize = bufsize; + return 0; +} + +static int buspirate_commbuf_init(int bufsize) +{ + bp_commbuf = malloc(bufsize); + if (!bp_commbuf) { + bp_commbufsize = 0; + msg_perr("Out of memory!\n"); + return OOM_ERROR; + } + + bp_commbufsize = bufsize; + return 0; +} + +static void buspirate_commbuf_shutdown(void) +{ + free(bp_commbuf); + bp_commbuf = NULL; + bp_commbufsize = 0; +} + static int buspirate_sendrecv(unsigned char *buf, unsigned int writecnt, unsigned int readcnt) { int i, ret = 0; @@ -231,6 +280,10 @@ return 1; } + /* Sensible default buffer size. */ + if (buspirate_commbuf_init(16 + 3)) + return OOM_ERROR; + buses_supported = CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_BUSPIRATE; @@ -267,6 +320,9 @@ ret = serialport_shutdown(); if (ret) return ret; + + buspirate_commbuf_shutdown(); + msg_pdbg("Bus Pirate shutdown completed.\n"); return 0; @@ -275,55 +331,51 @@ int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - static unsigned char *buf = NULL; int i = 0, ret = 0; if (writecnt > 16 || readcnt > 16 || (readcnt + writecnt) > 16) return SPI_INVALID_LENGTH; /* 3 bytes extra for CS#, len, CS#. */ - buf = realloc(buf, writecnt + readcnt + 3); - if (!buf) { - msg_perr("Out of memory!\n"); - exit(1); // -1 - } + if (buspirate_commbuf_resize(writecnt + readcnt + 3)) + return OOM_ERROR; /* Assert CS# */ - buf[i++] = 0x02; + bp_commbuf[i++] = 0x02; - buf[i++] = 0x10 | (writecnt + readcnt - 1); - memcpy(buf + i, writearr, writecnt); + bp_commbuf[i++] = 0x10 | (writecnt + readcnt - 1); + memcpy(bp_commbuf + i, writearr, writecnt); i += writecnt; - memset(buf + i, 0, readcnt); + memset(bp_commbuf + i, 0, readcnt); i += readcnt; /* De-assert CS# */ - buf[i++] = 0x03; + bp_commbuf[i++] = 0x03; - ret = buspirate_sendrecv(buf, i, i); + ret = buspirate_sendrecv(bp_commbuf, i, i); if (ret) { msg_perr("Bus Pirate communication error!\n"); return SPI_GENERIC_ERROR; } - if (buf[0] != 0x01) { + if (bp_commbuf[0] != 0x01) { msg_perr("Protocol error while lowering CS#!\n"); return SPI_GENERIC_ERROR; } - if (buf[1] != 0x01) { + if (bp_commbuf[1] != 0x01) { msg_perr("Protocol error while reading/writing SPI!\n"); return SPI_GENERIC_ERROR; } - if (buf[i - 1] != 0x01) { + if (bp_commbuf[i - 1] != 0x01) { msg_perr("Protocol error while raising CS#!\n"); return SPI_GENERIC_ERROR; } /* Skip CS#, length, writearr. */ - memcpy(readarr, buf + 2 + writecnt, readcnt); + memcpy(readarr, bp_commbuf + 2 + writecnt, readcnt); return ret; } -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH] Remove sharplhf00l04.c
by Carl-Daniel Hailfinger 16 May '12

16 May '12

Am 20.06.2011 01:13 schrieb Michael Karcher: > The currently unreferenced function in sharplhf00l04.c does a standard > FWH block protection reset (writes 0 to the protection register) and a > standard FWH block erase. > > The locking blocks of the FWH block lock cover 128KB areas, and thats > the only thing page_size is used for in the functions referenced in the > LHF00L04 entry. > My datasheet talks about 8 kB sectors and 64 kB blocks in "Figure 3. Memory Map", but "Table 8. FWH Flash Registers Configuration Map" only mentions registers for the 8 kB sectors in the top 64 kB block explicitly. "Table 8" also mentions "XX002H Whole Block Lock Register" as generic placeholder, and AFAICS those two X mean you have one block lock register for each of the 15 bottom 64 kB blocks and one for each of the 8 top 8 kB sectors. That also means the 82802ab unlocking as is can't be used. I was unable to find any 128 kB reference in my datasheet, so I'm going to Nack that part. > Finally, this adds a comment that there are non-volatile (flash memory) > lock bits for 8 sectors in the last 64KB. They are write-only and clearable > at once. Readback seems unsupported. > I have a slightly different interpretation of the datasheet (see above), so I'm not sure how to proceed. > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > Killing sharplhf00l04.c is a good thing, though, so that part is Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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flashrom December 2011