July 2010 - flashrom - mail.coreboot.org

[PATCH] Neuter probe for ITE SuperIO
by Ed Swierk Aug. 16, 2010

Aug. 16, 2010

If the system has an SMSC LPC47N217N SuperIO, enter_conf_mode_ite() enters configuration mode, and then exit_conf_mode_ite() kills power to the serial UART. I don't know if there is a proper way to detect what kind of SuperIO the system has, but probe_superio_ite() is unsafe in its current form. Signed-off-by: Ed Swierk <eswierk(a)aristanetworks.com> --- Index: flashrom-0.9.2-r1057/internal.c =================================================================== --- flashrom-0.9.2-r1057.orig/internal.c +++ flashrom-0.9.2-r1057/internal.c @@ -104,7 +104,10 @@ struct superio superio = {}; void probe_superio(void) { +#if 0 + /* ITE probe causes SMSC LPC47N217 to power off the serial UART! */ superio = probe_superio_ite(); +#endif #if 0 /* Winbond Super I/O code is not yet available. */ if (superio.vendor == SUPERIO_VENDOR_NONE)

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[PATCH] Check availability of GPO lines on Intel PIIX4
by Mattias Mattsson Aug. 15, 2010

Aug. 15, 2010

Hi, I'm not a skilled programmer so this patch may look rather ugly. (Suggestions to improve it are very welcome.) Anyways, this changes the intel_piix4_gpo_set() function to always check the GENCFG and XBCS register for the availability of the requested GPO line (unless called with safe=0) before raising/lowering it. This behaviour was suggested by Michael Karcher on the flashrom mailing list and this is an attempt implementing it. Also adds a board enable for Asus P2B-N. Probe/Read/Write/Erease tested and works with this board. Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com> Index: board_enable.c =================================================================== --- board_enable.c (revision 1091) +++ board_enable.c (working copy) @@ -947,13 +947,67 @@ } /** + * Helper function to check if a given gpo line is available on Intel PIIX4{,E,M}. + */ +static int intel_piix4_gpo_available(unsigned int gpo, struct pci_dev *pci_dev) +{ + + uint32_t gencfg; + uint16_t xbcs; + + gencfg = pci_read_long(pci_dev, 0xB0); /* GENCFG */ + xbcs = pci_read_word(pci_dev, 0x4E); /* XBCS */ + + if ((gpo == 0)) { + return 1; /* GPO0 is always available */ + + } else if ((gpo >= 1) && (gpo <= 7)) { + return ((gencfg & 1) == 0); /* GENCFG bit 0 */ + + } else if ((gpo == 8)) { + return -1; /* GPO8 is never available */ + + } else if ((gpo >= 9) && (gpo <= 11)) { + return ((gencfg & (1 << (gpo - 1))) == 0); /* GENCFG bit 8-10 */ + + } else if ((gpo >= 12) && (gpo <= 14)) { + return ((xbcs & (1 << 8)) == 0); /* XBCS bit 8 */ + + } else if ((gpo >= 15) && (gpo <= 16)) { + return ((gencfg & (1 << 17)) == 1); /* GENCFG bit 17 */ + + } else if ((gpo >= 17) && (gpo <= 21)) { + return ((gencfg & (1 << (gpo + 1))) == 1); /* GENCFG bit 18-22 */ + + } else if ((gpo >= 22) && (gpo <= 23)) { + return ((gencfg & (1 << 28)) == 1); /* GENCFG bit 28 */ + + } else if ((gpo >= 24) && (gpo <= 26)) { + return ((gencfg & (1 << (gpo + 5))) == 1); /* GENCFG bit 29-31 */ + + } else if ((gpo >= 27) && (gpo <= 28)) { + return 1; /* GPO27-28 is always available */ + + } else if ((gpo == 29)) { + return ((xbcs & (1 << 8)) == 0); /* XBCS bit 8 */ + + } else if ((gpo == 30)) { + return 1; /* GPO30 is always available */ + + } else { + return -1; + } +} + +/** * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}. */ -static int intel_piix4_gpo_set(unsigned int gpo, int raise) +static int intel_piix4_gpo_set(unsigned int gpo, int raise, int safe) { unsigned int gpo_byte, gpo_bit; struct pci_dev *dev; uint32_t tmp, base; + uint16_t tmp2; dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */ if (!dev) { @@ -967,36 +1021,86 @@ return -1; } - /* these are dual function pins which are most likely in use already */ - if (((gpo >= 1) && (gpo <= 7)) || - ((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) { - msg_perr("\nERROR: Unsupported PIIX4 GPO%d.\n", gpo); - return -1; - } + if (safe) { + if (intel_piix4_gpo_available(gpo, dev) == -1) { + msg_perr("\nERROR: Intel PIIX4 GPO%d not available.\n", gpo); + return -1; + } + } else { + /* dual function that need special enable. */ - /* dual function that need special enable. */ - if ((gpo >= 22) && (gpo <= 26)) { - tmp = pci_read_long(dev, 0xB0); /* GENCFG */ + tmp = pci_read_long(dev, 0xB0); /* GENCFG */ + tmp2 = pci_read_word(dev, 0x4E); /* XBCS */ switch (gpo) { - case 22: /* XBUS: XDIR#/GPO22 */ - case 23: /* XBUS: XOE#/GPO23 */ - tmp |= 1 << 28; + case 0: break; - case 24: /* RTCSS#/GPO24 */ - tmp |= 1 << 29; + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + tmp &= ~(1 << 0); /* GENCFG bit 0: 0 = GPI0+GPO1-7 / 1 = IOCHK#+LA17-23 */ break; - case 25: /* RTCALE/GPO25 */ - tmp |= 1 << 30; + case 8: break; - case 26: /* KBCSS#/GPO26 */ - tmp |= 1 << 31; + case 9: + tmp &= ~(1 << 8); /* GENCFG bit 8: 0 = GPI2+GPO9 / 1 = PC/PCI REQA+GNTA */ break; - } - pci_write_long(dev, 0xB0, tmp); - } + case 10: + tmp &= ~(1 << 9); /* GENCFG bit 9: 0 = GPI3+GPO10 / 1 = PC/PCI REQB+GNTB */ + break; + case 11: + tmp &= ~(1 << 10); /* GENCFG bit 10: 0 = GPI4+GPO11 / 1 = PC/PCI REQC+GNTC */ + break; + case 12: + case 13: + case 14: + case 29: + tmp2 &= ~(1 << 8); /* XBCS bit 8: 0 = GPI5+GPO12-14+GPO29 / 1 = APIC Chip select */ + break; + case 15: + case 16: + tmp |= 1 << 17; /* GENCFG bit 17: 0 = SUSB#+SUSC# / 1 = GPO15+GPO16 */ + break; + case 17: + tmp |= 1 << 18; /* GENCFG bit 18: 0 = CPU_STP# / 1 = GPO17 */ + break; + case 18: + tmp |= 1 << 19; /* GENCFG bit 19: 0 = PCI_STP# / 1 = GPO18 */ + break; + case 19: + tmp |= 1 << 20; /* GENCFG bit 20: 0 = ZZ / 1 = GPO19 */ + break; + case 20: + tmp |= 1 << 21; /* GENCFG bit 21: 0 = SUS_STAT1# / 1 = GPO20 */ + break; + case 21: + tmp |= 1 << 22; /* GENCFG bit 22: 0 = SUS_STAT2# / 1 = GPO21 */ + break; + case 22: + case 23: + tmp |= 1 << 28; /* GENCFG bit 28: 0 = XDIR#+XDIR# / 1 = GPO22+GPO23 */ + break; + case 24: + tmp |= 1 << 29; /* GENCFG bit 29: 0 = RTCSS# / 1 = GPO24 */ + break; + case 25: + tmp |= 1 << 30; /* GENCFG bit 30: 0 = RTCALE / 1 = GPO25 */ + break; + case 26: + tmp |= 1 << 31; /* GENCFG bit 31: 0 = KBCSS# / 1 = GPO26 */ + break; + case 27: + case 28: + case 30: + break; + } + pci_write_long(dev, 0xB0, tmp); + pci_write_word(dev, 0x4E, tmp2); + } - /* GPO {0,8,27,28,30} are always available. */ - dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */ if (!dev) { msg_perr("\nERROR: Intel PIIX4 PM not found.\n"); @@ -1023,15 +1127,23 @@ */ static int board_epox_ep_bx3(void) { - return intel_piix4_gpo_set(22, 1); + return intel_piix4_gpo_set(22, 1, 1); } /** + * Suited for Asus P2B-N + */ +static int intel_piix4_gpo18_lower(void) +{ + return intel_piix4_gpo_set(18, 0, 1); +} + +/** * Suited for Intel SE440BX-2 */ static int intel_piix4_gpo27_lower(void) { - return intel_piix4_gpo_set(27, 0); + return intel_piix4_gpo_set(27, 0, 1); } /** @@ -1672,6 +1784,7 @@ {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, "ASUS", "A8N-VM CSM", 0, NT, w83627ehf_gpio24_raise_2e}, {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, + {0x8086, 0x7190, 0, 0, 0x8086, 0x7191, 0, 0, "^P2B-N$", NULL, NULL, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower}, {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise}, {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise},

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Flashrom -V output from Tyan S2915
by Richard W.M. Jones Aug. 10, 2010

Aug. 10, 2010

It still doesn't work for me. The ROM image supplied by Tyan is larger than 1MB and flashrom reports: Error: Image size doesn't match Presumably there is some sort of header in the image file. Anyway, I hope this output is useful to you in some way. Rich. -- Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones libguestfs lets you edit virtual machines. Supports shell scripting, bindings from many languages. http://et.redhat.com/~rjones/libguestfs/ See what it can do: http://et.redhat.com/~rjones/libguestfs/recipes.html

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Re: [flashrom] [coreboot] Winflashrom plans
by Carl-Daniel Hailfinger Aug. 10, 2010

Aug. 10, 2010

Hi Darmawan, nice to see you're back. flashrom has its own mailing list and I added it to CC. On 15.06.2010 21:56, Darmawan Salihun wrote: > Sorry, I haven't been able to update Winflashrom for more than 3 years now. > I'm planning to add Windows 7 support next month. > Nice! > Therefore, I'm looking for suggestions. > > A bit of Winflashrom background of the currently available Winflashrom > (at flashrom.org) > > The programming model: > a. User mode application: > - Mostly "pure" flashrom source code recompiled with MinGW. > Current flashrom can be compiled with MinGW and Cygwin, but it doesn't support any PCI accesses (USB and serial work). > - libpci recompiled with MinGW (for PCI access logic). This is > required because > the PCI access functions in the Windows API is not guaranteed > (marked as obsolete), > in Windows XP SP2 and Windows 2003 server back then. > If the PCI access functions are still available in Windows 7, can we simply ignore the "deprecated" warnings? CF8/CFC accesses from userspace are not atomic and might cause mixed up PCI accesses. > b. Device driver: > - Provides POSIX mmap() implementation in the kernel, i.e. > provides an entrypoint for mmap() function to user mode application. > Please note that we need two types of memory mapping: sys_physmap_ro_cached() and sys_physmap_rw_uncached(). For example, the low memory mapping for coreboot tables uses the readonly cached variant, and any future DMI string access will also use the readonly cached variant. Any MMIO areas (including flash access) use the uncached rw variant. Some operating systems do not care at all about cached/uncached mapping (they simply use the default caching settings of that memory region), and for those you can use the uncached rw access for both access types. > - Provides direct I/O port access for libpci. > > Well, the reason for these programming model is to reduce the burden > when moving to newer flash chip support because this programming model > "preserves" the POSIX API in the user mode application (the device > driver is generic enough). > Therefore, "only" the user mode application need to be recompiled to > support new flash chip. > > Any suggestions on what to change from the current programming model? > Current flashrom already supports PCI device flashing and onboard flashing on DOS, Linux, FreeBSD, NetBSD, DragonFlyBSD, OpenSolaris, Mac OS X and a few others. Please take a look at hwaccess.c and hwaccess.h and physmap.c for things you might want to change for Windows PCI support. I expect Windows support in flashrom to need ~60 lines of code, maybe less. The device driver (and libpci support) is a different question, though. If you have to modify any file except hwaccess.c, hwaccess.h, physmap.c or Makefile please tell us. If you have any questions, feel free to ask at flashrom(a)flashrom.org or in #flashrom on irc.freenode.net. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH 05/11] Rebased Board Enable Patch: A8JM board_enable patch (was Re: A8JM flashrom unable to erase)
by Sean Nelson Aug. 8, 2010

Aug. 8, 2010

This patch replaces the earlier one sent, and adds A8JM (and possibly all A8J series) support, and additionally adds DMI detection of A8J, after the r896 fix to dmi detection. Signed-off-by: James Lancaster <deathstalker(a)gmail.com> The DMI identification triggers on either the 2nd or 5th dmi strings, which are both "A8J" followed by different numbers of spaces. Combined with the PCI IDs, it might work on any of the A8J series seeing that the main difference in all but the A8JS is the video card/screen (possibly that too, while there they did add sata in place of IDE). I believe (based on having a video card that was supposed to only be on the A8JS, that it has a different device number (1232), that the A8JS will not be picked up.) I've tested this on my own computer, it picks it up and appears to flash just fine. I think I probably should have added Acked by as it works, but I'll be conservative on the issue. --- board_enable.c | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletions(-) diff --git a/board_enable.c b/board_enable.c index 36bf6e4..89dad8a 100644 --- a/board_enable.c +++ b/board_enable.c @@ -910,26 +910,34 @@ static int intel_ich_gpio_set(int gpio, int raise) return 0; } /** * Suited for Abit IP35: Intel P35 + ICH9R. * Suited for Abit IP35 Pro: Intel P35 + ICH9R. */ static int intel_ich_gpio16_raise(const char *name) { return intel_ich_gpio_set(16, 1); } /** + * Suited for ASUS A8JM: Intel 945 + ICH7 + */ +static int intel_ich_gpio34_raise(const char *name) +{ + return intel_ich_gpio_set(34, 1); +} + +/** * Suited for MSI MS-7046: LGA775 + 915P + ICH6. */ static int intel_ich_gpio19_raise(const char *name) { return intel_ich_gpio_set(19, 1); } /** * Suited for: * - Asus P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2. * - Asus P4C800-E Deluxe: socket478 + 875P + ICH5. * - Asus P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R. */ @@ -1290,26 +1298,27 @@ struct board_pciid_enable board_pciid_enables[] = { {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "Abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, NT, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e}, + {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8JM", 0, NT, intel_ich_gpio34_raise}, {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25}, {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise}, {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, NULL, "Biostar", "P4M80-M4", 0, OK, it8705f_write_enable_2e}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, {0x1039, 0x5513, 0x1019, 0x0A41, 0x1039, 0x0018, 0, 0, NULL, NULL, NULL, "Elitegroup", "K7S6A", 0, OK, it8705f_write_enable_2e}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, it8705f_write_enable_2e}, @@ -1323,27 +1332,27 @@ struct board_pciid_enable board_pciid_enables[] = { {0x10DE, 0x0360, 0x1458, 0x0C11, 0x10DE, 0x0369, 0x1458, 0x5001, NULL, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", 0, OK, it87xx_probe_spi_flash}, {0x10de, 0x03e0, 0, 0, 0x10DE, 0x03D0, 0, 0, NULL, NULL, NULL, "GIGABYTE", "GA-M61P-S3", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x7910, 0x1458, 0x5000, 0x1002, 0x438D, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-MA69VM-S2", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, NULL, NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, NULL, NULL, NULL, "GIGABYTE", "GA-MA790FX-DQ6", 0, OK, it87xx_probe_spi_flash}, {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, - {0x8086, 0x27A0, 0, 0, 0x8086, 0x27b8, 0, 0, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, + {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio4_4_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e}, {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, board_soyo_sy_7vca}, -- 1.6.6

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[PATCH] Board enable for ASUS A8N-LA (HP NAGAMI)
by Sean Nelson Aug. 8, 2010

Aug. 8, 2010

Reversed-engineered board enable for the ASUS A8N-LA. IDs are ISA and SMBus. Added dmi string to match 3 HP boards: Nagami, Nagami2, Nagami2L. Signed-off-by: Sean Nelson <audiohacked(a)gmail.com>

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[PATCH] Board enable for Asus P4S800-MX
by David Borg Aug. 8, 2010

Aug. 8, 2010

Tested and works. Thanks to Carl-Daniel Hailfinger for simplifying the chipset enable for this board! Index: board_enable.c =================================================================== --- board_enable.c (revision 1127) +++ board_enable.c (working copy) @@ -352,7 +352,9 @@ } /** - * w83627: Enable MEMW# and set ROM size to max. + * Enable MEMW# and set ROM size to max. + * Supported chips: + * W83L517D, W83697HF/F/HG, W83697SF/UF/UG */ static void w836xx_memw_enable(uint16_t port) { @@ -1715,6 +1717,7 @@ {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise}, + {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x0003, 0, 0, "^P4S800-MX$", NULL, NULL, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, Signed-off-by: David Borg <borg.db(a)gmail.com> On 28 July 2010 03:06, David Borg <borg.db(a)gmail.com> wrote: > > Updated the patch to remove anything related to chip (un)locking, as there is no way to unlock the superio except by a cold reset. > > Logs for the different flashrom runs and the outputs of lspci -nnvvvxxx and superiotool -deV are also attached. > > w836xx_memw_enable will work for this board, however i'd still like to see the function corrected for completeness sake. I haven't yet found a datasheet for a superio in the w83627 family where the function is correct, and the supported superio's all work with sio_mask(port, 0x24, 0x28, 0x38); Perhaps it should be fixed in a separate patch? > > Regards, > David > > On 1 July 2010 11:50, David Borg <borg.db(a)gmail.com> wrote: >> >> Patch to add support for the Asus P4S800-MX motherboard and SIS 963 >> chipset. Invalidates previous patch: [PATCH] add support for SIS963 >> >> If anyone has the output of superiotool -deV for the following working >> boards, please forward them, so I can merge the functions >> w836xx_unlock_memw_enable_2e and w836xx_memw_enable_2e, and maybe fix >> the function w836xx_memw_enable which I believe has a typo, such that >> sio_mask(port, 0x24, 0x28, 0x28); >> becomes : sio_mask(port, 0x24, 0x28, 0x38); >> >> Motherboards: >> Albatron - PM266A Pro >> ASUS - A7V8X-MX SE >> EPoX - EP-8K5A2 >> Shuttle - AK31 >> Tyan - S2498 (Tomcat K7M) >> Termtek - TK-3370 (Rev:2.5B) >> MSI - MS-6590 (KT4 Ultra) >> MSI - MS-6712 (KT4V) >> MSI - MS-7005 (651M-L) >> >> Signed-off-by: David Borg <borg.db(a)gmail.com> >> >> Regards, >> David > > > > -- > David Borg -- David Borg

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[PATCH] nicnatsemi.c: Typo. s/are apparently don't/apparently don't/
by Paul Menzel Aug. 8, 2010

Aug. 8, 2010

Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- nicnatsemi.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/nicnatsemi.c b/nicnatsemi.c index 1878f51..5f44677 100644 --- a/nicnatsemi.c +++ b/nicnatsemi.c @@ -60,7 +60,7 @@ void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr) /* * The datasheet requires 32 bit accesses to this register, but it seems * that requirement might only apply if the register is memory mapped. - * Bit 8-31 of this register are apparently don't care, and if this + * Bit 8-31 of this register apparently don't care, and if this * register is I/O port mapped 8 bit accesses to the lowest byte of the * register seem to work fine. Due to that, we ignore the advice in the * data sheet. @@ -74,7 +74,7 @@ uint8_t nicnatsemi_chip_readb(const chipaddr addr) /* * The datasheet requires 32 bit accesses to this register, but it seems * that requirement might only apply if the register is memory mapped. - * Bit 8-31 of this register are apparently don't care, and if this + * Bit 8-31 of this register apparently don't care, and if this * register is I/O port mapped 8 bit accesses to the lowest byte of the * register seem to work fine. Due to that, we ignore the advice in the * data sheet. -- 1.7.1

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tested boardenable/flashing on iBase:MB899
by Bernhard M. Wiedemann Aug. 8, 2010

Aug. 8, 2010

# flashrom -p internal:boardenable=force -m iBASE:MB899 -w coreboot.rom flashrom v0.9.1-runknown on Linux 2.6.18-skas3-v9-pre9-default (i686), built with libpci 2.2.4-pre4, GCC 3.4.6 (Debian 3.4.6-5) No coreboot table found. Found chipset "Intel ICH7M", enabling flash write... OK. This chipset supports the following protocols: FWH. NOTE: Running an untested board enable procedure. Please report success/failure to flashrom(a)flashrom.org. Disabling flash write protection for board "iBASE MB899"... Intel ICH LPC Bridge: Raising GPIO26. OK. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Writing flash chip... Erasing flash chip... SUCCESS. Programming page: DONE!ss: 0x0007f000 COMPLETE. Verifying flash... VERIFIED. -- Bernhard M. Wiedemann software engineer

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flashing BIOS using flashrom on ASUS M2N-SLI DELUXE
by Kasper M. Nielsen Aug. 8, 2010

Aug. 8, 2010

hi I don't know is you still need info on this type of motherboard but here are the logs from my successful attempt to flash my BIOS with you software Kasper M. Nielsen

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