July 2010 - flashrom - mail.coreboot.org

[commit] r1066 - trunk
by repository service July 1, 2010

July 1, 2010

Author: hailfinger Date: Thu Jul 1 19:45:54 2010 New Revision: 1066 URL: http://flashrom.org/trac/coreboot/changeset/1066 Log: ICH9/10: display FRAP/FREGx access controls Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Thu Jul 1 13:16:28 2010 (r1065) +++ trunk/chipset_enable.c Thu Jul 1 19:45:54 2010 (r1066) @@ -430,6 +430,44 @@ return 0; } +#define ICH_BMWAG(x) ((x >> 24) & 0xff) +#define ICH_BMRAG(x) ((x >> 16) & 0xff) +#define ICH_BRWA(x) ((x >> 8) & 0xff) +#define ICH_BRRA(x) ((x >> 0) & 0xff) + +#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) +#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) + +static void do_ich9_spi_frap(uint32_t frap, int i) +{ + const char *access_names[4] = { + "locked", "read-only", "write-only", "read-write" + }; + const char *region_names[5] = { + "Flash Descriptor", "BIOS", "Management Engine", + "Gigabit Ethernet", "Platform Data" + }; + int rwperms = ((ICH_BRWA(frap) & (1 << i)) << 1) | + ((ICH_BRRA(frap) & (1 << i)) << 0); + int offset = 0x54 + i * 4; + uint32_t freg = mmio_readl(spibar + offset), base, limit; + + msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", + offset, freg, i, region_names[i]); + + base = ICH_FREG_BASE(freg); + limit = ICH_FREG_LIMIT(freg); + if (base == 0x1fff && limit == 0) { + /* this FREG is disabled */ + msg_pdbg("%s region is unused.\n", region_names[i]); + return; + } + + msg_pdbg("0x%08x-0x%08x is %s\n", + (base << 12), (limit << 12) | 0x0fff, + access_names[rwperms]); +} + static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, int ich_generation) { @@ -554,21 +592,15 @@ tmp = mmio_readl(spibar + 0x50); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); - msg_pdbg("BMWAG %i, ", (tmp >> 24) & 0xff); - msg_pdbg("BMRAG %i, ", (tmp >> 16) & 0xff); - msg_pdbg("BRWA %i, ", (tmp >> 8) & 0xff); - msg_pdbg("BRRA %i\n", (tmp >> 0) & 0xff); - - msg_pdbg("0x54: 0x%08x (FREG0)\n", - mmio_readl(spibar + 0x54)); - msg_pdbg("0x58: 0x%08x (FREG1)\n", - mmio_readl(spibar + 0x58)); - msg_pdbg("0x5C: 0x%08x (FREG2)\n", - mmio_readl(spibar + 0x5C)); - msg_pdbg("0x60: 0x%08x (FREG3)\n", - mmio_readl(spibar + 0x60)); - msg_pdbg("0x64: 0x%08x (FREG4)\n", - mmio_readl(spibar + 0x64)); + msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); + msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); + msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); + msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); + + /* print out the FREGx registers along with FRAP access bits */ + for(i = 0; i < 5; i++) + do_ich9_spi_frap(tmp, i); + msg_pdbg("0x74: 0x%08x (PR0)\n", mmio_readl(spibar + 0x74)); msg_pdbg("0x78: 0x%08x (PR1)\n",

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[PATCH] Support for HP DL165 G6
by Arne Georg Gleditsch July 1, 2010

July 1, 2010

Hi, Attached is a patch to board_enable.c for the HP DL165 board. Apparently, the PCI signature of the DL165 is identical to the DL145, but the enable pins are placed differently... :/ I'm not sure what the best way to handle that is. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch(a)numascale.com> -- Arne.

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[commit] r1065 - trunk
by repository service July 1, 2010

July 1, 2010

Author: hailfinger Date: Thu Jul 1 13:16:28 2010 New Revision: 1065 URL: http://flashrom.org/trac/coreboot/changeset/1065 Log: Add support for the HP DL165 G6. Change the match for the HP DL145 G3 to avoid matching on the DL165 G6. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch(a)numascale.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Tue Jun 29 16:44:40 2010 (r1064) +++ trunk/board_enable.c Thu Jul 1 13:16:28 2010 (r1065) @@ -648,6 +648,20 @@ return 0; } +/* + * Set GPIO lines in the Broadcom HT-1000 southbridge. + * + * It's not a Super I/O but it uses the same index/data port method. + */ +static int board_hp_dl165_g6_enable(void) +{ + /* Variant of DL145, with slightly different pin placement. */ + sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */ + sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */ + + return 0; +} + static int board_ibm_x3455(void) { /* raise gpio13 */ @@ -1607,7 +1621,8 @@ {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, NULL, "GIGABYTE", "GA-7VT600", 0, OK, it8705f_write_enable_2e}, {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, - {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, + {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, + {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", "HP", "DL165 G6", 0, OK, board_hp_dl165_g6_enable}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, NULL, NULL, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise},

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