flashrom July 2010

flashrom@flashrom.org

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273 discussions

[PATCH] Allow programmers to disallow writes
by Carl-Daniel Hailfinger 03 Jul '10

03 Jul '10

If a programmer has untested or non-working write/erase code, but probing/reading works, it makes sense to protect the user against write/erase accidents. This feature will be used by the Nvidia MCP SPI code, and it also might make sense for the gfxnvidia driver which has non-working write/erase. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-programmer_may_write/flash.h =================================================================== --- flashrom-programmer_may_write/flash.h (Revision 1065) +++ flashrom-programmer_may_write/flash.h (Arbeitskopie) @@ -569,6 +569,7 @@ uint32_t spi; }; extern struct decode_sizes max_rom_decode; +extern int programmer_may_write; extern char *programmer_param; extern unsigned long flashbase; extern int verbose; Index: flashrom-programmer_may_write/flashrom.c =================================================================== --- flashrom-programmer_may_write/flashrom.c (Revision 1065) +++ flashrom-programmer_may_write/flashrom.c (Arbeitskopie) @@ -109,6 +109,9 @@ .spi = 0xffffffff }; +/* Is writing allowed with this programmer? */ +int programmer_may_write = 1; + const struct programmer_entry programmer_table[] = { #if CONFIG_INTERNAL == 1 { @@ -1360,6 +1363,21 @@ size = flash->total_size * 1024; buf = (uint8_t *) calloc(size, sizeof(char)); + if (!programmer_may_write && (write_it || erase_it)) { + msg_perr("Write/erase is not working yet on your programmer in " + "its current configuration.\n"); + /* --force is the wrong approach, but it's the best we can do + * until the generic programmer parameter parser is merged. + */ + if (!force) { + msg_perr("Aborting.\n"); + programmer_shutdown(); + return 1; + } else { + msg_cerr("Continuing anyway.\n"); + } + } + if (erase_it) { if (flash->tested & TEST_BAD_ERASE) { msg_cerr("Erase is not working on this chip. "); -- http://www.hailfinger.org/

2 4

[commit] r1069 - trunk
by repository service 03 Jul '10

03 Jul '10

Author: hailfinger Date: Sat Jul 3 14:14:25 2010 New Revision: 1069 URL: http://flashrom.org/trac/coreboot/changeset/1069 Log: If a programmer has untested or non-working write/erase code, but probing/reading works, it makes sense to protect the user against write/erase accidents. This feature will be used by the Nvidia MCP SPI code, and it also might make sense for the gfxnvidia driver which has non-working write/erase. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/flash.h trunk/flashrom.c Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Sat Jul 3 13:02:10 2010 (r1068) +++ trunk/flash.h Sat Jul 3 14:14:25 2010 (r1069) @@ -569,6 +569,7 @@ uint32_t spi; }; extern struct decode_sizes max_rom_decode; +extern int programmer_may_write; extern char *programmer_param; extern unsigned long flashbase; extern int verbose; Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sat Jul 3 13:02:10 2010 (r1068) +++ trunk/flashrom.c Sat Jul 3 14:14:25 2010 (r1069) @@ -103,6 +103,9 @@ /* If nonzero, used as the start address of bottom-aligned flash. */ unsigned long flashbase; +/* Is writing allowed with this programmer? */ +int programmer_may_write; + const struct programmer_entry programmer_table[] = { #if CONFIG_INTERNAL == 1 { @@ -447,6 +450,8 @@ flashbase = 0; /* Registering shutdown functions is now allowed. */ may_register_shutdown = 1; + /* Default to allowing writes. Broken programmers set this to 0. */ + programmer_may_write = 1; programmer_param = param; msg_pdbg("Initializing %s programmer\n", @@ -1383,6 +1388,21 @@ size = flash->total_size * 1024; buf = (uint8_t *) calloc(size, sizeof(char)); + if (!programmer_may_write && (write_it || erase_it)) { + msg_perr("Write/erase is not working yet on your programmer in " + "its current configuration.\n"); + /* --force is the wrong approach, but it's the best we can do + * until the generic programmer parameter parser is merged. + */ + if (!force) { + msg_perr("Aborting.\n"); + programmer_shutdown(); + return 1; + } else { + msg_cerr("Continuing anyway.\n"); + } + } + if (erase_it) { if (flash->tested & TEST_BAD_ERASE) { msg_cerr("Erase is not working on this chip. ");

1 0

[PATCH] Kill globals, initialize programmer-related variables explicitly
by Carl-Daniel Hailfinger 03 Jul '10

03 Jul '10

Kill global variables, constants and functions if local scope suffices. Constify variables where possible. Initialize programmer-related variables explicitly in programmer_init to allow running programmer_init from a clean state after programmer_shutdown. Kill some dead code. Rename global variables with namespace-polluting names. This is needed for libflashrom. Some of the const pointer to const changes may be excessive. Comments welcome. Effects on the binary size of flashrom are minimal (300 bytes shrinkage), but the data section shrinks by 4384 bytes, and that's a good thing if flashrom is operating in constrained envionments. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-explicit_init/flash.h =================================================================== --- flashrom-explicit_init/flash.h (Revision 1066) +++ flashrom-explicit_init/flash.h (Arbeitskopie) @@ -300,7 +300,7 @@ int (*enable) (void); }; -extern struct board_pciid_enable board_pciid_enables[]; +extern const struct board_pciid_enable board_pciid_enables[]; struct board_info { const char *vendor; @@ -335,15 +335,15 @@ const char *vendor_name; const char *device_name; }; -uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, struct pcidev_status *devs); -uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, struct pcidev_status *devs, char *pcidev_bdf); +uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, const struct pcidev_status *devs); +uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, const struct pcidev_status *devs, char *pcidev_bdf); #endif /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); void print_supported(void); #if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1 -void print_supported_pcidevs(struct pcidev_status *devs); +void print_supported_pcidevs(const struct pcidev_status *devs); #endif void print_supported_wiki(void); @@ -463,7 +463,7 @@ int nic3com_shutdown(void); void nic3com_chip_writeb(uint8_t val, chipaddr addr); uint8_t nic3com_chip_readb(const chipaddr addr); -extern struct pcidev_status nics_3com[]; +extern const struct pcidev_status nics_3com[]; #endif /* gfxnvidia.c */ @@ -472,7 +472,7 @@ int gfxnvidia_shutdown(void); void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr); uint8_t gfxnvidia_chip_readb(const chipaddr addr); -extern struct pcidev_status gfx_nvidia[]; +extern const struct pcidev_status gfx_nvidia[]; #endif /* drkaiser.c */ @@ -481,7 +481,7 @@ int drkaiser_shutdown(void); void drkaiser_chip_writeb(uint8_t val, chipaddr addr); uint8_t drkaiser_chip_readb(const chipaddr addr); -extern struct pcidev_status drkaiser_pcidev[]; +extern const struct pcidev_status drkaiser_pcidev[]; #endif /* nicrealtek.c */ @@ -491,8 +491,8 @@ int nicrealtek_shutdown(void); void nicrealtek_chip_writeb(uint8_t val, chipaddr addr); uint8_t nicrealtek_chip_readb(const chipaddr addr); -extern struct pcidev_status nics_realtek[]; -extern struct pcidev_status nics_realteksmc1211[]; +extern const struct pcidev_status nics_realtek[]; +extern const struct pcidev_status nics_realteksmc1211[]; #endif /* nicnatsemi.c */ @@ -501,7 +501,7 @@ int nicnatsemi_shutdown(void); void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr); uint8_t nicnatsemi_chip_readb(const chipaddr addr); -extern struct pcidev_status nics_natsemi[]; +extern const struct pcidev_status nics_natsemi[]; #endif /* satasii.c */ @@ -510,7 +510,7 @@ int satasii_shutdown(void); void satasii_chip_writeb(uint8_t val, chipaddr addr); uint8_t satasii_chip_readb(const chipaddr addr); -extern struct pcidev_status satas_sii[]; +extern const struct pcidev_status satas_sii[]; #endif /* atahpt.c */ @@ -519,7 +519,7 @@ int atahpt_shutdown(void); void atahpt_chip_writeb(uint8_t val, chipaddr addr); uint8_t atahpt_chip_readb(const chipaddr addr); -extern struct pcidev_status ata_hpt[]; +extern const struct pcidev_status ata_hpt[]; #endif /* ft2232_spi.c */ @@ -572,7 +572,7 @@ extern char *programmer_param; extern unsigned long flashbase; extern int verbose; -extern const char *flashrom_version; +extern const char * const flashrom_version; extern char *chip_to_probe; void map_flash_registers(struct flashchip *flash); int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); @@ -671,7 +671,6 @@ extern enum spi_controller spi_controller; extern const struct spi_programmer spi_programmer[]; -extern void *spibar; int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int spi_send_multicommand(struct spi_command *cmds); @@ -683,6 +682,7 @@ /* ichspi.c */ extern int ichspi_lock; extern uint32_t ichspi_bbar; +extern void *ich_spibar; int ich_init_opcodes(void); int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); Index: flashrom-explicit_init/drkaiser.c =================================================================== --- flashrom-explicit_init/drkaiser.c (Revision 1066) +++ flashrom-explicit_init/drkaiser.c (Arbeitskopie) @@ -26,12 +26,12 @@ #define PCI_MAGIC_DRKAISER_ADDR 0x50 #define PCI_MAGIC_DRKAISER_VALUE 0xa971 -struct pcidev_status drkaiser_pcidev[] = { +const struct pcidev_status drkaiser_pcidev[] = { {0x1803, 0x5057, OK, "Dr. Kaiser", "PC-Waechter (Actel FPGA)"}, {}, }; -uint8_t *drkaiser_bar; +static uint8_t *drkaiser_bar; int drkaiser_init(void) { Index: flashrom-explicit_init/it87spi.c =================================================================== --- flashrom-explicit_init/it87spi.c (Revision 1066) +++ flashrom-explicit_init/it87spi.c (Arbeitskopie) @@ -36,7 +36,7 @@ uint16_t it8716f_flashport = 0; /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ -int fast_spi = 1; +static int fast_spi = 1; /* Helper functions for most recent ITE IT87xx Super I/O chips */ #define CHIP_ID_BYTE1_REG 0x20 Index: flashrom-explicit_init/pcidev.c =================================================================== --- flashrom-explicit_init/pcidev.c (Revision 1066) +++ flashrom-explicit_init/pcidev.c (Arbeitskopie) @@ -25,11 +25,11 @@ uint32_t io_base_addr; struct pci_access *pacc; -struct pci_filter filter; +static struct pci_filter filter; struct pci_dev *pcidev_dev = NULL; uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, - struct pcidev_status *devs) + const struct pcidev_status *devs) { int i; /* FIXME: 64 bit memory BARs need a 64 bit addr. */ @@ -79,7 +79,7 @@ } uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, - struct pcidev_status *devs, char *pcidev_bdf) + const struct pcidev_status *devs, char *pcidev_bdf) { struct pci_dev *dev; char *msg = NULL; @@ -125,7 +125,7 @@ return curaddr; } -void print_supported_pcidevs(struct pcidev_status *devs) +void print_supported_pcidevs(const struct pcidev_status *devs) { int i; Index: flashrom-explicit_init/gfxnvidia.c =================================================================== --- flashrom-explicit_init/gfxnvidia.c (Revision 1066) +++ flashrom-explicit_init/gfxnvidia.c (Arbeitskopie) @@ -27,7 +27,7 @@ uint8_t *nvidia_bar; -struct pcidev_status gfx_nvidia[] = { +const struct pcidev_status gfx_nvidia[] = { {0x10de, 0x0010, NT, "NVIDIA", "Mutara V08 [NV2]" }, {0x10de, 0x0018, NT, "NVIDIA", "RIVA 128" }, {0x10de, 0x0020, NT, "NVIDIA", "RIVA TNT" }, Index: flashrom-explicit_init/nicrealtek.c =================================================================== --- flashrom-explicit_init/nicrealtek.c (Revision 1066) +++ flashrom-explicit_init/nicrealtek.c (Arbeitskopie) @@ -29,12 +29,12 @@ #define BIOS_ROM_ADDR 0xD4 #define BIOS_ROM_DATA 0xD7 -struct pcidev_status nics_realtek[] = { +const struct pcidev_status nics_realtek[] = { {0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"}, {}, }; -struct pcidev_status nics_realteksmc1211[] = { +const struct pcidev_status nics_realteksmc1211[] = { {0x1113, 0x1211, OK, "SMC2", "1211TX"}, /* RTL8139 clone */ {}, }; Index: flashrom-explicit_init/nic3com.c =================================================================== --- flashrom-explicit_init/nic3com.c (Revision 1066) +++ flashrom-explicit_init/nic3com.c (Arbeitskopie) @@ -31,10 +31,10 @@ #define PCI_VENDOR_ID_3COM 0x10b7 -uint32_t internal_conf; -uint16_t id; +static uint32_t internal_conf; +static uint16_t id; -struct pcidev_status nics_3com[] = { +const struct pcidev_status nics_3com[] = { /* 3C90xB */ {0x10b7, 0x9055, OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"}, {0x10b7, 0x9001, NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" }, Index: flashrom-explicit_init/spi.c =================================================================== --- flashrom-explicit_init/spi.c (Revision 1066) +++ flashrom-explicit_init/spi.c (Arbeitskopie) @@ -28,7 +28,6 @@ #include "spi.h" enum spi_controller spi_controller = SPI_CONTROLLER_NONE; -void *spibar = NULL; void spi_prettyprint_status_register(struct flashchip *flash); Index: flashrom-explicit_init/satasii.c =================================================================== --- flashrom-explicit_init/satasii.c (Revision 1066) +++ flashrom-explicit_init/satasii.c (Arbeitskopie) @@ -28,7 +28,7 @@ uint8_t *sii_bar; uint16_t id; -struct pcidev_status satas_sii[] = { +const struct pcidev_status satas_sii[] = { {0x1095, 0x0680, OK, "Silicon Image", "PCI0680 Ultra ATA-133 Host Ctrl"}, {0x1095, 0x3112, OK, "Silicon Image", "SiI 3112 [SATALink/SATARaid] SATA Ctrl"}, {0x1095, 0x3114, OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] SATA Ctrl"}, Index: flashrom-explicit_init/ft2232_spi.c =================================================================== --- flashrom-explicit_init/ft2232_spi.c (Revision 1066) +++ flashrom-explicit_init/ft2232_spi.c (Arbeitskopie) @@ -47,7 +47,7 @@ static struct ftdi_context ftdic_context; -int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) +static int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) { int r; r = ftdi_write_data(ftdic, (unsigned char *) buf, size); @@ -59,7 +59,7 @@ return 0; } -int get_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) +static int get_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) { int r; r = ftdi_read_data(ftdic, (unsigned char *) buf, size); Index: flashrom-explicit_init/chipset_enable.c =================================================================== --- flashrom-explicit_init/chipset_enable.c (Revision 1066) +++ flashrom-explicit_init/chipset_enable.c (Arbeitskopie) @@ -417,10 +417,10 @@ /* Do we really need no write enable? */ mmio_base = (pci_read_long(dev, 0xbc)) << 8; msg_pdbg("MMIO base at = 0x%x\n", mmio_base); - spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); + ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", - mmio_readw(spibar + 0x6c)); + mmio_readw(ich_spibar + 0x6c)); /* Not sure if it speaks all these bus protocols. */ buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; @@ -450,7 +450,7 @@ int rwperms = ((ICH_BRWA(frap) & (1 << i)) << 1) | ((ICH_BRRA(frap) & (1 << i)) << 0); int offset = 0x54 + i * 4; - uint32_t freg = mmio_readl(spibar + offset), base, limit; + uint32_t freg = mmio_readl(ich_spibar + offset), base, limit; msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", offset, freg, i, region_names[i]); @@ -536,50 +536,50 @@ msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); /* Assign Virtual Address */ - spibar = rcrb + spibar_offset; + ich_spibar = rcrb + spibar_offset; switch (spi_controller) { case SPI_CONTROLLER_ICH7: msg_pdbg("0x00: 0x%04x (SPIS)\n", - mmio_readw(spibar + 0)); + mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", - mmio_readw(spibar + 2)); + mmio_readw(ich_spibar + 2)); msg_pdbg("0x04: 0x%08x (SPIA)\n", - mmio_readl(spibar + 4)); + mmio_readl(ich_spibar + 4)); for (i = 0; i < 8; i++) { int offs; offs = 8 + (i * 8); msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, - mmio_readl(spibar + offs), i); + mmio_readl(ich_spibar + offs), i); msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, - mmio_readl(spibar + offs + 4), i); + mmio_readl(ich_spibar + offs + 4), i); } - ichspi_bbar = mmio_readl(spibar + 0x50); + ichspi_bbar = mmio_readl(ich_spibar + 0x50); msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar); msg_pdbg("0x54: 0x%04x (PREOP)\n", - mmio_readw(spibar + 0x54)); + mmio_readw(ich_spibar + 0x54)); msg_pdbg("0x56: 0x%04x (OPTYPE)\n", - mmio_readw(spibar + 0x56)); + mmio_readw(ich_spibar + 0x56)); msg_pdbg("0x58: 0x%08x (OPMENU)\n", - mmio_readl(spibar + 0x58)); + mmio_readl(ich_spibar + 0x58)); msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", - mmio_readl(spibar + 0x5c)); + mmio_readl(ich_spibar + 0x5c)); for (i = 0; i < 4; i++) { int offs; offs = 0x60 + (i * 4); msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, - mmio_readl(spibar + offs), i); + mmio_readl(ich_spibar + offs), i); } msg_pdbg("\n"); - if (mmio_readw(spibar) & (1 << 15)) { + if (mmio_readw(ich_spibar) & (1 << 15)) { msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } ich_init_opcodes(); break; case SPI_CONTROLLER_ICH9: - tmp2 = mmio_readw(spibar + 4); + tmp2 = mmio_readw(ich_spibar + 4); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); @@ -590,7 +590,7 @@ msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); - tmp = mmio_readl(spibar + 0x50); + tmp = mmio_readl(ich_spibar + 0x50); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); @@ -602,30 +602,30 @@ do_ich9_spi_frap(tmp, i); msg_pdbg("0x74: 0x%08x (PR0)\n", - mmio_readl(spibar + 0x74)); + mmio_readl(ich_spibar + 0x74)); msg_pdbg("0x78: 0x%08x (PR1)\n", - mmio_readl(spibar + 0x78)); + mmio_readl(ich_spibar + 0x78)); msg_pdbg("0x7C: 0x%08x (PR2)\n", - mmio_readl(spibar + 0x7C)); + mmio_readl(ich_spibar + 0x7C)); msg_pdbg("0x80: 0x%08x (PR3)\n", - mmio_readl(spibar + 0x80)); + mmio_readl(ich_spibar + 0x80)); msg_pdbg("0x84: 0x%08x (PR4)\n", - mmio_readl(spibar + 0x84)); + mmio_readl(ich_spibar + 0x84)); msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", - mmio_readl(spibar + 0x90)); + mmio_readl(ich_spibar + 0x90)); msg_pdbg("0x94: 0x%04x (PREOP)\n", - mmio_readw(spibar + 0x94)); + mmio_readw(ich_spibar + 0x94)); msg_pdbg("0x96: 0x%04x (OPTYPE)\n", - mmio_readw(spibar + 0x96)); + mmio_readw(ich_spibar + 0x96)); msg_pdbg("0x98: 0x%08x (OPMENU)\n", - mmio_readl(spibar + 0x98)); + mmio_readl(ich_spibar + 0x98)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", - mmio_readl(spibar + 0x9C)); - ichspi_bbar = mmio_readl(spibar + 0xA0); + mmio_readl(ich_spibar + 0x9C)); + ichspi_bbar = mmio_readl(ich_spibar + 0xA0); msg_pdbg("0xA0: 0x%08x (BBAR)\n", ichspi_bbar); msg_pdbg("0xB0: 0x%08x (FDOC)\n", - mmio_readl(spibar + 0xB0)); + mmio_readl(ich_spibar + 0xB0)); if (tmp2 & (1 << 15)) { msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; Index: flashrom-explicit_init/flashrom.c =================================================================== --- flashrom-explicit_init/flashrom.c (Revision 1066) +++ flashrom-explicit_init/flashrom.c (Arbeitskopie) @@ -34,7 +34,7 @@ #include "flash.h" #include "flashchips.h" -const char *flashrom_version = FLASHROM_VERSION; +const char * const flashrom_version = FLASHROM_VERSION; char *chip_to_probe = NULL; int verbose = 0; @@ -89,26 +89,23 @@ ; #endif +/* programmer_param is programmer-specific, but it MUST NOT be initialized in + * programmer_init() because it is initialized in the command line parser. + */ char *programmer_param = NULL; -/** - * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host - * controller is found, the init routine sets the buses_supported bitfield to - * contain the supported buses for that controller. - */ -enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; +/* Supported buses for the current programmer. */ +enum chipbustype buses_supported; /** * Programmers supporting multiple buses can have differing size limits on * each bus. Store the limits for each bus in a common struct. */ -struct decode_sizes max_rom_decode = { - .parallel = 0xffffffff, - .lpc = 0xffffffff, - .fwh = 0xffffffff, - .spi = 0xffffffff -}; +struct decode_sizes max_rom_decode; +/* If nonzero, used as the start address of bottom-aligned flash. */ +unsigned long flashbase; + const struct programmer_entry programmer_table[] = { #if CONFIG_INTERNAL == 1 { @@ -428,6 +425,21 @@ int programmer_init(void) { + /* Initialize all programmer specific data. */ + /* Default to unlimited decode sizes. */ + max_rom_decode = (const struct decode_sizes) { + .parallel = 0xffffffff, + .lpc = 0xffffffff, + .fwh = 0xffffffff, + .spi = 0xffffffff + }; + /* Default to Parallel/LPC/FWH flash devices. If a known host controller + * is found, the init routine sets the buses_supported bitfield. + */ + buses_supported = CHIP_BUSTYPE_NONSPI; + /* Default to top aligned flash at 4 GB. */ + flashbase = 0; + return programmer_table[programmer].init(); } @@ -437,6 +449,7 @@ for (i = shutdown_fn_count - 1; i >= 0; i--) shutdown_fn[i].func(shutdown_fn[i].data); + /* FIXME: Clear the shutdown function array on shutdown or startup? */ return programmer_table[programmer].shutdown(); } @@ -512,8 +525,6 @@ return 0; } -unsigned long flashbase = 0; - int min(int a, int b) { return (a < b) ? a : b; Index: flashrom-explicit_init/layout.c =================================================================== --- flashrom-explicit_init/layout.c (Revision 1066) +++ flashrom-explicit_init/layout.c (Arbeitskopie) @@ -28,7 +28,7 @@ char *mainboard_vendor = NULL; char *mainboard_part = NULL; #endif -int romimages = 0; +static int romimages = 0; #define MAX_ROMLAYOUT 16 @@ -39,7 +39,7 @@ char name[256]; } romlayout_t; -romlayout_t rom_entries[MAX_ROMLAYOUT]; +static romlayout_t rom_entries[MAX_ROMLAYOUT]; #if CONFIG_INTERNAL == 1 /* FIXME: Move the whole block to cbtable.c? */ static char *def_name = "DEFAULT"; Index: flashrom-explicit_init/ichspi.c =================================================================== --- flashrom-explicit_init/ichspi.c (Revision 1066) +++ flashrom-explicit_init/ichspi.c (Arbeitskopie) @@ -105,6 +105,8 @@ uint32_t ichspi_bbar = 0; +void *ich_spibar = NULL; + typedef struct _OPCODE { uint8_t opcode; //This commands spi opcode uint8_t spi_type; //This commands spi type @@ -134,17 +136,17 @@ /* HW access functions */ static uint32_t REGREAD32(int X) { - return mmio_readl(spibar + X); + return mmio_readl(ich_spibar + X); } static uint16_t REGREAD16(int X) { - return mmio_readw(spibar + X); + return mmio_readw(ich_spibar + X); } -#define REGWRITE32(X,Y) mmio_writel(Y, spibar+X) -#define REGWRITE16(X,Y) mmio_writew(Y, spibar+X) -#define REGWRITE8(X,Y) mmio_writeb(Y, spibar+X) +#define REGWRITE32(X,Y) mmio_writel(Y, ich_spibar+X) +#define REGWRITE16(X,Y) mmio_writew(Y, ich_spibar+X) +#define REGWRITE8(X,Y) mmio_writeb(Y, ich_spibar+X) /* Common SPI functions */ static int find_opcode(OPCODES *op, uint8_t opcode); @@ -161,7 +163,7 @@ }; /* List of opcodes which need preopcodes and matching preopcodes. Unused. */ -struct preop_opcode_pair pops[] = { +const struct preop_opcode_pair pops[] = { {JEDEC_WREN, JEDEC_BYTE_PROGRAM}, {JEDEC_WREN, JEDEC_SE}, /* sector erase */ {JEDEC_WREN, JEDEC_BE_52}, /* block erase */ @@ -177,7 +179,7 @@ /* Reasonable default configuration. Needs ad-hoc modifications if we * encounter unlisted opcodes. Fun. */ -OPCODES O_ST_M25P = { +static OPCODES O_ST_M25P = { { JEDEC_WREN, JEDEC_EWSR, @@ -194,7 +196,7 @@ } }; -OPCODES O_EXISTING = {}; +static OPCODES O_EXISTING = {}; static int find_opcode(OPCODES *op, uint8_t opcode) { @@ -337,15 +339,15 @@ { switch (spi_controller) { case SPI_CONTROLLER_ICH7: - mmio_writel(minaddr, spibar + 0x50); - ichspi_bbar = mmio_readl(spibar + 0x50); + mmio_writel(minaddr, ich_spibar + 0x50); + ichspi_bbar = mmio_readl(ich_spibar + 0x50); /* We don't have any option except complaining. */ if (ichspi_bbar != minaddr) msg_perr("Setting BBAR failed!\n"); break; case SPI_CONTROLLER_ICH9: - mmio_writel(minaddr, spibar + 0xA0); - ichspi_bbar = mmio_readl(spibar + 0xA0); + mmio_writel(minaddr, ich_spibar + 0xA0); + ichspi_bbar = mmio_readl(ich_spibar + 0xA0); /* We don't have any option except complaining. */ if (ichspi_bbar != minaddr) msg_perr("Setting BBAR failed!\n"); Index: flashrom-explicit_init/print_wiki.c =================================================================== --- flashrom-explicit_init/print_wiki.c (Revision 1066) +++ flashrom-explicit_init/print_wiki.c (Arbeitskopie) @@ -26,7 +26,7 @@ #include "flash.h" #include "flashchips.h" -const char *wiki_header = "= Supported devices =\n\n\ +static const char * const wiki_header = "= Supported devices =\n\n\ <div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ background-color:#eeeeee; align:right; border:1px solid #aabbcc;\"><small>\n\ Please do '''not''' edit these tables in the wiki directly, they are \ @@ -34,16 +34,16 @@ '''Last update:''' %s(generated by flashrom %s)\n</small></div>\n"; #if CONFIG_INTERNAL == 1 -const char *chipset_th = "{| border=\"0\" style=\"font-size: smaller\"\n\ +static const char * const chipset_th = "{| border=\"0\" style=\"font-size: smaller\"\n\ |- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ ! align=\"left\" | Southbridge\n! align=\"left\" | PCI IDs\n\ ! align=\"left\" | Status\n\n"; -const char *board_th = "{| border=\"0\" style=\"font-size: smaller\" \ +static const char * const board_th = "{| border=\"0\" style=\"font-size: smaller\" \ valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ ! align=\"left\" | Mainboard\n! align=\"left\" | Required option\n! align=\"left\" | Status\n\n"; -const char *board_intro = "\ +static const char * const board_intro = "\ \n== Supported mainboards ==\n\n\ In general, it is very likely that flashrom works out of the box even if your \ mainboard is not listed below.\n\nThis is a list of mainboards where we have \ @@ -56,14 +56,14 @@ mainboards on the [[Mailinglist|mailing list]].\n"; #endif -const char *chip_th = "{| border=\"0\" style=\"font-size: smaller\" \ +static const char * const chip_th = "{| border=\"0\" style=\"font-size: smaller\" \ valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ ! align=\"left\" | Device\n! align=\"left\" | Size / KB\n\ ! align=\"left\" | Type\n! align=\"left\" colspan=\"4\" | Status\n\n\ |- bgcolor=\"#6699ff\"\n| colspan=\"4\" |  \n\ | Probe\n| Read\n| Erase\n| Write\n\n"; -const char *programmer_section = "\ +static const char * const programmer_section = "\ \n== Supported programmers ==\n\nThis is a list \ of supported PCI devices flashrom can use as programmer:\n\n{| border=\"0\" \ valign=\"top\"\n| valign=\"top\"|\n\n{| border=\"0\" style=\"font-size: \ @@ -72,7 +72,7 @@ ! align=\"left\" | Status\n\n"; #if CONFIG_INTERNAL == 1 -const char *laptop_intro = "\n== Supported laptops/notebooks ==\n\n\ +static const char * const laptop_intro = "\n== Supported laptops/notebooks ==\n\n\ In general, flashing laptops is more difficult because laptops\n\n\ * often use the flash chip for stuff besides the BIOS,\n\ * often have special protection stuff which has to be handled by flashrom,\n\ @@ -124,7 +124,7 @@ int num_notes = 0; char *notes = calloc(1, 1); char tmp[900 + 1]; - struct board_pciid_enable *b = board_pciid_enables; + const struct board_pciid_enable *b = board_pciid_enables; for (i = 0; boards[i].vendor != NULL; i++) { if (boards[i].working) @@ -245,7 +245,7 @@ printf("\n|}\n\n|}\n"); } -static void print_supported_pcidevs_wiki(struct pcidev_status *devs) +static void print_supported_pcidevs_wiki(const struct pcidev_status *devs) { int i = 0; static int c = 0; Index: flashrom-explicit_init/udelay.c =================================================================== --- flashrom-explicit_init/udelay.c (Revision 1066) +++ flashrom-explicit_init/udelay.c (Arbeitskopie) @@ -26,7 +26,7 @@ #include "flash.h" /* loops per microsecond */ -unsigned long micro = 1; +static unsigned long micro = 1; __attribute__ ((noinline)) void myusec_delay(int usecs) { Index: flashrom-explicit_init/nicnatsemi.c =================================================================== --- flashrom-explicit_init/nicnatsemi.c (Revision 1066) +++ flashrom-explicit_init/nicnatsemi.c (Arbeitskopie) @@ -28,7 +28,7 @@ #define BOOT_ROM_ADDR 0x50 #define BOOT_ROM_DATA 0x54 -struct pcidev_status nics_natsemi[] = { +const struct pcidev_status nics_natsemi[] = { {0x100b, 0x0020, NT, "National Semiconductor", "DP83815/DP83816"}, {0x100b, 0x0022, NT, "National Semiconductor", "DP83820"}, {}, Index: flashrom-explicit_init/print.c =================================================================== --- flashrom-explicit_init/print.c (Revision 1066) +++ flashrom-explicit_init/print.c (Arbeitskopie) @@ -173,7 +173,7 @@ const char *devicetype) { int i, j, boardcount_good = 0, boardcount_bad = 0; - struct board_pciid_enable *b = board_pciid_enables; + const struct board_pciid_enable *b = board_pciid_enables; for (i = 0; boards[i].vendor != NULL; i++) { if (boards[i].working) Index: flashrom-explicit_init/dediprog.c =================================================================== --- flashrom-explicit_init/dediprog.c (Revision 1066) +++ flashrom-explicit_init/dediprog.c (Arbeitskopie) @@ -24,19 +24,21 @@ #include "spi.h" #define DEFAULT_TIMEOUT 3000 -usb_dev_handle *dediprog_handle; +static usb_dev_handle *dediprog_handle; -int dediprog_do_stuff(void); - -void print_hex(void *buf, size_t len) +#if 0 +/* Might be useful for other pieces of code as well. */ +static void print_hex(void *buf, size_t len) { size_t i; for (i = 0; i < len; i++) msg_pdbg(" %02x", ((uint8_t *)buf)[i]); } +#endif -struct usb_device *get_device_by_vid_pid(uint16_t vid, uint16_t pid) +/* Might be useful for other USB devices as well. static for now. */ +static struct usb_device *get_device_by_vid_pid(uint16_t vid, uint16_t pid) { struct usb_bus *bus; struct usb_device *dev; @@ -323,10 +325,11 @@ return 0; } +#if 0 /* Leftovers from reverse engineering. Keep for documentation purposes until * completely understood. */ -int dediprog_do_stuff(void) +static int dediprog_do_stuff(void) { char buf[0x4]; /* SPI command processing starts here. */ @@ -341,7 +344,6 @@ return 1; msg_pdbg("Receiving response: "); print_hex(buf, JEDEC_RDID_INSIZE); -#if 0 /* URB 14-27 are more SPI commands. */ /* URB 28. Command Set SPI Voltage. */ if (dediprog_set_spi_voltage(0x0)) @@ -369,12 +371,10 @@ /* Command I is probably Start Bulk Read. Data is u16 blockcount, u16 blocksize. */ /* Command J is probably Start Bulk Write. Data is u16 blockcount, u16 blocksize. */ /* Bulk transfer sizes for Command I/J are always 512 bytes, rest is filled with 0xff. */ -#endif - msg_pinfo("All probes will fail because this driver is not hooked up " - "to the SPI infrastructure yet."); return 0; } +#endif int dediprog_shutdown(void) { Index: flashrom-explicit_init/board_enable.c =================================================================== --- flashrom-explicit_init/board_enable.c (Revision 1066) +++ flashrom-explicit_init/board_enable.c (Arbeitskopie) @@ -1577,7 +1577,7 @@ */ /* Please keep this list alphabetically ordered by vendor/board name. */ -struct board_pciid_enable board_pciid_enables[] = { +const struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ #if defined(__i386__) || defined(__x86_64__) @@ -1661,11 +1661,11 @@ * Match boards on coreboot table gathered vendor and part name. * Require main PCI IDs to match too as extra safety. */ -static struct board_pciid_enable *board_match_coreboot_name(const char *vendor, +static const struct board_pciid_enable *board_match_coreboot_name(const char *vendor, const char *part) { - struct board_pciid_enable *board = board_pciid_enables; - struct board_pciid_enable *partmatch = NULL; + const struct board_pciid_enable *board = board_pciid_enables; + const struct board_pciid_enable *partmatch = NULL; for (; board->vendor_name; board++) { if (vendor && (!board->lb_vendor @@ -1714,9 +1714,9 @@ * Match boards on PCI IDs and subsystem IDs. * Second set of IDs can be main only or missing completely. */ -static struct board_pciid_enable *board_match_pci_card_ids(void) +const static struct board_pciid_enable *board_match_pci_card_ids(void) { - struct board_pciid_enable *board = board_pciid_enables; + const struct board_pciid_enable *board = board_pciid_enables; for (; board->vendor_name; board++) { if ((!board->first_card_vendor || !board->first_card_device) && @@ -1762,7 +1762,7 @@ int board_flash_enable(const char *vendor, const char *part) { - struct board_pciid_enable *board = NULL; + const struct board_pciid_enable *board = NULL; int ret = 0; if (part) -- http://www.hailfinger.org/

2 6

[commit] r1068 - trunk
by repository service 03 Jul '10

03 Jul '10

Author: hailfinger Date: Sat Jul 3 13:02:10 2010 New Revision: 1068 URL: http://flashrom.org/trac/coreboot/changeset/1068 Log: Kill global variables, constants and functions if local scope suffices. Constify variables where possible. Initialize programmer-related variables explicitly in programmer_init to allow running programmer_init from a clean state after programmer_shutdown. Prohibit registering programmer shutdown functions before init or after shutdown. Kill some dead code. Rename global variables with namespace-polluting names. Use a previously unused locking helper function in sst49lfxxxc.c. This is needed for libflashrom. Effects on the binary size of flashrom are minimal (300 bytes shrinkage), but the data section shrinks by 4384 bytes, and that's a good thing if flashrom is operating in constrained envionments. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/board_enable.c trunk/buspirate_spi.c trunk/chipset_enable.c trunk/cli_classic.c trunk/dediprog.c trunk/dmi.c trunk/drkaiser.c trunk/flash.h trunk/flashrom.c trunk/ft2232_spi.c trunk/gfxnvidia.c trunk/ichspi.c trunk/it87spi.c trunk/jedec.c trunk/layout.c trunk/nic3com.c trunk/nicnatsemi.c trunk/nicrealtek.c trunk/pcidev.c trunk/physmap.c trunk/pm49fl00x.c trunk/print.c trunk/print_wiki.c trunk/satasii.c trunk/spi.c trunk/sst28sf040.c trunk/sst49lfxxxc.c trunk/sst_fwhub.c trunk/stm50flw0x0x.c trunk/udelay.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/board_enable.c Sat Jul 3 13:02:10 2010 (r1068) @@ -1577,7 +1577,7 @@ */ /* Please keep this list alphabetically ordered by vendor/board name. */ -struct board_pciid_enable board_pciid_enables[] = { +const struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ #if defined(__i386__) || defined(__x86_64__) @@ -1661,11 +1661,11 @@ * Match boards on coreboot table gathered vendor and part name. * Require main PCI IDs to match too as extra safety. */ -static struct board_pciid_enable *board_match_coreboot_name(const char *vendor, +static const struct board_pciid_enable *board_match_coreboot_name(const char *vendor, const char *part) { - struct board_pciid_enable *board = board_pciid_enables; - struct board_pciid_enable *partmatch = NULL; + const struct board_pciid_enable *board = board_pciid_enables; + const struct board_pciid_enable *partmatch = NULL; for (; board->vendor_name; board++) { if (vendor && (!board->lb_vendor @@ -1714,9 +1714,9 @@ * Match boards on PCI IDs and subsystem IDs. * Second set of IDs can be main only or missing completely. */ -static struct board_pciid_enable *board_match_pci_card_ids(void) +const static struct board_pciid_enable *board_match_pci_card_ids(void) { - struct board_pciid_enable *board = board_pciid_enables; + const struct board_pciid_enable *board = board_pciid_enables; for (; board->vendor_name; board++) { if ((!board->first_card_vendor || !board->first_card_device) && @@ -1762,7 +1762,7 @@ int board_flash_enable(const char *vendor, const char *part) { - struct board_pciid_enable *board = NULL; + const struct board_pciid_enable *board = NULL; int ret = 0; if (part) Modified: trunk/buspirate_spi.c ============================================================================== --- trunk/buspirate_spi.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/buspirate_spi.c Sat Jul 3 13:02:10 2010 (r1068) @@ -30,7 +30,7 @@ #undef FAKE_COMMUNICATION #ifndef FAKE_COMMUNICATION -int buspirate_serialport_setup(char *dev) +static int buspirate_serialport_setup(char *dev) { /* 115200bps, 8 databits, no parity, 1 stopbit */ sp_fd = sp_openserport(dev, 115200); @@ -44,7 +44,7 @@ #define sp_flush_incoming(...) 0 #endif -int buspirate_sendrecv(unsigned char *buf, unsigned int writecnt, unsigned int readcnt) +static int buspirate_sendrecv(unsigned char *buf, unsigned int writecnt, unsigned int readcnt) { int i, ret = 0; Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/chipset_enable.c Sat Jul 3 13:02:10 2010 (r1068) @@ -417,10 +417,10 @@ /* Do we really need no write enable? */ mmio_base = (pci_read_long(dev, 0xbc)) << 8; msg_pdbg("MMIO base at = 0x%x\n", mmio_base); - spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); + ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", - mmio_readw(spibar + 0x6c)); + mmio_readw(ich_spibar + 0x6c)); /* Not sure if it speaks all these bus protocols. */ buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; @@ -450,7 +450,7 @@ int rwperms = ((ICH_BRWA(frap) & (1 << i)) << 1) | ((ICH_BRRA(frap) & (1 << i)) << 0); int offset = 0x54 + i * 4; - uint32_t freg = mmio_readl(spibar + offset), base, limit; + uint32_t freg = mmio_readl(ich_spibar + offset), base, limit; msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", offset, freg, i, region_names[i]); @@ -536,50 +536,50 @@ msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); /* Assign Virtual Address */ - spibar = rcrb + spibar_offset; + ich_spibar = rcrb + spibar_offset; switch (spi_controller) { case SPI_CONTROLLER_ICH7: msg_pdbg("0x00: 0x%04x (SPIS)\n", - mmio_readw(spibar + 0)); + mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", - mmio_readw(spibar + 2)); + mmio_readw(ich_spibar + 2)); msg_pdbg("0x04: 0x%08x (SPIA)\n", - mmio_readl(spibar + 4)); + mmio_readl(ich_spibar + 4)); for (i = 0; i < 8; i++) { int offs; offs = 8 + (i * 8); msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, - mmio_readl(spibar + offs), i); + mmio_readl(ich_spibar + offs), i); msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, - mmio_readl(spibar + offs + 4), i); + mmio_readl(ich_spibar + offs + 4), i); } - ichspi_bbar = mmio_readl(spibar + 0x50); + ichspi_bbar = mmio_readl(ich_spibar + 0x50); msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar); msg_pdbg("0x54: 0x%04x (PREOP)\n", - mmio_readw(spibar + 0x54)); + mmio_readw(ich_spibar + 0x54)); msg_pdbg("0x56: 0x%04x (OPTYPE)\n", - mmio_readw(spibar + 0x56)); + mmio_readw(ich_spibar + 0x56)); msg_pdbg("0x58: 0x%08x (OPMENU)\n", - mmio_readl(spibar + 0x58)); + mmio_readl(ich_spibar + 0x58)); msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", - mmio_readl(spibar + 0x5c)); + mmio_readl(ich_spibar + 0x5c)); for (i = 0; i < 4; i++) { int offs; offs = 0x60 + (i * 4); msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, - mmio_readl(spibar + offs), i); + mmio_readl(ich_spibar + offs), i); } msg_pdbg("\n"); - if (mmio_readw(spibar) & (1 << 15)) { + if (mmio_readw(ich_spibar) & (1 << 15)) { msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } ich_init_opcodes(); break; case SPI_CONTROLLER_ICH9: - tmp2 = mmio_readw(spibar + 4); + tmp2 = mmio_readw(ich_spibar + 4); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); @@ -590,7 +590,7 @@ msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); - tmp = mmio_readl(spibar + 0x50); + tmp = mmio_readl(ich_spibar + 0x50); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); @@ -602,30 +602,30 @@ do_ich9_spi_frap(tmp, i); msg_pdbg("0x74: 0x%08x (PR0)\n", - mmio_readl(spibar + 0x74)); + mmio_readl(ich_spibar + 0x74)); msg_pdbg("0x78: 0x%08x (PR1)\n", - mmio_readl(spibar + 0x78)); + mmio_readl(ich_spibar + 0x78)); msg_pdbg("0x7C: 0x%08x (PR2)\n", - mmio_readl(spibar + 0x7C)); + mmio_readl(ich_spibar + 0x7C)); msg_pdbg("0x80: 0x%08x (PR3)\n", - mmio_readl(spibar + 0x80)); + mmio_readl(ich_spibar + 0x80)); msg_pdbg("0x84: 0x%08x (PR4)\n", - mmio_readl(spibar + 0x84)); + mmio_readl(ich_spibar + 0x84)); msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", - mmio_readl(spibar + 0x90)); + mmio_readl(ich_spibar + 0x90)); msg_pdbg("0x94: 0x%04x (PREOP)\n", - mmio_readw(spibar + 0x94)); + mmio_readw(ich_spibar + 0x94)); msg_pdbg("0x96: 0x%04x (OPTYPE)\n", - mmio_readw(spibar + 0x96)); + mmio_readw(ich_spibar + 0x96)); msg_pdbg("0x98: 0x%08x (OPMENU)\n", - mmio_readl(spibar + 0x98)); + mmio_readl(ich_spibar + 0x98)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", - mmio_readl(spibar + 0x9C)); - ichspi_bbar = mmio_readl(spibar + 0xA0); + mmio_readl(ich_spibar + 0x9C)); + ichspi_bbar = mmio_readl(ich_spibar + 0xA0); msg_pdbg("0xA0: 0x%08x (BBAR)\n", ichspi_bbar); msg_pdbg("0xB0: 0x%08x (FDOC)\n", - mmio_readl(spibar + 0xB0)); + mmio_readl(ich_spibar + 0xB0)); if (tmp2 & (1 << 15)) { msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/cli_classic.c Sat Jul 3 13:02:10 2010 (r1068) @@ -31,7 +31,7 @@ #include "flash.h" #include "flashchips.h" -void cli_classic_usage(const char *name) +static void cli_classic_usage(const char *name) { const char *pname; int pnamelen; @@ -118,7 +118,7 @@ "flash chips.\n\n"); } -void cli_classic_abort_usage(void) +static void cli_classic_abort_usage(void) { printf("Please run \"flashrom --help\" for usage info.\n"); exit(1); @@ -166,6 +166,7 @@ char *filename = NULL; char *tempstr = NULL; + char *pparam = NULL; print_version(); print_banner(); @@ -287,10 +288,10 @@ if (strncmp(optarg, name, namelen) == 0) { switch (optarg[namelen]) { case ':': - programmer_param = strdup(optarg + namelen + 1); - if (!strlen(programmer_param)) { - free(programmer_param); - programmer_param = NULL; + pparam = strdup(optarg + namelen + 1); + if (!strlen(pparam)) { + free(pparam); + pparam = NULL; } break; case '\0': @@ -381,9 +382,7 @@ /* FIXME: Delay calibration should happen in programmer code. */ myusec_calibrate_delay(); - msg_pdbg("Initializing %s programmer\n", - programmer_table[programmer].name); - if (programmer_init()) { + if (programmer_init(pparam)) { fprintf(stderr, "Error: Programmer initialization failed.\n"); exit(1); } Modified: trunk/dediprog.c ============================================================================== --- trunk/dediprog.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/dediprog.c Sat Jul 3 13:02:10 2010 (r1068) @@ -24,19 +24,21 @@ #include "spi.h" #define DEFAULT_TIMEOUT 3000 -usb_dev_handle *dediprog_handle; +static usb_dev_handle *dediprog_handle; -int dediprog_do_stuff(void); - -void print_hex(void *buf, size_t len) +#if 0 +/* Might be useful for other pieces of code as well. */ +static void print_hex(void *buf, size_t len) { size_t i; for (i = 0; i < len; i++) msg_pdbg(" %02x", ((uint8_t *)buf)[i]); } +#endif -struct usb_device *get_device_by_vid_pid(uint16_t vid, uint16_t pid) +/* Might be useful for other USB devices as well. static for now. */ +static struct usb_device *get_device_by_vid_pid(uint16_t vid, uint16_t pid) { struct usb_bus *bus; struct usb_device *dev; @@ -52,7 +54,7 @@ //int usb_control_msg(usb_dev_handle *dev, int requesttype, int request, int value, int index, char *bytes, int size, int timeout); -int dediprog_set_spi_voltage(uint16_t voltage) +static int dediprog_set_spi_voltage(uint16_t voltage) { int ret; unsigned int mv; @@ -85,6 +87,7 @@ return 0; } +#if 0 /* After dediprog_set_spi_speed, the original app always calls * dediprog_set_spi_voltage(0) and then * dediprog_check_devicestring() four times in a row. @@ -92,7 +95,7 @@ * This looks suspiciously like the microprocessor in the SF100 has to be * restarted/reinitialized in case the speed changes. */ -int dediprog_set_spi_speed(uint16_t speed) +static int dediprog_set_spi_speed(uint16_t speed) { int ret; unsigned int khz; @@ -140,6 +143,7 @@ } return 0; } +#endif int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { @@ -183,7 +187,7 @@ return 0; } -int dediprog_check_devicestring(void) +static int dediprog_check_devicestring(void) { int ret; char buf[0x11]; @@ -223,7 +227,7 @@ * dediprog_check_devicestring (often) or Command A (often) or * Command F (once). */ -int dediprog_command_a(void) +static int dediprog_command_a(void) { int ret; char buf[0x1]; @@ -242,7 +246,7 @@ * dediprog_command_a(); dediprog_check_devicestring() sequence in each session. * I'm tempted to call this one start_SPI_engine or finish_init. */ -int dediprog_command_c(void) +static int dediprog_command_c(void) { int ret; @@ -254,11 +258,12 @@ return 0; } +#if 0 /* Very strange. Seems to be a programmer keepalive or somesuch. * Wait unsuccessfully for timeout ms to read one byte. * Is usually called after setting voltage to 0. */ -int dediprog_command_f(int timeout) +static int dediprog_command_f(int timeout) { int ret; char buf[0x1]; @@ -271,6 +276,7 @@ } return 0; } +#endif /* URB numbers refer to the first log ever captured. */ int dediprog_init(void) @@ -323,10 +329,11 @@ return 0; } +#if 0 /* Leftovers from reverse engineering. Keep for documentation purposes until * completely understood. */ -int dediprog_do_stuff(void) +static int dediprog_do_stuff(void) { char buf[0x4]; /* SPI command processing starts here. */ @@ -341,7 +348,6 @@ return 1; msg_pdbg("Receiving response: "); print_hex(buf, JEDEC_RDID_INSIZE); -#if 0 /* URB 14-27 are more SPI commands. */ /* URB 28. Command Set SPI Voltage. */ if (dediprog_set_spi_voltage(0x0)) @@ -369,12 +375,10 @@ /* Command I is probably Start Bulk Read. Data is u16 blockcount, u16 blocksize. */ /* Command J is probably Start Bulk Write. Data is u16 blockcount, u16 blocksize. */ /* Bulk transfer sizes for Command I/J are always 512 bytes, rest is filled with 0xff. */ -#endif - msg_pinfo("All probes will fail because this driver is not hooked up " - "to the SPI infrastructure yet."); return 0; } +#endif int dediprog_shutdown(void) { Modified: trunk/dmi.c ============================================================================== --- trunk/dmi.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/dmi.c Sat Jul 3 13:02:10 2010 (r1068) @@ -44,7 +44,7 @@ #else /* STANDALONE */ -const char *dmidecode_names[] = { +static const char *dmidecode_names[] = { "system-manufacturer", "system-product-name", "system-version", @@ -54,9 +54,9 @@ }; #define DMI_COMMAND_LEN_MAX 260 -const char *dmidecode_command = "dmidecode"; +static const char *dmidecode_command = "dmidecode"; -char *dmistrings[ARRAY_SIZE(dmidecode_names)]; +static char *dmistrings[ARRAY_SIZE(dmidecode_names)]; /* Strings longer than 4096 in DMI are just insane. */ #define DMI_MAX_ANSWER_LEN 4096 Modified: trunk/drkaiser.c ============================================================================== --- trunk/drkaiser.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/drkaiser.c Sat Jul 3 13:02:10 2010 (r1068) @@ -26,12 +26,12 @@ #define PCI_MAGIC_DRKAISER_ADDR 0x50 #define PCI_MAGIC_DRKAISER_VALUE 0xa971 -struct pcidev_status drkaiser_pcidev[] = { +const struct pcidev_status drkaiser_pcidev[] = { {0x1803, 0x5057, OK, "Dr. Kaiser", "PC-Waechter (Actel FPGA)"}, {}, }; -uint8_t *drkaiser_bar; +static uint8_t *drkaiser_bar; int drkaiser_init(void) { Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/flash.h Sat Jul 3 13:02:10 2010 (r1068) @@ -112,7 +112,7 @@ int register_shutdown(void (*function) (void *data), void *data); -int programmer_init(void); +int programmer_init(char *param); int programmer_shutdown(void); void *programmer_map_flash_region(const char *descr, unsigned long phys_addr, size_t len); @@ -300,7 +300,7 @@ int (*enable) (void); }; -extern struct board_pciid_enable board_pciid_enables[]; +extern const struct board_pciid_enable board_pciid_enables[]; struct board_info { const char *vendor; @@ -335,15 +335,15 @@ const char *vendor_name; const char *device_name; }; -uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, struct pcidev_status *devs); -uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, struct pcidev_status *devs, char *pcidev_bdf); +uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, const struct pcidev_status *devs); +uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, const struct pcidev_status *devs, char *pcidev_bdf); #endif /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); void print_supported(void); #if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1 -void print_supported_pcidevs(struct pcidev_status *devs); +void print_supported_pcidevs(const struct pcidev_status *devs); #endif void print_supported_wiki(void); @@ -463,7 +463,7 @@ int nic3com_shutdown(void); void nic3com_chip_writeb(uint8_t val, chipaddr addr); uint8_t nic3com_chip_readb(const chipaddr addr); -extern struct pcidev_status nics_3com[]; +extern const struct pcidev_status nics_3com[]; #endif /* gfxnvidia.c */ @@ -472,7 +472,7 @@ int gfxnvidia_shutdown(void); void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr); uint8_t gfxnvidia_chip_readb(const chipaddr addr); -extern struct pcidev_status gfx_nvidia[]; +extern const struct pcidev_status gfx_nvidia[]; #endif /* drkaiser.c */ @@ -481,7 +481,7 @@ int drkaiser_shutdown(void); void drkaiser_chip_writeb(uint8_t val, chipaddr addr); uint8_t drkaiser_chip_readb(const chipaddr addr); -extern struct pcidev_status drkaiser_pcidev[]; +extern const struct pcidev_status drkaiser_pcidev[]; #endif /* nicrealtek.c */ @@ -491,8 +491,8 @@ int nicrealtek_shutdown(void); void nicrealtek_chip_writeb(uint8_t val, chipaddr addr); uint8_t nicrealtek_chip_readb(const chipaddr addr); -extern struct pcidev_status nics_realtek[]; -extern struct pcidev_status nics_realteksmc1211[]; +extern const struct pcidev_status nics_realtek[]; +extern const struct pcidev_status nics_realteksmc1211[]; #endif /* nicnatsemi.c */ @@ -501,7 +501,7 @@ int nicnatsemi_shutdown(void); void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr); uint8_t nicnatsemi_chip_readb(const chipaddr addr); -extern struct pcidev_status nics_natsemi[]; +extern const struct pcidev_status nics_natsemi[]; #endif /* satasii.c */ @@ -510,7 +510,7 @@ int satasii_shutdown(void); void satasii_chip_writeb(uint8_t val, chipaddr addr); uint8_t satasii_chip_readb(const chipaddr addr); -extern struct pcidev_status satas_sii[]; +extern const struct pcidev_status satas_sii[]; #endif /* atahpt.c */ @@ -519,7 +519,7 @@ int atahpt_shutdown(void); void atahpt_chip_writeb(uint8_t val, chipaddr addr); uint8_t atahpt_chip_readb(const chipaddr addr); -extern struct pcidev_status ata_hpt[]; +extern const struct pcidev_status ata_hpt[]; #endif /* ft2232_spi.c */ @@ -572,7 +572,7 @@ extern char *programmer_param; extern unsigned long flashbase; extern int verbose; -extern const char *flashrom_version; +extern const char * const flashrom_version; extern char *chip_to_probe; void map_flash_registers(struct flashchip *flash); int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); @@ -671,7 +671,6 @@ extern enum spi_controller spi_controller; extern const struct spi_programmer spi_programmer[]; -extern void *spibar; int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int spi_send_multicommand(struct spi_command *cmds); @@ -683,6 +682,7 @@ /* ichspi.c */ extern int ichspi_lock; extern uint32_t ichspi_bbar; +extern void *ich_spibar; int ich_init_opcodes(void); int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/flashrom.c Sat Jul 3 13:02:10 2010 (r1068) @@ -34,7 +34,7 @@ #include "flash.h" #include "flashchips.h" -const char *flashrom_version = FLASHROM_VERSION; +const char * const flashrom_version = FLASHROM_VERSION; char *chip_to_probe = NULL; int verbose = 0; @@ -91,23 +91,17 @@ char *programmer_param = NULL; -/** - * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host - * controller is found, the init routine sets the buses_supported bitfield to - * contain the supported buses for that controller. - */ -enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; +/* Supported buses for the current programmer. */ +enum chipbustype buses_supported; /** * Programmers supporting multiple buses can have differing size limits on * each bus. Store the limits for each bus in a common struct. */ -struct decode_sizes max_rom_decode = { - .parallel = 0xffffffff, - .lpc = 0xffffffff, - .fwh = 0xffffffff, - .spi = 0xffffffff -}; +struct decode_sizes max_rom_decode; + +/* If nonzero, used as the start address of bottom-aligned flash. */ +unsigned long flashbase; const struct programmer_entry programmer_table[] = { #if CONFIG_INTERNAL == 1 @@ -402,7 +396,11 @@ struct shutdown_func_data { void (*func) (void *data); void *data; -} shutdown_fn[SHUTDOWN_MAXFN]; +} static shutdown_fn[SHUTDOWN_MAXFN]; +/* Initialize to 0 to make sure nobody registers a shutdown function before + * programmer init. + */ +static int may_register_shutdown = 0; /* Register a function to be executed on programmer shutdown. * The advantage over atexit() is that you can supply a void pointer which will @@ -419,6 +417,11 @@ SHUTDOWN_MAXFN); return 1; } + if (!may_register_shutdown) { + msg_perr("Tried to register a shutdown function before " + "programmer init.\n"); + return 1; + } shutdown_fn[shutdown_fn_count].func = function; shutdown_fn[shutdown_fn_count].data = data; shutdown_fn_count++; @@ -426,17 +429,39 @@ return 0; } -int programmer_init(void) +int programmer_init(char *param) { + /* Initialize all programmer specific data. */ + /* Default to unlimited decode sizes. */ + max_rom_decode = (const struct decode_sizes) { + .parallel = 0xffffffff, + .lpc = 0xffffffff, + .fwh = 0xffffffff, + .spi = 0xffffffff + }; + /* Default to Parallel/LPC/FWH flash devices. If a known host controller + * is found, the init routine sets the buses_supported bitfield. + */ + buses_supported = CHIP_BUSTYPE_NONSPI; + /* Default to top aligned flash at 4 GB. */ + flashbase = 0; + /* Registering shutdown functions is now allowed. */ + may_register_shutdown = 1; + + programmer_param = param; + msg_pdbg("Initializing %s programmer\n", + programmer_table[programmer].name); return programmer_table[programmer].init(); } int programmer_shutdown(void) { - int i; - - for (i = shutdown_fn_count - 1; i >= 0; i--) + /* Registering shutdown functions is no longer allowed. */ + may_register_shutdown = 0; + while (shutdown_fn_count > 0) { + int i = --shutdown_fn_count; shutdown_fn[i].func(shutdown_fn[i].data); + } return programmer_table[programmer].shutdown(); } @@ -512,8 +537,6 @@ return 0; } -unsigned long flashbase = 0; - int min(int a, int b) { return (a < b) ? a : b; @@ -1059,7 +1082,7 @@ /* This function shares a lot of its structure with erase_flash(). * Even if an error is found, the function will keep going and check the rest. */ -int selfcheck_eraseblocks(struct flashchip *flash) +static int selfcheck_eraseblocks(struct flashchip *flash) { int i, j, k; int ret = 0; Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/ft2232_spi.c Sat Jul 3 13:02:10 2010 (r1068) @@ -47,7 +47,7 @@ static struct ftdi_context ftdic_context; -int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) +static int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) { int r; r = ftdi_write_data(ftdic, (unsigned char *) buf, size); @@ -59,7 +59,7 @@ return 0; } -int get_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) +static int get_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) { int r; r = ftdi_read_data(ftdic, (unsigned char *) buf, size); Modified: trunk/gfxnvidia.c ============================================================================== --- trunk/gfxnvidia.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/gfxnvidia.c Sat Jul 3 13:02:10 2010 (r1068) @@ -27,7 +27,7 @@ uint8_t *nvidia_bar; -struct pcidev_status gfx_nvidia[] = { +const struct pcidev_status gfx_nvidia[] = { {0x10de, 0x0010, NT, "NVIDIA", "Mutara V08 [NV2]" }, {0x10de, 0x0018, NT, "NVIDIA", "RIVA 128" }, {0x10de, 0x0020, NT, "NVIDIA", "RIVA TNT" }, Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/ichspi.c Sat Jul 3 13:02:10 2010 (r1068) @@ -105,6 +105,8 @@ uint32_t ichspi_bbar = 0; +void *ich_spibar = NULL; + typedef struct _OPCODE { uint8_t opcode; //This commands spi opcode uint8_t spi_type; //This commands spi type @@ -134,17 +136,17 @@ /* HW access functions */ static uint32_t REGREAD32(int X) { - return mmio_readl(spibar + X); + return mmio_readl(ich_spibar + X); } static uint16_t REGREAD16(int X) { - return mmio_readw(spibar + X); + return mmio_readw(ich_spibar + X); } -#define REGWRITE32(X,Y) mmio_writel(Y, spibar+X) -#define REGWRITE16(X,Y) mmio_writew(Y, spibar+X) -#define REGWRITE8(X,Y) mmio_writeb(Y, spibar+X) +#define REGWRITE32(X,Y) mmio_writel(Y, ich_spibar+X) +#define REGWRITE16(X,Y) mmio_writew(Y, ich_spibar+X) +#define REGWRITE8(X,Y) mmio_writeb(Y, ich_spibar+X) /* Common SPI functions */ static int find_opcode(OPCODES *op, uint8_t opcode); @@ -161,7 +163,7 @@ }; /* List of opcodes which need preopcodes and matching preopcodes. Unused. */ -struct preop_opcode_pair pops[] = { +const struct preop_opcode_pair pops[] = { {JEDEC_WREN, JEDEC_BYTE_PROGRAM}, {JEDEC_WREN, JEDEC_SE}, /* sector erase */ {JEDEC_WREN, JEDEC_BE_52}, /* block erase */ @@ -177,7 +179,7 @@ /* Reasonable default configuration. Needs ad-hoc modifications if we * encounter unlisted opcodes. Fun. */ -OPCODES O_ST_M25P = { +static OPCODES O_ST_M25P = { { JEDEC_WREN, JEDEC_EWSR, @@ -194,7 +196,7 @@ } }; -OPCODES O_EXISTING = {}; +static OPCODES O_EXISTING = {}; static int find_opcode(OPCODES *op, uint8_t opcode) { @@ -337,15 +339,15 @@ { switch (spi_controller) { case SPI_CONTROLLER_ICH7: - mmio_writel(minaddr, spibar + 0x50); - ichspi_bbar = mmio_readl(spibar + 0x50); + mmio_writel(minaddr, ich_spibar + 0x50); + ichspi_bbar = mmio_readl(ich_spibar + 0x50); /* We don't have any option except complaining. */ if (ichspi_bbar != minaddr) msg_perr("Setting BBAR failed!\n"); break; case SPI_CONTROLLER_ICH9: - mmio_writel(minaddr, spibar + 0xA0); - ichspi_bbar = mmio_readl(spibar + 0xA0); + mmio_writel(minaddr, ich_spibar + 0xA0); + ichspi_bbar = mmio_readl(ich_spibar + 0xA0); /* We don't have any option except complaining. */ if (ichspi_bbar != minaddr) msg_perr("Setting BBAR failed!\n"); Modified: trunk/it87spi.c ============================================================================== --- trunk/it87spi.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/it87spi.c Sat Jul 3 13:02:10 2010 (r1068) @@ -36,7 +36,7 @@ uint16_t it8716f_flashport = 0; /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ -int fast_spi = 1; +static int fast_spi = 1; /* Helper functions for most recent ITE IT87xx Super I/O chips */ #define CHIP_ID_BYTE1_REG 0x20 Modified: trunk/jedec.c ============================================================================== --- trunk/jedec.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/jedec.c Sat Jul 3 13:02:10 2010 (r1068) @@ -38,7 +38,7 @@ return (val ^ (val >> 1)) & 0x1; } -void toggle_ready_jedec_common(chipaddr dst, int delay) +static void toggle_ready_jedec_common(chipaddr dst, int delay) { unsigned int i = 0; uint8_t tmp1, tmp2; @@ -70,7 +70,7 @@ * Given that erase is slow on all chips, it is recommended to use * toggle_ready_jedec_slow in erase functions. */ -void toggle_ready_jedec_slow(chipaddr dst) +static void toggle_ready_jedec_slow(chipaddr dst) { toggle_ready_jedec_common(dst, 8 * 1000); } @@ -92,7 +92,7 @@ msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i); } -void start_program_jedec_common(struct flashchip *flash, unsigned int mask) +static void start_program_jedec_common(struct flashchip *flash, unsigned int mask) { chipaddr bios = flash->virtual_memory; chip_writeb(0xAA, bios + (0x5555 & mask)); @@ -100,7 +100,7 @@ chip_writeb(0xA0, bios + (0x5555 & mask)); } -int probe_jedec_common(struct flashchip *flash, unsigned int mask) +static int probe_jedec_common(struct flashchip *flash, unsigned int mask) { chipaddr bios = flash->virtual_memory; uint8_t id1, id2; @@ -199,7 +199,7 @@ return 1; } -int erase_sector_jedec_common(struct flashchip *flash, unsigned int page, +static int erase_sector_jedec_common(struct flashchip *flash, unsigned int page, unsigned int pagesize, unsigned int mask) { chipaddr bios = flash->virtual_memory; @@ -229,7 +229,7 @@ return 0; } -int erase_block_jedec_common(struct flashchip *flash, unsigned int block, +static int erase_block_jedec_common(struct flashchip *flash, unsigned int block, unsigned int blocksize, unsigned int mask) { chipaddr bios = flash->virtual_memory; @@ -259,7 +259,7 @@ return 0; } -int erase_chip_jedec_common(struct flashchip *flash, unsigned int mask) +static int erase_chip_jedec_common(struct flashchip *flash, unsigned int mask) { int total_size = flash->total_size * 1024; chipaddr bios = flash->virtual_memory; @@ -288,7 +288,7 @@ return 0; } -int write_byte_program_jedec_common(struct flashchip *flash, uint8_t *src, +static int write_byte_program_jedec_common(struct flashchip *flash, uint8_t *src, chipaddr dst, unsigned int mask) { int tried = 0, failed = 0; @@ -335,7 +335,7 @@ return failed; } -int write_page_write_jedec_common(struct flashchip *flash, uint8_t *src, +static int write_page_write_jedec_common(struct flashchip *flash, uint8_t *src, int start, int page_size, unsigned int mask) { int i, tried = 0, failed; @@ -374,7 +374,7 @@ return failed; } -int getaddrmask(struct flashchip *flash) +static int getaddrmask(struct flashchip *flash) { switch (flash->feature_bits & FEATURE_ADDR_MASK) { case FEATURE_ADDR_FULL: Modified: trunk/layout.c ============================================================================== --- trunk/layout.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/layout.c Sat Jul 3 13:02:10 2010 (r1068) @@ -28,7 +28,7 @@ char *mainboard_vendor = NULL; char *mainboard_part = NULL; #endif -int romimages = 0; +static int romimages = 0; #define MAX_ROMLAYOUT 16 @@ -39,7 +39,7 @@ char name[256]; } romlayout_t; -romlayout_t rom_entries[MAX_ROMLAYOUT]; +static romlayout_t rom_entries[MAX_ROMLAYOUT]; #if CONFIG_INTERNAL == 1 /* FIXME: Move the whole block to cbtable.c? */ static char *def_name = "DEFAULT"; Modified: trunk/nic3com.c ============================================================================== --- trunk/nic3com.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/nic3com.c Sat Jul 3 13:02:10 2010 (r1068) @@ -31,10 +31,10 @@ #define PCI_VENDOR_ID_3COM 0x10b7 -uint32_t internal_conf; -uint16_t id; +static uint32_t internal_conf; +static uint16_t id; -struct pcidev_status nics_3com[] = { +const struct pcidev_status nics_3com[] = { /* 3C90xB */ {0x10b7, 0x9055, OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"}, {0x10b7, 0x9001, NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" }, Modified: trunk/nicnatsemi.c ============================================================================== --- trunk/nicnatsemi.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/nicnatsemi.c Sat Jul 3 13:02:10 2010 (r1068) @@ -28,7 +28,7 @@ #define BOOT_ROM_ADDR 0x50 #define BOOT_ROM_DATA 0x54 -struct pcidev_status nics_natsemi[] = { +const struct pcidev_status nics_natsemi[] = { {0x100b, 0x0020, NT, "National Semiconductor", "DP83815/DP83816"}, {0x100b, 0x0022, NT, "National Semiconductor", "DP83820"}, {}, Modified: trunk/nicrealtek.c ============================================================================== --- trunk/nicrealtek.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/nicrealtek.c Sat Jul 3 13:02:10 2010 (r1068) @@ -29,12 +29,12 @@ #define BIOS_ROM_ADDR 0xD4 #define BIOS_ROM_DATA 0xD7 -struct pcidev_status nics_realtek[] = { +const struct pcidev_status nics_realtek[] = { {0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"}, {}, }; -struct pcidev_status nics_realteksmc1211[] = { +const struct pcidev_status nics_realteksmc1211[] = { {0x1113, 0x1211, OK, "SMC2", "1211TX"}, /* RTL8139 clone */ {}, }; Modified: trunk/pcidev.c ============================================================================== --- trunk/pcidev.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/pcidev.c Sat Jul 3 13:02:10 2010 (r1068) @@ -25,11 +25,10 @@ uint32_t io_base_addr; struct pci_access *pacc; -struct pci_filter filter; struct pci_dev *pcidev_dev = NULL; uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, - struct pcidev_status *devs) + const struct pcidev_status *devs) { int i; /* FIXME: 64 bit memory BARs need a 64 bit addr. */ @@ -79,9 +78,10 @@ } uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, - struct pcidev_status *devs, char *pcidev_bdf) + const struct pcidev_status *devs, char *pcidev_bdf) { struct pci_dev *dev; + struct pci_filter filter; char *msg = NULL; int found = 0; uint32_t addr = 0, curaddr = 0; @@ -125,7 +125,7 @@ return curaddr; } -void print_supported_pcidevs(struct pcidev_status *devs) +void print_supported_pcidevs(const struct pcidev_status *devs) { int i; Modified: trunk/physmap.c ============================================================================== --- trunk/physmap.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/physmap.c Sat Jul 3 13:02:10 2010 (r1068) @@ -62,7 +62,7 @@ return realmem_map + phys_addr; } -void *sys_physmap(unsigned long phys_addr, size_t len) +static void *sys_physmap(unsigned long phys_addr, size_t len) { int ret; __dpmi_meminfo mi; @@ -110,7 +110,7 @@ #define MEM_DEV "DirectIO" -void *sys_physmap(unsigned long phys_addr, size_t len) +static void *sys_physmap(unsigned long phys_addr, size_t len) { return map_physical(phys_addr, len); } @@ -137,7 +137,7 @@ static int fd_mem_cached = -1; /* For MMIO access. Must be uncached, doesn't make sense to restrict to ro. */ -void *sys_physmap_rw_uncached(unsigned long phys_addr, size_t len) +static void *sys_physmap_rw_uncached(unsigned long phys_addr, size_t len) { void *virt_addr; @@ -157,7 +157,7 @@ /* For reading DMI/coreboot/whatever tables. We should never write, and we * do not care about caching. */ -void *sys_physmap_ro_cached(unsigned long phys_addr, size_t len) +static void *sys_physmap_ro_cached(unsigned long phys_addr, size_t len) { void *virt_addr; @@ -190,7 +190,7 @@ #define PHYSMAP_RW 0 #define PHYSMAP_RO 1 -void *physmap_common(const char *descr, unsigned long phys_addr, size_t len, int mayfail, int readonly) +static void *physmap_common(const char *descr, unsigned long phys_addr, size_t len, int mayfail, int readonly) { void *virt_addr; Modified: trunk/pm49fl00x.c ============================================================================== --- trunk/pm49fl00x.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/pm49fl00x.c Sat Jul 3 13:02:10 2010 (r1068) @@ -23,7 +23,7 @@ #include "flash.h" #include "chipdrivers.h" -void write_lockbits_49fl00x(chipaddr bios, int size, +static void write_lockbits_49fl00x(chipaddr bios, int size, unsigned char bits, int block_size) { int i, left = size; Modified: trunk/print.c ============================================================================== --- trunk/print.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/print.c Sat Jul 3 13:02:10 2010 (r1068) @@ -73,7 +73,7 @@ return i; } -void print_supported_chips(void) +static void print_supported_chips(void) { int okcol = 0, pos = 0, i, chipcount = 0; struct flashchip *f; @@ -146,7 +146,7 @@ } #if CONFIG_INTERNAL == 1 -void print_supported_chipsets(void) +static void print_supported_chipsets(void) { int i, j, chipsetcount = 0; const struct penable *c = chipset_enables; @@ -169,11 +169,11 @@ } } -void print_supported_boards_helper(const struct board_info *boards, +static void print_supported_boards_helper(const struct board_info *boards, const char *devicetype) { int i, j, boardcount_good = 0, boardcount_bad = 0; - struct board_pciid_enable *b = board_pciid_enables; + const struct board_pciid_enable *b = board_pciid_enables; for (i = 0; boards[i].vendor != NULL; i++) { if (boards[i].working) Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/print_wiki.c Sat Jul 3 13:02:10 2010 (r1068) @@ -26,7 +26,7 @@ #include "flash.h" #include "flashchips.h" -const char *wiki_header = "= Supported devices =\n\n\ +static const char * const wiki_header = "= Supported devices =\n\n\ <div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ background-color:#eeeeee; align:right; border:1px solid #aabbcc;\"><small>\n\ Please do '''not''' edit these tables in the wiki directly, they are \ @@ -34,16 +34,16 @@ '''Last update:''' %s(generated by flashrom %s)\n</small></div>\n"; #if CONFIG_INTERNAL == 1 -const char *chipset_th = "{| border=\"0\" style=\"font-size: smaller\"\n\ +static const char * const chipset_th = "{| border=\"0\" style=\"font-size: smaller\"\n\ |- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ ! align=\"left\" | Southbridge\n! align=\"left\" | PCI IDs\n\ ! align=\"left\" | Status\n\n"; -const char *board_th = "{| border=\"0\" style=\"font-size: smaller\" \ +static const char * const board_th = "{| border=\"0\" style=\"font-size: smaller\" \ valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ ! align=\"left\" | Mainboard\n! align=\"left\" | Required option\n! align=\"left\" | Status\n\n"; -const char *board_intro = "\ +static const char * const board_intro = "\ \n== Supported mainboards ==\n\n\ In general, it is very likely that flashrom works out of the box even if your \ mainboard is not listed below.\n\nThis is a list of mainboards where we have \ @@ -56,14 +56,14 @@ mainboards on the [[Mailinglist|mailing list]].\n"; #endif -const char *chip_th = "{| border=\"0\" style=\"font-size: smaller\" \ +static const char * const chip_th = "{| border=\"0\" style=\"font-size: smaller\" \ valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ ! align=\"left\" | Device\n! align=\"left\" | Size / KB\n\ ! align=\"left\" | Type\n! align=\"left\" colspan=\"4\" | Status\n\n\ |- bgcolor=\"#6699ff\"\n| colspan=\"4\" |  \n\ | Probe\n| Read\n| Erase\n| Write\n\n"; -const char *programmer_section = "\ +static const char * const programmer_section = "\ \n== Supported programmers ==\n\nThis is a list \ of supported PCI devices flashrom can use as programmer:\n\n{| border=\"0\" \ valign=\"top\"\n| valign=\"top\"|\n\n{| border=\"0\" style=\"font-size: \ @@ -72,7 +72,7 @@ ! align=\"left\" | Status\n\n"; #if CONFIG_INTERNAL == 1 -const char *laptop_intro = "\n== Supported laptops/notebooks ==\n\n\ +static const char * const laptop_intro = "\n== Supported laptops/notebooks ==\n\n\ In general, flashing laptops is more difficult because laptops\n\n\ * often use the flash chip for stuff besides the BIOS,\n\ * often have special protection stuff which has to be handled by flashrom,\n\ @@ -124,7 +124,7 @@ int num_notes = 0; char *notes = calloc(1, 1); char tmp[900 + 1]; - struct board_pciid_enable *b = board_pciid_enables; + const struct board_pciid_enable *b = board_pciid_enables; for (i = 0; boards[i].vendor != NULL; i++) { if (boards[i].working) @@ -245,7 +245,7 @@ printf("\n|}\n\n|}\n"); } -static void print_supported_pcidevs_wiki(struct pcidev_status *devs) +static void print_supported_pcidevs_wiki(const struct pcidev_status *devs) { int i = 0; static int c = 0; Modified: trunk/satasii.c ============================================================================== --- trunk/satasii.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/satasii.c Sat Jul 3 13:02:10 2010 (r1068) @@ -26,9 +26,9 @@ #define PCI_VENDOR_ID_SII 0x1095 uint8_t *sii_bar; -uint16_t id; +static uint16_t id; -struct pcidev_status satas_sii[] = { +const struct pcidev_status satas_sii[] = { {0x1095, 0x0680, OK, "Silicon Image", "PCI0680 Ultra ATA-133 Host Ctrl"}, {0x1095, 0x3112, OK, "Silicon Image", "SiI 3112 [SATALink/SATARaid] SATA Ctrl"}, {0x1095, 0x3114, OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] SATA Ctrl"}, Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/spi.c Sat Jul 3 13:02:10 2010 (r1068) @@ -28,7 +28,6 @@ #include "spi.h" enum spi_controller spi_controller = SPI_CONTROLLER_NONE; -void *spibar = NULL; void spi_prettyprint_status_register(struct flashchip *flash); Modified: trunk/sst28sf040.c ============================================================================== --- trunk/sst28sf040.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/sst28sf040.c Sat Jul 3 13:02:10 2010 (r1068) @@ -69,7 +69,7 @@ return 0; } -int write_sector_28sf040(chipaddr bios, uint8_t *src, chipaddr dst, +static int write_sector_28sf040(chipaddr bios, uint8_t *src, chipaddr dst, unsigned int page_size) { int i; @@ -92,7 +92,7 @@ return 0; } -int erase_28sf040(struct flashchip *flash) +static int erase_28sf040(struct flashchip *flash) { chipaddr bios = flash->virtual_memory; Modified: trunk/sst49lfxxxc.c ============================================================================== --- trunk/sst49lfxxxc.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/sst49lfxxxc.c Sat Jul 3 13:02:10 2010 (r1068) @@ -23,7 +23,7 @@ #include "flash.h" #include "chipdrivers.h" -int unlock_block_49lfxxxc(struct flashchip *flash, unsigned long address, unsigned char bits) +static int write_lockbits_block_49lfxxxc(struct flashchip *flash, unsigned long address, unsigned char bits) { unsigned long lock = flash->virtual_registers + address + 2; msg_cdbg("lockbits at address=0x%08lx is 0x%01x\n", lock, chip_readb(lock)); @@ -40,31 +40,16 @@ msg_cdbg("\nbios=0x%08lx\n", registers); for (i = 0; left > 65536; i++, left -= 65536) { - msg_cdbg("lockbits at address=0x%08lx is 0x%01x\n", - registers + (i * 65536) + 2, - chip_readb(registers + (i * 65536) + 2)); - chip_writeb(bits, registers + (i * 65536) + 2); + write_lockbits_block_49lfxxxc(flash, i * 65536, bits); } address = i * 65536; - msg_cdbg("lockbits at address=0x%08lx is 0x%01x\n", - registers + address + 2, - chip_readb(registers + address + 2)); - chip_writeb(bits, registers + address + 2); + write_lockbits_block_49lfxxxc(flash, address, bits); address += 32768; - msg_cdbg("lockbits at address=0x%08lx is 0x%01x\n", - registers + address + 2, - chip_readb(registers + address + 2)); - chip_writeb(bits, registers + address + 2); + write_lockbits_block_49lfxxxc(flash, address, bits); address += 8192; - msg_cdbg("lockbits at address=0x%08lx is 0x%01x\n", - registers + address + 2, - chip_readb(registers + address + 2)); - chip_writeb(bits, registers + address + 2); + write_lockbits_block_49lfxxxc(flash, address, bits); address += 8192; - msg_cdbg("lockbits at address=0x%08lx is 0x%01x\n", - registers + address + 2, - chip_readb(registers + address + 2)); - chip_writeb(bits, registers + address + 2); + write_lockbits_block_49lfxxxc(flash, address, bits); return 0; } Modified: trunk/sst_fwhub.c ============================================================================== --- trunk/sst_fwhub.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/sst_fwhub.c Sat Jul 3 13:02:10 2010 (r1068) @@ -25,7 +25,7 @@ #include "flash.h" #include "chipdrivers.h" -int check_sst_fwhub_block_lock(struct flashchip *flash, int offset) +static int check_sst_fwhub_block_lock(struct flashchip *flash, int offset) { chipaddr registers = flash->virtual_registers; uint8_t blockstatus; @@ -51,7 +51,7 @@ return blockstatus & 0x1; } -int clear_sst_fwhub_block_lock(struct flashchip *flash, int offset) +static int clear_sst_fwhub_block_lock(struct flashchip *flash, int offset) { chipaddr registers = flash->virtual_registers; uint8_t blockstatus; Modified: trunk/stm50flw0x0x.c ============================================================================== --- trunk/stm50flw0x0x.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/stm50flw0x0x.c Sat Jul 3 13:02:10 2010 (r1068) @@ -36,7 +36,7 @@ * The ST M50FLW080B and STM50FLW080B chips have to be unlocked, * before you can erase them or write to them. */ -int unlock_block_stm50flw0x0x(struct flashchip *flash, int offset) +static int unlock_block_stm50flw0x0x(struct flashchip *flash, int offset) { chipaddr wrprotect = flash->virtual_registers + 2; const uint8_t unlock_sector = 0x00; Modified: trunk/udelay.c ============================================================================== --- trunk/udelay.c Fri Jul 2 19:12:50 2010 (r1067) +++ trunk/udelay.c Sat Jul 3 13:02:10 2010 (r1068) @@ -26,7 +26,7 @@ #include "flash.h" /* loops per microsecond */ -unsigned long micro = 1; +static unsigned long micro = 1; __attribute__ ((noinline)) void myusec_delay(int usecs) { @@ -37,7 +37,7 @@ } } -unsigned long measure_os_delay_resolution(void) +static unsigned long measure_os_delay_resolution(void) { unsigned long timeusec; struct timeval start, end; @@ -61,7 +61,7 @@ return timeusec; } -unsigned long measure_delay(int usecs) +static unsigned long measure_delay(int usecs) { unsigned long timeusec; struct timeval start, end;

1 0

ASUS M3N78 PRO
by Brad Rogers 03 Jul '10

03 Jul '10

flashrom v0.9.2-r1028 on Linux 2.6.32-5-amd64 (x86_64), built with libpci 3.1.7, GCC 4.4.4, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1032M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 999 us, 10000 myus = 10024 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "M3N78 PRO" DMI string baseboard-version: "1.XX" DMI string chassis-type: "Desktop" Found ITE Super I/O, id 8716 Found chipset "NVIDIA MCP78S", enabling flash write... chipset PCI ID is 10de:075c, This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Guessed flash bus type is SPI Found SMBus device 10de:0752 at 00:01:1 SPI BAR is at 0xfdf80000, after clearing low bits BAR is at 0xfdf80000 SPI control is 0xc01a, enable=0, idle=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. SPI on this chipset is not supported yet. OK. This chipset supports the following protocols: None. No IT87* serial flash segment enabled. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for ASD AE49F2008, 256 KB: skipped. Probing for Atmel AT25DF021, 256 KB: skipped. Probing for Atmel AT25DF041A, 512 KB: skipped. Probing for Atmel AT25DF081, 1024 KB: skipped. Probing for Atmel AT25DF161, 2048 KB: skipped. Probing for Atmel AT25DF321, 4096 KB: skipped. Probing for Atmel AT25DF321A, 4096 KB: skipped. Probing for Atmel AT25DF641, 8192 KB: skipped. Probing for Atmel AT25F512B, 64 KB: skipped. Probing for Atmel AT25FS010, 128 KB: skipped. Probing for Atmel AT25FS040, 512 KB: skipped. Probing for Atmel AT26DF041, 512 KB: skipped. Probing for Atmel AT26DF081A, 1024 KB: skipped. Probing for Atmel AT26DF161, 2048 KB: skipped. Probing for Atmel AT26DF161A, 2048 KB: skipped. Probing for Atmel AT26F004, 512 KB: skipped. Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: skipped. Probing for Atmel AT45DB011D, 128 KB: skipped. Probing for Atmel AT45DB021D, 256 KB: skipped. Probing for Atmel AT45DB041D, 512 KB: skipped. Probing for Atmel AT45DB081D, 1024 KB: skipped. Probing for Atmel AT45DB161D, 2048 KB: skipped. Probing for Atmel AT45DB321C, 4224 KB: skipped. Probing for Atmel AT45DB321D, 4096 KB: skipped. Probing for Atmel AT45DB642D, 8192 KB: skipped. Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: skipped. Probing for AMIC A25L40PU, 512 KB: skipped. Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for Eon EN25B05, 64 KB: skipped. Probing for Eon EN25B05T, 64 KB: skipped. Probing for Eon EN25B10, 128 KB: skipped. Probing for Eon EN25B10T, 128 KB: skipped. Probing for Eon EN25B20, 256 KB: skipped. Probing for Eon EN25B20T, 256 KB: skipped. Probing for Eon EN25B40, 512 KB: skipped. Probing for Eon EN25B40T, 512 KB: skipped. Probing for Eon EN25B80, 1024 KB: skipped. Probing for Eon EN25B80T, 1024 KB: skipped. Probing for Eon EN25B16, 2048 KB: skipped. Probing for Eon EN25B16T, 2048 KB: skipped. Probing for Eon EN25B32, 4096 KB: skipped. Probing for Eon EN25B32T, 4096 KB: skipped. Probing for Eon EN25B64, 8192 KB: skipped. Probing for Eon EN25B64T, 8192 KB: skipped. Probing for Eon EN25D16, 2048 KB: skipped. Probing for Eon EN25F05, 64 KB: skipped. Probing for Eon EN25F10, 128 KB: skipped. Probing for Eon EN25F20, 256 KB: skipped. Probing for Eon EN25F40, 512 KB: skipped. Probing for Eon EN25F80, 1024 KB: skipped. Probing for Eon EN25F16, 2048 KB: skipped. Probing for Eon EN25F32, 4096 KB: skipped. Probing for Eon EN29F010, 128 KB: skipped. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Intel 28F001BX-B, 128 KB: skipped. Probing for Intel 28F001BX-T, 128 KB: skipped. Probing for Intel 28F004S5, 512 KB: skipped. Probing for Intel 28F004BV/BE-B, 512 KB: skipped. Probing for Intel 28F004BV/BE-T, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-B, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: skipped. Probing for Macronix MX25L1005, 128 KB: skipped. Probing for Macronix MX25L2005, 256 KB: skipped. Probing for Macronix MX25L4005, 512 KB: skipped. Probing for Macronix MX25L8005, 1024 KB: skipped. Probing for Macronix MX25L1605, 2048 KB: skipped. Probing for Macronix MX25L1635D, 2048 KB: skipped. Probing for Macronix MX25L3205, 4096 KB: skipped. Probing for Macronix MX25L3235D, 4096 KB: skipped. Probing for Macronix MX25L6405, 8192 KB: skipped. Probing for Macronix MX25L12805, 16384 KB: skipped. Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for Numonyx M25PE10, 128 KB: skipped. Probing for Numonyx M25PE20, 256 KB: skipped. Probing for Numonyx M25PE40, 512 KB: skipped. Probing for Numonyx M25PE80, 1024 KB: skipped. Probing for Numonyx M25PE16, 2048 KB: skipped. Probing for PMC Pm25LV010, 128 KB: skipped. Probing for PMC Pm25LV016B, 2048 KB: skipped. Probing for PMC Pm25LV020, 256 KB: skipped. Probing for PMC Pm25LV040, 512 KB: skipped. Probing for PMC Pm25LV080B, 1024 KB: skipped. Probing for PMC Pm25LV512, 64 KB: skipped. Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: skipped. Probing for PMC Pm49FL004, 512 KB: skipped. Probing for Sanyo LF25FW203A, 2048 KB: skipped. Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: skipped. Probing for Spansion S25FL016A, 2048 KB: skipped. Probing for SST SST25VF016B, 2048 KB: skipped. Probing for SST SST25VF032B, 4096 KB: skipped. Probing for SST SST25VF040.REMS, 512 KB: skipped. Probing for SST SST25VF040B, 512 KB: skipped. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Probing for SST SST25VF080B, 1024 KB: skipped. Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: skipped. Probing for ST M25P05.RES, 64 KB: skipped. Probing for ST M25P10-A, 128 KB: skipped. Probing for ST M25P10.RES, 128 KB: skipped. Probing for ST M25P20, 256 KB: skipped. Probing for ST M25P40, 512 KB: skipped. Probing for ST M25P40-old, 512 KB: skipped. Probing for ST M25P80, 1024 KB: skipped. Probing for ST M25P16, 2048 KB: skipped. Probing for ST M25P32, 4096 KB: skipped. Probing for ST M25P64, 8192 KB: skipped. Probing for ST M25P128, 16384 KB: skipped. Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: skipped. Probing for ST M50FLW040B, 512 KB: skipped. Probing for ST M50FLW080A, 1024 KB: skipped. Probing for ST M50FLW080B, 1024 KB: skipped. Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS S29C31004T, 512 KB: skipped. Probing for SyncMOS S29C51001T, 128 KB: skipped. Probing for SyncMOS S29C51002T, 256 KB: skipped. Probing for SyncMOS S29C51004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: skipped. Probing for Winbond W25Q16, 2048 KB: skipped. Probing for Winbond W25Q32, 4096 KB: skipped. Probing for Winbond W25x10, 128 KB: skipped. Probing for Winbond W25x20, 256 KB: skipped. Probing for Winbond W25x40, 512 KB: skipped. Probing for Winbond W25x80, 1024 KB: skipped. Probing for Winbond W25x16, 2048 KB: skipped. Probing for Winbond W25x32, 4096 KB: skipped. Probing for Winbond W25x64, 8192 KB: skipped. Probing for Winbond W29C011, 128 KB: skipped. Probing for Winbond W29C020C, 256 KB: skipped. Probing for Winbond W29C040P, 512 KB: skipped. Probing for Winbond W29EE011, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040B, 512 KB: skipped. Probing for Winbond W39V040C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Probing for EON unknown EON SPI chip, 0 KB: skipped. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Probing for SST unknown SST SPI chip, 0 KB: skipped. Probing for ST unknown ST SPI chip, 0 KB: skipped. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. -- Regards _ / ) "The blindingly obvious is / _)rad never immediately apparent" I ain't got no time for intellectual music, e.g. Hergest Ridge Alberto y Lost Trios Paranoias

1 0

ASUSTeK Computer INC. M4N78-VM
by Rainer Stumbaum 02 Jul '10

02 Jul '10

flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "M4N78-VM" DMI string baseboard-version: "Rev X.0x" DMI string chassis-type: "Desktop" Found ITE Super I/O, id 8712 Found chipset "NVIDIA MCP78S", enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Guessed flash bus type is SPI Found SMBus device 10de:0752 at 00:01:1 SPI BAR is at 0xf5f80000, after clearing low bits BAR is at 0xf5f80000 Mapping MCP67 SPI at 0xf5f80000, unaligned size 0x544. SPI control is 0xc01a, enable=0, idle=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. SPI on this chipset is not supported yet. OK. This chipset supports the following protocols: None. Calibrating delay loop... 607M loops per second, 100 myus = 173 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for EMST F49B002UA, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN29F010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Intel 82802AC, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Macronix MX25L512, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for PMC Pm49FL004, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF003A/B, 384 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF004A/B, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF004C, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF008A, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF008C, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF016C, 2048 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF020, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF020A, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF040, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF040B, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF080A, 1024 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF160C, 2048 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for ST M25P05-A, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW040B, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080A, 1024 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080B, 1024 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FW002, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW016, 2048 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW040, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW080, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50LPW116, 2048 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040B, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040C, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040FA, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080A, 1024 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W49F002U, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W49V002FA, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080FA, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically.

1 0

Re: [flashrom] Porting flashrom to OpenBSD
by Carl-Daniel Hailfinger 02 Jul '10

02 Jul '10

On 28.06.2010 22:01, Stuart Henderson wrote: > On 2010/06/29 00:06, Ian McWilliam wrote: > >> On 28/06/2010, at 6:41 PM, Matthieu Herrb wrote: >> >> >>> On Sun, Jun 27, 2010 at 10:38:30PM +0200, Carl-Daniel Hailfinger wrote: >>> >>>> Could I ask you to write one or two short sentences which will be >>>> printed if flashrom detects insufficient permisions on OpenBSD? Maybe >>>> something like this (feel free to change it completely): >>>> >>>> "Error: Insufficient permissions to access hardware. Please set >>>> securelevel=-1 in /etc/rc.securelevel and reboot, or reboot into single >>>> user mode." >>>> >>> This message looks good to me. You could add "See the securelevel(7) >>> and init(8) manual pages for details". >>> >>> Thanks for your work on this port. >>> -- >>> Matthieu Herrb >>> > > I agree with both points :) > Thanks. >> I think in the port we could probably add a README.OpenBSD file where >> we could explain the situation in more detail like we do for many other ports >> stored in the share/doc/flashrom directory as well. >> > > We could, but I think it's even better to have proper instructions > for OpenBSD in the main distribution. > I added the message to strategic places in the code and the man page. Add OpenBSD support. Add a requirements section to the man page which lists the needed access permissions for each programmer. This patch needs the libpci 8/16-bit write patch I sent earlier. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-openbsd/flashrom.8 =================================================================== --- flashrom-openbsd/flashrom.8 (revision 1063) +++ flashrom-openbsd/flashrom.8 (working copy) @@ -306,7 +306,7 @@ Example: .B "flashrom \-p dummy:lpc,fwh" .TP -.BR "nic3com" , " nicrealtek" , " nicsmc1211" , " gfxnvidia" , " satasii\ +.BR "nic3com" , " nicrealtek" , " nicsmc1211" , " gfxnvidia" , " satasii \ " and " atahpt " programmers These programmers have an option to specify the PCI address of the card your want to use, which must be specified if more than one card supported @@ -391,6 +391,51 @@ .SH EXIT STATUS flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem (/dev/xsvc on Solaris) can not be opened and with 3 if a call to mmap() fails. +.SH REQUIREMENTS +flashrom needs different access permissions for different programmers. +.sp +.B internal +needs raw memory access, PCI configuration space access, raw I/O port +access (x86) and MSR access (x86). +.sp +.B it87spi +needs raw I/O port access (x86). +.sp +.BR nic3com ", " nicrealtek ", " nicsmc1211 " and " nicnatsemi " +need PCI configuration space read access and raw I/O port access. +.sp +.B atahpt +needs PCI configuration space access and raw I/O port access. +.sp +.BR gfxnvidia " and " drkaiser +need PCI configuration space access and raw memory access. +.sp +.B satasii +needs PCI configuration space read access and raw memory access. +.sp +.B serprog +needs TCP access to the network or userspace access to a serial port. +.sp +.B buspirate_spi +needs userspace access to a serial port. +.sp +.BR dediprog " and " ft2232_spi +need access to the USB device via libusb. +.sp +.B dummy +needs no access permissions at all. +.sp +.BR internal ", " it87spi ", " nic3com ", " nicrealtek ", " nicsmc1211 ", " +.BR nicnatsemi ", " "gfxnvidia" ", " drkaiser ", " satasii " and " atahpt +have to be run as superuser/root, and need additional raw access permission. +.sp +.BR serprog ", " buspirate_spi ", " dediprog " and " ft2232_spi +can be run as normal user on most operating systems if appropriate device +permissions are set. +.sp +On OpenBSD, you can obtain raw access permission by setting +securelevel=-1 in /etc/rc.securelevel and rebooting, or rebooting into single +user mode. .SH BUGS Please report any bugs at .sp Index: flashrom-openbsd/hwaccess.c =================================================================== --- flashrom-openbsd/hwaccess.c (revision 1063) +++ flashrom-openbsd/hwaccess.c (working copy) @@ -57,6 +57,11 @@ #endif msg_perr("ERROR: Could not get I/O privileges (%s).\n" "You need to be root.\n", strerror(errno)); +#if defined (__OpenBSD__) + msg_perr("Please set securelevel=-1 in /etc/rc.securelevel " + "and reboot, or reboot into \n"); + msg_perr("single user mode.\n"); +#endif exit(1); } #endif Index: flashrom-openbsd/hwaccess.h =================================================================== --- flashrom-openbsd/hwaccess.h (revision 1063) +++ flashrom-openbsd/hwaccess.h (working copy) @@ -228,17 +228,25 @@ #endif #endif -#if defined(__NetBSD__) +#if defined(__NetBSD__) || defined (__OpenBSD__) #define off64_t off_t #define lseek64 lseek #if defined(__i386__) || defined(__x86_64__) #include <sys/types.h> #include <machine/sysarch.h> +#if defined(__NetBSD__) #if defined(__i386__) #define iopl i386_iopl #elif defined(__x86_64__) #define iopl x86_64_iopl #endif +#elif defined (__OpenBSD__) + #if defined(__i386__) + #define iopl i386_iopl + #elif defined(__amd64__) + #define iopl amd64_iopl + #endif +#endif #include <stdint.h> static inline void outb(uint8_t value, uint16_t port) Index: flashrom-openbsd/physmap.c =================================================================== --- flashrom-openbsd/physmap.c (revision 1063) +++ flashrom-openbsd/physmap.c (working copy) @@ -229,6 +229,10 @@ msg_perr("You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n"); msg_perr("disabling the other option unfortunately requires a kernel recompile. Sorry!\n"); } +#elif defined (__OpenBSD__) + msg_perr("Please set securelevel=-1 in /etc/rc.securelevel " + "and reboot, or reboot into \n"); + msg_perr("single user mode.\n"); #endif if (!mayfail) exit(3); Index: flashrom-openbsd/Makefile =================================================================== --- flashrom-openbsd/Makefile (revision 1063) +++ flashrom-openbsd/Makefile (working copy) @@ -48,6 +48,10 @@ CPPFLAGS += -I/usr/local/include LDFLAGS += -L/usr/local/lib endif +ifeq ($(OS_ARCH), OpenBSD) +CPPFLAGS += -I/usr/local/include +LDFLAGS += -L/usr/local/lib +endif ifeq ($(OS_ARCH), DOS) EXEC_SUFFIX := .exe CPPFLAGS += -I../libgetopt -I../libpci/include @@ -259,9 +263,13 @@ LIBS += ../libpci/lib/libpci.a else LIBS += -lpci +ifeq ($(OS_ARCH), OpenBSD) +# For (i386|amd64)_iopl(2). +LIBS += -l$(shell uname -m) endif endif endif +endif ifeq ($(CONFIG_PRINT_WIKI), yes) FEATURE_CFLAGS += -D'CONFIG_PRINT_WIKI=1' Index: flashrom-openbsd/README =================================================================== --- flashrom-openbsd/README (revision 1063) +++ flashrom-openbsd/README (working copy) @@ -55,6 +55,11 @@ * devel/gmake * devel/libpci +On OpenBSD, you need the following ports: + + * devel/gmake + * sysutils/pciutils + To compile on Linux, use: make @@ -76,6 +81,10 @@ ln -s /usr/pkg/include/pciutils pci gmake CPPFLAGS=-I. LDFLAGS="-L/usr/pkg/lib -Wl,-rpath-link,/usr/pkg/lib" +To compile on OpenBSD, use: + + gmake + To compile and run on Darwin/Mac OS X: Install DirectIO from coresystems GmbH. -- http://www.hailfinger.org/

2 3

[commit] r1067 - trunk
by repository service 02 Jul '10

02 Jul '10

Author: hailfinger Date: Fri Jul 2 19:12:50 2010 New Revision: 1067 URL: http://flashrom.org/trac/coreboot/changeset/1067 Log: Add OpenBSD support. Add a requirements section to the man page which lists the needed access permissions for each programmer. This feature needs my pciutils/libpci 8/16-bit write emulation patch at http://marc.info/?l=openbsd-ports&m=127780030728045 titled [PATCH] Fix pciutils non-32bit PCI write on OpenBSD Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stuart Henderson <sthen(a)openbsd.org> Modified: trunk/Makefile trunk/README trunk/flashrom.8 trunk/hwaccess.c trunk/hwaccess.h trunk/physmap.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Thu Jul 1 19:45:54 2010 (r1066) +++ trunk/Makefile Fri Jul 2 19:12:50 2010 (r1067) @@ -48,6 +48,10 @@ CPPFLAGS += -I/usr/local/include LDFLAGS += -L/usr/local/lib endif +ifeq ($(OS_ARCH), OpenBSD) +CPPFLAGS += -I/usr/local/include +LDFLAGS += -L/usr/local/lib +endif ifeq ($(OS_ARCH), DOS) EXEC_SUFFIX := .exe CPPFLAGS += -I../libgetopt -I../libpci/include @@ -259,6 +263,10 @@ LIBS += ../libpci/lib/libpci.a else LIBS += -lpci +ifeq ($(OS_ARCH), OpenBSD) +# For (i386|amd64)_iopl(2). +LIBS += -l$(shell uname -m) +endif endif endif endif Modified: trunk/README ============================================================================== --- trunk/README Thu Jul 1 19:45:54 2010 (r1066) +++ trunk/README Fri Jul 2 19:12:50 2010 (r1067) @@ -55,6 +55,11 @@ * devel/gmake * devel/libpci +On OpenBSD, you need the following ports: + + * devel/gmake + * sysutils/pciutils + To compile on Linux, use: make @@ -76,6 +81,10 @@ ln -s /usr/pkg/include/pciutils pci gmake CPPFLAGS=-I. LDFLAGS="-L/usr/pkg/lib -Wl,-rpath-link,/usr/pkg/lib" +To compile on OpenBSD, use: + + gmake + To compile and run on Darwin/Mac OS X: Install DirectIO from coresystems GmbH. Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Thu Jul 1 19:45:54 2010 (r1066) +++ trunk/flashrom.8 Fri Jul 2 19:12:50 2010 (r1067) @@ -306,7 +306,7 @@ Example: .B "flashrom \-p dummy:lpc,fwh" .TP -.BR "nic3com" , " nicrealtek" , " nicsmc1211" , " gfxnvidia" , " satasii\ +.BR "nic3com" , " nicrealtek" , " nicsmc1211" , " gfxnvidia" , " satasii \ " and " atahpt " programmers These programmers have an option to specify the PCI address of the card your want to use, which must be specified if more than one card supported @@ -391,6 +391,51 @@ .SH EXIT STATUS flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem (/dev/xsvc on Solaris) can not be opened and with 3 if a call to mmap() fails. +.SH REQUIREMENTS +flashrom needs different access permissions for different programmers. +.sp +.B internal +needs raw memory access, PCI configuration space access, raw I/O port +access (x86) and MSR access (x86). +.sp +.B it87spi +needs raw I/O port access (x86). +.sp +.BR nic3com ", " nicrealtek ", " nicsmc1211 " and " nicnatsemi " +need PCI configuration space read access and raw I/O port access. +.sp +.B atahpt +needs PCI configuration space access and raw I/O port access. +.sp +.BR gfxnvidia " and " drkaiser +need PCI configuration space access and raw memory access. +.sp +.B satasii +needs PCI configuration space read access and raw memory access. +.sp +.B serprog +needs TCP access to the network or userspace access to a serial port. +.sp +.B buspirate_spi +needs userspace access to a serial port. +.sp +.BR dediprog " and " ft2232_spi +need access to the USB device via libusb. +.sp +.B dummy +needs no access permissions at all. +.sp +.BR internal ", " it87spi ", " nic3com ", " nicrealtek ", " nicsmc1211 ", " +.BR nicnatsemi ", " "gfxnvidia" ", " drkaiser ", " satasii " and " atahpt +have to be run as superuser/root, and need additional raw access permission. +.sp +.BR serprog ", " buspirate_spi ", " dediprog " and " ft2232_spi +can be run as normal user on most operating systems if appropriate device +permissions are set. +.sp +On OpenBSD, you can obtain raw access permission by setting +securelevel=-1 in /etc/rc.securelevel and rebooting, or rebooting into single +user mode. .SH BUGS Please report any bugs at .sp Modified: trunk/hwaccess.c ============================================================================== --- trunk/hwaccess.c Thu Jul 1 19:45:54 2010 (r1066) +++ trunk/hwaccess.c Fri Jul 2 19:12:50 2010 (r1067) @@ -57,6 +57,11 @@ #endif msg_perr("ERROR: Could not get I/O privileges (%s).\n" "You need to be root.\n", strerror(errno)); +#if defined (__OpenBSD__) + msg_perr("Please set securelevel=-1 in /etc/rc.securelevel " + "and reboot, or reboot into \n"); + msg_perr("single user mode.\n"); +#endif exit(1); } #endif Modified: trunk/hwaccess.h ============================================================================== --- trunk/hwaccess.h Thu Jul 1 19:45:54 2010 (r1066) +++ trunk/hwaccess.h Fri Jul 2 19:12:50 2010 (r1067) @@ -228,17 +228,25 @@ #endif #endif -#if defined(__NetBSD__) +#if defined(__NetBSD__) || defined (__OpenBSD__) #define off64_t off_t #define lseek64 lseek #if defined(__i386__) || defined(__x86_64__) #include <sys/types.h> #include <machine/sysarch.h> +#if defined(__NetBSD__) #if defined(__i386__) #define iopl i386_iopl #elif defined(__x86_64__) #define iopl x86_64_iopl #endif +#elif defined (__OpenBSD__) + #if defined(__i386__) + #define iopl i386_iopl + #elif defined(__amd64__) + #define iopl amd64_iopl + #endif +#endif #include <stdint.h> static inline void outb(uint8_t value, uint16_t port) Modified: trunk/physmap.c ============================================================================== --- trunk/physmap.c Thu Jul 1 19:45:54 2010 (r1066) +++ trunk/physmap.c Fri Jul 2 19:12:50 2010 (r1067) @@ -229,6 +229,10 @@ msg_perr("You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n"); msg_perr("disabling the other option unfortunately requires a kernel recompile. Sorry!\n"); } +#elif defined (__OpenBSD__) + msg_perr("Please set securelevel=-1 in /etc/rc.securelevel " + "and reboot, or reboot into \n"); + msg_perr("single user mode.\n"); #endif if (!mayfail) exit(3);

1 0

(no subject)
by Benjamin 02 Jul '10

02 Jul '10

flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "Dell Inc." DMI string system-product-name: "Studio XPS 1340" DMI string system-version: "A11" DMI string baseboard-manufacturer: "Dell Inc." DMI string baseboard-product-name: " " DMI string baseboard-version: "A11" DMI string chassis-type: "Portable" Found chipset "NVIDIA MCP79", enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Guessed flash bus type is LPC Found SMBus device 10de:0aa2 at 00:03:2 SPI BAR is at 0xf0600000, after clearing low bits BAR is at 0xf0600000 Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI enabled. Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. LPC on this chipset is not supported yet. OK. This chipset supports the following protocols: LPC. Calibrating delay loop... 671M loops per second, 100 myus = 197 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN29F010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Intel 82802AC, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Macronix MX25L512, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF003A/B, 384 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF004A/B, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF004C, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF008A, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF008C, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF016C, 2048 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0x02, id2 0x0e Probing for ST M25P05-A, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW002, 256 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50FW016, 2048 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50FW040, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50FW080, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0x02, id2 0x0e Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0x02, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Winbond W39V080FA, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically.

1 0

[PATCH] ICH9/10: display FRAP/FREGx access controls
by Joshua Roys 01 Jul '10

01 Jul '10

Hello, Attached is a patch to display the FRAP access controls on the FREGx regions of the flash chip. Also attached is the output from `flashrom -Vr foo.bin' on an ICH10 machine. Thanks, Josh

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flashrom July 2010