flashrom July 2010

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Testing MCP SPI patch
by Andrew Morgan 22 Jul '10

22 Jul '10

Attached is the result of flashrom -V with the latest MCP SPI patch. -- Andrew.

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Re: [flashrom] [PATCH] Move SB600 SPI initialization to sb600spi.c
by Carl-Daniel Hailfinger 22 Jul '10

22 Jul '10

On 22.07.2010 18:56, Michael Karcher wrote: > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > > --- a/sb600spi.c > +++ b/sb600spi.c > @@ -152,4 +152,80 @@ int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return 0; > } > > +int sb600_probe_spi(struct pci_dev *dev) > +{ > [...] > + msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); > + msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); > + if (reg != 0x00) > + return 0; > [...] > + msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); > + msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); > + if ((reg & 0x80) != 0x00) > + return 0; > [...] > + msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); > + if (reg != 0x00) > + return 0; > We might want to print a short msg_pdbg("Not enabling SPI"); in each of the cases where we return 0, but that's not strictly required and I want to get this patch in now. Please go ahead. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH 1/3] Move Intel SPI initialisation to ichspi.c
by Carl-Daniel Hailfinger 22 Jul '10

22 Jul '10

On 18.07.2010 16:19, Michael Karcher wrote: > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > --- > chipset_enable.c | 202 +-------------------------------------------------- > flash.h | 6 +- > ichspi.c | 214 +++++++++++++++++++++++++++++++++++++++++++++++++++++- > 3 files changed, 218 insertions(+), 204 deletions(-) > > diff --git a/chipset_enable.c b/chipset_enable.c > index dc0e55f..7434d65 100644 > --- a/chipset_enable.c > +++ b/chipset_enable.c > @@ -417,69 +417,15 @@ static int enable_flash_poulsbo(struct pci_dev *dev, const char *name) > > static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) > { > - uint32_t mmio_base; > - > /* Do we really need no write enable? */ > - mmio_base = (pci_read_long(dev, 0xbc)) << 8; > - msg_pdbg("MMIO base at = 0x%x\n", mmio_base); > - ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); > - > - msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", > - mmio_readw(ich_spibar + 0x6c)); > - > - /* Not sure if it speaks all these bus protocols. */ > - buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_VIA; > - ich_init_opcodes(); > - > - return 0; > -} > - > -#define ICH_BMWAG(x) ((x >> 24) & 0xff) > -#define ICH_BMRAG(x) ((x >> 16) & 0xff) > -#define ICH_BRWA(x) ((x >> 8) & 0xff) > -#define ICH_BRRA(x) ((x >> 0) & 0xff) > - > -#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) > -#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) > - > -static void do_ich9_spi_frap(uint32_t frap, int i) > -{ > - const char *access_names[4] = { > - "locked", "read-only", "write-only", "read-write" > - }; > - const char *region_names[5] = { > - "Flash Descriptor", "BIOS", "Management Engine", > - "Gigabit Ethernet", "Platform Data" > - }; > - uint32_t base, limit; > - int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | > - (((ICH_BRRA(frap) >> i) & 1) << 0); > - int offset = 0x54 + i * 4; > - uint32_t freg = mmio_readl(ich_spibar + offset); > - > - msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", > - offset, freg, i, region_names[i]); > - > - base = ICH_FREG_BASE(freg); > - limit = ICH_FREG_LIMIT(freg); > - if (base == 0x1fff && limit == 0) { > - /* this FREG is disabled */ > - msg_pdbg("%s region is unused.\n", region_names[i]); > - return; > - } > - > - msg_pdbg("0x%08x-0x%08x is %s\n", > - (base << 12), (limit << 12) | 0x0fff, > - access_names[rwperms]); > + return via_init_spi(dev); > } > > static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, > int ich_generation) > { > - int ret, i; > - uint8_t old, new, bbs, buc; > - uint16_t spibar_offset, tmp2; > + int ret; > + uint8_t bbs, buc; > uint32_t tmp, gcs; > void *rcrb; > //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line > @@ -518,147 +464,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, > return ret; > } > > - switch (ich_generation) { > - case 7: > - buses_supported = CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_ICH7; > - spibar_offset = 0x3020; > - break; > - case 8: > - buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_ICH9; > - spibar_offset = 0x3020; > - break; > - case 9: > - case 10: > - default: /* Future version might behave the same */ > - buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_ICH9; > - spibar_offset = 0x3800; > - break; > - } > - > - /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ > - msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); > - > - /* Assign Virtual Address */ > - ich_spibar = rcrb + spibar_offset; > - > - switch (spi_controller) { > - case SPI_CONTROLLER_ICH7: > - msg_pdbg("0x00: 0x%04x (SPIS)\n", > - mmio_readw(ich_spibar + 0)); > - msg_pdbg("0x02: 0x%04x (SPIC)\n", > - mmio_readw(ich_spibar + 2)); > - msg_pdbg("0x04: 0x%08x (SPIA)\n", > - mmio_readl(ich_spibar + 4)); > - for (i = 0; i < 8; i++) { > - int offs; > - offs = 8 + (i * 8); > - msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, > - mmio_readl(ich_spibar + offs), i); > - msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, > - mmio_readl(ich_spibar + offs + 4), i); > - } > - ichspi_bbar = mmio_readl(ich_spibar + 0x50); > - msg_pdbg("0x50: 0x%08x (BBAR)\n", > - ichspi_bbar); > - msg_pdbg("0x54: 0x%04x (PREOP)\n", > - mmio_readw(ich_spibar + 0x54)); > - msg_pdbg("0x56: 0x%04x (OPTYPE)\n", > - mmio_readw(ich_spibar + 0x56)); > - msg_pdbg("0x58: 0x%08x (OPMENU)\n", > - mmio_readl(ich_spibar + 0x58)); > - msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", > - mmio_readl(ich_spibar + 0x5c)); > - for (i = 0; i < 4; i++) { > - int offs; > - offs = 0x60 + (i * 4); > - msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, > - mmio_readl(ich_spibar + offs), i); > - } > - msg_pdbg("\n"); > - if (mmio_readw(ich_spibar) & (1 << 15)) { > - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); > - ichspi_lock = 1; > - } > - ich_init_opcodes(); > - break; > - case SPI_CONTROLLER_ICH9: > - tmp2 = mmio_readw(ich_spibar + 4); > - msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); > - msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); > - msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); > - msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); > - msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); > - msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); > - msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); > - msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); > - msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); > - > - tmp = mmio_readl(ich_spibar + 0x50); > - msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); > - msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); > - msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); > - msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); > - msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); > - > - /* print out the FREGx registers along with FRAP access bits */ > - for(i = 0; i < 5; i++) > - do_ich9_spi_frap(tmp, i); > - > - msg_pdbg("0x74: 0x%08x (PR0)\n", > - mmio_readl(ich_spibar + 0x74)); > - msg_pdbg("0x78: 0x%08x (PR1)\n", > - mmio_readl(ich_spibar + 0x78)); > - msg_pdbg("0x7C: 0x%08x (PR2)\n", > - mmio_readl(ich_spibar + 0x7C)); > - msg_pdbg("0x80: 0x%08x (PR3)\n", > - mmio_readl(ich_spibar + 0x80)); > - msg_pdbg("0x84: 0x%08x (PR4)\n", > - mmio_readl(ich_spibar + 0x84)); > - msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", > - mmio_readl(ich_spibar + 0x90)); > - msg_pdbg("0x94: 0x%04x (PREOP)\n", > - mmio_readw(ich_spibar + 0x94)); > - msg_pdbg("0x96: 0x%04x (OPTYPE)\n", > - mmio_readw(ich_spibar + 0x96)); > - msg_pdbg("0x98: 0x%08x (OPMENU)\n", > - mmio_readl(ich_spibar + 0x98)); > - msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", > - mmio_readl(ich_spibar + 0x9C)); > - ichspi_bbar = mmio_readl(ich_spibar + 0xA0); > - msg_pdbg("0xA0: 0x%08x (BBAR)\n", > - ichspi_bbar); > - msg_pdbg("0xB0: 0x%08x (FDOC)\n", > - mmio_readl(ich_spibar + 0xB0)); > - if (tmp2 & (1 << 15)) { > - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); > - ichspi_lock = 1; > - } > - ich_init_opcodes(); > - break; > - default: > - /* Nothing */ > - break; > - } > - > - old = pci_read_byte(dev, 0xdc); > - msg_pdbg("SPI Read Configuration: "); > - new = (old >> 2) & 0x3; > - switch (new) { > - case 0: > - case 1: > - case 2: > - msg_pdbg("prefetching %sabled, caching %sabled, ", > - (new & 0x2) ? "en" : "dis", > - (new & 0x1) ? "dis" : "en"); > - break; > - default: > - msg_pdbg("invalid prefetching/caching settings, "); > - break; > - } > - > + ich_init_spi(dev, tmp, rcrb, ich_generation); > check for the return value? > return ret; > } > > diff --git a/flash.h b/flash.h > index c3302c4..a8ca6d7 100644 > --- a/flash.h > +++ b/flash.h > @@ -680,10 +680,10 @@ int default_spi_send_multicommand(struct spi_command *cmds); > uint32_t spi_get_valid_read_addr(void); > > /* ichspi.c */ > -extern int ichspi_lock; > extern uint32_t ichspi_bbar; > -extern void *ich_spibar; > -int ich_init_opcodes(void); > +void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, > whitespace after * and at the end of the line. > + int ich_generation); > +int via_init_spi(struct pci_dev * dev); > whitespace after * > int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr); > int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > diff --git a/ichspi.c b/ichspi.c > index d6f9118..246f3ae 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -101,11 +101,11 @@ > #define ICH7_REG_OPMENU 0x58 /* 64 Bits */ > > /* ICH SPI configuration lock-down. May be set during chipset enabling. */ > -int ichspi_lock = 0; > +static int ichspi_lock = 0; > > uint32_t ichspi_bbar = 0; > > -void *ich_spibar = NULL; > +static void *ich_spibar = NULL; > > typedef struct _OPCODE { > uint8_t opcode; //This commands spi opcode > @@ -364,7 +364,7 @@ void ich_set_bbar(uint32_t minaddr) > * > * It should be called before ICH sends any spi command. > */ > -int ich_init_opcodes(void) > +static int ich_init_opcodes(void) > { > int rc = 0; > OPCODES *curopcodes_done; > @@ -398,6 +398,214 @@ int ich_init_opcodes(void) > } > } > > +#define ICH_BMWAG(x) ((x >> 24) & 0xff) > +#define ICH_BMRAG(x) ((x >> 16) & 0xff) > +#define ICH_BRWA(x) ((x >> 8) & 0xff) > +#define ICH_BRRA(x) ((x >> 0) & 0xff) > + > +#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) > +#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) > + > +static void do_ich9_spi_frap(uint32_t frap, int i) > +{ > + const char *access_names[4] = { > + "locked", "read-only", "write-only", "read-write" > + }; > + const char *region_names[5] = { > + "Flash Descriptor", "BIOS", "Management Engine", > + "Gigabit Ethernet", "Platform Data" > + }; > + uint32_t base, limit; > + int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | > + (((ICH_BRRA(frap) >> i) & 1) << 0); > + int offset = 0x54 + i * 4; > + uint32_t freg = mmio_readl(ich_spibar + offset); > + > + msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", > + offset, freg, i, region_names[i]); > + > + base = ICH_FREG_BASE(freg); > + limit = ICH_FREG_LIMIT(freg); > + if (base == 0x1fff && limit == 0) { > + /* this FREG is disabled */ > + msg_pdbg("%s region is unused.\n", region_names[i]); > + return; > + } > + > + msg_pdbg("0x%08x-0x%08x is %s\n", > + (base << 12), (limit << 12) | 0x0fff, > + access_names[rwperms]); > +} > Is the FRAP/FREG stuff really SPI specific? If not, it should stay in chipset_enable.c AFAICS. > + > +void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, > whitespace after * and at end of line Can you make this function return an error value? > + int ich_generation) > +{ > + int i; > + uint8_t old, new; > + uint16_t spibar_offset, tmp2; > + uint32_t tmp; > + > + switch (ich_generation) { > + case 7: > + buses_supported = CHIP_BUSTYPE_SPI; > + spi_controller = SPI_CONTROLLER_ICH7; > + spibar_offset = 0x3020; > + break; > + case 8: > + buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > Is adding BUSTYPE_FWH to buses_supported a good idea here in ichspi.c? > + spi_controller = SPI_CONTROLLER_ICH9; > + spibar_offset = 0x3020; > + break; > + case 9: > + case 10: > + default: /* Future version might behave the same */ > + buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > + spi_controller = SPI_CONTROLLER_ICH9; > + spibar_offset = 0x3800; > + break; > + } > + > + /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ > + msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset); > + > + /* Assign Virtual Address */ > + ich_spibar = rcrb + spibar_offset; > + > + switch (spi_controller) { > + case SPI_CONTROLLER_ICH7: > + msg_pdbg("0x00: 0x%04x (SPIS)\n", > + mmio_readw(ich_spibar + 0)); > + msg_pdbg("0x02: 0x%04x (SPIC)\n", > + mmio_readw(ich_spibar + 2)); > + msg_pdbg("0x04: 0x%08x (SPIA)\n", > + mmio_readl(ich_spibar + 4)); > + for (i = 0; i < 8; i++) { > + int offs; > + offs = 8 + (i * 8); > + msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, > + mmio_readl(ich_spibar + offs), i); > + msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, > + mmio_readl(ich_spibar + offs + 4), i); > + } > + ichspi_bbar = mmio_readl(ich_spibar + 0x50); > + msg_pdbg("0x50: 0x%08x (BBAR)\n", > + ichspi_bbar); > + msg_pdbg("0x54: 0x%04x (PREOP)\n", > + mmio_readw(ich_spibar + 0x54)); > + msg_pdbg("0x56: 0x%04x (OPTYPE)\n", > + mmio_readw(ich_spibar + 0x56)); > + msg_pdbg("0x58: 0x%08x (OPMENU)\n", > + mmio_readl(ich_spibar + 0x58)); > + msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", > + mmio_readl(ich_spibar + 0x5c)); > + for (i = 0; i < 4; i++) { > + int offs; > + offs = 0x60 + (i * 4); > + msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, > + mmio_readl(ich_spibar + offs), i); > + } > + msg_pdbg("\n"); > + if (mmio_readw(ich_spibar) & (1 << 15)) { > + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); > + ichspi_lock = 1; > + } > + ich_init_opcodes(); > + break; > + case SPI_CONTROLLER_ICH9: > + tmp2 = mmio_readw(ich_spibar + 4); > + msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); > + msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); > + msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); > + msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); > + msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); > + msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); > + msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); > + msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); > + msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); > + > + tmp = mmio_readl(ich_spibar + 0x50); > + msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); > + msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); > + msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); > + msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); > + msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); > + > + /* print out the FREGx registers along with FRAP access bits */ > + for(i = 0; i < 5; i++) > + do_ich9_spi_frap(tmp, i); > + > + msg_pdbg("0x74: 0x%08x (PR0)\n", > + mmio_readl(ich_spibar + 0x74)); > + msg_pdbg("0x78: 0x%08x (PR1)\n", > + mmio_readl(ich_spibar + 0x78)); > + msg_pdbg("0x7C: 0x%08x (PR2)\n", > + mmio_readl(ich_spibar + 0x7C)); > + msg_pdbg("0x80: 0x%08x (PR3)\n", > + mmio_readl(ich_spibar + 0x80)); > + msg_pdbg("0x84: 0x%08x (PR4)\n", > + mmio_readl(ich_spibar + 0x84)); > + msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", > + mmio_readl(ich_spibar + 0x90)); > + msg_pdbg("0x94: 0x%04x (PREOP)\n", > + mmio_readw(ich_spibar + 0x94)); > + msg_pdbg("0x96: 0x%04x (OPTYPE)\n", > + mmio_readw(ich_spibar + 0x96)); > + msg_pdbg("0x98: 0x%08x (OPMENU)\n", > + mmio_readl(ich_spibar + 0x98)); > + msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", > + mmio_readl(ich_spibar + 0x9C)); > + ichspi_bbar = mmio_readl(ich_spibar + 0xA0); > + msg_pdbg("0xA0: 0x%08x (BBAR)\n", > + ichspi_bbar); > + msg_pdbg("0xB0: 0x%08x (FDOC)\n", > + mmio_readl(ich_spibar + 0xB0)); > + if (tmp2 & (1 << 15)) { > + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); > + ichspi_lock = 1; > + } > + ich_init_opcodes(); > + break; > + default: > + /* Nothing */ > + break; > + } > + > + old = pci_read_byte(dev, 0xdc); > + msg_pdbg("SPI Read Configuration: "); > + new = (old >> 2) & 0x3; > + switch (new) { > + case 0: > + case 1: > + case 2: > + msg_pdbg("prefetching %sabled, caching %sabled, ", > + (new & 0x2) ? "en" : "dis", > + (new & 0x1) ? "dis" : "en"); > + break; > + default: > + msg_pdbg("invalid prefetching/caching settings, "); > + break; > + } > +} > + > +int via_init_spi(struct pci_dev * dev) > whitespace after * > +{ > + uint32_t mmio_base; > + > + mmio_base = (pci_read_long(dev, 0xbc)) << 8; > + msg_pdbg("MMIO base at = 0x%x\n", mmio_base); > + ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); > + > + msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", > + mmio_readw(ich_spibar + 0x6c)); > + > + /* Not sure if it speaks all these bus protocols. */ > + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > + spi_controller = SPI_CONTROLLER_VIA; > + ich_init_opcodes(); > + > + return 0; > +} > + > static int ich7_run_opcode(OPCODE op, uint32_t offset, > uint8_t datalength, uint8_t * data, int maxdata) > { > Looks good otherwise. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[results of]# lspci -vvvnnxxx
by Greg Scantlen 22 Jul '10

22 Jul '10

see attached lspci.txt

1 0

[commit] r1099 - trunk
by repository service 22 Jul '10

22 Jul '10

Author: mkarcher Date: Thu Jul 22 20:04:19 2010 New Revision: 1099 URL: http://flashrom.org/trac/coreboot/changeset/1099 Log: Move SB600 SPI initialization to sb600spi.c Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c trunk/flash.h trunk/sb600spi.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Thu Jul 22 20:04:15 2010 (r1098) +++ trunk/chipset_enable.c Thu Jul 22 20:04:19 2010 (r1099) @@ -693,10 +693,9 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name) { - uint32_t tmp, prot; + uint32_t prot; uint8_t reg; - struct pci_dev *smbus_dev; - int has_spi = 1; + int ret; /* Clear ROM protect 0-3. */ for (reg = 0x50; reg < 0x60; reg += 4) { @@ -720,80 +719,9 @@ (prot & 0xfffffc00) + ((prot & 0x3ff) << 8)); } - /* Read SPI_BaseAddr */ - tmp = pci_read_long(dev, 0xa0); - tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ - msg_pdbg("SPI base address is at 0x%x\n", tmp); - - /* If the BAR has address 0, it is unlikely SPI is used. */ - if (!tmp) - has_spi = 0; - - if (has_spi) { - /* Physical memory has to be mapped at page (4k) boundaries. */ - sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, - 0x1000); - /* The low bits of the SPI base address are used as offset into - * the mapped page. - */ - sb600_spibar += tmp & 0xfff; - - tmp = pci_read_long(dev, 0xa0); - msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " - "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, - (tmp & 0x4) >> 2); - tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; - msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); - - tmp = pci_read_byte(dev, 0xbb); - msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", - tmp & 0x1, (tmp & 0x20) >> 5); - tmp = mmio_readl(sb600_spibar); - msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " - "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " - "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", - (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, - (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, - (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); - } - - /* Look for the SMBus device. */ - smbus_dev = pci_dev_find(0x1002, 0x4385); - - if (has_spi && !smbus_dev) { - msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); - has_spi = 0; - } - if (has_spi) { - /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ - /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ - reg = pci_read_byte(smbus_dev, 0xAB); - reg &= 0xC0; - msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); - msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); - if (reg != 0x00) - has_spi = 0; - /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ - reg = pci_read_byte(smbus_dev, 0x83); - reg &= 0xC0; - msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); - msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); - /* SPI_HOLD is not used on all boards, filter it out. */ - if ((reg & 0x80) != 0x00) - has_spi = 0; - /* GPIO47/SPI_CLK status */ - reg = pci_read_byte(smbus_dev, 0xA7); - reg &= 0x40; - msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); - if (reg != 0x00) - has_spi = 0; - } - buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; - if (has_spi) { - buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_SB600; - } + + ret = sb600_probe_spi(dev); /* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); @@ -830,7 +758,7 @@ OUTB(0x0e, 0xcd7); */ - return 0; + return ret; } static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name) Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Thu Jul 22 20:04:15 2010 (r1098) +++ trunk/flash.h Thu Jul 22 20:04:19 2010 (r1099) @@ -719,11 +719,11 @@ int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* sb600spi.c */ +int sb600_probe_spi(struct pci_dev *dev); int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); -extern uint8_t *sb600_spibar; /* wbsio_spi.c */ int wbsio_check_for_spi(void); Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Thu Jul 22 20:04:15 2010 (r1098) +++ trunk/sb600spi.c Thu Jul 22 20:04:19 2010 (r1099) @@ -40,7 +40,7 @@ *}; */ -uint8_t *sb600_spibar = NULL; +static uint8_t *sb600_spibar = NULL; int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { @@ -152,4 +152,86 @@ return 0; } +int sb600_probe_spi(struct pci_dev *dev) +{ + struct pci_dev *smbus_dev; + uint32_t tmp; + uint8_t reg; + /* Read SPI_BaseAddr */ + tmp = pci_read_long(dev, 0xa0); + tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ + msg_pdbg("SPI base address is at 0x%x\n", tmp); + + /* If the BAR has address 0, it is unlikely SPI is used. */ + if (!tmp) + return 0; + + /* Physical memory has to be mapped at page (4k) boundaries. */ + sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, + 0x1000); + /* The low bits of the SPI base address are used as offset into + * the mapped page. + */ + sb600_spibar += tmp & 0xfff; + + tmp = pci_read_long(dev, 0xa0); + msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " + "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, + (tmp & 0x4) >> 2); + tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; + msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); + + tmp = pci_read_byte(dev, 0xbb); + msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", + tmp & 0x1, (tmp & 0x20) >> 5); + tmp = mmio_readl(sb600_spibar); + msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " + "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " + "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", + (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, + (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, + (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); + + /* Look for the SMBus device. */ + smbus_dev = pci_dev_find(0x1002, 0x4385); + + if (!smbus_dev) { + msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); + return ERROR_NONFATAL; + } + + /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ + /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ + reg = pci_read_byte(smbus_dev, 0xAB); + reg &= 0xC0; + msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); + msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); + if (reg != 0x00) { + msg_pdbg("Not enabling SPI"); + return 0; + } + /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ + reg = pci_read_byte(smbus_dev, 0x83); + reg &= 0xC0; + msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); + msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); + /* SPI_HOLD is not used on all boards, filter it out. */ + if ((reg & 0x80) != 0x00) { + msg_pdbg("Not enabling SPI"); + return 0; + } + /* GPIO47/SPI_CLK status */ + reg = pci_read_byte(smbus_dev, 0xA7); + reg &= 0x40; + msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); + if (reg != 0x00) { + msg_pdbg("Not enabling SPI"); + return 0; + } + + buses_supported |= CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_SB600; + return 0; +} + #endif

1 0

[commit] r1098 - trunk
by repository service 22 Jul '10

22 Jul '10

Author: mkarcher Date: Thu Jul 22 20:04:15 2010 New Revision: 1098 URL: http://flashrom.org/trac/coreboot/changeset/1098 Log: Move Intel SPI initialisation to ichspi.c Smarter version could decide whether SPI is vital or not depending on straps. Straps are currently implemented for ICH7. EP80579 is in the comment, PCH of 5 Series/3400 Series has "LPC, reserved, PCI, SPI". Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c trunk/flash.h trunk/ichspi.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Thu Jul 22 17:20:43 2010 (r1097) +++ trunk/chipset_enable.c Thu Jul 22 20:04:15 2010 (r1098) @@ -417,69 +417,15 @@ static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) { - uint32_t mmio_base; - /* Do we really need no write enable? */ - mmio_base = (pci_read_long(dev, 0xbc)) << 8; - msg_pdbg("MMIO base at = 0x%x\n", mmio_base); - ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); - - msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", - mmio_readw(ich_spibar + 0x6c)); - - /* Not sure if it speaks all these bus protocols. */ - buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_VIA; - ich_init_opcodes(); - - return 0; -} - -#define ICH_BMWAG(x) ((x >> 24) & 0xff) -#define ICH_BMRAG(x) ((x >> 16) & 0xff) -#define ICH_BRWA(x) ((x >> 8) & 0xff) -#define ICH_BRRA(x) ((x >> 0) & 0xff) - -#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) -#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) - -static void do_ich9_spi_frap(uint32_t frap, int i) -{ - const char *access_names[4] = { - "locked", "read-only", "write-only", "read-write" - }; - const char *region_names[5] = { - "Flash Descriptor", "BIOS", "Management Engine", - "Gigabit Ethernet", "Platform Data" - }; - uint32_t base, limit; - int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | - (((ICH_BRRA(frap) >> i) & 1) << 0); - int offset = 0x54 + i * 4; - uint32_t freg = mmio_readl(ich_spibar + offset); - - msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", - offset, freg, i, region_names[i]); - - base = ICH_FREG_BASE(freg); - limit = ICH_FREG_LIMIT(freg); - if (base == 0x1fff && limit == 0) { - /* this FREG is disabled */ - msg_pdbg("%s region is unused.\n", region_names[i]); - return; - } - - msg_pdbg("0x%08x-0x%08x is %s\n", - (base << 12), (limit << 12) | 0x0fff, - access_names[rwperms]); + return via_init_spi(dev); } static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, int ich_generation) { - int ret, i; - uint8_t old, new, bbs, buc; - uint16_t spibar_offset, tmp2; + int ret; + uint8_t bbs, buc; uint32_t tmp, gcs; void *rcrb; //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line @@ -512,152 +458,22 @@ * on ICH7 when the southbridge is strapped to LPC */ - if (ich_generation == 7 && bbs == ICH_STRAP_LPC) { - buses_supported = CHIP_BUSTYPE_FWH; - /* No further SPI initialization required */ - return ret; - } - - switch (ich_generation) { - case 7: - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH7; - spibar_offset = 0x3020; - break; - case 8: - buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH9; - spibar_offset = 0x3020; - break; - case 9: - case 10: - default: /* Future version might behave the same */ - buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH9; - spibar_offset = 0x3800; - break; - } - - /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ - msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); - - /* Assign Virtual Address */ - ich_spibar = rcrb + spibar_offset; - - switch (spi_controller) { - case SPI_CONTROLLER_ICH7: - msg_pdbg("0x00: 0x%04x (SPIS)\n", - mmio_readw(ich_spibar + 0)); - msg_pdbg("0x02: 0x%04x (SPIC)\n", - mmio_readw(ich_spibar + 2)); - msg_pdbg("0x04: 0x%08x (SPIA)\n", - mmio_readl(ich_spibar + 4)); - for (i = 0; i < 8; i++) { - int offs; - offs = 8 + (i * 8); - msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, - mmio_readl(ich_spibar + offs), i); - msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, - mmio_readl(ich_spibar + offs + 4), i); - } - ichspi_bbar = mmio_readl(ich_spibar + 0x50); - msg_pdbg("0x50: 0x%08x (BBAR)\n", - ichspi_bbar); - msg_pdbg("0x54: 0x%04x (PREOP)\n", - mmio_readw(ich_spibar + 0x54)); - msg_pdbg("0x56: 0x%04x (OPTYPE)\n", - mmio_readw(ich_spibar + 0x56)); - msg_pdbg("0x58: 0x%08x (OPMENU)\n", - mmio_readl(ich_spibar + 0x58)); - msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", - mmio_readl(ich_spibar + 0x5c)); - for (i = 0; i < 4; i++) { - int offs; - offs = 0x60 + (i * 4); - msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, - mmio_readl(ich_spibar + offs), i); - } - msg_pdbg("\n"); - if (mmio_readw(ich_spibar) & (1 << 15)) { - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); - ichspi_lock = 1; - } - ich_init_opcodes(); - break; - case SPI_CONTROLLER_ICH9: - tmp2 = mmio_readw(ich_spibar + 4); - msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); - msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); - msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); - msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); - msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); - msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); - msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); - msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); - msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); - - tmp = mmio_readl(ich_spibar + 0x50); - msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); - msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); - msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); - msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); - msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); - - /* print out the FREGx registers along with FRAP access bits */ - for(i = 0; i < 5; i++) - do_ich9_spi_frap(tmp, i); - - msg_pdbg("0x74: 0x%08x (PR0)\n", - mmio_readl(ich_spibar + 0x74)); - msg_pdbg("0x78: 0x%08x (PR1)\n", - mmio_readl(ich_spibar + 0x78)); - msg_pdbg("0x7C: 0x%08x (PR2)\n", - mmio_readl(ich_spibar + 0x7C)); - msg_pdbg("0x80: 0x%08x (PR3)\n", - mmio_readl(ich_spibar + 0x80)); - msg_pdbg("0x84: 0x%08x (PR4)\n", - mmio_readl(ich_spibar + 0x84)); - msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", - mmio_readl(ich_spibar + 0x90)); - msg_pdbg("0x94: 0x%04x (PREOP)\n", - mmio_readw(ich_spibar + 0x94)); - msg_pdbg("0x96: 0x%04x (OPTYPE)\n", - mmio_readw(ich_spibar + 0x96)); - msg_pdbg("0x98: 0x%08x (OPMENU)\n", - mmio_readl(ich_spibar + 0x98)); - msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", - mmio_readl(ich_spibar + 0x9C)); - ichspi_bbar = mmio_readl(ich_spibar + 0xA0); - msg_pdbg("0xA0: 0x%08x (BBAR)\n", - ichspi_bbar); - msg_pdbg("0xB0: 0x%08x (FDOC)\n", - mmio_readl(ich_spibar + 0xB0)); - if (tmp2 & (1 << 15)) { - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); - ichspi_lock = 1; - } - ich_init_opcodes(); - break; - default: - /* Nothing */ - break; - } - - old = pci_read_byte(dev, 0xdc); - msg_pdbg("SPI Read Configuration: "); - new = (old >> 2) & 0x3; - switch (new) { - case 0: - case 1: - case 2: - msg_pdbg("prefetching %sabled, caching %sabled, ", - (new & 0x2) ? "en" : "dis", - (new & 0x1) ? "dis" : "en"); - break; - default: - msg_pdbg("invalid prefetching/caching settings, "); - break; - } + buses_supported = CHIP_BUSTYPE_FWH; + if (ich_generation == 7) { + if(bbs == ICH_STRAP_LPC) { + /* No further SPI initialization required */ + return ret; + } + else + /* Disable LPC/FWH if strapped to PCI or SPI */ + buses_supported = 0; + } + + /* this adds CHIP_BUSTYPE_SPI */ + if (ich_init_spi(dev, tmp, rcrb, ich_generation) != 0) { + if (!ret) + ret = ERROR_NONFATAL; + } return ret; } @@ -1546,6 +1362,8 @@ msg_pinfo("FAILED!\n"); else if(ret == 0) msg_pinfo("OK.\n"); + else if(ret == ERROR_NONFATAL) + msg_pinfo("PROBLEMS, continuing anyway\n"); } msg_pinfo("This chipset supports the following protocols: %s.\n", Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Thu Jul 22 17:20:43 2010 (r1097) +++ trunk/flash.h Thu Jul 22 20:04:15 2010 (r1098) @@ -607,6 +607,9 @@ #define OK 0 #define NT 1 /* Not tested */ +/* Something happened that shouldn't happen, but we can go on */ +#define ERROR_NONFATAL 0x100 + /* cli_output.c */ /* Let gcc and clang check for correct printf-style format strings. */ int print(int type, const char *fmt, ...) __attribute__((format(printf, 2, 3))); @@ -694,10 +697,10 @@ uint32_t spi_get_valid_read_addr(void); /* ichspi.c */ -extern int ichspi_lock; extern uint32_t ichspi_bbar; -extern void *ich_spibar; -int ich_init_opcodes(void); +int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, + int ich_generation); +int via_init_spi(struct pci_dev *dev); int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Thu Jul 22 17:20:43 2010 (r1097) +++ trunk/ichspi.c Thu Jul 22 20:04:15 2010 (r1098) @@ -101,11 +101,11 @@ #define ICH7_REG_OPMENU 0x58 /* 64 Bits */ /* ICH SPI configuration lock-down. May be set during chipset enabling. */ -int ichspi_lock = 0; +static int ichspi_lock = 0; uint32_t ichspi_bbar = 0; -void *ich_spibar = NULL; +static void *ich_spibar = NULL; typedef struct _OPCODE { uint8_t opcode; //This commands spi opcode @@ -364,7 +364,7 @@ * * It should be called before ICH sends any spi command. */ -int ich_init_opcodes(void) +static int ich_init_opcodes(void) { int rc = 0; OPCODES *curopcodes_done; @@ -863,4 +863,211 @@ return ret; } +#define ICH_BMWAG(x) ((x >> 24) & 0xff) +#define ICH_BMRAG(x) ((x >> 16) & 0xff) +#define ICH_BRWA(x) ((x >> 8) & 0xff) +#define ICH_BRRA(x) ((x >> 0) & 0xff) + +#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) +#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) + +static void do_ich9_spi_frap(uint32_t frap, int i) +{ + const char *access_names[4] = { + "locked", "read-only", "write-only", "read-write" + }; + const char *region_names[5] = { + "Flash Descriptor", "BIOS", "Management Engine", + "Gigabit Ethernet", "Platform Data" + }; + uint32_t base, limit; + int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | + (((ICH_BRRA(frap) >> i) & 1) << 0); + int offset = 0x54 + i * 4; + uint32_t freg = mmio_readl(ich_spibar + offset); + + msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", + offset, freg, i, region_names[i]); + + base = ICH_FREG_BASE(freg); + limit = ICH_FREG_LIMIT(freg); + if (base == 0x1fff && limit == 0) { + /* this FREG is disabled */ + msg_pdbg("%s region is unused.\n", region_names[i]); + return; + } + + msg_pdbg("0x%08x-0x%08x is %s\n", + (base << 12), (limit << 12) | 0x0fff, + access_names[rwperms]); +} + +int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, + int ich_generation) +{ + int i; + uint8_t old, new; + uint16_t spibar_offset, tmp2; + uint32_t tmp; + + buses_supported |= CHIP_BUSTYPE_SPI; + switch (ich_generation) { + case 7: + spi_controller = SPI_CONTROLLER_ICH7; + spibar_offset = 0x3020; + break; + case 8: + spi_controller = SPI_CONTROLLER_ICH9; + spibar_offset = 0x3020; + break; + case 9: + case 10: + default: /* Future version might behave the same */ + spi_controller = SPI_CONTROLLER_ICH9; + spibar_offset = 0x3800; + break; + } + + /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ + msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset); + + /* Assign Virtual Address */ + ich_spibar = rcrb + spibar_offset; + + switch (spi_controller) { + case SPI_CONTROLLER_ICH7: + msg_pdbg("0x00: 0x%04x (SPIS)\n", + mmio_readw(ich_spibar + 0)); + msg_pdbg("0x02: 0x%04x (SPIC)\n", + mmio_readw(ich_spibar + 2)); + msg_pdbg("0x04: 0x%08x (SPIA)\n", + mmio_readl(ich_spibar + 4)); + for (i = 0; i < 8; i++) { + int offs; + offs = 8 + (i * 8); + msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, + mmio_readl(ich_spibar + offs), i); + msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, + mmio_readl(ich_spibar + offs + 4), i); + } + ichspi_bbar = mmio_readl(ich_spibar + 0x50); + msg_pdbg("0x50: 0x%08x (BBAR)\n", + ichspi_bbar); + msg_pdbg("0x54: 0x%04x (PREOP)\n", + mmio_readw(ich_spibar + 0x54)); + msg_pdbg("0x56: 0x%04x (OPTYPE)\n", + mmio_readw(ich_spibar + 0x56)); + msg_pdbg("0x58: 0x%08x (OPMENU)\n", + mmio_readl(ich_spibar + 0x58)); + msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", + mmio_readl(ich_spibar + 0x5c)); + for (i = 0; i < 4; i++) { + int offs; + offs = 0x60 + (i * 4); + msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, + mmio_readl(ich_spibar + offs), i); + } + msg_pdbg("\n"); + if (mmio_readw(ich_spibar) & (1 << 15)) { + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); + ichspi_lock = 1; + } + ich_init_opcodes(); + break; + case SPI_CONTROLLER_ICH9: + tmp2 = mmio_readw(ich_spibar + 4); + msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); + msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); + msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); + msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); + msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); + msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); + msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); + msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); + msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); + + tmp = mmio_readl(ich_spibar + 0x50); + msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); + msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); + msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); + msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); + msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); + + /* print out the FREGx registers along with FRAP access bits */ + for(i = 0; i < 5; i++) + do_ich9_spi_frap(tmp, i); + + msg_pdbg("0x74: 0x%08x (PR0)\n", + mmio_readl(ich_spibar + 0x74)); + msg_pdbg("0x78: 0x%08x (PR1)\n", + mmio_readl(ich_spibar + 0x78)); + msg_pdbg("0x7C: 0x%08x (PR2)\n", + mmio_readl(ich_spibar + 0x7C)); + msg_pdbg("0x80: 0x%08x (PR3)\n", + mmio_readl(ich_spibar + 0x80)); + msg_pdbg("0x84: 0x%08x (PR4)\n", + mmio_readl(ich_spibar + 0x84)); + msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", + mmio_readl(ich_spibar + 0x90)); + msg_pdbg("0x94: 0x%04x (PREOP)\n", + mmio_readw(ich_spibar + 0x94)); + msg_pdbg("0x96: 0x%04x (OPTYPE)\n", + mmio_readw(ich_spibar + 0x96)); + msg_pdbg("0x98: 0x%08x (OPMENU)\n", + mmio_readl(ich_spibar + 0x98)); + msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", + mmio_readl(ich_spibar + 0x9C)); + ichspi_bbar = mmio_readl(ich_spibar + 0xA0); + msg_pdbg("0xA0: 0x%08x (BBAR)\n", + ichspi_bbar); + msg_pdbg("0xB0: 0x%08x (FDOC)\n", + mmio_readl(ich_spibar + 0xB0)); + if (tmp2 & (1 << 15)) { + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); + ichspi_lock = 1; + } + ich_init_opcodes(); + break; + default: + /* Nothing */ + break; + } + + old = pci_read_byte(dev, 0xdc); + msg_pdbg("SPI Read Configuration: "); + new = (old >> 2) & 0x3; + switch (new) { + case 0: + case 1: + case 2: + msg_pdbg("prefetching %sabled, caching %sabled, ", + (new & 0x2) ? "en" : "dis", + (new & 0x1) ? "dis" : "en"); + break; + default: + msg_pdbg("invalid prefetching/caching settings, "); + break; + } + return 0; +} + +int via_init_spi(struct pci_dev *dev) +{ + uint32_t mmio_base; + + mmio_base = (pci_read_long(dev, 0xbc)) << 8; + msg_pdbg("MMIO base at = 0x%x\n", mmio_base); + ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); + + msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", + mmio_readw(ich_spibar + 0x6c)); + + /* Not sure if it speaks all these bus protocols. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_VIA; + ich_init_opcodes(); + + return 0; +} + #endif

1 0

[results of]# flashrom -VV
by Greg Scantlen 22 Jul '10

22 Jul '10

[bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Eon EN25F10, 128 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Eon EN25F20, 256 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Eon EN25F40, 512 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Eon EN25F80, 1024 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Eon EN25F16, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Eon EN25F32, 4096 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Eon EN29F010, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F004BV/BE-B, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F004BV/BE-T, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F400BV/CV/CE-B, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F400BV/CV/CE-T, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX25L1005, 128 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX25L2005, 256 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX25L4005, 512 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX25L8005, 1024 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX25L1605, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX25L1635D, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX25L3205, 4096 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX25L3235D, 4096 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX25L6405, 8192 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX25L12805, 16384 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Numonyx M25PE20, 256 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Numonyx M25PE40, 512 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Numonyx M25PE80, 1024 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Numonyx M25PE16, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for PMC Pm25LV010, 128 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for PMC Pm25LV016B, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for PMC Pm25LV020, 256 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for PMC Pm25LV040, 512 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for PMC Pm25LV080B, 1024 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for PMC Pm25LV512, 64 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm39LV020, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm39LV040, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL008A, 1024 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Spansion S25FL016A, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for SST SST25VF016B, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for SST SST25VF032B, 4096 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for SST SST25VF040.REMS, 512 KB: sb600_spi_send_command, cmd=90, writecnt=3, readcnt=2 [0] [0] [0] [ 0][ 0][ 0]The FIFO pointer after skipping is 0. [00][00] REMS returned 00 00. probe_spi_rems: id1 0x0, id2 0x0 Probing for SST SST25VF040B, 512 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for SST SST25VF040B.REMS, 512 KB: sb600_spi_send_command, cmd=90, writecnt=3, readcnt=2 [0] [0] [0] [ 0][ 0][ 0]The FIFO pointer after skipping is 0. [00][00] REMS returned 00 00. probe_spi_rems: id1 0x0, id2 0x0 Probing for SST SST25VF080B, 1024 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for SST SST28SF040A, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for ST M25P05.RES, 64 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for ST M25P10.RES, 128 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for ST M25P40, 512 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for ST M25P40-old, 512 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for ST M25P16, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for ST M25P32, 4096 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for ST M25P64, 8192 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for ST M25P128, 16384 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for ST M29F002B, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W25Q80, 1024 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Winbond W25Q16, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Winbond W25Q32, 4096 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Winbond W25x10, 128 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Winbond W25x20, 256 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Winbond W25x40, 512 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Winbond W25x80, 1024 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Winbond W25x16, 2048 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Winbond W25x32, 4096 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Winbond W25x64, 8192 KB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Probing for Winbond W29C011, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel unknown Atmel SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Not unmapping zero size at (nil) Probing for EON unknown EON SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Not unmapping zero size at (nil) Probing for Macronix unknown Macronix SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Not unmapping zero size at (nil) Probing for PMC unknown PMC SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Not unmapping zero size at (nil) Probing for SST unknown SST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Found chip "SST unknown SST SPI chip" (0 KB, SPI) at physical address 0x0. Probing for ST unknown ST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Not unmapping zero size at (nil) Probing for Sanyo unknown Sanyo SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Not unmapping zero size at (nil) Probing for Generic unknown SPI chip (RDID), 0 KB: Not mapping flash chip, zero size at 0x00000000. sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=3 The FIFO pointer after skipping is 0. [bf][bf][bf] RDID returned 0xbf 0xbf 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0xbfbf Not unmapping zero size at (nil) Probing for Generic unknown SPI chip (REMS), 0 KB: Not mapping flash chip, zero size at 0x00000000. sb600_spi_send_command, cmd=90, writecnt=3, readcnt=2 [0] [0] [0] [ 0][ 0][ 0]The FIFO pointer after skipping is 0. [00][00] REMS returned 00 00. probe_spi_rems: id1 0x0, id2 0x0 Not unmapping zero size at (nil) === This flash part has status NOT WORKING for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Thanks for your help! === No operations were specified. [root@slinux ~]#

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Re: [flashrom] [PATCH 2/3] Move SB600 SPI initialization to sb600spi.c
by Carl-Daniel Hailfinger 22 Jul '10

22 Jul '10

On 18.07.2010 16:19, Michael Karcher wrote: > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > --- > chipset_enable.c | 79 ++--------------------------------------------------- > flash.h | 2 +- > sb600spi.c | 77 +++++++++++++++++++++++++++++++++++++++++++++++++++- > 3 files changed, 80 insertions(+), 78 deletions(-) > > diff --git a/chipset_enable.c b/chipset_enable.c > index 7434d65..ad3b732 100644 > --- a/chipset_enable.c > +++ b/chipset_enable.c > @@ -683,10 +683,8 @@ static int enable_flash_amd8111(struct pci_dev *dev, const char *name) > > static int enable_flash_sb600(struct pci_dev *dev, const char *name) > { > - uint32_t tmp, prot; > + uint32_t prot; > uint8_t reg; > - struct pci_dev *smbus_dev; > - int has_spi = 1; > > /* Clear ROM protect 0-3. */ > for (reg = 0x50; reg < 0x60; reg += 4) { > @@ -710,80 +708,9 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name) > (prot & 0xfffffc00) + ((prot & 0x3ff) << 8)); > } > > - /* Read SPI_BaseAddr */ > - tmp = pci_read_long(dev, 0xa0); > - tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ > - msg_pdbg("SPI base address is at 0x%x\n", tmp); > - > - /* If the BAR has address 0, it is unlikely SPI is used. */ > - if (!tmp) > - has_spi = 0; > - > - if (has_spi) { > - /* Physical memory has to be mapped at page (4k) boundaries. */ > - sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, > - 0x1000); > - /* The low bits of the SPI base address are used as offset into > - * the mapped page. > - */ > - sb600_spibar += tmp & 0xfff; > - > - tmp = pci_read_long(dev, 0xa0); > - msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " > - "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, > - (tmp & 0x4) >> 2); > - tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; > - msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); > - > - tmp = pci_read_byte(dev, 0xbb); > - msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", > - tmp & 0x1, (tmp & 0x20) >> 5); > - tmp = mmio_readl(sb600_spibar); > - msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " > - "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " > - "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", > - (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, > - (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, > - (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); > - } > - > - /* Look for the SMBus device. */ > - smbus_dev = pci_dev_find(0x1002, 0x4385); > - > - if (has_spi && !smbus_dev) { > - msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); > - has_spi = 0; > - } > - if (has_spi) { > - /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ > - /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ > - reg = pci_read_byte(smbus_dev, 0xAB); > - reg &= 0xC0; > - msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); > - msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); > - if (reg != 0x00) > - has_spi = 0; > - /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ > - reg = pci_read_byte(smbus_dev, 0x83); > - reg &= 0xC0; > - msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); > - msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); > - /* SPI_HOLD is not used on all boards, filter it out. */ > - if ((reg & 0x80) != 0x00) > - has_spi = 0; > - /* GPIO47/SPI_CLK status */ > - reg = pci_read_byte(smbus_dev, 0xA7); > - reg &= 0x40; > - msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); > - if (reg != 0x00) > - has_spi = 0; > - } > - > buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; > - if (has_spi) { > - buses_supported |= CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_SB600; > - } > + > + sb600_probe_spi(dev); > sb600_spi_probe should return an error code which is checked. > > /* Read ROM strap override register. */ > OUTB(0x8f, 0xcd6); > diff --git a/flash.h b/flash.h > index a8ca6d7..8ebea29 100644 > --- a/flash.h > +++ b/flash.h > @@ -702,11 +702,11 @@ int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int > int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* sb600spi.c */ > +void sb600_probe_spi(struct pci_dev * dev); > space after * > int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr); > int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > -extern uint8_t *sb600_spibar; > > /* wbsio_spi.c */ > int wbsio_check_for_spi(void); > diff --git a/sb600spi.c b/sb600spi.c > index caf1a99..e42b20b 100644 > --- a/sb600spi.c > +++ b/sb600spi.c > @@ -40,7 +40,82 @@ > *}; > */ > > -uint8_t *sb600_spibar = NULL; > +static uint8_t *sb600_spibar = NULL; > + > +void sb600_probe_spi(struct pci_dev * dev) > please make it return int, and kill the space after * > +{ > + struct pci_dev *smbus_dev; > + uint32_t tmp; > + uint8_t reg; > + /* Read SPI_BaseAddr */ > + tmp = pci_read_long(dev, 0xa0); > + tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ > + msg_pdbg("SPI base address is at 0x%x\n", tmp); > + > + /* If the BAR has address 0, it is unlikely SPI is used. */ > + if (!tmp) > + return; > that would be return 0 > + > + /* Physical memory has to be mapped at page (4k) boundaries. */ > + sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, > + 0x1000); > + /* The low bits of the SPI base address are used as offset into > + * the mapped page. > + */ > + sb600_spibar += tmp & 0xfff; > + > + tmp = pci_read_long(dev, 0xa0); > + msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " > + "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, > + (tmp & 0x4) >> 2); > + tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; > + msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); > + > + tmp = pci_read_byte(dev, 0xbb); > + msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", > + tmp & 0x1, (tmp & 0x20) >> 5); > + tmp = mmio_readl(sb600_spibar); > + msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " > + "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " > + "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", > + (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, > + (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, > + (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); > + > + /* Look for the SMBus device. */ > + smbus_dev = pci_dev_find(0x1002, 0x4385); > + > + if (!smbus_dev) { > + msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); > + return; > And this should be an error return. Do we want some define for ERROR_NONFATAL and make it some otherwise unusued value? Maybe 0x100 or something? > + } > + > + /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ > + /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ > + reg = pci_read_byte(smbus_dev, 0xAB); > + reg &= 0xC0; > + msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); > + msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); > + if (reg != 0x00) > + return; > Not an error, just a sign that SPI is not used. return 0; > + /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ > + reg = pci_read_byte(smbus_dev, 0x83); > + reg &= 0xC0; > + msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); > + msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); > + /* SPI_HOLD is not used on all boards, filter it out. */ > + if ((reg & 0x80) != 0x00) > + return; > return 0; > + /* GPIO47/SPI_CLK status */ > + reg = pci_read_byte(smbus_dev, 0xA7); > + reg &= 0x40; > + msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); > + if (reg != 0x00) > + return; > return 0; > + > + buses_supported |= CHIP_BUSTYPE_SPI; > + spi_controller = SPI_CONTROLLER_SB600; > +} > > int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > Looks good otherwise. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Intel SE440BX
by Mattias Mattsson 22 Jul '10

22 Jul '10

Hi, I'm trying latest flashrom (r1082) an an Intel SE440BX. No flashchip is detected. I also tried to reuse the SE440BX-2 board enable but couldn't make it work. The flash on the board is an Intel E28F002BC-T80. Datasheet here: http://www.ezoflash.com/datasheets/flash/Intel/28F002BC.pdf I would like to add the chip to flashchips.c but was unsure how to interpret the datasheet and the corresponding values for probe/read/write function. Logs attached -mattias

4 5

[commit] r1097 - trunk
by repository service 22 Jul '10

22 Jul '10

Author: hailfinger Date: Thu Jul 22 17:20:43 2010 New Revision: 1097 URL: http://flashrom.org/trac/coreboot/changeset/1097 Log: Add support for the Intel 28F002BC-T. Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Thu Jul 22 13:44:38 2010 (r1096) +++ trunk/flashchips.c Thu Jul 22 17:20:43 2010 (r1097) @@ -2814,6 +2814,33 @@ { .vendor = "Intel", + .name = "28F002BC-T", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = INTEL_ID, + .model_id = P28F002BC, + .total_size = 256, + .page_size = 256 * 1024, + .tested = TEST_UNTESTED, + .probe = probe_82802ab, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .block_erasers = + { + { + .eraseblocks = { + {128 * 1024, 1}, + {96 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_block_82802ab, + }, + }, + .write = write_82802ab, + .read = read_memmapped, + }, + + { + .vendor = "Intel", .name = "28F004S5", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Thu Jul 22 13:44:38 2010 (r1096) +++ trunk/flashchips.h Thu Jul 22 17:20:43 2010 (r1097) @@ -274,6 +274,7 @@ #define E_28F016S5 0xAA #define P28F001BXT 0x94 /* 28F001BX-T */ #define P28F001BXB 0x95 /* 28F001BX-B */ +#define P28F002BC 0x7C /* 28F002BC-T */ #define P28F004BT 0x78 /* 28F004BV/BE-T */ #define P28F004BB 0x79 /* 28F004BV/BE-B */ #define P28F400BT 0x70 /* 28F400BV/CV/CE-T */

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flashrom July 2010