flashrom February 2010

flashrom@flashrom.org

55 participants
173 discussions

Re: [flashrom] [commit] r885 - trunk
by Luc Verhaegen 04 Feb '10

04 Feb '10

On Thu, Jan 28, 2010 at 08:02:37PM +0100, svn(a)flashrom.org wrote: > Author: uwe > Date: 2010-01-28 20:02:36 +0100 (Thu, 28 Jan 2010) > New Revision: 885 > > Modified: > trunk/board_enable.c > Log: > The GIGABYTE GA-7ZM has a maximum decode size (parallel chips) of 512 KB. > > Add this information to the new field in the board-enable table. We match the > board via two sets of PCI IDs. However, as we don't need a board-enable > function for this board (… [View More]it works out of the box; well, at least if you remove > the JP9 jumper on the board), change the code to allow NULL as value for > the board-enable function. There will likely be more boards in the future where > we want to record a maximum decode size but which don't need a board-enable. > > This is hardware-tested on the GIGABYTE GA-7ZM by successfully writing a 512KB > image of random bytes to a chip in this board. > > Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> > Acked-by: Sean Nelson <audiohacked(a)gmail.com> > > > > Modified: trunk/board_enable.c > =================================================================== > --- trunk/board_enable.c 2010-01-27 10:08:33 UTC (rev 884) > +++ trunk/board_enable.c 2010-01-28 19:02:36 UTC (rev 885) > @@ -1208,6 +1208,7 @@ > {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, w836xx_memw_enable_2e}, > {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, nvidia_mcp_gpio31_raise}, > {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, board_epox_ep_bx3}, > + {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, NULL}, > {0x1039, 0x0761, 0, 0, 0x10EC, 0x8168, 0, 0, NULL, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", 0, it87xx_probe_spi_flash}, > {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, NULL, "GIGABYTE", "GA-7VT600", 0, it8705f_write_enable_2e}, > {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, nvidia_mcp_gpio21_raise}, http://www.google.de/#q=1106%3A0686+1106%3A0686+1106%3A3058+1458%3Aa000&aq=… reveals that there are at least two different boards which matches this. You are only matching the southbridge here, and a relatively bogus (and common) subsystem id, which only tells us that it's a gigabyte board. The VT82C686 was a _hugely_ successful southbridge. I cannot even begin to count how many gigabyte boards use this chipset. So, first; swap the pairs around. Second, use 0x1106, 0x0305, 0, 0 to at least narrow the northbridge down. A further check on the gigabyte gives me 17 possible combinations of the different kt133 variations and the 686 southbridge. This makes it completely impossible to even consider the above change a sufficient match. Please provide the output of flashrom -V so we can identify a DMI match. The above logic should give you some idea of the investigation required to get a good match. It just takes a few minutes to do so too. Luc Verhaegen. [View Less]

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[commit] r887 - trunk
by repository service 04 Feb '10

04 Feb '10

Author: uwe Date: Sun Jan 31 21:13:06 2010 New Revision: 887 URL: http://flashrom.org/trac/coreboot/changeset/887 Log: Add the Tekram P6Pro-A5 board as supported (trivial). The board doesn't need a board-enable, writing works out of the box. Also, the board can only decode 256KB. I verified this by writing a 512KB image of random bytes (which fails), whereas 256KB of random bytes can be written correctly. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(… [View More]a)hermann-uwe.de> Modified: trunk/board_enable.c trunk/print_wiki.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Fri Jan 29 00:55:12 2010 (r886) +++ trunk/board_enable.c Sun Jan 31 21:13:06 2010 (r887) @@ -1235,6 +1235,7 @@ {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, board_soyo_sy_7vca}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, w836xx_memw_enable_2e}, + {0x1106, 0x3038, 0x0925, 0x1234, 0, 0, 0, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, NULL}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, via_vt823x_gpio9_raise}, {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, NULL, NULL, NULL, "VIA", "PC3500G", 0, it87xx_probe_spi_flash}, Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Fri Jan 29 00:55:12 2010 (r886) +++ trunk/print_wiki.c Sun Jan 31 21:13:06 2010 (r887) @@ -167,6 +167,7 @@ { "RCA", "RM4100", "http://www.settoplinux.org/index.php?title=RCA_RM4100" }, { "Sun", "Blade x6250", "http://www.sun.com/servers/blades/x6250/" }, { "Supermicro", "H8QC8", "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm" }, + { "Tekram", "P6Pro-A5", "http://www.motherboard.cz/mb/tekram/P6Pro-A5.htm" }, { "Thomson", "IP1000", "http://www.settoplinux.org/index.php?title=Thomson_IP1000" }, { "TriGem", "Lomita", "http://www.e4allupgraders.info/dir1/motherboards/socket370/lomita.shtml" }, { "T-Online", "S-100", "http://wiki.freifunk-hannover.de/T-Online_S_100" }, [View Less]

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[commit] r890 - trunk
by repository service 04 Feb '10

04 Feb '10

Author: uwe Date: Thu Feb 4 03:40:16 2010 New Revision: 890 URL: http://flashrom.org/trac/coreboot/changeset/890 Log: Add a second set of PCI IDs for the Tekram P6Pro-A5 (trivial). (Re-)tested on hardware, detection works OK. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/… [View More]

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ANNOUNCE: flashrom 0.9.1 is out
by Carl-Daniel Hailfinger 03 Feb '10

03 Feb '10

After many months of testing, and 5 months after tagging the release, we are happy to announce that flashrom 0.9.1 is ready for your machines. flashrom is a utility for reading, writing, erasing and verifying flash ROM chips on mainboards, SATA/network controller cards and external programmers. flashrom is often used to flash BIOS/EFI/coreboot/firmware images because it allows you to update your BIOS/EFI/coreboot/firmware without opening the computer and without any special boot procedures. … [View More]After nine years of development and constant improvement, we have added support for every BIOS flash ROM technology present on x86 mainboards and every flash ROM chip we ever saw in the wild. Highlights of flashrom include: * Parallel, LPC, FWH and SPI flash interfaces. * Support for on-mainboard programming and external programmers. * 192 flash chip families and half a dozen variants of each family. * Flash chip package agnostic. DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, TSOP40 and more have all been verified to work. * 78 different chipsets, some with multiple flash controllers. * Special mainboard enabling code for dozens of nonstandard mainboards. * No physical access needed. root access is sufficient. * No bootable floppy disk, bootable CD-ROM or other media needed. * No keyboard or monitor needed. Simply reflash remotely via SSH. * No instant reboot needed. Reflash your ROM in a running system, verify it, be happy. The new firmware will be present next time you boot. * Crossflashing and hotflashing is possible as long as the flash chips are electrically and logically compatible (same protocol). Great for recovery. * Scriptability. Reflash a whole pool of identical machines at the same time from the command line. It is recommended to check flashrom output and error codes. * Speed. flashrom is much faster than vendor flash tools. * Supports Linux, FreeBSD, DragonFly BSD, Nexenta, Solaris, Mac OS X. Please refer to the README for build instructions. Thanks go to everyone who contributed to flashrom over the years. Please note that rewriting your flash chip can be dangerous and flashrom developers make no guarantees whatsoever. That said, many users have successfully replaced proprietary tools such as awdflash, amiflash and afudos with flashrom. If you have a laptop, we advise against using flashrom for now. Many laptops share their flash chip between the main CPU and an undocumented embedded controller which may crash the machine during flashing. This will be addressed once we manage to get docs for those embedded controllers. flashrom has its own home page at http://www.flashrom.org/ You can see a list of downloads at http://www.flashrom.org/Downloads New major user-visible features include: * 3Com NICs flashing * Silicon Image SATA controller flashing * ITE IT87* SuperI/O SPI flashing * FT2232H/FT4232H based SPI external programmer support * Universal external programmer protocol * AVR based external programmer support attached via serial line * Dummy flasher driver to trace execution * Automatic write/erase verification * Dozens of added flash chips * Support for new chipsets * Support for new boards * Fast bus type dependent probing * No root privileges needed for most external flashers Infrastructural improvements and fixes: * External flasher infrastructure * Improved SPI abstraction * SPI multicommand infrastructure * Partial read support infrastructure * Accurate timing information for probing * Tarball export target * User interface cleanup * Block protection printing for more chips * Probing accuracy improvements for old SPI chips on ICH * MMIO abstraction layer * Chip access abstraction layer * More intelligent error handling for ICH/VIA SPI * Fix corner case SB600 SPI hangs on non-SPI boards * Downgrade to byte program for certain chip families because they don't support page program * Detection of no-ID responses from chips * Elan SC520 runtime detection * 100x speedup for writes to some SPI chips * Improved error messages * Correctness fixes * Various workarounds for broken hardware * Code cleanups [View Less]

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Error reading Winbond W25x16 on Intel DX48BT2
by Finnbarr Murphy 03 Feb '10

03 Feb '10

Greetings, Here is a failure report against an Intel DX48BT2 motherboard which uses a ICH9R and a Winbond W25x16 containing the BIOS. Command I executed was: ./flashrom -c W25x16 -rV out.bin flashrom v0.9.1-r889 No coreboot table found. DMI string 0: " " DMI string 1: " " DMI string 2: " " DMI string 3: "Intel Corporation" DMI string 4: "DX48BT2" DMI string 5: "AAE26191-205" Found chipset "Intel ICH9R", … [View More]enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0xa tried to set 0xdc to 0xb on ICH9R failed (WARNING ONLY) Root Complex Register Block address = 0xfed1c000 GCS = 0x171464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) FLOCKDN 1, FDV 1, FDOPSS 1, SCIP 0, BERASE 1, AEL 0, FCERR 0, FDONE 0 0x50: 0x00001a1b (FRAP) BMWAG 0, BMRAG 0, BRWA 26, BRRA 27 0x54: 0x00000000 (FREG0) 0x58: 0x01ff003a (FREG1) 0x5C: 0x00390003 (FREG2) 0x60: 0x00020001 (FREG3) 0x64: 0x00000fff (FREG4) 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0x00420004 (SSFS, SSFC) 0x94: 0x0006 (PREOP) 0x96: 0x00f0 (OPTYPE) 0x98: 0x2002009f (OPMENU) 0x9C: 0x00000000 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xB0: 0x00000000 (FDOC) WARNING: SPI Configuration Lockdown activated. Generating OPCODES... done SPI Read Configuration: prefetching enabled, caching enabled, FAILED! This chipset supports the following protocols: FWH,SPI. Calibrating delay loop... 805M loops per second, 100 myus = 199 us. OK. Probing for Winbond W25x16, 2048 KB: RDID returned 0xef 0x30 0x15. probe_spi_rdid_generic: id1 0xef, id2 0x3015 Invalid OPCODE 0x05 Chip status register is 0a Found chip "Winbond W25x16" (2048 KB, SPI) at physical address 0xffe00000. === This flash part has status UNTESTED for operations: ERASE WRITE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === Reading flash... Invalid OPCODE 0x03 done. Any idea what is going on? According to the W25x16 documentation opcodes 0x03 and 0x05 are supported. OS is Fedora 12. - Finnbarr P. Murphy [View Less]

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SST SST49LF080A status report - TEST_OK_PR
by Peter Lemenkov 03 Feb '10

03 Feb '10

Hello All! Here are various logs for this chip. Flashrom successfully detects chipset and flash-chip and reads bios image, which was later processed by bios_extract. Unfortunately, I don't know too much about this board, except what can be read from dmidecode, because I've got only ssh access on it. -- With best regards, Peter Lemenkov. Sent from Moscow, Mow, Russia

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Write the second flash device
by Piotr Piwko 03 Feb '10

03 Feb '10

Hello, Does flashrom support writing the second flash devices connected to LPC bus? In my system I have one built-in flash device and the second one which is connected to the same LPC bus. I can also change device ID[3:0] pins, so I'm able to choose from which flash the system should be run. In this case I would like to write the flash device which is not bootable, but unfortunately the flashrom application detects only the boot device (under 0xFFF0 0000) - no matter from which flash device … [View More]

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[PATCH] Handle denied access to cbtable gracefuly
by Carl-Daniel Hailfinger 02 Feb '10

02 Feb '10

Stefan: Could you please test this one on Mac OS X? In theory it should even allow us to kill the start=0x400 special case for Mac OS X. Create a physical memory mapping function which requests cached readonly memory. This should take care of picky Linux kernels which do not allow uncached mappings to cached areas. Handle mapping failure gracefully (no forced exit()) if the caller specifies it. Such cached areas which can handle mapping failure are DMI tables and coreboot tables. On retry and … [View More]repeated failure we just ignore those tables. That is not perfect, but a lot better than aborting flashrom due to an error in nonessential functionality. This should fix flashrom on a sizable number of machines where it currently aborts early. Yes, I could have exploited a Linux kernel bug to "solve" this, but relying on such bugs is not exactly the best idea. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-physmap_graceful_error_cbtable/flash.h =================================================================== --- flashrom-physmap_graceful_error_cbtable/flash.h (Revision 886) +++ flashrom-physmap_graceful_error_cbtable/flash.h (Arbeitskopie) @@ -343,6 +343,7 @@ /* physmap.c */ void *physmap(const char *descr, unsigned long phys_addr, size_t len); +void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len); void physunmap(void *virt_addr, size_t len); int setup_cpu_msr(int cpu); void cleanup_cpu_msr(void); Index: flashrom-physmap_graceful_error_cbtable/physmap.c =================================================================== --- flashrom-physmap_graceful_error_cbtable/physmap.c (Revision 886) +++ flashrom-physmap_graceful_error_cbtable/physmap.c (Arbeitskopie) @@ -3,6 +3,7 @@ * * Copyright (C) 2009 Peter Stuge <peter(a)stuge.se> * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -36,6 +37,10 @@ return map_physical(phys_addr, len); } +/* The OS X driver does not differentiate between mapping types. */ +#define sys_physmap_rw_uncached sys_physmap +#define sys_physmap_ro_cached sys_physmap + void physunmap(void *virt_addr, size_t len) { unmap_physical(virt_addr, len); @@ -51,8 +56,10 @@ #endif static int fd_mem = -1; +static int fd_mem_cached = -1; -void *sys_physmap(unsigned long phys_addr, size_t len) +/* For MMIO access. Must be uncached, doesn't make sense to restrict to ro. */ +void *sys_physmap_rw_uncached(unsigned long phys_addr, size_t len) { void *virt_addr; @@ -69,6 +76,26 @@ return MAP_FAILED == virt_addr ? NULL : virt_addr; } +/* For reading DMI/coreboot/whatever tables. We should never write, and we + * do not care about caching. + */ +void *sys_physmap_ro_cached(unsigned long phys_addr, size_t len) +{ + void *virt_addr; + + if (-1 == fd_mem_cached) { + /* Open the memory device CACHED. */ + if (-1 == (fd_mem_cached = open(MEM_DEV, O_RDWR))) { + perror("Critical error: open(" MEM_DEV ")"); + exit(2); + } + } + + virt_addr = mmap(0, len, PROT_READ, MAP_SHARED, + fd_mem_cached, (off_t)phys_addr); + return MAP_FAILED == virt_addr ? NULL : virt_addr; +} + void physunmap(void *virt_addr, size_t len) { if (len == 0) { @@ -80,7 +107,12 @@ } #endif -void *physmap(const char *descr, unsigned long phys_addr, size_t len) +#define PHYSMAP_NOFAIL 0 +#define PHYSMAP_MAYFAIL 1 +#define PHYSMAP_RW 0 +#define PHYSMAP_RO 1 + +void *physmap_common(const char *descr, unsigned long phys_addr, size_t len, int mayfail, int readonly) { void *virt_addr; @@ -100,7 +132,11 @@ descr, (unsigned long)len, phys_addr); } - virt_addr = sys_physmap(phys_addr, len); + if (readonly) { + virt_addr = sys_physmap_ro_cached(phys_addr, len); + } else { + virt_addr = sys_physmap_rw_uncached(phys_addr, len); + } if (NULL == virt_addr) { if (NULL == descr) @@ -114,12 +150,23 @@ fprintf(stderr, "You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n"); fprintf(stderr, "disabling the other option unfortunately requires a kernel recompile. Sorry!\n"); } - exit(3); + if (!mayfail) + exit(3); } return virt_addr; } +void *physmap(const char *descr, unsigned long phys_addr, size_t len) +{ + return physmap_common(descr, phys_addr, len, PHYSMAP_NOFAIL, PHYSMAP_RW); +} + +void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len) +{ + return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO); +} + #ifdef __linux__ /* * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr, Index: flashrom-physmap_graceful_error_cbtable/cbtable.c =================================================================== --- flashrom-physmap_graceful_error_cbtable/cbtable.c (Revision 886) +++ flashrom-physmap_graceful_error_cbtable/cbtable.c (Arbeitskopie) @@ -6,6 +6,7 @@ * (Written by Eric Biederman <ebiederman(a)lnxi.com> for Linux Networx) * Copyright (C) 2006-2009 coresystems GmbH * (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) + * Copyright (C) 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -194,24 +195,36 @@ #define BYTES_TO_MAP (1024*1024) int coreboot_init(void) { - uint8_t *table_area; + uint8_t *table_area = NULL; unsigned long addr, start; - struct lb_header *lb_table; + struct lb_header *lb_table = NULL; struct lb_record *rec, *last; #ifdef __DARWIN__ /* This is a hack. DirectIO fails to map physical address 0x00000000. * Why? + * FIXME: This hack should be unnecessary with the low megabyte retries. */ start = 0x400; #else start = 0x0; #endif - table_area = physmap("low megabyte", start, BYTES_TO_MAP); + table_area = physmap_try_ro("low megabyte", start, BYTES_TO_MAP - start); + while (!table_area) { + msg_pinfo("Trying a smaller mapping.\n"); + start += 0x400; + /* Outside lower 1 MB? Abort. */ + if (start > 0x100000) { + msg_perr("Failed getting access to low megabyte. " + "Ignoring any coreboot tables.\n"); + return -1; + } + table_area = physmap_try_ro("low megabyte", start, BYTES_TO_MAP - start); + } lb_table = find_lb_table(table_area, 0x00000, 0x1000); if (!lb_table) - lb_table = find_lb_table(table_area, 0xf0000, BYTES_TO_MAP); + lb_table = find_lb_table(table_area, 0xf0000 - start, BYTES_TO_MAP - start); if (lb_table) { struct lb_forward *forward = (struct lb_forward *) (((char *)lb_table) + lb_table->header_bytes); @@ -219,7 +232,12 @@ start = forward->forward; start &= ~(getpagesize() - 1); physunmap(table_area, BYTES_TO_MAP); - table_area = physmap("high tables", start, BYTES_TO_MAP); + table_area = physmap_try_ro("high tables", start, BYTES_TO_MAP); + if (!table_area) { + msg_perr("Failed getting access to coreboot " + "high tables.\n"); + return -1; + } lb_table = find_lb_table(table_area, 0x00000, 0x1000); } } -- Developer quote of the year: "We are juggling too many chainsaws and flaming arrows and tigers." [View Less]

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[commit] r889 - trunk
by repository service 02 Feb '10

02 Feb '10

Author: hailfinger Date: Tue Feb 2 12:09:03 2010 New Revision: 889 URL: http://flashrom.org/trac/coreboot/changeset/889 Log: Create a physical memory mapping function which requests cached readonly memory. This should take care of picky Linux kernels which do not allow uncached mappings to cached areas. Handle mapping failure gracefully (no forced exit()) if the caller specifies it. Such cached areas which can handle mapping failure are DMI tables and coreboot tables. On failure we just … [View More]ignore those tables. That is not perfect, but a lot better than aborting flashrom due to an error in nonessential functionality. This should fix flashrom on a sizable number of machines where it currently aborts early. Yes, I could have exploited a Linux kernel bug to "solve" this, but relying on such bugs is not exactly the best idea. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Vincent Pelletier <plr.vincent(a)gmail.com> Modified: trunk/cbtable.c trunk/flash.h trunk/physmap.c Modified: trunk/cbtable.c ============================================================================== --- trunk/cbtable.c Mon Feb 1 06:49:46 2010 (r888) +++ trunk/cbtable.c Tue Feb 2 12:09:03 2010 (r889) @@ -6,6 +6,7 @@ * (Written by Eric Biederman <ebiederman(a)lnxi.com> for Linux Networx) * Copyright (C) 2006-2009 coresystems GmbH * (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) + * Copyright (C) 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -207,11 +208,15 @@ #else start = 0x0; #endif - table_area = physmap("low megabyte", start, BYTES_TO_MAP); + table_area = physmap_try_ro("low megabyte", start, BYTES_TO_MAP - start); + if (!table_area) { + msg_perr("Failed getting access to coreboot low tables.\n"); + return -1; + } lb_table = find_lb_table(table_area, 0x00000, 0x1000); if (!lb_table) - lb_table = find_lb_table(table_area, 0xf0000, BYTES_TO_MAP); + lb_table = find_lb_table(table_area, 0xf0000 - start, BYTES_TO_MAP - start); if (lb_table) { struct lb_forward *forward = (struct lb_forward *) (((char *)lb_table) + lb_table->header_bytes); @@ -219,7 +224,12 @@ start = forward->forward; start &= ~(getpagesize() - 1); physunmap(table_area, BYTES_TO_MAP); - table_area = physmap("high tables", start, BYTES_TO_MAP); + table_area = physmap_try_ro("high tables", start, BYTES_TO_MAP); + if (!table_area) { + msg_perr("Failed getting access to coreboot " + "high tables.\n"); + return -1; + } lb_table = find_lb_table(table_area, 0x00000, 0x1000); } } Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Mon Feb 1 06:49:46 2010 (r888) +++ trunk/flash.h Tue Feb 2 12:09:03 2010 (r889) @@ -343,6 +343,7 @@ /* physmap.c */ void *physmap(const char *descr, unsigned long phys_addr, size_t len); +void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len); void physunmap(void *virt_addr, size_t len); int setup_cpu_msr(int cpu); void cleanup_cpu_msr(void); Modified: trunk/physmap.c ============================================================================== --- trunk/physmap.c Mon Feb 1 06:49:46 2010 (r888) +++ trunk/physmap.c Tue Feb 2 12:09:03 2010 (r889) @@ -3,6 +3,7 @@ * * Copyright (C) 2009 Peter Stuge <peter(a)stuge.se> * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -36,6 +37,10 @@ return map_physical(phys_addr, len); } +/* The OS X driver does not differentiate between mapping types. */ +#define sys_physmap_rw_uncached sys_physmap +#define sys_physmap_ro_cached sys_physmap + void physunmap(void *virt_addr, size_t len) { unmap_physical(virt_addr, len); @@ -51,8 +56,10 @@ #endif static int fd_mem = -1; +static int fd_mem_cached = -1; -void *sys_physmap(unsigned long phys_addr, size_t len) +/* For MMIO access. Must be uncached, doesn't make sense to restrict to ro. */ +void *sys_physmap_rw_uncached(unsigned long phys_addr, size_t len) { void *virt_addr; @@ -69,6 +76,26 @@ return MAP_FAILED == virt_addr ? NULL : virt_addr; } +/* For reading DMI/coreboot/whatever tables. We should never write, and we + * do not care about caching. + */ +void *sys_physmap_ro_cached(unsigned long phys_addr, size_t len) +{ + void *virt_addr; + + if (-1 == fd_mem_cached) { + /* Open the memory device CACHED. */ + if (-1 == (fd_mem_cached = open(MEM_DEV, O_RDWR))) { + perror("Critical error: open(" MEM_DEV ")"); + exit(2); + } + } + + virt_addr = mmap(0, len, PROT_READ, MAP_SHARED, + fd_mem_cached, (off_t)phys_addr); + return MAP_FAILED == virt_addr ? NULL : virt_addr; +} + void physunmap(void *virt_addr, size_t len) { if (len == 0) { @@ -80,7 +107,12 @@ } #endif -void *physmap(const char *descr, unsigned long phys_addr, size_t len) +#define PHYSMAP_NOFAIL 0 +#define PHYSMAP_MAYFAIL 1 +#define PHYSMAP_RW 0 +#define PHYSMAP_RO 1 + +void *physmap_common(const char *descr, unsigned long phys_addr, size_t len, int mayfail, int readonly) { void *virt_addr; @@ -100,7 +132,11 @@ descr, (unsigned long)len, phys_addr); } - virt_addr = sys_physmap(phys_addr, len); + if (readonly) { + virt_addr = sys_physmap_ro_cached(phys_addr, len); + } else { + virt_addr = sys_physmap_rw_uncached(phys_addr, len); + } if (NULL == virt_addr) { if (NULL == descr) @@ -114,12 +150,23 @@ fprintf(stderr, "You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n"); fprintf(stderr, "disabling the other option unfortunately requires a kernel recompile. Sorry!\n"); } - exit(3); + if (!mayfail) + exit(3); } return virt_addr; } +void *physmap(const char *descr, unsigned long phys_addr, size_t len) +{ + return physmap_common(descr, phys_addr, len, PHYSMAP_NOFAIL, PHYSMAP_RW); +} + +void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len) +{ + return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO); +} + #ifdef __linux__ /* * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr, [View Less]

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flashrom February 2010