flashrom November 2010

flashrom@flashrom.org

58 participants
146 discussions

Success report: Tyan S2723
by Uwe Hermann 19 Jun '11

19 Jun '11

Hi, I tested flashrom on the Tyan S2723 board, works fine. Logs attached. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[PATCH][FIXME] Add missing Intel/VIA chipset IDs
by Carl-Daniel Hailfinger 13 Jun '11

13 Jun '11

This patch is unfinished, and _you_ can finish it! Reorder chipset entries by PCI ID instead of by name. Makes it easier to keep track of what's already there. Add VIA VX855. Add countless Intel IDs (unfinished). If you have some spare time, please take a look at all the new Intel entries which have no name and no chipset enable function. They all represent LPC bridges I found in the PCI ID database. Intel may have deleted the names for some of the IDs in the database because these chips were "Engineering samples", but I know of at least one engineering sample which was used in production boards. You can add a comment to the entry or use a name that contains "ICH... Engineering Sample". Your choice. Patch does not compile because the Intel entries are unfinished. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-chipset_support_intel_via/chipset_enable.c =================================================================== --- flashrom-chipset_support_intel_via/chipset_enable.c (Revision 987) +++ flashrom-chipset_support_intel_via/chipset_enable.c (Arbeitskopie) @@ -1285,69 +1285,51 @@ return 0; } -/* Please keep this list alphabetically sorted by vendor/device. */ +/* Please keep this list numerically sorted by vendor/device. */ const struct penable chipset_enables[] = { - {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, + {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400}, + {0x1002, 0x438d, OK, "AMD", "SB600", enable_flash_sb600}, + {0x1002, 0x439d, OK, "AMD", "SB700/SB710/SB750", enable_flash_sb600}, + {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100}, + {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536}, + {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536}, + {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, + {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501}, + {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496}, + {0x1039, 0x0530, NT, "SiS", "530", enable_flash_sis530}, + {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540}, + {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530}, + {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis540}, + {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540}, + {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540}, + {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540}, + {0x1039, 0x0646, NT, "SiS", "645DX", enable_flash_sis540}, + {0x1039, 0x0648, NT, "SiS", "648", enable_flash_sis540}, + {0x1039, 0x0650, NT, "SiS", "650", enable_flash_sis540}, + {0x1039, 0x0651, NT, "SiS", "651", enable_flash_sis540}, + {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540}, + {0x1039, 0x0730, NT, "SiS", "730", enable_flash_sis540}, + {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540}, + {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540}, + {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540}, + {0x1039, 0x0745, NT, "SiS", "745", enable_flash_sis540}, + {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540}, + {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540}, + {0x1039, 0x0755, NT, "SiS", "755", enable_flash_sis540}, + {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511}, + {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530}, + {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530}, + {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5511}, + {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530}, + {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530}, {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530}, - {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536}, - {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536}, - {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, - {0x1002, 0x438D, OK, "AMD", "SB600", enable_flash_sb600}, - {0x1002, 0x439d, OK, "AMD", "SB700/SB710/SB750", enable_flash_sb600}, - {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100}, - {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400}, - {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, - {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_ich10}, - {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_ich10}, - {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_ich10}, - {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4}, - {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e}, - {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc}, - {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7}, - {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e}, - {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10}, - {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10}, - {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10}, - {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10}, - {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e}, - {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich_4e}, - {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich_4e}, - {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich_4e}, - {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich_4e}, - {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich_4e}, - {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich_4e}, - {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich_dc}, - {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich_dc}, - {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7}, - {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7}, - {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7}, - {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7}, - {0x8086, 0x27bc, OK, "Intel", "NM10", enable_flash_ich7}, - {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e}, - {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8}, - {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8}, - {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8}, - {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8}, - {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8}, - {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9}, - {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9}, - {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9}, - {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9}, - {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9}, - {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9}, - {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9}, - {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, - {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, - {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, - {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, - {0x8086, 0x8119, OK, "Intel", "Poulsbo", enable_flash_poulsbo}, + {0x10b9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2}, {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */ {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */ {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2}, - /* Slave, should not be here, to fix known bug for A01. */ {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804}, {0x10de, 0x0260, NT, "NVIDIA", "MCP51", enable_flash_ck804}, {0x10de, 0x0261, NT, "NVIDIA", "MCP51", enable_flash_ck804}, @@ -1377,46 +1359,105 @@ {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp7x}, {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp7x}, {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp7x}, - {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496}, - {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501}, - {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511}, - {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5511}, - {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530}, - {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530}, - {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530}, - {0x1039, 0x0530, NT, "SiS", "530", enable_flash_sis530}, - {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530}, - {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530}, - {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540}, - {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis540}, - {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540}, - {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540}, - {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540}, - {0x1039, 0x0646, NT, "SiS", "645DX", enable_flash_sis540}, - {0x1039, 0x0648, NT, "SiS", "648", enable_flash_sis540}, - {0x1039, 0x0650, NT, "SiS", "650", enable_flash_sis540}, - {0x1039, 0x0651, NT, "SiS", "651", enable_flash_sis540}, - {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540}, - {0x1039, 0x0730, NT, "SiS", "730", enable_flash_sis540}, - {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540}, - {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540}, - {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540}, - {0x1039, 0x0745, NT, "SiS", "745", enable_flash_sis540}, - {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540}, - {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540}, - {0x1039, 0x0755, NT, "SiS", "755", enable_flash_sis540}, - {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x}, - {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x}, + {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, + {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, + {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, {0x1106, 0x3074, NT, "VIA", "VT8233", enable_flash_vt823x}, {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x}, {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x}, {0x1106, 0x3227, OK, "VIA", "VT8237", enable_flash_vt823x}, {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x}, {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi}, - {0x1106, 0x8353, OK, "VIA", "VX800", enable_flash_vt8237s_spi}, - {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, - {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, - {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, + {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x}, + {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x}, + {0x1106, 0x8353, OK, "VIA", "VX800/VX820", enable_flash_vt8237s_spi}, + {0x1106, 0x8409, NT, "VIA", "VX855/VX875", enable_flash_vt8237s_spi}, + {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, + {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, + {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, + {0x8086, 0x1c42, NT, "Intel", "", enable_flash_}, + {0x8086, 0x1c43, NT, "Intel", "", enable_flash_}, + {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e}, + {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e}, + {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e}, + {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich_4e}, + {0x8086, 0x2450, NT, "Intel", "", enable_flash_}, + {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich_4e}, + {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich_4e}, + {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich_4e}, + {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich_4e}, + {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich_4e}, + {0x8086, 0x24dc, NT, "Intel", "", enable_flash_}, + {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e}, + {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich_dc}, + {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich_dc}, + {0x8086, 0x2642, NT, "Intel", "", enable_flash_}, + {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc}, + {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7}, + {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7}, + {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7}, + {0x8086, 0x27bc, OK, "Intel", "NM10", enable_flash_ich7}, + {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7}, + {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8}, + {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8}, + {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8}, + {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8}, + {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8}, + {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9}, + {0x8086, 0x2911, NT, "Intel", "", enable_flash_}, + {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9}, + {0x8086, 0x2913, NT, "Intel", "", enable_flash_}, + {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9}, + {0x8086, 0x2915, NT, "Intel", "", enable_flash_}, + {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9}, + {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9}, + {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9}, + {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9}, + {0x8086, 0x3a10, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10}, + {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10}, + {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10}, + {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10}, + {0x8086, 0x3a1e, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_ich10}, + {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_ich10}, + {0x8086, 0x3b02, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b03, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b04, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b05, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b06, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b07, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b08, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b09, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b0a, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b0b, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b0c, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_ich10}, + {0x8086, 0x3b0e, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b0f, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b10, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b11, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b12, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b13, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b14, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b15, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b16, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b17, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b18, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b19, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b1a, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b1b, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b1c, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b1d, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b1e, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b1f, NT, "Intel", "", enable_flash_}, + {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7}, + {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, + {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, + {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4}, + {0x8086, 0x7600, NT, "Intel", "", enable_flash_}, + {0x8086, 0x8119, OK, "Intel", "Poulsbo", enable_flash_poulsbo}, + {0x8086, 0x8186, NT, "Intel", "", enable_flash_}, {}, }; -- http://www.hailfinger.org/

3 4

Voltage & form-factor spreadsheet
by Steven Zakulec 04 Jun '11

04 Jun '11

Hello, some weeks ago I asked carldani what I could do to help the flashrom project, and he mentioned that they could really use someone to go thru all the chips in flashchips.c and get the voltage range and form factor(s) for each chip listed there. This is the result of that project: a spreadsheet with the chip name, voltage range, form factors, connector type (pins, leads, etc). This covers all the chips as of v1143. If anyone else is interested, I also have a short text file with all of the form factor acronyms I came across and what they mean (I grabbed the definition from the datasheet). There's a few missing chips, and some values that I wasn't quite sure about. Comments would be greatly appreciated.

4 19

[PATCH] Mark MX25L4005 tested for erase
by GatoLoko 18 May '11

18 May '11

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 I've tested the erase operation on Macronix MX25L4005 SPI chip. Signed-off-by: Raúl Soriano <GatoLoko(a)gmail.com> -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAkzDjmAACgkQ063tJLOwQufNLgCeOiPRPOPkQNaYhsBrWagIE4oR n9EAn3Z6UXgsQSzEYNtOZrRRi53QhT6V =MHSr -----END PGP SIGNATURE-----

3 2

Re: [flashrom] new bios to support
by Joe Tym 18 May '11

18 May '11

hi, thanks for your help in the irc channel with my hosed bios, my motherboard is an aopen i975xa-ydg, drivers are here: http://download.aopen.com.tw/Default.aspx ( no direct link i'm afraid ) i've attached the bin which i was trying to install + txt files containing the output you requested, if you could get it working that would be fantastic thanks, Joe Tym A non-text attachment has been removed: ICA1AC.BIN

6 9

[Patch] Mark w25q80, w25q32, and w25q64 chips tested for write and erase
by David Hendricks 18 May '11

18 May '11

I'm actually not entirely sure why the W25Q80 and W25Q32 were marked as "OK" for erase but not write. In any case, I've successfully read/erased/written all three of these Winbond chips using nm10 and amd870 based mainboards. I see no reason why the W25Q16 would not work as well, but I don't have one to try so I left it out of this patch. Signed-off-by: David Hendricks <dhendrix(a)google.com> -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

3 2

[Patch] Remove filename parameter from chip_safety_check()
by David Hendricks 18 May '11

18 May '11

Seems like the filename parameter was left in by accident. This patch has only been compile tested. Signed-off-by: David Hendricks <dhendrix(a)google.com> -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

3 2

[PATCH 1/1] Kill unused __FLASHROM_HAVE_OUTB__ define
by Peter Lemenkov 17 May '11

17 May '11

Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- hwaccess.h | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/hwaccess.h b/hwaccess.h index 63a2bf2..d125890 100644 --- a/hwaccess.h +++ b/hwaccess.h @@ -163,8 +163,6 @@ cpu_to_be(64) #if NEED_PCI == 1 #if defined (__i386__) || defined (__x86_64__) -#define __FLASHROM_HAVE_OUTB__ 1 - /* for iopl and outb under Solaris */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) #include <strings.h> -- 1.7.2.3

2 1

[PATCH] Revert MMIO space writes on shutdown as needed.
by Carl-Daniel Hailfinger 03 May '11

03 May '11

Revert MMIO space writes on shutdown as needed. Reversible MMIO space writes now use rmmio_write*(). MMIO space writes which are one-shot (e.g. communication with some chip) should continue to use the permanent mmio_write* variants. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-mmio_shutdown_restore/hwaccess.c =================================================================== --- flashrom-mmio_shutdown_restore/hwaccess.c (Revision 1234) +++ flashrom-mmio_shutdown_restore/hwaccess.c (Arbeitskopie) @@ -184,3 +184,71 @@ { return le_to_cpu32(mmio_readl(addr)); } + +enum mmio_write_type { + mmio_write_type_b, + mmio_write_type_w, + mmio_write_type_l, +}; + +struct undo_mmio_write_data { + void *addr; + int reg; + enum mmio_write_type type; + union { + uint8_t bdata; + uint16_t wdata; + uint32_t ldata; + }; +}; + +void undo_mmio_write(void *p) +{ + struct undo_mmio_write_data *data = p; + msg_pdbg("Restoring MMIO space at %p\n", data->addr); + switch (data->type) { + case mmio_write_type_b: + mmio_writeb(data->bdata, data->addr); + break; + case mmio_write_type_w: + mmio_writeb(data->wdata, data->addr); + break; + case mmio_write_type_l: + mmio_writeb(data->ldata, data->addr); + break; + } + /* p was allocated in register_undo_mmio_write. */ + free(p); +} + +#define register_undo_mmio_write(a, c) \ +{ \ + struct undo_mmio_write_data *undo_mmio_write_data; \ + undo_mmio_write_data = malloc(sizeof(struct undo_mmio_write_data)); \ + undo_mmio_write_data->addr = a; \ + undo_mmio_write_data->type = mmio_write_type_##c; \ + undo_mmio_write_data->c##data = mmio_read##c(a); \ + register_shutdown(undo_mmio_write, undo_mmio_write_data); \ +} + +#define register_undo_mmio_writeb(a) register_undo_mmio_write(a, b) +#define register_undo_mmio_writew(a) register_undo_mmio_write(a, w) +#define register_undo_mmio_writel(a) register_undo_mmio_write(a, l) + +void rmmio_writeb(uint8_t val, void *addr) +{ + register_undo_mmio_writeb(addr); + mmio_writeb(val, addr); +} + +void rmmio_writew(uint16_t val, void *addr) +{ + register_undo_mmio_writew(addr); + mmio_writew(val, addr); +} + +void rmmio_writel(uint32_t val, void *addr) +{ + register_undo_mmio_writel(addr); + mmio_writel(val, addr); +} Index: flashrom-mmio_shutdown_restore/ichspi.c =================================================================== --- flashrom-mmio_shutdown_restore/ichspi.c (Revision 1234) +++ flashrom-mmio_shutdown_restore/ichspi.c (Arbeitskopie) @@ -382,16 +382,16 @@ switch (spi_controller) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: - REGWRITE16(ICH7_REG_PREOP, preop); - REGWRITE16(ICH7_REG_OPTYPE, optype); - REGWRITE32(ICH7_REG_OPMENU, opmenu[0]); - REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]); + rmmio_writew(preop, ich_spibar + ICH7_REG_PREOP); + rmmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE); + rmmio_writew(opmenu[0], ich_spibar + ICH7_REG_OPMENU); + rmmio_writew(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4); break; case SPI_CONTROLLER_ICH9: - REGWRITE16(ICH9_REG_PREOP, preop); - REGWRITE16(ICH9_REG_OPTYPE, optype); - REGWRITE32(ICH9_REG_OPMENU, opmenu[0]); - REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]); + rmmio_writew(preop, ich_spibar + ICH9_REG_PREOP); + rmmio_writew(optype, ich_spibar + ICH9_REG_OPTYPE); + rmmio_writew(opmenu[0], ich_spibar + ICH9_REG_OPMENU); + rmmio_writew(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4); break; default: msg_perr("%s: unsupported chipset\n", __func__); @@ -409,16 +409,20 @@ { switch (spi_controller) { case SPI_CONTROLLER_ICH7: - mmio_writel(minaddr, ich_spibar + 0x50); + rmmio_writel(minaddr, ich_spibar + 0x50); ichspi_bbar = mmio_readl(ich_spibar + 0x50); - /* We don't have any option except complaining. */ + /* We don't have any option except complaining. And if the write + * failed, the restore will fail as well, so no problem there. + */ if (ichspi_bbar != minaddr) msg_perr("Setting BBAR failed!\n"); break; case SPI_CONTROLLER_ICH9: - mmio_writel(minaddr, ich_spibar + 0xA0); + rmmio_writel(minaddr, ich_spibar + 0xA0); ichspi_bbar = mmio_readl(ich_spibar + 0xA0); - /* We don't have any option except complaining. */ + /* We don't have any option except complaining. And if the write + * failed, the restore will fail as well, so no problem there. + */ if (ichspi_bbar != minaddr) msg_perr("Setting BBAR failed!\n"); break; Index: flashrom-mmio_shutdown_restore/nicintel_spi.c =================================================================== --- flashrom-mmio_shutdown_restore/nicintel_spi.c (Revision 1234) +++ flashrom-mmio_shutdown_restore/nicintel_spi.c (Arbeitskopie) @@ -149,6 +149,7 @@ nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, 4096); + /* Automatic restore is not possible because we only change two bits. */ tmp = pci_mmio_readl(nicintel_spibar + EECD); tmp &= ~FLASH_WRITES_DISABLED; tmp |= FLASH_WRITES_ENABLED; @@ -168,6 +169,7 @@ { uint32_t tmp; + /* Automatic restore is not possible because we only change two bits. */ tmp = pci_mmio_readl(nicintel_spibar + EECD); tmp &= ~FLASH_WRITES_ENABLED; tmp |= FLASH_WRITES_DISABLED; Index: flashrom-mmio_shutdown_restore/programmer.h =================================================================== --- flashrom-mmio_shutdown_restore/programmer.h (Revision 1234) +++ flashrom-mmio_shutdown_restore/programmer.h (Arbeitskopie) @@ -311,6 +311,9 @@ #define pci_mmio_readb mmio_le_readb #define pci_mmio_readw mmio_le_readw #define pci_mmio_readl mmio_le_readl +void rmmio_writeb(uint8_t val, void *addr); +void rmmio_writew(uint16_t val, void *addr); +void rmmio_writel(uint32_t val, void *addr); /* programmer.c */ int noop_shutdown(void); -- http://www.hailfinger.org/

2 4

[PATCH] ICH SPI paranoid error handling
by Carl-Daniel Hailfinger 24 Apr '11

24 Apr '11

Some people have reported that running flashrom on Ibex Peak (after patching in the PCI ID 0x8086:0x3b02) will not only hang flashrom during the first RES/REMS command issued, it may even cause the machine to lock up or issue a hard reset. We suspect this is because RES/REMS are commands with an address, whereas RDID does not take an address and works fine. Our current ICH SPI code doesn't really follow the datasheets and uses lots of hope instead of error checking in the wrong places. This patch will fail early and fail often if something is odd. As such, merge is not recommended, but running it should definitely generating interesting results on all Intel chipsets with SPI, and especially on Ibex Peak. It probably won't fix the hang, but it should be pretty good at spewing an error before the machine dies. Untested. Highly likely to explode on VIA chipsets which use the same interface but have docs only under NDA. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ich_spi_fcerr_fcdone_paranoia/chipset_enable.c =================================================================== --- flashrom-ich_spi_fcerr_fcdone_paranoia/chipset_enable.c (Revision 1052) +++ flashrom-ich_spi_fcerr_fcdone_paranoia/chipset_enable.c (Arbeitskopie) @@ -579,8 +579,20 @@ mmio_readl(spibar + 0x80)); msg_pdbg("0x84: 0x%08x (PR4)\n", mmio_readl(spibar + 0x84)); - msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", - mmio_readl(spibar + 0x90)); + + tmp = mmio_readl(spibar + 0x90); + msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); + msg_pdbg("AEL %i, ", (tmp >> 4) & 1); + msg_pdbg("FCERR %i, ", (tmp >> 3) & 1); + msg_pdbg("FDONE %i, ", (tmp >> 2) & 1); + msg_pdbg("SCIP %i\n", (tmp >> 0) & 1); + if (tmp & (1 << 3)) { + msg_pdbg("Clearing SSFS.FCERR\n"); + mmio_writeb(1 << 3, spibar + 0x90); + } + tmp >>= 8; + msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp); + msg_pdbg("0x94: 0x%04x (PREOP)\n", mmio_readw(spibar + 0x94)); msg_pdbg("0x96: 0x%04x (OPTYPE)\n", Index: flashrom-ich_spi_fcerr_fcdone_paranoia/ichspi.c =================================================================== --- flashrom-ich_spi_fcerr_fcdone_paranoia/ichspi.c (Revision 1052) +++ flashrom-ich_spi_fcerr_fcdone_paranoia/ichspi.c (Arbeitskopie) @@ -413,6 +413,12 @@ write_cmd = 1; } + /* FIXME: This should be a time-limited while loop. */ + if (REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) { + msg_perr("Error: Totally unhandled SCIP condition!\n"); + return 1; + } + /* Programm Offset in Flash into FADDR */ REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */ @@ -486,18 +492,22 @@ /* write it */ REGWRITE16(ICH7_REG_SPIC, temp16); - /* wait for cycle complete */ - timeout = 100 * 1000 * 60; // 60s is a looong timeout. - while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) { + /* Wait for Cycle Done Status or Flash Cycle Error. */ + timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ + while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) && + --timeout) { programmer_delay(10); } if (!timeout) { msg_perr("timeout\n"); + return 1; } /* FIXME: make sure we do not needlessly cause transaction errors. */ - if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) { - msg_pdbg("Transaction error!\n"); + if (REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) { + msg_perr("Transaction error for opcode 0x%02x!\n", + op.opcode); + REGWRITE16(ICH7_REG_SPIS, SPIS_FCERR); return 1; } @@ -532,6 +542,12 @@ write_cmd = 1; } + /* FIXME: This should be a time-limited while loop. */ + if (REGREAD16(ICH9_REG_SSFS) & SSFS_SCIP) { + msg_perr("Error: Totally unhandled SCIP condition!\n"); + return 1; + } + /* Programm Offset in Flash into FADDR */ REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */ @@ -605,18 +621,23 @@ /* write it */ REGWRITE32(ICH9_REG_SSFS, temp32); - /*wait for cycle complete */ - timeout = 100 * 1000 * 60; // 60s is a looong timeout. - while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) { + /* Wait for Cycle Done Status or Flash Cycle Error. */ + timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ + while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_CDS | SSFS_FCERR)) == 0) && + --timeout) { programmer_delay(10); } if (!timeout) { msg_perr("timeout\n"); + return 1; } /* FIXME make sure we do not needlessly cause transaction errors. */ - if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) { - msg_pdbg("Transaction error!\n"); + if (REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) { + msg_perr("Transaction error for opcode 0x%02x!\n", + op.opcode); + //FIXME: Really REGWRITE8? + REGWRITE8(ICH9_REG_SSFS, SSFS_FCERR); return 1; } -- http://www.hailfinger.org/

5 12

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flashrom November 2010