flashrom January 2010

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[PATCH] Convert wbsio_spi to msg_*
by Sean Nelson 10 Jan '10

10 Jan '10

Convert all messages in wbsio_spi.c to the new message infrastructure. Signed-off-by: Sean Nelson <audiohacked(a)gmail.com>

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[commit] r847 - trunk
by svn＠flashrom.org 10 Jan '10

10 Jan '10

Author: snelson Date: 2010-01-10 00:34:45 +0100 (Sun, 10 Jan 2010) New Revision: 847 Modified: trunk/wbsio_spi.c Log: Convert all messages in wbsio_spi.c to the new message infrastructure. Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/wbsio_spi.c =================================================================== --- trunk/wbsio_spi.c 2010-01-09 23:31:13 UTC (rev 846) +++ trunk/wbsio_spi.c 2010-01-09 23:34:45 UTC (rev 847) @@ -22,17 +22,6 @@ #include "flash.h" #include "spi.h" -/* Change this to #define if you want lowlevel debugging of commands - * sent to the Winbond W836xx SPI controller. - */ -#undef COMM_DEBUG - -#ifdef COMM_DEBUG -#define msg_comm_debug printf_debug -#else -#define msg_comm_debug(...) do {} while (0) -#endif - #define WBSIO_PORT1 0x2e #define WBSIO_PORT2 0x4e @@ -46,18 +35,18 @@ w836xx_ext_enter(port); id = sio_read(port, 0x20); if (id != 0xa0) { - fprintf(stderr, "\nW83627 not found at 0x%x, id=0x%02x want=0xa0.\n", port, id); + msg_perr("\nW83627 not found at 0x%x, id=0x%02x want=0xa0.\n", port, id); goto done; } if (0 == (sio_read(port, 0x24) & 2)) { - fprintf(stderr, "\nW83627 found at 0x%x, but SPI pins are not enabled. (CR[0x24] bit 1=0)\n", port); + msg_perr("\nW83627 found at 0x%x, but SPI pins are not enabled. (CR[0x24] bit 1=0)\n", port); goto done; } sio_write(port, 0x07, 0x06); if (0 == (sio_read(port, 0x30) & 1)) { - fprintf(stderr, "\nW83627 found at 0x%x, but SPI is not enabled. (LDN6[0x30] bit 0=0)\n", port); + msg_perr("\nW83627 found at 0x%x, but SPI is not enabled. (LDN6[0x30] bit 0=0)\n", port); goto done; } @@ -74,7 +63,7 @@ if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT2))) return 1; - msg_comm_debug("\nwbsio_spibase = 0x%x\n", wbsio_spibase); + msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase); buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_WBSIO; @@ -108,42 +97,42 @@ int i; uint8_t mode = 0; - msg_comm_debug("%s:", __func__); + msg_pspew("%s:", __func__); if (1 == writecnt && 0 == readcnt) { mode = 0x10; } else if (2 == writecnt && 0 == readcnt) { OUTB(writearr[1], wbsio_spibase + 4); - msg_comm_debug(" data=0x%02x", writearr[1]); + msg_pspew(" data=0x%02x", writearr[1]); mode = 0x20; } else if (1 == writecnt && 2 == readcnt) { mode = 0x30; } else if (4 == writecnt && 0 == readcnt) { - msg_comm_debug(" addr=0x%02x", (writearr[1] & 0x0f)); + msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); for (i = 2; i < writecnt; i++) { OUTB(writearr[i], wbsio_spibase + i); - msg_comm_debug("%02x", writearr[i]); + msg_pspew("%02x", writearr[i]); } mode = 0x40 | (writearr[1] & 0x0f); } else if (5 == writecnt && 0 == readcnt) { - msg_comm_debug(" addr=0x%02x", (writearr[1] & 0x0f)); + msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); for (i = 2; i < 4; i++) { OUTB(writearr[i], wbsio_spibase + i); - msg_comm_debug("%02x", writearr[i]); + msg_pspew("%02x", writearr[i]); } OUTB(writearr[i], wbsio_spibase + i); - msg_comm_debug(" data=0x%02x", writearr[i]); + msg_pspew(" data=0x%02x", writearr[i]); mode = 0x50 | (writearr[1] & 0x0f); } else if (8 == writecnt && 0 == readcnt) { - msg_comm_debug(" addr=0x%02x", (writearr[1] & 0x0f)); + msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); for (i = 2; i < 4; i++) { OUTB(writearr[i], wbsio_spibase + i); - msg_comm_debug("%02x", writearr[i]); + msg_pspew("%02x", writearr[i]); } - msg_comm_debug(" data=0x"); + msg_pspew(" data=0x"); for (; i < writecnt; i++) { OUTB(writearr[i], wbsio_spibase + i); - msg_comm_debug("%02x", writearr[i]); + msg_pspew("%02x", writearr[i]); } mode = 0x60 | (writearr[1] & 0x0f); } else if (5 == writecnt && 4 == readcnt) { @@ -154,17 +143,17 @@ */ ; } else if (4 == writecnt && readcnt >= 1 && readcnt <= 4) { - msg_comm_debug(" addr=0x%02x", (writearr[1] & 0x0f)); + msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); for (i = 2; i < writecnt; i++) { OUTB(writearr[i], wbsio_spibase + i); - msg_comm_debug("%02x", writearr[i]); + msg_pspew("%02x", writearr[i]); } mode = ((7 + readcnt) << 4) | (writearr[1] & 0x0f); } - msg_comm_debug(" cmd=%02x mode=%02x\n", writearr[0], mode); + msg_pspew(" cmd=%02x mode=%02x\n", writearr[0], mode); if (!mode) { - fprintf(stderr, "%s: unsupported command type wr=%d rd=%d\n", + msg_perr("%s: unsupported command type wr=%d rd=%d\n", __func__, writecnt, readcnt); /* Command type refers to the number of bytes read/written. */ return SPI_INVALID_LENGTH; @@ -177,12 +166,12 @@ if (!readcnt) return 0; - msg_comm_debug("%s: returning data =", __func__); + msg_pspew("%s: returning data =", __func__); for (i = 0; i < readcnt; i++) { readarr[i] = INB(wbsio_spibase + 4 + i); - msg_comm_debug(" 0x%02x", readarr[i]); + msg_pspew(" 0x%02x", readarr[i]); } - msg_comm_debug("\n"); + msg_pspew("\n"); return 0; } @@ -191,7 +180,7 @@ int size = flash->total_size * 1024; if (size > 1024 * 1024) { - fprintf(stderr, "%s: Winbond saved on 4 register bits so max chip size is 1024 KB!\n", __func__); + msg_perr("%s: Winbond saved on 4 register bits so max chip size is 1024 KB!\n", __func__); return 1; } @@ -203,7 +192,7 @@ int size = flash->total_size * 1024; if (size > 1024 * 1024) { - fprintf(stderr, "%s: Winbond saved on 4 register bits so max chip size is 1024 KB!\n", __func__); + msg_perr("%s: Winbond saved on 4 register bits so max chip size is 1024 KB!\n", __func__); return 1; }

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Fix mess-up in commit 845
by Michael Karcher 10 Jan '10

10 Jan '10

commit 845 is wrong, as I deleted a wrong line when I wanted to remove debugging print code. This (hopefully obviously correct) patch fixes the issue. As a previous version (before adding the debugging statement) was already executed on the board, the missing OUTW was executed on the testers machine on an earlier flashrom run. Regards, Michael Karcher Index: board_enable.c =================================================================== --- board_enable.c (Revision 845) +++ board_enable.c (Arbeitskopie) @@ -967,7 +967,7 @@ base = pci_read_word(dev, 0x74); temp = INW(base + 0x68); temp &= ~(1 << 0); /* Make pin output? */ - printf_debug("changed to %04x\n",temp); + OUTW(temp, base + 0x68); temp = INW(base + 0x64); temp |= (1 << 0); /* Raise output? */

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[commit] r846 - trunk
by svn＠flashrom.org 10 Jan '10

10 Jan '10

Author: mkarcher Date: 2010-01-10 00:31:13 +0100 (Sun, 10 Jan 2010) New Revision: 846 Modified: trunk/board_enable.c Log: commit 845 is wrong, as I deleted a wrong line when I wanted to remove debugging print code. This (hopefully obviously correct) patch fixes the issue. As a previous version (before adding the debugging statement) was already executed on the board, the missing OUTW was executed on the testers machine on an earlier flashrom run. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Luc Verhaegen <libv(a)skynet.be> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2010-01-09 17:36:06 UTC (rev 845) +++ trunk/board_enable.c 2010-01-09 23:31:13 UTC (rev 846) @@ -967,7 +967,7 @@ base = pci_read_word(dev, 0x74); temp = INW(base + 0x68); temp &= ~(1 << 0); /* Make pin output? */ - printf_debug("changed to %04x\n",temp); + OUTW(temp, base + 0x68); temp = INW(base + 0x64); temp |= (1 << 0); /* Raise output? */

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Re: [flashrom] Big problem after flash of SST SST25VF016B on HP Compaq 615
by Carl-Daniel Hailfinger 09 Jan '10

09 Jan '10

Hi Parallix, I have re-added the flashrom list so others can follow our conversation. I just wanted to avoid any BIOS images on the list for legal reasons. On 09.01.2010 22:17, Parallix wrote: > Am Samstag, 9. Januar 2010 21:55:56 schrieben Sie: > >> On 09.01.2010 20:33, Parallix wrote: >> >>> COMPLETE. >>> Verifying flash... VERIFY FAILED at 0x00010058! Expected=0x15, Read=0x05, failed byte count from 0x00000000-0x001fffff: 0x12d075 >>> >>> A verification by reading the BIOS (via flashrom -r <file>) and comparing it with >>> the original bios (via diff) shows the same difference. >>> >>> >> This is very odd. Can you try flashing the backup BIOS with unmodified >> latest flashrom, then read back the result? >> > > I used the unpatched flashrom v0.9.1-r845. > Thanks. >> Please mail me personally at <c-d.hailfinger.devel.2006(a)gmx.net> the >> following files (preferably bz2 compressed): >> - original backup >> > > Is attatched > > >> - readback image after flashing with unmodified latest flashrom >> > > Is attachted, too. It contains a lot of identical bytes and thus results > in a much smaller bz2 file. > Thanks. >From your log file: > Chip status register is 8c > Chip status register: Block Protect Write Disable (BPL) is set This means it is probably not possible to undo the locking. > Chip status register: Auto Address Increment Programming (AAI) is not set > Chip status register: Bit 5 / Block Protect 3 (BP3) is not set > Chip status register: Bit 4 / Block Protect 2 (BP2) is not set > Chip status register: Bit 3 / Block Protect 1 (BP1) is set > Chip status register: Bit 2 / Block Protect 0 (BP0) is set > Chip status register: Write Enable Latch (WEL) is not set > Chip status register: Write In Progress (WIP/BUSY) is not set > Resulting block protection : 1C0000H-1FFFFFH The good news is that the erase result is as expected from the block protection data. The not-so-good news is that we need a board enable routine for your laptop if we want to flash the protected blocks. The bad news is that we probably need SuperIO or EC information (which we don't have) to write the board enable routine. Now let us focus on recovery. Can you read back the flash chip again and compare it against the last readback? They should be identical. If not, we have a really big problem where some unknown software is modifying the flash chip. Then try to write with a flashrom patched with the following patch. It will also turn up at http://patchwork.coreboot.org/project/flashrom/list/ shortly in case you have problems extracting the patch from this mail. Do not erase, check only if 0x0-0x1BFFFF is erased, then write 0x0-0x1BFFFF. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-parallix/spi.c =================================================================== --- flashrom-parallix/spi.c (Revision 845) +++ flashrom-parallix/spi.c (Arbeitskopie) @@ -997,10 +997,11 @@ */ int spi_chip_write_1(struct flashchip *flash, uint8_t *buf) { - int total_size = 1024 * flash->total_size; + int total_size = 0x1C0000; int i, result = 0; spi_disable_blockprotect(); +#if 0 /* Erase first */ printf("Erasing flash before programming... "); if (erase_flash(flash)) { @@ -1008,6 +1009,11 @@ return -1; } printf("done.\n"); +#endif + if (check_erased_range(flash, 0, total_size)) { + fprintf(stderr, "WTF erased area failed erasecheck!\n"); + return 1; + } for (i = 0; i < total_size; i++) { result = spi_byte_program(i, buf[i]); if (result) -- Developer quote of the year: "We are juggling too many chainsaws and flaming arrows and tigers."

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[PATCH] Convert ichspi to msg_*
by Sean Nelson 09 Jan '10

09 Jan '10

Convert all messages in ichspi.c to the new message infrastructure. Signed-off-by: Sean Nelson <audiohacked(a)gmail.com>

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Big problem after flash of SST SST25VF016B on HP Compaq 615
by Parallix 09 Jan '10

09 Jan '10

Somewhat strage: After flashing the old bios with the suggested patch I got the following error output: flashrom v0.9.1-r845 No coreboot table found. Found chipset "AMD SB700/SB710/SB750", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "SST SST25VF016B" (2048 KB, SPI) at physical address 0xffe00000. === This flash part has status UNTESTED for operations: ERASE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash before programming... done. COMPLETE. Verifying flash... VERIFY FAILED at 0x00010058! Expected=0x15, Read=0x05, failed byte count from 0x00000000-0x001fffff: 0x12d075 Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! A verification by reading the BIOS (via flashrom -r <file>) and comparing it with the original bios (via diff) shows the same difference. Best, Parallix

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Big problem after flash of SST SST25VF016B on HP Compaq 615
by Parallix 09 Jan '10

09 Jan '10

Dear Carl-Daniel (Hailfinger), dear Michael (Karcher) here comes the information of the HP Compaq 615 you asked for. Best, Parallix

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Re: [flashrom] Big problem after flash of SST SST25VF016B on HP Compaq 615
by Michael Karcher 09 Jan '10

09 Jan '10

Am Samstag, den 09.01.2010, 20:00 +0100 schrieb Parallix: > should I now flash the old (and buggy) bios or the new (hopefully bugless) > one? The old one, to recover your system to a safe state. Fixing the real issue is left for later. You might want to compare whether the last 256KB of the old and new BIOS are the same. In that case, an update without removing the boot block lock is possible, although not yet implemented in flashrom (partial write). > Should I use the trunk/developers version of flashrom or the released > one? You should use the developers version with the suggested modification applied. Please also send the info Carl-Daniel Hailfinger requested. Regards, Michael Karcher

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Big problem after flash of SST SST25VF016B on HP Compaq 615
by Parallix 09 Jan '10

09 Jan '10

I've a big problem. Of course, I made a backup of my old bios with flashrom -r oldbios.bin. Then I tried to flash my HP Compaq 615 with flashrom v0.9.1-r792 and got the following "warning": No coreboot table found. Found chipset "AMD SB700/SB710/SB750", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "SST SST25VF016B" (2048 KB, SPI) at physical address 0xffe00000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash before programming... Erasing flash chip... ERASE FAILED at 0x001c0000! Expected=0xff, Read=0xfc, failed byte count from 0x00000000-0x001fffff: 0x37386 ERASE FAILED! FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! After reading the flash contents with flashrom -r newbios.bin I compared the old bios with the new one. They differ. What can I now do? Best, Parallix

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flashrom January 2010