flashrom December 2009

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[Flashrom] [PATCH] Convert flashchips to use struct eraseblock - Atmel
by Sean Nelson 23 Dec '09

23 Dec '09

2 5

[commit] r817 - trunk
by svn＠flashrom.org 23 Dec '09

23 Dec '09

Author: hailfinger Date: 2009-12-23 13:02:55 +0100 (Wed, 23 Dec 2009) New Revision: 817 Modified: trunk/flashchips.c Log: Convert the following chips to use struct eraseblock: AT25DF021, AT25DF041A, AT25DF081, AT25DF161, AT25DF321, AT25DF321A, AT25DF641, AT25F512B, AT25FS010, AT25FS040, AT26DF041, AT26DF081A, AT26DF161, AT26DF161A, AT26F004, AT29C512, AT29C010A, AT29C020, AT29C040A, AT49BV512, AT49F002(N), AT49F002(N)T A possible future patch would to add spi_block_erase_d7 to spi.c as an alternate to spi_block_erase_20. Only some SPI chips support d7. Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-12-23 03:01:36 UTC (rev 816) +++ trunk/flashchips.c 2009-12-23 12:02:55 UTC (rev 817) @@ -298,7 +298,26 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 8} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -314,7 +333,26 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 16} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -330,7 +368,26 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 32} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -346,7 +403,26 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -359,10 +435,29 @@ .model_id = AT_25DF321, .total_size = 4096, .page_size = 256, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -378,7 +473,26 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -394,7 +508,26 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -410,7 +543,26 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 16} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 2} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {32 * 1024, 2} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -426,7 +578,26 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 4} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {32 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -442,7 +613,26 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -459,6 +649,13 @@ .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + } + }, .write = NULL /* Incompatible Page write */, .read = spi_chip_read, }, @@ -474,7 +671,26 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 32} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -490,7 +706,26 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -506,7 +741,26 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, .write = spi_chip_write_256, .read = spi_chip_read, }, @@ -539,7 +793,26 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .erase = spi_chip_erase_60_c7, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 16} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, .write = NULL /* Incompatible Page write */, .read = spi_chip_read, }, @@ -552,10 +825,17 @@ .model_id = AT_29C512, .total_size = 64, .page_size = 128, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRW, .probe = probe_jedec, .probe_timing = 10000, /* 10mS, Enter=Exec */ - .erase = erase_chip_jedec, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + }, .write = write_jedec, .read = read_memmapped, @@ -569,10 +849,17 @@ .model_id = AT_29C010A, .total_size = 128, .page_size = 128, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PR, .probe = probe_jedec, .probe_timing = 10000, /* 10mS, Enter=Exec */ - .erase = erase_chip_jedec, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + }, .write = write_jedec, /* FIXME */ .read = read_memmapped, }, @@ -585,10 +872,17 @@ .model_id = AT_29C020, .total_size = 256, .page_size = 256, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRW, .probe = probe_jedec, .probe_timing = 10000, /* 10ms */ - .erase = erase_chip_jedec, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + }, .write = write_jedec, .read = read_memmapped, }, @@ -604,7 +898,14 @@ .tested = TEST_UNTESTED, .probe = probe_jedec, .probe_timing = 10000, /* 10 ms */ - .erase = erase_chip_jedec, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + }, .write = write_jedec, .read = read_memmapped, }, @@ -761,10 +1062,17 @@ .model_id = AT_49BV512, .total_size = 64, .page_size = 64, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRW, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ - .erase = erase_chip_jedec, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + }, .write = write_49f002, .read = read_memmapped, }, @@ -780,7 +1088,22 @@ .tested = TEST_UNTESTED, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ - .erase = erase_chip_jedec, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {96 * 1024, 1}, + {128 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + }, .write = write_49f002, .read = read_memmapped, }, @@ -793,10 +1116,25 @@ .model_id = AT_49F002NT, .total_size = 256, .page_size = 256, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRW, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ - .erase = erase_chip_jedec, + .erase = NULL, + .block_erasers = + { + { + .eraseblocks = { + {128 * 1024, 1}, + {96 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + }, .write = write_49f002, .read = read_memmapped, },

1 0

Scary error message
by Fraser Hanson 23 Dec '09

23 Dec '09

Hi, I flashed my bios with flashrom tonight and got the scary warning message saying "erase failed" and "do not reboot". I haven't rebooted. As far as I can tell from using flashrom itself, everything is actually fine. The erase appears to have failed at physical address 0, which I would guess means that nothing actually happened. I had taken a dump of the original bios before starting, and "flashrom -v" now verifies that it is identical. Furthermore, a new dump of the bios matches the original dump from before I tried to write the bios. My board is an MSI K8N Neo4 Platinum. Output from my dump attempt and subsequent messing around follows. Do I have your blessing to reboot my machine? --Fraser ====================================================================== fraser@ged:/tmp/7125v1D$ sudo flashrom flashrom v0.9.1-r706 No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000. No operations were specified. fraser@ged:/tmp/7125v1D$ sudo flashrom -w W7125NMS.1D0 flashrom v0.9.1-r706 No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Programming page: ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0000ffff: 0x599 ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net channel #flashrom or mail flashrom(a)flashrom.org ------------------------------------------------------------ DO NOT REBOOT OR POWEROFF! fraser@ged:/tmp/7125v1D$ sudo flashrom -w original.bios flashrom v0.9.1-r706 No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Programming page: ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0000ffff: 0x599 ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net channel #flashrom or mail flashrom(a)flashrom.org ------------------------------------------------------------ DO NOT REBOOT OR POWEROFF! fraser@ged:/tmp/7125v1D$ sudo flashrom -r bios flashrom v0.9.1-r706 No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000. Reading flash... done. fraser@ged:/tmp/7125v1D$ md5sum bios 8382ac62ffcfe57a86514dad936deb82 bios fraser@ged:/tmp/7125v1D$ md5sum original.bios 8382ac62ffcfe57a86514dad936deb82 original.bios fraser@ged:/tmp/7125v1D$ sudo flashrom -v original.bios flashrom v0.9.1-r706 No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... VERIFIED.

3 4

[commit] r816 - trunk
by svn＠flashrom.org 23 Dec '09

23 Dec '09

Author: libv Date: 2009-12-23 04:01:36 +0100 (Wed, 23 Dec 2009) New Revision: 816 Modified: trunk/board_enable.c Log: Board: Add MSI K8N Neo4-F Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Fraser Hanson <fraser.hanson(a)gmail.com> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-12-23 00:54:26 UTC (rev 815) +++ trunk/board_enable.c 2009-12-23 03:01:36 UTC (rev 816) @@ -474,6 +474,14 @@ } /** + * Suited for MSI K8N Neo4: nVidia CK804. + */ +static int nvidia_mcp_gpio2_raise(const char *name) +{ + return nvidia_mcp_gpio_set(0x02, 1); +} + +/** * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04. */ static int nvidia_mcp_gpio10_raise(const char *name) @@ -1209,6 +1217,7 @@ {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, "MSI", "MS-6712 (KT4V)", board_msi_kt4v}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", intel_ich_gpio19_raise}, {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, + {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, "MSI", "K8N Neo4-F", nvidia_mcp_gpio2_raise}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, "shuttle", "ak31", "Shuttle", "AK31", w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", shuttle_ak38n}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25},

1 0

flash erase failure
by Thao Hoang 23 Dec '09

23 Dec '09

Hi there. I'm trying to use flashrom and although the program can detect both my chipset and my flash part (which are both tested & supported), the erase routine fails. (Although I don't think it even erase since the content read after this failure was the same and the board does boot up properly.) What do you think is going on? Do you think it's something with my mainboard (per some of the discussion I have seen?) Here is what I get when I do a write.... Thanks also for all the good work! root@slax:/home/user/flashrom_folder/flashrom_unrelease# ./flashrom -f -w backup.rom flashrom v0.9.1-runknown No coreboot table found. Found chipset "Intel ICH7M", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000- 0x0000ffff: 0x13de ERASE FAILED! ERASE FAILED! ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF!

3 2

[PATCH] Boards: Add iBase MB899.
by Luc Verhaegen 23 Dec '09

23 Dec '09

Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 763a58b..09efb97 100644 --- a/board_enable.c +++ b/board_enable.c @@ -852,6 +852,14 @@ static int intel_ich_gpio23_raise(const char *name) } /** + * Suited for IBase MB899: i945GM + ICH7. + */ +static int intel_ich_gpio26_raise(const char *name) +{ + return intel_ich_gpio_set(26, 1); +} + +/** * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2. */ static int board_acorp_6a815epd(const char *name) @@ -1199,6 +1207,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", it87xx_probe_spi_flash}, {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, NULL, NULL, "GIGABYTE", "GA-MA790FX-DQ6", it87xx_probe_spi_flash}, {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, "hp", "dl145_g3", "HP", "DL145 G3", board_hp_dl145_g3_enable}, + {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, "ibase", "mb899", "iBASE", "MB899", intel_ich_gpio26_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, "IBM", "x3455", board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, "Intel", "D201GLY", wbsio_check_for_spi}, {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, "iwill", "dk8_htx", "IWILL", "DK8-HTX", w83627hf_gpio24_raise_2e}, -- 1.6.0.2 --vtzGhvizbBRQ85DL--

1 0

[PATCH] Updated vt823x "set all writes to lpc".
by Luc Verhaegen 23 Dec '09

23 Dec '09

We've had some changes pushed which breaks the previous patch. So here is an update. Luc Verhaegen.

2 7

[commit] r815 - trunk
by svn＠flashrom.org 23 Dec '09

23 Dec '09

Author: libv Date: 2009-12-23 01:54:26 +0100 (Wed, 23 Dec 2009) New Revision: 815 Modified: trunk/board_enable.c trunk/chipset_enable.c trunk/print.c Log: Chipset/Board: vt8237: Set All mem cycles to LPC in chipset enable. Only done for VT8237R (possibly needed for VT8237 too), VT8235 does not need this (even if the original bios does so: Asus A7V8X-MX SE, MSI KT4V were verified). This then opens a floodgate of cleanups in the board enables. * EPIA SP board enable vanishes, taking EPIA CN match with it. * Asus A7V8X-MX/Tyan S2498 board enable then equals w836xx_memw_enable_2e * AOpen vKM400Am-S board enable then equals it8705_rom_write_enable * Epia M board enable becomes via_vt823x_gpio15_raise * Epia N board enable becomes via_vt823x_gpio9_raise * Asus M2V-MX board enable becomes via_vt823x_gpio5_raise * vt823x_gpio_set becomes via_vt823x_gpio_set, and now detects ISA bridge itself, in concordance with intel ich and nvidia mcp gpio. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-12-22 23:54:10 UTC (rev 814) +++ trunk/board_enable.c 2009-12-23 00:54:26 UTC (rev 815) @@ -191,26 +191,41 @@ } /** - * Common routine for several VT823x based boards. + * Suited for: + * - EPoX EP-8K5A2: VIA KT333 + VT8235. + * - Albatron PM266A Pro: VIA P4M266A + VT8235. + * - Shuttle AK31 (all versions): VIA KT266 + VT8233. + * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235 + * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237. */ -static void vt823x_set_all_writes_to_lpc(struct pci_dev *dev) +static int w836xx_memw_enable_2e(const char *name) { - uint8_t val; + w836xx_memw_enable(0x2E); - /* All memory cycles, not just ROM ones, go to LPC. */ - val = pci_read_byte(dev, 0x59); - val &= ~0x80; - pci_write_byte(dev, 0x59, val); + return 0; } + /** * VT823x: Set one of the GPIO pins. */ -static void vt823x_gpio_set(struct pci_dev *dev, uint8_t gpio, int raise) +static int via_vt823x_gpio_set(uint8_t gpio, int raise) { + struct pci_dev *dev; uint16_t base; uint8_t val, bit, offset; + dev = pci_dev_find_vendorclass(0x1106, 0x0601); + switch (dev->device_id) { + case 0x3177: /* VT8235 */ + case 0x3227: /* VT8237R */ + case 0x3337: /* VT8237A */ + break; + default: + fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n"); + return -1; + } + if ((gpio >= 12) && (gpio <= 15)) { /* GPIO12-15 -> output */ val = pci_read_byte(dev, 0xE4); @@ -228,7 +243,7 @@ } else { fprintf(stderr, "\nERROR: " "VT823x GPIO%02d is not implemented.\n", gpio); - return; + return -1; } /* We need the I/O Base Address for this board's flash enable. */ @@ -243,103 +258,53 @@ else val &= ~bit; OUTB(val, base + offset); -} -/** - * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs. - * - * We don't need to do this when using coreboot, GPIO15 is never lowered there. - */ -static int board_via_epia_m(const char *name) -{ - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8235 ISA bridge not found.\n"); - return -1; - } - - /* GPIO15 is connected to write protect. */ - vt823x_gpio_set(dev, 15, 1); - return 0; } /** - * Suited for: - * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235 - * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237. + * Suited for Asus M2V-MX: VIA K8M890 + VT8237A + IT8716F */ -static int board_asus_a7v8x_mx(const char *name) +static int via_vt823x_gpio5_raise(const char *name) { - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */ - if (!dev) - dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n"); - return -1; - } - - vt823x_set_all_writes_to_lpc(dev); - w836xx_memw_enable(0x2E); - - return 0; + /* On M2V-MX: GPO5 is connected to WP# and TBL#. */ + return via_vt823x_gpio_set(5, 1); } /** - * Suited for VIAs EPIA SP and EPIA CN. + * Suited for VIAs EPIA N & NL. */ -static int board_via_epia_sp(const char *name) +static int via_vt823x_gpio9_raise(const char *name) { - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3227); /* VT8237R ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8237R ISA bridge not found.\n"); - return -1; - } - - vt823x_set_all_writes_to_lpc(dev); - - return 0; + return via_vt823x_gpio_set(9, 1); } /** - * Suited for VIAs EPIA N & NL. + * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs. + * + * We don't need to do this for EPIA M when using coreboot, GPIO15 is never + * lowered there. */ -static int board_via_epia_n(const char *name) +static int via_vt823x_gpio15_raise(const char *name) { - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3227); /* VT8237R ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8237R ISA bridge not found.\n"); - return -1; - } - - /* All memory cycles, not just ROM ones, go to LPC */ - vt823x_set_all_writes_to_lpc(dev); - - /* GPIO9 -> output */ - vt823x_gpio_set(dev, 9, 1); - - return 0; + return via_vt823x_gpio_set(15, 1); } /** + * Winbond W83697HF Super I/O + VIA VT8235 southbridge + * * Suited for: - * - EPoX EP-8K5A2: VIA KT333 + VT8235. - * - Albatron PM266A Pro: VIA P4M266A + VT8235. - * - Shuttle AK31 (all versions): VIA KT266 + VT8233. + * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235 + * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235 */ -static int w836xx_memw_enable_2e(const char *name) +static int board_msi_kt4v(const char *name) { + int ret; + + ret = via_vt823x_gpio_set(12, 1); w836xx_memw_enable(0x2E); - return 0; + return ret; } /** @@ -919,6 +884,7 @@ * Suited for: * - Biostar P4M80-M4: VIA P4M800 + VT8237 + IT8705AF * - GIGABYTE GA-7VT600: VIA KT600 + VT8237 + IT8705 + * - AOpen vKM400Am-S: VIA KM400 + VT8237 + IT8705F. * * SIS950 superio probably requires the same flash write enable. */ @@ -942,49 +908,6 @@ } /** - * Suited for AOpen vKM400Am-S: VIA KM400 + VT8237 + IT8705F. - */ -static int board_aopen_vkm400(const char *name) -{ - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8237 ISA bridge not found.\n"); - return -1; - } - - vt823x_set_all_writes_to_lpc(dev); - - return it8705_rom_write_enable(name); -} - -/** - * Winbond W83697HF Super I/O + VIA VT8235 southbridge - * - * Suited for: - * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235 - * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235 - */ -static int board_msi_kt4v(const char *name) -{ - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n"); - return -1; - } - - vt823x_set_all_writes_to_lpc(dev); - - vt823x_gpio_set(dev, 12, 1); - w836xx_memw_enable(0x2E); - - return 0; -} - -/** * Suited for Soyo SY-7VCA: Pro133A + VT82C686. */ static int board_soyo_sy_7vca(const char *name) @@ -1215,26 +1138,6 @@ } /** - * Suited for Asus M2V-MX: VIA K8M890 + VT8237A + IT8716F - */ -static int board_asus_m2v_mx(const char *name) -{ - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3337); /* VT8237A ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8237A ISA bridge not found.\n"); - return -1; - } - - /* GPO5 is connected to WP# and TBL#. */ - vt823x_gpio_set(dev, 5, 1); - - return 0; -} - - -/** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. * @@ -1268,13 +1171,13 @@ {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, "ASRock", "P4i65GV", intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A", w836xx_memw_enable_2e}, - {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400Am-S", board_aopen_vkm400}, + {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400Am-S", it8705_rom_write_enable}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group", "DBE62", board_artecgroup_dbe6x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, "ASUS", "A7V600-X", board_asus_a7v600x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x}, - {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", board_asus_a7v8x_mx}, - {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, "ASUS", "M2V-MX", board_asus_m2v_mx}, + {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", w836xx_memw_enable_2e}, + {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, "ASUS", "M2V-MX", via_vt823x_gpio5_raise}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", intel_ich_gpio22_raise}, {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, "ASUS", "P4B266-LM", intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", intel_ich_gpio21_raise}, @@ -1310,11 +1213,9 @@ {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", shuttle_ak38n}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, "Soyo", "SY-7VCA", board_soyo_sy_7vca}, - {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx}, - {0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, NULL, NULL, "VIA", "EPIA-CN", board_via_epia_sp}, - {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA M/MII/...", board_via_epia_m}, - {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, "VIA", "EPIA-N/NL", board_via_epia_n}, - {0x1106, 0x3227, 0x1106, 0xAA01, 0x1106, 0x0259, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA SP", board_via_epia_sp}, + {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", w836xx_memw_enable_2e}, + {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA M/MII/...", via_vt823x_gpio15_raise}, + {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, "VIA", "EPIA-N/NL", via_vt823x_gpio9_raise}, {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, NULL, NULL, "VIA", "PC3500G", it87xx_probe_spi_flash}, { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL}, /* end marker */ Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-12-22 23:54:10 UTC (rev 814) +++ trunk/chipset_enable.c 2009-12-23 00:54:26 UTC (rev 815) @@ -667,6 +667,13 @@ return -1; } + if (dev->device_id == 0x3227) { /* VT8237R */ + /* All memory cycles, not just ROM ones, go to LPC. */ + val = pci_read_byte(dev, 0x59); + val &= ~0x80; + pci_write_byte(dev, 0x59, val); + } + return 0; } Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-12-22 23:54:10 UTC (rev 814) +++ trunk/print.c 2009-12-23 00:54:26 UTC (rev 815) @@ -346,10 +346,12 @@ { "Tyan", "S5376G2NR/S5376WAG2NR", }, { "Tyan", "S5377", }, { "Tyan", "S5397", }, + { "VIA", "EPIA-CN", }, { "VIA", "EPIA-EX15000G", }, { "VIA", "EPIA-LN", }, { "VIA", "EPIA-M700", }, { "VIA", "EPIA-NX15000G", }, + { "VIA", "EPIA-SP", }, { "VIA", "NAB74X0", }, { "VIA", "pc2500e", }, { "VIA", "VB700X", },

1 0

[commit] r814 - trunk
by svn＠flashrom.org 23 Dec '09

23 Dec '09

Author: hailfinger Date: 2009-12-23 00:54:10 +0100 (Wed, 23 Dec 2009) New Revision: 814 Modified: trunk/spi.c Log: Add a few FIXME comments to the generic SPI code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-12-22 23:42:04 UTC (rev 813) +++ trunk/spi.c 2009-12-22 23:54:10 UTC (rev 814) @@ -807,6 +807,7 @@ int result; struct spi_command cmds[] = { { + /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */ .writecnt = JEDEC_EWSR_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_EWSR }, .readcnt = 0, @@ -1059,6 +1060,7 @@ fprintf(stderr, "ERASE FAILED!\n"); return -1; } + /* FIXME: This will fail on ICH/VIA SPI. */ result = spi_write_enable(); if (result) return result;

1 0

[PATCH] Refactor ITE SuperI/O detection/access
by Carl-Daniel Hailfinger 23 Dec '09

23 Dec '09

Refactor ITE SuperI/O detection/access. The new code reduces duplications and paves the way for generic SuperI/O detection. Additional cost: We enter/exit the SuperI/O configuration mode twice. Once for detecting which SuperI/O it is, and once for actually changing the settings. Additional benefit: This has the potential of allowing some sort of primitive laptop detection (by way of checking whether an EC or a simple SuperI/O is present). I have added a call to a not yet implemented Winbond SuperI/O detection function inside #if 0 to make extension more straighforward. This affects most SiS chipsets and IT87 SPI translation, so tests in verbose mode would be appreciated. In theory, functionality should be unchanged. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-superio_ite_refactor/flash.h =================================================================== --- flashrom-superio_ite_refactor/flash.h (Revision 761) +++ flashrom-superio_ite_refactor/flash.h (Arbeitskopie) @@ -388,6 +388,11 @@ #endif /* internal.c */ +struct superio { + uint16_t vendor; + uint16_t port; + uint16_t model; +}; struct pci_dev *pci_dev_find_filter(struct pci_filter filter); struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class); struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); @@ -395,6 +400,7 @@ uint16_t card_vendor, uint16_t card_device); void get_io_perms(void); void release_io_perms(void); +struct superio probe_superio(void); int internal_init(void); int internal_shutdown(void); void internal_chip_writeb(uint8_t val, chipaddr addr); @@ -611,9 +617,12 @@ int ich_spi_send_multicommand(struct spi_command *cmds); /* it87spi.c */ +#define SUPERIO_VENDOR_NONE 0x0 +#define SUPERIO_VENDOR_ITE 0x1 extern uint16_t it8716f_flashport; void enter_conf_mode_ite(uint16_t port); void exit_conf_mode_ite(uint16_t port); +struct superio probe_superio_ite(void); int it87spi_init(void); int it87xx_probe_spi_flash(const char *name); int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, Index: flashrom-superio_ite_refactor/it87spi.c =================================================================== --- flashrom-superio_ite_refactor/it87spi.c (Revision 761) +++ flashrom-superio_ite_refactor/it87spi.c (Arbeitskopie) @@ -54,19 +54,56 @@ sio_write(port, 0x02, 0x02); } -static uint16_t find_ite_spi_flash_port(uint16_t port) +uint16_t probe_id_ite(uint16_t port) { - uint8_t tmp = 0; - char *portpos = NULL; - uint16_t id, flashport = 0; + uint16_t id; enter_conf_mode_ite(port); - id = sio_read(port, CHIP_ID_BYTE1_REG) << 8; id |= sio_read(port, CHIP_ID_BYTE2_REG); + exit_conf_mode_ite(port); - /* TODO: Handle more IT87xx if they support flash translation */ - if (0x8716 == id || 0x8718 == id) { + return id; +} + +struct superio probe_superio_ite(void) +{ + struct superio ret = {}; + uint16_t ite_ports[] = {ITE_SUPERIO_PORT1, ITE_SUPERIO_PORT2, 0}; + uint16_t *i = ite_ports; + + i++; + ret.vendor = SUPERIO_VENDOR_ITE; + for (; *i; i++) { + ret.port = *i; + ret.model = probe_id_ite(ret.port); + switch (ret.model >> 8) { + case 0x82: + case 0x86: + case 0x87: + printf_debug("Found ITE SuperI/O, id %04hx\n", + ret.model); + return ret; + } + } + + /* No good ID found. */ + ret.vendor = SUPERIO_VENDOR_NONE; + ret.port = 0; + ret.model = 0; + return ret; +} + +static uint16_t find_ite_spi_flash_port(uint16_t port, uint16_t id) +{ + uint8_t tmp = 0; + char *portpos = NULL; + uint16_t flashport = 0; + + switch (id) { + case 0x8716: + case 0x8718: + enter_conf_mode_ite(port); /* NOLDN, reg 0x24, mask out lowest bit (suspend) */ tmp = sio_read(port, 0x24) & 0xFE; printf("Serial flash segment 0x%08x-0x%08x %sabled\n", @@ -105,18 +142,26 @@ sio_write(port, 0x64, (flashport >> 8)); sio_write(port, 0x65, (flashport & 0xff)); } + exit_conf_mode_ite(port); + break; + /* TODO: Handle more IT87xx if they support flash translation */ + default: + printf("SuperI/O ID %04hx is not on the controller list.\n", id); } - exit_conf_mode_ite(port); return flashport; } int it87spi_common_init(void) { - it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT1); - if (!it8716f_flashport) - it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT2); + struct superio superio; + superio = probe_superio_ite(); + if (superio.vendor == SUPERIO_VENDOR_NONE) + return 1; + + it8716f_flashport = find_ite_spi_flash_port(superio.port, superio.model); + if (it8716f_flashport) spi_controller = SPI_CONTROLLER_IT87XX; Index: flashrom-superio_ite_refactor/chipset_enable.c =================================================================== --- flashrom-superio_ite_refactor/chipset_enable.c (Revision 761) +++ flashrom-superio_ite_refactor/chipset_enable.c (Arbeitskopie) @@ -225,37 +225,40 @@ return ret; } -static int enable_flash_sis630(struct pci_dev *dev, const char *name) +static int enable_flash_decode_superio(void) { + int ret; uint8_t tmp; - uint16_t siobase; - int ret; + struct superio superio; - ret = enable_flash_sis540(dev, name); - - /* The same thing on SiS 950 Super I/O side... */ - - /* First probe for Super I/O on config port 0x2e. */ - siobase = 0x2e; - enter_conf_mode_ite(siobase); - - if (INB(siobase + 1) != 0x87) { - /* If that failed, try config port 0x4e. */ - siobase = 0x4e; - enter_conf_mode_ite(siobase); - if (INB(siobase + 1) != 0x87) { - printf("Can not find SuperI/O.\n"); - return -1; - } + superio = probe_superio(); + switch (superio.vendor) { + case SUPERIO_VENDOR_NONE: + ret = -1; + break; + case SUPERIO_VENDOR_ITE: + enter_conf_mode_ite(superio.port); + /* Enable flash mapping. Works for most old ITE style SuperI/O. */ + tmp = sio_read(superio.port, 0x24); + tmp |= 0xfc; + sio_write(superio.port, 0x24, tmp); + exit_conf_mode_ite(superio.port); + ret = 0; + break; + default: + printf_debug("Unhandled SuperI/O type!\n"); + ret = -1; + break; } + return ret; +} - /* Enable flash mapping. Works for most old ITE style SuperI/O. */ - tmp = sio_read(siobase, 0x24); - tmp |= 0xfc; - sio_write(siobase, 0x24, tmp); +static int enable_flash_sis630(struct pci_dev *dev, const char *name) +{ + int ret; - exit_conf_mode_ite(siobase); - + ret = enable_flash_sis540(dev, name); + ret |= enable_flash_decode_superio(); return ret; } Index: flashrom-superio_ite_refactor/internal.c =================================================================== --- flashrom-superio_ite_refactor/internal.c (Revision 761) +++ flashrom-superio_ite_refactor/internal.c (Arbeitskopie) @@ -122,6 +122,18 @@ #endif } +struct superio probe_superio(void) +{ + struct superio superio; + + superio = probe_superio_ite(); +#if 0 /* Winbond SuperI/O code is not yet available. */ + if (superio.vendor == SUPERIO_VENDOR_NONE) + superio = probe_superio_winbond(); +#endif + return superio; +} + int internal_init(void) { int ret = 0; -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

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flashrom December 2009