Patch for Macronix MX77L25650F
Read/Erase/Write tested
Datasheet (of 128Mbit part. 256Mbit not public) - https://www.macronix.com/Lists/Datasheet/Attachments/8760/MX77L12850F,%203V, %20128Mb,%20v1.2.pdf
ID is 1 higher than that variant (memory density)
_______________________________
From 945fc85e1a0f1884644df6f6d82e2403b70d3726 Mon Sep 17 00:00:00 2001
From: ServError 1589596+ServError@users.noreply.github.com
Date: Sun, 11 Jun 2023 02:19:32 -0400
Subject: [PATCH] Add support for Macronix MX77L25650F
---
flashchips.c | 40 ++++++++++++++++++++++++++++++++++++++++
include/flashchips.h | 2 ++
2 files changed, 42 insertions(+)
diff --git a/flashchips.c b/flashchips.c
index 3e19659c..32135995 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -10610,6 +10610,46 @@ const struct flashchip flashchips[] = {
.voltage = {2700, 3600},
},
+ {
+ .vendor = "Macronix",
+ .name = "MX77L25650F",
+ .bustype = BUS_SPI,
+ .manufacture_id = MACRONIX_ID,
+ .model_id = MACRONIX_MX77L25650F,
+ .total_size = 32768,
+ .page_size = 256,
+ /* OTP: 512B total; enter 0xB1, exit 0xC1 */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA,
+ .tested = TEST_OK_PREW,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 8192} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 1024} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 512} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ .eraseblocks = { {32 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ .eraseblocks = { {32 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ }
+ },
+ /* TODO: security register and SBLK/SBULK, configuration register */
+ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */
+ .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD,
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ, /* Fast read (0x0B) supported */
+ .voltage = {2700, 3600},
+ },
+
/* The ST M25P05 is a bit of a problem. It has the same ID as the
* ST M25P05-A in RES mode, but supports only 128 byte writes instead
* of 256 byte writes. We rely heavily on the fact that PROBE_SPI_RES1
diff --git a/include/flashchips.h b/include/flashchips.h
index dc4a0595..829c4141 100644
--- a/include/flashchips.h
+++ b/include/flashchips.h
@@ -581,6 +581,8 @@
#define MACRONIX_MX29SL800CB 0x6B /* Same as MX29SL802CB */
#define MACRONIX_MX29SL800CT 0xEA /* Same as MX29SL802CT */
+#define MACRONIX_MX77L25650F 0x7519
+
/* Nantronics Semiconductors is listed in JEP106AJ in bank 7, so it should have 6 continuation codes in front
* of the manufacturer ID of 0xD5. http://www.nantronicssemi.com */
#define NANTRONICS_ID 0x7F7F7F7F7F7FD5 /* Nantronics */
Hello, thank you for the patch! There is currently a patch under review adding the same chip: https://review.coreboot.org/c/flashrom/+/68557 Do you have a Gerrit account? If yes, you can add yourself to the patch and watch the progress. If not, just check the link. I see your patch has more, so the end result would probably be combining the two.
In general, we do code reviews in Gerrit (not the mailing list). Even if you send a patch on a mailing list, someone needs to push it to Gerrit to continue. Another thing is: commit message required to have a Signed-off-by line. You don't need to push this patch (since there is already the same chip under review), but for future if you would try to push to gerrit next time, that would be great!
https://www.flashrom.org/Development_Guidelines
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Anastasia Klimchuk