Good morning,
I am trying to revive a computer which had a failed BIOS update.
I bought a BUS Pirate and started using Flashrom to take a copy of an identical fully working model. Strangely this machine has two chips:
MX25L6405D MX25L3205D
From the dump's I have made, I believe the MX25L6405D holds the BIOS and the MX25L3205D possibly holds the ME Firmware.
Don't know if this is any use but an output from fptw64 on the working machine shows me the following:
C:\FPTw64>fptw64.exe -i
Intel (R) Flash Programming Tool. Version: 8.0.10.1464 Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.
Platform: Intel(R) Q77 Express Chipset Reading HSFSTS register... Flash Descriptor: Valid
--- Flash Devices Found --- MX25L6405D ID:0xC22017 Size: 8192KB (65536Kb) MX25L3205D ID:0xC22016 Size: 4096KB (32768Kb)
--- Flash Image Information -- Signature: VALID Number of Flash Components: 2 Component 1 - 8192KB (65536Kb) Component 2 - 4096KB (32768Kb) Regions: Descriptor - Base: 0x000000, Limit: 0x000FFF BIOS - Base: 0x600000, Limit: 0xBFFFFF ME - Base: 0x005000, Limit: 0x5FFFFF GbE - Base: 0x001000, Limit: 0x004FFF PDR - Not present Master Region Access: CPU/BIOS - ID: 0x0000, Read: 0x0B, Write: 0x0A ME - ID: 0x0000, Read: 0x0D, Write: 0x0C GbE - ID: 0x0118, Read: 0x08, Write: 0x08
Total Accessable SPI Memory: 12288KB, Total Installed SPI Memory : 12288KB
I am struggling to properly erase/write to both of these chips so I wondered if you could offer any advise on trying to get this working?
These are the errors I am getting on both chips, have tried with both Linux and Windows on each chip and get pretty much the same output:
flashrom v0.9.7-r1711 on Linux 3.14.48-std454-amd64 (x86_64) flashrom was built with libpci 3.2.0, GCC 4.8.4, little endian Command line (8 args): flashrom -p buspirate_spi:dev=/dev/ttyUSB0, -c MX25L6405(D) -E -V -o /media/usb/log2.txt Calibrating delay loop... OS timer resolution is 1 usecs, 1456M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 997 us, 10000 myus = 9996 us, 4 myus = 4 us, OK. Initializing buspirate_spi programmer Baud rate is 115200. Detected Bus Pirate hardware v3.a Detected Bus Pirate firmware 6.3 ("v6.3-beta1") Using SPI command set v2. SPI speed is 8MHz Raw bitbang mode version 1 Raw SPI mode version 1 The following protocols are supported: SPI. Probing for Macronix MX25L6405(D), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on buspirate_spi. Chip status register is 0x80. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is set Chip status register: Bit 6 is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Block protection is disabled. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x00ffff:EFAILED at 0x00001000! Expected=0xff, Found=0x90, failed byte count from 0x00000000-0x0000ffff: 0x3aa8 ERASE FAILED! Reading current flash chip contents...
At one point the above was the same output as below that everything was set but still failed on "unsetting lock bits" but I have forgotten to save that output.
flashrom was built with GCC 4.9.2, little endian Command line (6 args): flashrom -p buspirate_spi:dev=COM3 -c MX25L3205D/MX25L3208D -E -V Calibrating delay loop... OS timer resolution is 501 usecs, 1771M loops per second, 10 myus = 0 us, 100 myus = 0 us, 1000 myus = 1000 us, 10000 myus = 10008 us, 2004 myus = 2002 us, OK. Initializing buspirate_spi programmer Baud rate is 115200. Detected Bus Pirate hardware v3.a Detected Bus Pirate firmware 6.3 Using SPI command set v2. SPI speed is 8MHz Raw bitbang mode version 1 Raw SPI mode version 1 The following protocols are supported: SPI. Probing for Macronix MX25L3205D/MX25L3208D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Found Macronix flash chip "MX25L3205D/MX25L3208D" (4096 kB, SPI) on buspirate_spi. Chip status register is 0xff. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is set Chip status register: Bit 6 is set Chip status register: Block Protect 3 (BP3) is set Chip status register: Block Protect 2 (BP2) is set Chip status register: Block Protect 1 (BP1) is set Chip status register: Block Protect 0 (BP0) is set Chip status register: Write Enable Latch (WEL) is set Chip status register: Write In Progress (WIP/BUSY) is set This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Some block protection in effect, disabling... Need to disable the register lock first... Unsetting lock bit(s) failed. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:EFAILED at 0x00000000! Expected=0xff, Found=0xe8, failed byte count from 0x00000000-0x00000fff: 0x1000 ERASE FAILED! Reading current flash chip contents... ^C
This is a link to the datasheet for both chips : http://www.macronix.com/Lists/DataSheet/Attachments/2453/MX25L6405D,%203V,%2...
It mentions something about having to give 9.5v-10.5v to the WP pin so maybe that is the problem? does this mean i would have to externally source this voltage outside of bus pirate to enable write enable properly?
Many Thanks
On Tue, 4 Aug 2015 08:57:58 +0100 Adam Clarke adam@ajclarke.co.uk wrote:
Good morning,
I am trying to revive a computer which had a failed BIOS update.
I bought a BUS Pirate and started using Flashrom to take a copy of an identical fully working model. Strangely this machine has two chips:
MX25L6405D MX25L3205D
From the dump's I have made, I believe the MX25L6405D holds the BIOS and the MX25L3205D possibly holds the ME Firmware.
Yes, that's about right. The CPU sees only the combined address range of both chips. The BIOS region actually spans both... a rather unusual setup AFAIK but that's not the main problem here (yet). I wrote a blog post about some details of that dual-chip setup a few years ago... http://blogs.coreboot.org/blog/2011/06/11/gsoc-2011-flashrom-part-1/
Either the board is powered enough so that the ME interferes, or there is not enough power from the BP to power the chip because other components suck energy as well, or there are other problems as mentioned on http://www.flashrom.org/ISP