It looks like running your patch disturbed the SPI controller's internal state. I'm not able to write to flash using either your patch or the old patch now, as during chip erasing, flashrom expected 0xff but read something else.
On Thu, Aug 8, 2013 at 5:15 PM, Wei Hu wei@aristanetworks.com wrote:
Stefan,
Thanks for your great work. I just tested it on AMD Olive Hill, and found a few issues.
- Your patch defaults SPI clock to 16.5 MHz, which didn't work. I
also found none of 22, 33, 100 MHz worked. Only passing -p internal:spispeed="66 MHz" worked.
- Reading is much faster than my/Carl's patch, but some bits were
incorrect. The speedup must have come from your use of the now longer FIFO, but why is it reading bad values?