[patch] mark PMC Pm49FL004, SST SST49LF002, SST SST49LF004 and Winbond_W39V040FB as write tested

[Idwer Vollering]

Signed-off-by: Idwer Vollering

Index: flashchips.c
===================================================================
--- flashchips.c        (revision 1261)
+++ flashchips.c        (working copy)
@@ -4933,7 +4933,7 @@
                .total_size     = 512,
                .page_size      = 64 * 1024,
                .feature_bits   = FEATURE_REGISTERMAP | FEATURE_EITHER_RESET,
-               .tested         = TEST_OK_PRE,
+               .tested         = TEST_OK_PREW,
                .probe          = probe_jedec,
                .probe_timing   = TIMING_ZERO,  /* routine is wrapper
to probe_jedec (pm49fl00x.c) */
                .block_erasers  =
@@ -5804,7 +5804,7 @@
                .total_size     = 256,
                .page_size      = 16 * 1024,
                .feature_bits   = FEATURE_REGISTERMAP | FEATURE_EITHER_RESET,
-               .tested         = TEST_OK_PRE,
+               .tested         = TEST_OK_PREW,
                .probe          = probe_jedec,
                .probe_timing   = 1,            /* 150 ns */
                .block_erasers  =
@@ -5869,7 +5869,7 @@
                .total_size     = 512,
                .page_size      = 64 * 1024,
                .feature_bits   = FEATURE_REGISTERMAP | FEATURE_EITHER_RESET,
-               .tested         = TEST_OK_PRE,
+               .tested         = TEST_OK_PREW,
                .probe          = probe_jedec,
                .probe_timing   = 1,            /* 150 ns */
                .block_erasers  =
@@ -7939,7 +7939,7 @@
                .total_size     = 512,
                .page_size      = 64 * 1024,
                .feature_bits   = FEATURE_REGISTERMAP | FEATURE_EITHER_RESET,
-               .tested         = TEST_OK_PRE,
+               .tested         = TEST_OK_PREW,
                .probe          = probe_jedec,
                .probe_timing   = 10,
                .block_erasers  =

---

flashrom v0.9.3-r1261 on Linux 2.6.37-ARCH (i686), built with libpci
3.1.7, GCC 4.5.2 20110127 (prerelease), little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... delay loop is unreliable, trying to continue OK.
No coreboot table found.
Found chipset "Intel ICH5/ICH5R", enabling flash write... OK.
This chipset supports the following protocols: FWH.
Disabling flash write protection for board "ASUS P4P800-VM"... OK.
Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000.
===
This flash part has status UNTESTED for operations: WRITE
The test status of this chip may have been updated in the latest development
version of flashrom. If you are running the latest development version,
please email a report to [e-mail] if any of the above operations
work correctly for you with this flash part. Please include the flashrom
output with the additional -V option for all operations you tested (-V, -Vr,
-Vw, -VE), and mention which mainboard or programmer you tested.
Please mention your board in the subject line. Thanks for your help!
Flash image seems to be a legacy BIOS. Disabling checks.
Erasing and writing flash chip... Done.
Verifying flash... VERIFIED.

flashrom v0.9.3-r1261 on Linux 2.6.37-ARCH (i686), built with libpci
3.1.7, GCC 4.5.2 20110127 (prerelease), little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... delay loop is unreliable, trying to continue OK.
No coreboot table found.
Found chipset "Intel ICH5/ICH5R", enabling flash write... OK.
This chipset supports the following protocols: FWH.
Disabling flash write protection for board "ASUS P4P800-VM"... OK.
Found chip "SST SST49LF002A/B" (256 KB, FWH) at physical address 0xfffc0000.
===
This flash part has status UNTESTED for operations: WRITE
The test status of this chip may have been updated in the latest development
version of flashrom. If you are running the latest development version,
please email a report to [e-mail] if any of the above operations
work correctly for you with this flash part. Please include the flashrom
output with the additional -V option for all operations you tested (-V, -Vr,
-Vw, -VE), and mention which mainboard or programmer you tested.
Please mention your board in the subject line. Thanks for your help!
Flash image seems to be a legacy BIOS. Disabling checks.
Erasing and writing flash chip... Done.
Verifying flash... VERIFIED.

flashrom v0.9.3-r1261 on Linux 2.6.37-ARCH (i686), built with libpci
3.1.7, GCC 4.5.2 20110127 (prerelease), little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel ICH5/ICH5R", enabling flash write... OK.
This chipset supports the following protocols: FWH.
Disabling flash write protection for board "ASUS P4P800-VM"... OK.
Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000.
===
This flash part has status UNTESTED for operations: WRITE
The test status of this chip may have been updated in the latest development
version of flashrom. If you are running the latest development version,
please email a report to [e-mail] if any of the above operations
work correctly for you with this flash part. Please include the flashrom
output with the additional -V option for all operations you tested (-V, -Vr,
-Vw, -VE), and mention which mainboard or programmer you tested.
Please mention your board in the subject line. Thanks for your help!
Flash image seems to be a legacy BIOS. Disabling checks.
Erasing and writing flash chip... Done.
Verifying flash... VERIFIED.

flashrom v0.9.3-r1261 on Linux 2.6.37-ARCH (i686), built with libpci
3.1.7, GCC 4.5.2 20110127 (prerelease), little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel ICH5/ICH5R", enabling flash write... OK.
This chipset supports the following protocols: FWH.
Disabling flash write protection for board "ASUS P4P800-VM"... OK.
Found chip "Winbond W39V040FB" (512 KB, FWH) at physical address 0xfff80000.
===
This flash part has status UNTESTED for operations: WRITE
The test status of this chip may have been updated in the latest development
version of flashrom. If you are running the latest development version,
please email a report to [e-mail] if any of the above operations
work correctly for you with this flash part. Please include the flashrom
output with the additional -V option for all operations you tested (-V, -Vr,
-Vw, -VE), and mention which mainboard or programmer you tested.
Please mention your board in the subject line. Thanks for your help!
Flash image seems to be a legacy BIOS. Disabling checks.
Erasing and writing flash chip... Done.
Verifying flash... VERIFIED.

[Carl-Daniel Hailfinger]

Thanks for your patch!

Auf 20.02.2011 22:51, Idwer Vollering schrieb:
> Signed-off-by: Idwer Vollering

Acked-by: Carl-Daniel Hailfinger

Can you commit?

Regards,
Carl-Daniel

[Idwer Vollering]

2011/3/4 Carl-Daniel Hailfinger
> Thanks for your patch!
>
> Auf 20.02.2011 22:51, Idwer Vollering schrieb:
> > Signed-off-by: Idwer Vollering
>
> Acked-by: Carl-Daniel Hailfinger
>
> Can you commit?

No (not yet.. ?).
Aren't patches that update the status of a chip/board collected and
committed once in a while ?
> Regards,
> Carl-Daniel

[Carl-Daniel Hailfinger]

Auf 06.03.2011 13:21, Idwer Vollering schrieb:
> > Thanks for your patch!
> > > Auf 20.02.2011 22:51, Idwer Vollering schrieb:
> > > > > Signed-off-by: Idwer Vollering
> > >
> > > Acked-by: Carl-Daniel Hailfinger
> > >
> > > Can you commit?
>
> No (not yet.. ?).

Committed in r1272.
> Aren't patches that update the status of a chip/board collected and
> committed once in a while ?

I decided to stop collecting this stuff because merging different
patches is harder than just committing them one at a time.
Reports without patches can still be put together into one changeset,
but if someone submits a patch, he/she should get credited for that.

Regards,
Carl-Daniel