Only call path where exit is reached is from physmap().
Callers of physmap() that where not prepared to handle the ERROR_PTR return value have been handled.
Signed-off-by: Niklas Söderlund niso@kth.se --- chipset_enable.c | 6 ++++++ drkaiser.c | 2 ++ gfxnvidia.c | 2 ++ ichspi.c | 2 ++ it85spi.c | 2 ++ mcp6x_spi.c | 2 ++ nicintel_spi.c | 2 ++ ogp_spi.c | 2 ++ physmap.c | 12 +++--------- satasii.c | 2 ++ sb600spi.c | 2 ++ 11 files changed, 27 insertions(+), 9 deletions(-)
diff --git a/chipset_enable.c b/chipset_enable.c index fa79511..b1738ea 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -494,6 +494,8 @@ static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name)
/* Map RCBA to virtual memory */ rcrb = physmap("ICH RCRB", tmp, 0x4000); + if (rcrb == ERROR_PTR) + return ERROR_FATAL;
/* Test Boot BIOS Strap Status */ bnt = mmio_readl(rcrb + 0x3410); @@ -565,6 +567,8 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
/* Map RCBA to virtual memory */ rcrb = physmap("ICH RCRB", tmp, 0x4000); + if (rcrb == ERROR_PTR) + return ERROR_FATAL;
gcs = mmio_readl(rcrb + 0x3410); msg_pdbg("GCS = 0x%x: ", gcs); @@ -1235,6 +1239,8 @@ static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
/* 1. Map MMCR */ mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize()); + if (mmcr == ERROR_PTR) + return -1;
/* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for * BOOTCS region (PARx[31:29] = 100b)e diff --git a/drkaiser.c b/drkaiser.c index 83b8b3d..71981e8 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -82,6 +82,8 @@ int drkaiser_init(void) /* Map 128kB flash memory window. */ drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory", addr, DRKAISER_MEMMAP_SIZE); + if (drkaiser_bar == ERROR_PTR) + return 1;
if (register_shutdown(drkaiser_shutdown, NULL)) return 1; diff --git a/gfxnvidia.c b/gfxnvidia.c index 9232677..9600675 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -102,6 +102,8 @@ int gfxnvidia_init(void) msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr);
nvidia_bar = physmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE); + if (nvidia_bar == ERROR_PTR) + return 1;
/* Must be done before rpci calls. */ if (register_shutdown(gfxnvidia_shutdown, NULL)) diff --git a/ichspi.c b/ichspi.c index bbe2b06..f6b77ad 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1836,6 +1836,8 @@ int via_init_spi(struct pci_dev *dev, uint32_t mmio_base) int i;
ich_spibar = physmap("VIA SPI MMIO registers", mmio_base, 0x70); + if (ich_spibar == ERROR_PTR) + return ERROR_FATAL; /* Do we really need no write enable? Like the LPC one at D17F0 0x40 */
/* Not sure if it speaks all these bus protocols. */ diff --git a/it85spi.c b/it85spi.c index 0b074eb..e15a287 100644 --- a/it85spi.c +++ b/it85spi.c @@ -262,6 +262,8 @@ static int it85xx_spi_common_init(struct superio s) * Major TODO here, and it will be a lot of work. */ base = (chipaddr)physmap("it85 communication", 0xFFFFF000, 0x1000); + if (base == ERROR_PTR) + return 1; msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, (unsigned int)base); ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */ diff --git a/mcp6x_spi.c b/mcp6x_spi.c index ac40557..438e661 100644 --- a/mcp6x_spi.c +++ b/mcp6x_spi.c @@ -149,6 +149,8 @@ int mcp6x_spi_init(int want_spi) } /* Map the BAR. Bytewise/wordwise access at 0x530 and 0x540. */ mcp6x_spibar = physmap("NVIDIA MCP6x SPI", mcp6x_spibaraddr, 0x544); + if (mcp6x_spibar == ERROR_PTR) + return 1;
#if 0 /* FIXME: Run the physunmap in a shutdown function. */ diff --git a/nicintel_spi.c b/nicintel_spi.c index 72b470b..6dc40f5 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -178,6 +178,8 @@ int nicintel_spi_init(void)
nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, MEMMAP_SIZE); + if (nicintel_spibar == ERROR_PTR) + return 1; /* Automatic restore of EECD on shutdown is not possible because EECD * does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED, * but other bits with side effects as well. Those other bits must be diff --git a/ogp_spi.c b/ogp_spi.c index 9b596bf..b3963c2 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -138,6 +138,8 @@ int ogp_spi_init(void) return 1;
ogp_spibar = physmap("OGP registers", io_base_addr, 4096); + if (ogp_spibar == ERROR_PTR) + return 1;
if (register_shutdown(ogp_spi_shutdown, NULL)) return 1; diff --git a/physmap.c b/physmap.c index adce315..35dcfb8 100644 --- a/physmap.c +++ b/physmap.c @@ -211,13 +211,11 @@ void physunmap(void *virt_addr, size_t len) } #endif
-#define PHYSMAP_NOFAIL 0 -#define PHYSMAP_MAYFAIL 1 #define PHYSMAP_RW 0 #define PHYSMAP_RO 1
static void *physmap_common(const char *descr, unsigned long phys_addr, - size_t len, int mayfail, int readonly) + size_t len, int readonly) { void *virt_addr;
@@ -261,8 +259,6 @@ static void *physmap_common(const char *descr, unsigned long phys_addr, "and reboot, or reboot into\n" "single user mode.\n"); #endif - if (!mayfail) - exit(3); }
return virt_addr; @@ -270,14 +266,12 @@ static void *physmap_common(const char *descr, unsigned long phys_addr,
void *physmap(const char *descr, unsigned long phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSMAP_NOFAIL, - PHYSMAP_RW); + return physmap_common(descr, phys_addr, len, PHYSMAP_RW); }
void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len) { - return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, - PHYSMAP_RO); + return physmap_common(descr, phys_addr, len, PHYSMAP_RO); }
#if defined(__i386__) || defined(__x86_64__) diff --git a/satasii.c b/satasii.c index 838fff4..9f9bb7f 100644 --- a/satasii.c +++ b/satasii.c @@ -97,6 +97,8 @@ int satasii_init(void) }
sii_bar = physmap("SATA SiI registers", addr, SATASII_MEMMAP_SIZE) + reg_offset; + if (sii_bar == ERROR_PTR) + return 1;
/* Check if ROM cycle are OK. */ if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26)))) diff --git a/sb600spi.c b/sb600spi.c index fe60aa9..a4ca20b 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -226,6 +226,8 @@ int sb600_probe_spi(struct pci_dev *dev) /* Physical memory has to be mapped at page (4k) boundaries. */ sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); + if (sb600_spibar == ERROR_PTR) + return ERROR_FATAL; /* The low bits of the SPI base address are used as offset into * the mapped page. */
On Thu, 8 Nov 2012 23:34:56 +0100 Niklas Söderlund niso@kth.se wrote:
Only call path where exit is reached is from physmap().
Callers of physmap() that where not prepared to handle the ERROR_PTR return value have been handled.
Signed-off-by: Niklas Söderlund niso@kth.se
Hi again,
I had to rework this patch a bit because many callers where modified already and physmap_common got new features in the meantime. Acked-by: Stefan Tauner stefan.tauner@student.tuwien.ac.at and committed in r1745. Thanks!
-
Niklas Söderlund -
Stefan Tauner