Re: [flashrom] [PATCH] Board enable for Samsung Polaris 32

[Carl-Daniel Hailfinger]

Hi Alex,

did Michael's patch work for you?

On 12.07.2010 17:42, Michael Karcher wrote:
> lspci/superiotool:
> http://www.coreboot.org/pipermail/flashrom/2010-July/003889.html
>
> Signed-off-by: Michael Karcher

Regards,
Carl-Daniel

[PATCH] Board enable for Samsung Polaris 32

[Alex Loktionoff]

YEA! IT WORKS!

Please include this patch in release, I want to use it in Ubuntu just by apt-get.

I downloaded SRC from SVN, manually added just two lines of data in two .C files
Here in Korea I saw also another "Polaris-32" M/B, it's not SAMSUNG.
I think Polaris-32 made some small company as outsource.

Thank you for the support.
You guys work fast, I just had no time to check it.

Here is the dump:

<>
root@AXP:/home/love/tmp/flashrom# ./flashrom -r original.rom 
flashrom v0.9.2-r1091 on Linux 2.6.31-22-generic (i686), built with libpci 3.0.0, GCC 
4.4.1, little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel ICH5/ICH5R", enabling flash write... OK.
This chipset supports the following protocols: FWH.
Disabling flash write protection for board "Samsung Polaris 32"... OK.
Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000.
Reading flash... done.
root@AXP:/home/love/tmp/flashrom# 
root@AXP:/home/love/tmp/flashrom# 
root@AXP:/home/love/tmp/flashrom# ./flashrom -w original.rom 
flashrom v0.9.2-r1091 on Linux 2.6.31-22-generic (i686), built with libpci 3.0.0, GCC 
4.4.1, little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel ICH5/ICH5R", enabling flash write... OK.
This chipset supports the following protocols: FWH.
Disabling flash write protection for board "Samsung Polaris 32"... OK.
Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000.
Flash image seems to be a legacy BIOS. Disabling checks.
Writing flash chip... Erasing flash chip... SUCCESS.
Programming page: DONE!ss: 0x0007f000
COMPLETE.
Verifying flash... VERIFIED.          
root@AXP:/home/love/tmp/flashrom# 
</>

Thu, 15 Jul 2010 00:55:55 +0200 п©п╦я│я▄п╪п╬ п╬я┌ Carl-Daniel Hailfinger <c-
[e-mail]>:
> Hi Alex,
>
> did Michael's patch work for you?
>
> On 12.07.2010 17:42, Michael Karcher wrote:
> > lspci/superiotool:
> > http://www.coreboot.org/pipermail/flashrom/2010-July/003889.html
> >
> > Signed-off-by: Michael Karcher
>
> Regards,
> Carl-Daniel

п╒п╣я│я┌я▀ п╫п╬п╡п╣п╧я┬п╦я┘ пЁп╟п╢п╤п╣я┌п╬п╡ п╫п╟ Hi-tech.Mail.Ru
http://r.mail.ru/cln5823/hi-tech.mail.ru/

[PATCH] Board enable for Samsung Polaris 32

[Carl-Daniel Hailfinger]

On 18.07.2010 07:23, Alex Loktionoff wrote:
> YEA! IT WORKS!
>
> Please include this patch in release, I want to use it in Ubuntu just by apt-get.

Great, thanks for checking.
Tested-by: Alex Loktionoff 
Acked-by: Carl-Daniel Hailfinger
> I downloaded SRC from SVN, manually added just two lines of data in two .C files
> Here in Korea I saw also another "Polaris-32" M/B, it's not SAMSUNG.
> I think Polaris-32 made some small company as outsource.
>
> Thank you for the support.
> You guys work fast, I just had no time to check it.
>
> Here is the dump:
>
> <>
> root@AXP:/home/love/tmp/flashrom# ./flashrom -r original.rom 
> flashrom v0.9.2-r1091 on Linux 2.6.31-22-generic (i686), built with libpci 3.0.0, GCC 
> 4.4.1, little endian
> flashrom is free software, get the source code at http://www.flashrom.org
>
> Calibrating delay loop... OK.
> No coreboot table found.
> Found chipset "Intel ICH5/ICH5R", enabling flash write... OK.
> This chipset supports the following protocols: FWH.
> Disabling flash write protection for board "Samsung Polaris 32"... OK.
> Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000.
> Reading flash... done.
> root@AXP:/home/love/tmp/flashrom# 
> root@AXP:/home/love/tmp/flashrom# 
> root@AXP:/home/love/tmp/flashrom# ./flashrom -w original.rom 
> flashrom v0.9.2-r1091 on Linux 2.6.31-22-generic (i686), built with libpci 3.0.0, GCC 
> 4.4.1, little endian
> flashrom is free software, get the source code at http://www.flashrom.org
>
> Calibrating delay loop... OK.
> No coreboot table found.
> Found chipset "Intel ICH5/ICH5R", enabling flash write... OK.
> This chipset supports the following protocols: FWH.
> Disabling flash write protection for board "Samsung Polaris 32"... OK.
> Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000.
> Flash image seems to be a legacy BIOS. Disabling checks.
> Writing flash chip... Erasing flash chip... SUCCESS.
> Programming page: DONE!ss: 0x0007f000
> COMPLETE.
> Verifying flash... VERIFIED.          
> root@AXP:/home/love/tmp/flashrom# 
> </>
>
> Thu, 15 Jul 2010 00:55:55 +0200 письмо от Carl-Daniel Hailfinger <c-
> [e-mail]>:
> > Hi Alex,
> >
> > did Michael's patch work for you?
> >
> > On 12.07.2010 17:42, Michael Karcher wrote:
> > > lspci/superiotool:
> > > http://www.coreboot.org/pipermail/flashrom/2010-July/003889.html
> > >
> > > Signed-off-by: Michael Karcher

Regards,
Carl-Daniel

[PATCH] Board enable for Samsung Polaris 32

[Michael Karcher]

Am Samstag, den 24.07.2010, 00:54 +0200 schrieb Carl-Daniel Hailfinger:
> On 18.07.2010 07:23, Alex Loktionoff wrote:
> > YEA! IT WORKS!
> >
> > Please include this patch in release, I want to use it in Ubuntu just by apt-get.
>
> Great, thanks for checking.
> Tested-by: Alex Loktionoff 
> Acked-by: Carl-Daniel Hailfinger

Thanks for testing and reviewing, this is now in r1107, and will be in
flashrom 0.9.3.

Regards,
  Michael Karcher