adds board enable for ABIT AV8 (first revision).
Signed-off-by: Christoph Grenz <christophg+cb at grenz-bonn.de>
Index: print.c =================================================================== --- print.c (Revision 1450) +++ print.c (Arbeitskopie) @@ -535,6 +535,7 @@ #if defined(__i386__) || defined(__x86_64__) B("A-Trend", "ATC-6220", 1, "http://www.motherboard.cz/mb/atrend/atc6220.htm", NULL), B("abit", "AN-M2", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=Y... M2", NULL), + B("abit", "AV8", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=Y...", NULL), B("abit", "AX8", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=Y...", NULL), B("abit", "BM6", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NAM...", NULL), B("abit", "Fatal1ty F-I90HD", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NAM... I90HD&fMTYPE=LGA775", NULL), Index: board_enable.c =================================================================== --- board_enable.c (Revision 1450) +++ board_enable.c (Arbeitskopie) @@ -1830,6 +1830,22 @@
/* * Suited for: + * - abit AV8 (first revision): Socket939 + K8T800Pro + VT8237 + */ +static int board_abit_av8_enable(void) +{ + uint8_t val; + + /* Enable board GPO ports GP22 & GP23 */ + val = INB(0x404E); + val |= 0xC0; + OUTB(val, 0x404E); + + return 0; +} + +/* + * Suited for: * - ASUS A7V333: VIA KT333 + VT8233A + IT8703F * - ASUS A7V8X: VIA KT400 + VT8235 + IT8703F */ @@ -1979,6 +1995,7 @@ /* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */ #if defined(__i386__) || defined(__x86_64__) {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, P3, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, + {0x1106, 0x0282, 0x147B, 0x1415, 0x1106, 0x3227, 0x147B, 0x1415, "^AV8 ", NULL, NULL, P3, "abit", "AV8", 0, OK, board_abit_av8_enable}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, P3, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower}, {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, P3, "abit", "IC7", 0, NT, intel_ich_gpio23_raise}, {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, P3, "abit", "IP35", 0, OK, intel_ich_gpio16_raise},
On Sat, 1 Oct 2011 08:04:44 +0200 Christoph Grenz christophg+cb@grenz-bonn.de wrote:
adds board enable for ABIT AV8 (first revision).
Signed-off-by: Christoph Grenz <christophg+cb at grenz-bonn.de>
hello christoph and thanks for the patch!
i guess you own such a board and have tested the board enable yourself? could you please provide a verbose log of its action? also we would like to see lspci -nn and lspci -xxnnvvv logs to verify that the pci ids are well chosen.
i cant really comment the enabling function itself besides that it maybe it would make sense to add a more general function to set/clear GPO on that chipset? though that is probably overkill yet.
how did you find out what to do? is there a public datasheet? etc. please tell us the story :)
btw i think we usually use the designation "rev. 1.0" (or whatever the vendor used) instead of "first revision". did you name it yourself like that or was it documented by abit that way?
Hello Stefan,
Am Donnerstag, 6. Oktober 2011, um 23:27:32 schrieb Stefan Tauner:
On Sat, 1 Oct 2011 08:04:44 +0200
Christoph Grenz christophg+cb@grenz-bonn.de wrote:
adds board enable for ABIT AV8 (first revision).
Signed-off-by: Christoph Grenz <christophg+cb at grenz-bonn.de>
hello christoph and thanks for the patch!
i guess you own such a board and have tested the board enable yourself? could you please provide a verbose log of its action? also we would like to see lspci -nn and lspci -xxnnvvv logs to verify that the pci ids are well chosen.
Yes, i own it and tested the board enable. The board's temporarily in use by a family member, but I can provide a verbose log in about a week. Ok, I'll append the lspci outputs for verification when I send the verbose log. (btw, I chose the pci ids by the K8 host bride (00:00.0) and the SuperIO ISA bridge)
i cant really comment the enabling function itself besides that it maybe it would make sense to add a more general function to set/clear GPO on that chipset? though that is probably overkill yet.
how did you find out what to do? is there a public datasheet? etc. please tell us the story :)
I disassembled the write enable and the write disable functions from the Award BIOS image and reconstructed C code to understand for myself what happens. (Only took me half a night, until this weekend I have semester break, so I had spare time ;-) )
The ABIT AV8 board uses both the VT8237 chipset write protection, which is already handled by the code in chipset_enable.c, and the write protection I handled in my patch, which apparently is connected to some GPIO ports. After reading the DSDT I found they were called GP22 und GP23 in a region called GPOB (0x404C-0x404F). I can't really tell which chip they are connected to and found no writes to the same region in another board enable function, so I didn't add a general function.
I attached the C code I reconstructed from the bios image to this mail.
btw i think we usually use the designation "rev. 1.0" (or whatever the vendor used) instead of "first revision". did you name it yourself like that or was it documented by abit that way?
I named it myself like that because I couldn't find any reference to a revision number by abit, but as there is a board AV8-3rd-Eye which slightly differs from the original AV8 and as I don't own it I couldn't test if it works the same way, so I just wanted to add an indicator which revision I tested on. So I could change it to "rev. 1.0" or omit it if that's better.
Kind regards, Christoph Grenz
Hello,
here the promised flashrom and lspci logs.
As I wrote earlier, the board enable simply sets two bits I could identify as GPIOs by their name in the DSDT.
All flashrom actions were done with an earlier erased rom chip.
Kind regards, Christoph Grenz
Am Donnerstag, 6. Oktober 2011, um 23:27:32 schrieb Stefan Tauner:
On Sat, 1 Oct 2011 08:04:44 +0200
Christoph Grenz christophg+cb@grenz-bonn.de wrote:
adds board enable for ABIT AV8 (first revision).
Signed-off-by: Christoph Grenz <christophg+cb at grenz-bonn.de>
hello christoph and thanks for the patch!
i guess you own such a board and have tested the board enable yourself? could you please provide a verbose log of its action? also we would like to see lspci -nn and lspci -xxnnvvv logs to verify that the pci ids are well chosen. [...]
On Thu, 13 Oct 2011 03:01:24 +0200 Christoph Grenz christophg+cb@grenz-bonn.de wrote:
Hello,
here the promised flashrom and lspci logs.
As I wrote earlier, the board enable simply sets two bits I could identify as GPIOs by their name in the DSDT.
All flashrom actions were done with an earlier erased rom chip.
thanks, looks good!
can you please... - drop the mentioning of "first revision" (maybe add "not AV8-3rd-Eye" or so to the commit log instead?), - rename board_abit_av8_enable to board_abit_av8 (yes, there are similar wrong names already there, sorry :) - remove "board" from /* Enable board GPO ports GP22 & GP23 */ if you also think it is (not) appropriate, - use tabs instead of spaces, - resend the patch as an attachment (got mangled previously)?
adds board enable for ABIT AV8.
I compared the download pages of both, abit AV8 and abit AV8-3rd Eye, and the BIOS downloads are the same. So it's save to assume that this board enable works on both revisions of abit AV8. (Tested on AV8)
Signed-off-by: Christoph Grenz <christophg+cb at grenz-bonn.de>
On 10/13/11 11:44 AM, Christoph Grenz wrote:
=================================================================== --- board_enable.c (Revision 1450) +++ board_enable.c (Arbeitskopie) @@ -1830,6 +1830,22 @@
/*
- Suited for:
- abit AV8: Socket939 + K8T800Pro + VT8237
- */
+static int board_abit_av8(void) +{
- uint8_t val;
- /* Raise GPO ports GP22& GP23 */
- val = INB(0x404E);
- val |= 0xC0;
- OUTB(val, 0x404E);
- return 0;
+}
It would be better to read out the GPIO base and use offsets to that instead of hard coding the IO address.
Am Donnerstag, 13. Oktober 2011, um 23:10:39 schrieb Stefan Reinauer:
It would be better to read out the GPIO base and use offsets to that instead of hard coding the IO address.
The IO address is hardcoded in the BIOS image and I couldn't find a reference to the base address besides in the DSDT, so it should always be the same. And IMO parsing the DSDT would be a little overkill.
On Fri, 14 Oct 2011 10:52:31 +0200 Christoph Grenz christophg+cb@grenz-bonn.de wrote:
Am Donnerstag, 13. Oktober 2011, um 23:10:39 schrieb Stefan Reinauer:
It would be better to read out the GPIO base and use offsets to that instead of hard coding the IO address.
The IO address is hardcoded in the BIOS image and I couldn't find a reference to the base address besides in the DSDT, so it should always be the same. And IMO parsing the DSDT would be a little overkill.
and, it is certainly good enough already to be committed. else it will sit forever in the queue like so many other patches i have cleaned up in the last months. criticism is valued (thanks for the suggestion stefan!), but i think it should go in now, hence Acked-by: Stefan Tauner stefan.tauner@student.tuwien.ac.at and committed in r1455.
Thanks for your contribution Christoph and gl in the current semester ;)
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Christoph Grenz -
Stefan Reinauer -
Stefan Tauner