Sometimes-working board submission: Siemens D2703

[Stefaan]

Hi!  I've just spent some quality time with my Siemens D2703-board.
Sometimes flashing works, sometimes it doesn't.  I've done lots of
power cycling and also soft reboots, changing and resetting BIOS
settings, ... but I could not discern a determining factor.

The short log of a working flash looks like this:
flashrom v0.9.1-r710
No coreboot table found.
Found chipset "AMD SB600", enabling flash write... OK.
This chipset supports the following protocols: LPC,FWH,SPI.
Calibrating delay loop... OK.
Found chip "Atmel AT26DF081A" (1024 KB, SPI) at physical address 0xfff00000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to [e-mail] if any of the above operations
work correctly for you with this flash part. Please include the flashrom
output with the additional -V option for all operations you tested (-V, -rV,
-wV, -EV), and mention which mainboard you tested. Thanks for your help!
===
Flash image seems to be a legacy BIOS. Disabling checks.
Writing flash chip... Erasing flash before programming... done.
Programming flash................................ done.
COMPLETE.
Verifying flash... VERIFIED.

The top verbose output of a working write looks like:
flashrom v0.9.1-r710
No coreboot table found.
Found chipset "AMD SB600", enabling flash write... SPI base address is
at 0xffefff80
AltSpiCSEnable=0, SpiRomEnable=0, AbortEnable=0
PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=0, SpiOpEnInLpcMode=0
SpiArbEnable=0, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1,
ArbWaitCount=4, SpiBridgeDisable=0, DropOneClkOnRd=0
GPIO11 used for SPI_DO
GPIO12 used for SPI_DI
GPIO31 used for GPIO
GPIO32 used for SPI_CS
GPIO47 used for SPI_CLK
ROM strap override is not active
OK.
This chipset supports the following protocols: LPC,FWH,SPI.
Calibrating delay loop... 451M loops per second, 100 myus = 185 us. OK.
Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type
LPC,FWH,SPI and chip bus type Parallel are incompatible.
Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type
LPC,FWH,SPI and chip bus type Parallel are incompatible.
...

The top verbose output of a non-working log:
flashrom v0.9.1-r710
No coreboot table found.
Found chipset "AMD SB600", enabling flash write... SPI base address is at 0x0
ROM strap override is not active
OK.
This chipset supports the following protocols: LPC,FWH.
Calibrating delay loop... 454M loops per second, 100 myus = 185 us. OK.
Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type LPC,FWH
and chip bus type Parallel are incompatible.
Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type LPC,FWH
and chip bus type Parallel are incompatible.
...

So somehow, SPI seems to be detected intermittently.  Retrying without
a reboot has never (up till now) solved the problem.

I hope my report is helpful.  If you desire any additional
information, you need only ask :)
Many thanks, I really like your flashrom project, and am looking
forward to using it more often,

Stefaan