Rudolf Marek added some preliminary DOS support to flashrom. He kindly gave me the tarball, and I tried to generate a patch from it. Any omissions are my fault.
If anyone wants a big (130 MB) tarball with cross compiler, matching libpci and other stuff, just ask me. The server hosting the tarball is has a transfer quota, and I'd rather avoid exhausting it with everybody downloading the thing in question.
(It's Rudolf's code, so I'll let him sign off on it.)
Index: hwaccess.c =================================================================== --- hwaccess.c (revision 927) +++ hwaccess.c (working copy) @@ -37,7 +37,7 @@ #elif defined(__FreeBSD__) || defined (__DragonFly__) if ((io_fd = open("/dev/io", O_RDWR)) < 0) { #else - if (iopl(3) != 0) { + if (0) { #endif fprintf(stderr, "ERROR: Could not get I/O privileges (%s).\n" "You need to be root.\n", strerror(errno)); Index: getopt.c =================================================================== --- getopt.c (revision 0) +++ getopt.c (revision 0) @@ -0,0 +1,709 @@ +/* Getopt for GNU. + NOTE: getopt is now part of the C library, so if you don't know what + "Keep this file name-space clean" means, talk to roland@gnu.ai.mit.edu + before changing it! + + Copyright (C) 1987, 88, 89, 90, 91, 92, 1993 + Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#ifndef __STDC__ +# ifndef const +# define const +# endif +#endif + +/* This tells Alpha OSF/1 not to define a getopt prototype in <stdio.h>. */ +#ifndef _NO_PROTO +#define _NO_PROTO +#endif + +#include <stdio.h> +#include <string.h> + +/* Comment out all this code if we are using the GNU C Library, and are not + actually compiling the library itself. This code is part of the GNU C + Library, but also included in many other GNU distributions. Compiling + and linking in this code is a waste when using the GNU C library + (especially if it is a shared library). Rather than having every GNU + program understand `configure --with-gnu-libc' and omit the object files, + it is simpler to just do this in the source for each such file. */ + +#if defined (_LIBC) || !defined (__GNU_LIBRARY__) + + +/* This needs to come after some library #include + to get __GNU_LIBRARY__ defined. */ +#ifdef __GNU_LIBRARY__ +/* Don't include stdlib.h for non-GNU C libraries because some of them + contain conflicting prototypes for getopt. */ +#include <stdlib.h> +#endif /* GNU C library. */ + +/* If GETOPT_COMPAT is defined, `+' as well as `--' can introduce a + long-named option. Because this is not POSIX.2 compliant, it is + being phased out. */ +/* #define GETOPT_COMPAT */ + +/* This version of `getopt' appears to the caller like standard Unix `getopt' + but it behaves differently for the user, since it allows the user + to intersperse the options with the other arguments. + + As `getopt' works, it permutes the elements of ARGV so that, + when it is done, all the options precede everything else. Thus + all application programs are extended to handle flexible argument order. + + Setting the environment variable POSIXLY_CORRECT disables permutation. + Then the behavior is completely standard. + + GNU application programs can use a third alternative mode in which + they can distinguish the relative order of options and other arguments. */ + +#include "getopt.h" + +/* For communication from `getopt' to the caller. + When `getopt' finds an option that takes an argument, + the argument value is returned here. + Also, when `ordering' is RETURN_IN_ORDER, + each non-option ARGV-element is returned here. */ + +char *optarg = 0; + +/* Index in ARGV of the next element to be scanned. + This is used for communication to and from the caller + and for communication between successive calls to `getopt'. + + On entry to `getopt', zero means this is the first call; initialize. + + When `getopt' returns EOF, this is the index of the first of the + non-option elements that the caller should itself scan. + + Otherwise, `optind' communicates from one call to the next + how much of ARGV has been scanned so far. */ + +/* XXX 1003.2 says this must be 1 before any call. */ +int optind = 0; + +/* The next char to be scanned in the option-element + in which the last option character we returned was found. + This allows us to pick up the scan where we left off. + + If this is zero, or a null string, it means resume the scan + by advancing to the next ARGV-element. */ + +static char *nextchar; + +/* Callers store zero here to inhibit the error message + for unrecognized options. */ + +int opterr = 1; + +/* Set to an option character which was unrecognized. + This must be initialized on some systems to avoid linking in the + system's own getopt implementation. */ + +#define BAD_OPTION '\0' +int optopt = BAD_OPTION; + +/* Describe how to deal with options that follow non-option ARGV-elements. + + If the caller did not specify anything, + the default is REQUIRE_ORDER if the environment variable + POSIXLY_CORRECT is defined, PERMUTE otherwise. + + REQUIRE_ORDER means don't recognize them as options; + stop option processing when the first non-option is seen. + This is what Unix does. + This mode of operation is selected by either setting the environment + variable POSIXLY_CORRECT, or using `+' as the first character + of the list of option characters. + + PERMUTE is the default. We permute the contents of ARGV as we scan, + so that eventually all the non-options are at the end. This allows options + to be given in any order, even with programs that were not written to + expect this. + + RETURN_IN_ORDER is an option available to programs that were written + to expect options and other ARGV-elements in any order and that care about + the ordering of the two. We describe each non-option ARGV-element + as if it were the argument of an option with character code 1. + Using `-' as the first character of the list of option characters + selects this mode of operation. + + The special argument `--' forces an end of option-scanning regardless + of the value of `ordering'. In the case of RETURN_IN_ORDER, only + `--' can cause `getopt' to return EOF with `optind' != ARGC. */ + +static enum { + REQUIRE_ORDER, PERMUTE, RETURN_IN_ORDER +} ordering; + +#ifdef __GNU_LIBRARY__ +/* We want to avoid inclusion of string.h with non-GNU libraries + because there are many ways it can cause trouble. + On some systems, it contains special magic macros that don't work + in GCC. */ +#include <string.h> +#define my_index strchr +#define my_strlen strlen +#else + +/* Avoid depending on library functions or files + whose names are inconsistent. */ + +#if __STDC__ || defined(PROTO) +extern char *getenv(const char *name); +extern int strcmp(const char *s1, const char *s2); +//extern int strncmp(const char *s1, const char *s2, int n); + +static int my_strlen(const char *s); +static char *my_index(const char *str, int chr); +#else +extern char *getenv(); +#endif + +static int my_strlen(const char *str) +{ + int n = 0; + while (*str++) + n++; + return n; +} + +static char *my_index(const char *str, int chr) +{ + while (*str) { + if (*str == chr) + return (char *) str; + str++; + } + return 0; +} + +#endif /* GNU C library. */ + +/* Handle permutation of arguments. */ + +/* Describe the part of ARGV that contains non-options that have + been skipped. `first_nonopt' is the index in ARGV of the first of them; + `last_nonopt' is the index after the last of them. */ + +static int first_nonopt; +static int last_nonopt; + +/* Exchange two adjacent subsequences of ARGV. + One subsequence is elements [first_nonopt,last_nonopt) + which contains all the non-options that have been skipped so far. + The other is elements [last_nonopt,optind), which contains all + the options processed since those non-options were skipped. + + `first_nonopt' and `last_nonopt' are relocated so that they describe + the new indices of the non-options in ARGV after they are moved. + + To perform the swap, we first reverse the order of all elements. So + all options now come before all non options, but they are in the + wrong order. So we put back the options and non options in original + order by reversing them again. For example: + original input: a b c -x -y + reverse all: -y -x c b a + reverse options: -x -y c b a + reverse non options: -x -y a b c +*/ + +#if __STDC__ || defined(PROTO) +static void exchange(char **argv); +#endif + +static void exchange(char **argv) +{ + char *temp, **first, **last; + + /* Reverse all the elements [first_nonopt, optind) */ + first = &argv[first_nonopt]; + last = &argv[optind - 1]; + while (first < last) { + temp = *first; + *first = *last; + *last = temp; + first++; + last--; + } + /* Put back the options in order */ + first = &argv[first_nonopt]; + first_nonopt += (optind - last_nonopt); + last = &argv[first_nonopt - 1]; + while (first < last) { + temp = *first; + *first = *last; + *last = temp; + first++; + last--; + } + + /* Put back the non options in order */ + first = &argv[first_nonopt]; + last_nonopt = optind; + last = &argv[last_nonopt - 1]; + while (first < last) { + temp = *first; + *first = *last; + *last = temp; + first++; + last--; + } +} + +/* Scan elements of ARGV (whose length is ARGC) for option characters + given in OPTSTRING. + + If an element of ARGV starts with '-', and is not exactly "-" or "--", + then it is an option element. The characters of this element + (aside from the initial '-') are option characters. If `getopt' + is called repeatedly, it returns successively each of the option characters + from each of the option elements. + + If `getopt' finds another option character, it returns that character, + updating `optind' and `nextchar' so that the next call to `getopt' can + resume the scan with the following option character or ARGV-element. + + If there are no more option characters, `getopt' returns `EOF'. + Then `optind' is the index in ARGV of the first ARGV-element + that is not an option. (The ARGV-elements have been permuted + so that those that are not options now come last.) + + OPTSTRING is a string containing the legitimate option characters. + If an option character is seen that is not listed in OPTSTRING, + return BAD_OPTION after printing an error message. If you set `opterr' to + zero, the error message is suppressed but we still return BAD_OPTION. + + If a char in OPTSTRING is followed by a colon, that means it wants an arg, + so the following text in the same ARGV-element, or the text of the following + ARGV-element, is returned in `optarg'. Two colons mean an option that + wants an optional arg; if there is text in the current ARGV-element, + it is returned in `optarg', otherwise `optarg' is set to zero. + + If OPTSTRING starts with `-' or `+', it requests different methods of + handling the non-option ARGV-elements. + See the comments about RETURN_IN_ORDER and REQUIRE_ORDER, above. + + Long-named options begin with `--' instead of `-'. + Their names may be abbreviated as long as the abbreviation is unique + or is an exact match for some defined option. If they have an + argument, it follows the option name in the same ARGV-element, separated + from the option name by a `=', or else the in next ARGV-element. + When `getopt' finds a long-named option, it returns 0 if that option's + `flag' field is nonzero, the value of the option's `val' field + if the `flag' field is zero. + + The elements of ARGV aren't really const, because we permute them. + But we pretend they're const in the prototype to be compatible + with other systems. + + LONGOPTS is a vector of `struct option' terminated by an + element containing a name which is zero. + + LONGIND returns the index in LONGOPT of the long-named option found. + It is only valid when a long-named option has been found by the most + recent call. + + If LONG_ONLY is nonzero, '-' as well as '--' can introduce + long-named options. */ + +int _getopt_internal(int argc, char *const *argv, const char *optstring, + const struct option *longopts, int *longind, int long_only) +{ + int option_index; + + optarg = 0; + + /* Initialize the internal data when the first call is made. + Start processing options with ARGV-element 1 (since ARGV-element 0 + is the program name); the sequence of previously skipped + non-option ARGV-elements is empty. */ + + if (optind == 0) { + first_nonopt = last_nonopt = optind = 1; + + nextchar = NULL; + + /* Determine how to handle the ordering of options and nonoptions. */ + + if (optstring[0] == '-') { + ordering = RETURN_IN_ORDER; + ++optstring; + } else if (optstring[0] == '+') { + ordering = REQUIRE_ORDER; + ++optstring; + } else if (getenv("POSIXLY_CORRECT") != NULL) + ordering = REQUIRE_ORDER; + else + ordering = PERMUTE; + } + + if (nextchar == NULL || *nextchar == '\0') { + if (ordering == PERMUTE) { + /* If we have just processed some options following some non-options, + exchange them so that the options come first. */ + + if (first_nonopt != last_nonopt && last_nonopt != optind) + exchange((char **) argv); + else if (last_nonopt != optind) + first_nonopt = optind; + + /* Now skip any additional non-options + and extend the range of non-options previously skipped. */ + + while (optind < argc && (argv[optind][0] != '-' || argv[optind][1] == '\0') +#ifdef GETOPT_COMPAT + && (longopts == NULL + || argv[optind][0] != '+' || argv[optind][1] == '\0') +#endif /* GETOPT_COMPAT */ + ) + optind++; + last_nonopt = optind; + } + + /* Special ARGV-element `--' means premature end of options. + Skip it like a null option, + then exchange with previous non-options as if it were an option, + then skip everything else like a non-option. */ + + if (optind != argc && !strcmp(argv[optind], "--")) { + optind++; + + if (first_nonopt != last_nonopt && last_nonopt != optind) + exchange((char **) argv); + else if (first_nonopt == last_nonopt) + first_nonopt = optind; + last_nonopt = argc; + + optind = argc; + } + + /* If we have done all the ARGV-elements, stop the scan + and back over any non-options that we skipped and permuted. */ + + if (optind == argc) { + /* Set the next-arg-index to point at the non-options + that we previously skipped, so the caller will digest them. */ + if (first_nonopt != last_nonopt) + optind = first_nonopt; + return EOF; + } + + /* If we have come to a non-option and did not permute it, + either stop the scan or describe it to the caller and pass it by. */ + + if ((argv[optind][0] != '-' || argv[optind][1] == '\0') +#ifdef GETOPT_COMPAT + && (longopts == NULL || argv[optind][0] != '+' || argv[optind][1] == '\0') +#endif /* GETOPT_COMPAT */ + ) { + if (ordering == REQUIRE_ORDER) + return EOF; + optarg = argv[optind++]; + return 1; + } + + /* We have found another option-ARGV-element. + Start decoding its characters. */ + + nextchar = (argv[optind] + 1 + (longopts != NULL && argv[optind][1] == '-')); + } + + if (longopts != NULL && ((argv[optind][0] == '-' && (argv[optind][1] == '-' || long_only)) +#ifdef GETOPT_COMPAT + || argv[optind][0] == '+' +#endif /* GETOPT_COMPAT */ + )) { + const struct option *p; + char *s = nextchar; + int exact = 0; + int ambig = 0; + const struct option *pfound = NULL; + int indfound = 0; + + while (*s && *s != '=') + s++; + + /* Test all options for either exact match or abbreviated matches. */ + for (p = longopts, option_index = 0; p->name; p++, option_index++) + if (!strncmp(p->name, nextchar, s - nextchar)) { + if (s - nextchar == my_strlen(p->name)) { + /* Exact match found. */ + pfound = p; + indfound = option_index; + exact = 1; + break; + } else if (pfound == NULL) { + /* First nonexact match found. */ + pfound = p; + indfound = option_index; + } else + /* Second nonexact match found. */ + ambig = 1; + } + + if (ambig && !exact) { + if (opterr) + fprintf(stderr, "%s: option `%s' is ambiguous\n", + argv[0], argv[optind]); + nextchar += my_strlen(nextchar); + optind++; + return BAD_OPTION; + } + + if (pfound != NULL) { + option_index = indfound; + optind++; + if (*s) { + /* Don't test has_arg with >, because some C compilers don't + allow it to be used on enums. */ + if (pfound->has_arg) + optarg = s + 1; + else { + if (opterr) { + if (argv[optind - 1][1] == '-') + /* --option */ + fprintf(stderr, + "%s: option `--%s' doesn't allow an argument\n", + argv[0], pfound->name); + else + /* +option or -option */ + fprintf(stderr, + "%s: option `%c%s' doesn't allow an argument\n", + argv[0], argv[optind - 1][0], + pfound->name); + } + nextchar += my_strlen(nextchar); + return BAD_OPTION; + } + } else if (pfound->has_arg == 1) { + if (optind < argc) + optarg = argv[optind++]; + else { + if (opterr) + fprintf(stderr, + "%s: option `%s' requires an argument\n", + argv[0], argv[optind - 1]); + nextchar += my_strlen(nextchar); + return optstring[0] == ':' ? ':' : BAD_OPTION; + } + } + nextchar += my_strlen(nextchar); + if (longind != NULL) + *longind = option_index; + if (pfound->flag) { + *(pfound->flag) = pfound->val; + return 0; + } + return pfound->val; + } + /* Can't find it as a long option. If this is not getopt_long_only, + or the option starts with '--' or is not a valid short + option, then it's an error. + Otherwise interpret it as a short option. */ + if (!long_only || argv[optind][1] == '-' +#ifdef GETOPT_COMPAT + || argv[optind][0] == '+' +#endif /* GETOPT_COMPAT */ + || my_index(optstring, *nextchar) == NULL) { + if (opterr) { + if (argv[optind][1] == '-') + /* --option */ + fprintf(stderr, "%s: unrecognized option `--%s'\n", + argv[0], nextchar); + else + /* +option or -option */ + fprintf(stderr, "%s: unrecognized option `%c%s'\n", + argv[0], argv[optind][0], nextchar); + } + nextchar = (char *) ""; + optind++; + return BAD_OPTION; + } + } + + /* Look at and handle the next option-character. */ + + { + char c = *nextchar++; + char *temp = my_index(optstring, c); + + /* Increment `optind' when we start to process its last character. */ + if (*nextchar == '\0') + ++optind; + + if (temp == NULL || c == ':') { + if (opterr) { +#if 0 + if (c < 040 || c >= 0177) + fprintf(stderr, + "%s: unrecognized option, character code 0%o\n", + argv[0], c); + else + fprintf(stderr, "%s: unrecognized option `-%c'\n", argv[0], + c); +#else + /* 1003.2 specifies the format of this message. */ + fprintf(stderr, "%s: illegal option -- %c\n", argv[0], c); +#endif + } + optopt = c; + return BAD_OPTION; + } + if (temp[1] == ':') { + if (temp[2] == ':') { + /* This is an option that accepts an argument optionally. */ + if (*nextchar != '\0') { + optarg = nextchar; + optind++; + } else + optarg = 0; + nextchar = NULL; + } else { + /* This is an option that requires an argument. */ + if (*nextchar != '\0') { + optarg = nextchar; + /* If we end this ARGV-element by taking the rest as an arg, + we must advance to the next element now. */ + optind++; + } else if (optind == argc) { + if (opterr) { +#if 0 + fprintf(stderr, + "%s: option `-%c' requires an argument\n", + argv[0], c); +#else + /* 1003.2 specifies the format of this message. */ + fprintf(stderr, + "%s: option requires an argument -- %c\n", + argv[0], c); +#endif + } + optopt = c; + if (optstring[0] == ':') + c = ':'; + else + c = BAD_OPTION; + } else + /* We already incremented `optind' once; + increment it again when taking next ARGV-elt as argument. */ + optarg = argv[optind++]; + nextchar = NULL; + } + } + return c; + } +} + +int getopt(int argc, char *const *argv, const char *optstring) +{ + return _getopt_internal(argc, argv, optstring, (const struct option *) 0, (int *) 0, 0); +} + + + +/* +extern int getopt_long (int argc, char *const *argv, const char *options, + const struct option *longopts, int *longind); + + +int _getopt_internal(int argc, char *const *argv, const char *optstring, + const struct option *longopts, int *longind, int long_only) + + +extern int getopt_long (int argc, char *const *argv, const char *shortopts, + const struct option *longopts, int *longind); + */ + + +int getopt_long(int argc, char *const *argv, const char *options, const struct option *long_options, int *opt_index) +{ + return _getopt_internal(argc, argv, options, long_options, opt_index, 0); +} + +#endif /* _LIBC or not __GNU_LIBRARY__. */ + +#ifdef TEST + +/* Compile with -DTEST to make an executable for use in testing + the above definition of `getopt'. */ + +int main(int argc, char **argv) +{ + int c; + int digit_optind = 0; + + while (1) { + int this_option_optind = optind ? optind : 1; + + c = getopt(argc, argv, "abc:d:0123456789"); + if (c == EOF) + break; + + switch (c) { + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + if (digit_optind != 0 && digit_optind != this_option_optind) + printf("digits occur in two different argv-elements.\n"); + digit_optind = this_option_optind; + printf("option %c\n", c); + break; + + case 'a': + printf("option a\n"); + break; + + case 'b': + printf("option b\n"); + break; + + case 'c': + printf("option c with value `%s'\n", optarg); + break; + + case BAD_OPTION: + break; + + default: + printf("?? getopt returned character code 0%o ??\n", c); + } + } + + if (optind < argc) { + printf("non-option ARGV-elements: "); + while (optind < argc) + printf("%s ", argv[optind++]); + printf("\n"); + } + + exit(0); +} + +#endif /* TEST */ Index: hwaccess.h =================================================================== --- hwaccess.h (revision 927) +++ hwaccess.h (working copy) @@ -67,12 +67,21 @@ #define INW inw #define INL inl #else - #define OUTB outb - #define OUTW outw - #define OUTL outl - #define INB inb - #define INW inw - #define INL inl +//#error "a" + +//#include <pc.h> + + #define OUTB(x,y) outportb(y, x) + #define OUTW(x,y) outportw(y, x) + #define OUTL(x,y) outportl(y, x) + + + #define INB inportb + #define INW inportw + #define INL inportl + + + #endif #endif
@@ -89,47 +98,6 @@ #endif #include <stdint.h>
-static inline void -outb(uint8_t value, uint16_t port) -{ - asm volatile ("outb %b0,%w1": :"a" (value), "Nd" (port)); -} - -static inline uint8_t -inb(uint16_t port) -{ - uint8_t value; - asm volatile ("inb %w1,%0":"=a" (value):"Nd" (port)); - return value; -} - -static inline void -outw(uint16_t value, uint16_t port) -{ - asm volatile ("outw %w0,%w1": :"a" (value), "Nd" (port)); -} - -static inline uint16_t -inw(uint16_t port) -{ - uint16_t value; - asm volatile ("inw %w1,%0":"=a" (value):"Nd" (port)); - return value; -} - -static inline void -outl(uint32_t value, uint16_t port) -{ - asm volatile ("outl %0,%w1": :"a" (value), "Nd" (port)); -} - -static inline uint32_t -inl(uint16_t port) -{ - uint32_t value; - asm volatile ("inl %1,%0":"=a" (value):"Nd" (port)); - return value; -} #endif #endif
Index: getopt.h =================================================================== --- getopt.h (revision 0) +++ getopt.h (revision 0) @@ -0,0 +1,129 @@ +/* Declarations for getopt. + Copyright (C) 1989, 1990, 1991, 1992, 1993 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#ifndef _GETOPT_H +#define _GETOPT_H 1 + +#ifdef __cplusplus +extern "C" { +#endif + +/* For communication from `getopt' to the caller. + When `getopt' finds an option that takes an argument, + the argument value is returned here. + Also, when `ordering' is RETURN_IN_ORDER, + each non-option ARGV-element is returned here. */ + +extern char *optarg; + +/* Index in ARGV of the next element to be scanned. + This is used for communication to and from the caller + and for communication between successive calls to `getopt'. + + On entry to `getopt', zero means this is the first call; initialize. + + When `getopt' returns EOF, this is the index of the first of the + non-option elements that the caller should itself scan. + + Otherwise, `optind' communicates from one call to the next + how much of ARGV has been scanned so far. */ + +extern int optind; + +/* Callers store zero here to inhibit the error message `getopt' prints + for unrecognized options. */ + +extern int opterr; + +/* Set to an option character which was unrecognized. */ + +extern int optopt; + +/* Describe the long-named options requested by the application. + The LONG_OPTIONS argument to getopt_long or getopt_long_only is a vector + of `struct option' terminated by an element containing a name which is + zero. + + The field `has_arg' is: + no_argument (or 0) if the option does not take an argument, + required_argument (or 1) if the option requires an argument, + optional_argument (or 2) if the option takes an optional argument. + + If the field `flag' is not NULL, it points to a variable that is set + to the value given in the field `val' when the option is found, but + left unchanged if the option is not found. + + To have a long-named option do something other than set an `int' to + a compiled-in constant, such as set a value from `optarg', set the + option's `flag' field to zero and its `val' field to a nonzero + value (the equivalent single-letter option character, if there is + one). For long options that have a zero `flag' field, `getopt' + returns the contents of the `val' field. */ + +struct option +{ +#if __STDC__ + const char *name; +#else + char *name; +#endif + /* has_arg can't be an enum because some compilers complain about + type mismatches in all the code that assumes it is an int. */ + int has_arg; + int *flag; + int val; +}; + +/* Names for the values of the `has_arg' field of `struct option'. */ + +#define no_argument 0 +#define required_argument 1 +#define optional_argument 2 + +#if __STDC__ || defined(PROTO) +#if defined(__GNU_LIBRARY__) +/* Many other libraries have conflicting prototypes for getopt, with + differences in the consts, in stdlib.h. To avoid compilation + errors, only prototype getopt for the GNU C library. */ +extern int getopt (int argc, char *const *argv, const char *shortopts); +#endif /* not __GNU_LIBRARY__ */ +extern int getopt_long (int argc, char *const *argv, const char *shortopts, + const struct option *longopts, int *longind); + + +extern int getopt_long_only (int argc, char *const *argv, + const char *shortopts, + const struct option *longopts, int *longind); + +/* Internal only. Users should not call this directly. */ +extern int _getopt_internal (int argc, char *const *argv, + const char *shortopts, + const struct option *longopts, int *longind, + int long_only); +#else /* not __STDC__ */ +extern int getopt (); +extern int getopt_long (); +extern int getopt_long_only (); + +extern int _getopt_internal (); +#endif /* not __STDC__ */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GETOPT_H */ Index: physmap.c =================================================================== --- physmap.c (revision 927) +++ physmap.c (working copy) @@ -58,21 +58,38 @@ static int fd_mem = -1; static int fd_mem_cached = -1;
+#define MAP_FAILED 0 + +//***************** call DPMI physical memory mapping and allocate LDT descriptor for the memory block +void *map_physical_memory(uint32_t phys_base, uint32_t size) // phys_base must be page aligned +{ // size will be aligned automatically + void *p; + if (size == 0) // if zero block size, do nothing + return(NULL); + if ((size & 0x0FFF) != 0) // if size is not page-aligned + size = (size + 4096) & (~0x0FFF); // make it page-aligned + if ((p = valloc(size)) == NULL) // allocate page-aligned memory (__djgpp_map_physical_memory required this) + { // allocation failed + printf("ERROR: cannot allocate %lu bytes for memory mapped device\n",size); + exit(-1); // exit program + } + if (__djgpp_map_physical_memory(p,size,phys_base)) + { // failed to map physmem + printf("ERROR: failed to map physical memory range: 0x%08lX - 0x%08lX\nDPMI 1.0 server or support of DPMI function 0508h is needed.\nIt doesn't work under Windows, use win32 version instead.\n",phys_base,phys_base+size-1); + return MAP_FAILED; // exit program + } + return(p); // return pointer to memory block aliasing physical memory area +} + + + /* For MMIO access. Must be uncached, doesn't make sense to restrict to ro. */ void *sys_physmap_rw_uncached(unsigned long phys_addr, size_t len) { void *virt_addr;
- if (-1 == fd_mem) { - /* Open the memory device UNCACHED. Important for MMIO. */ - if (-1 == (fd_mem = open(MEM_DEV, O_RDWR | O_SYNC))) { - perror("Critical error: open(" MEM_DEV ")"); - exit(2); - } - }
- virt_addr = mmap(0, len, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t)phys_addr); + virt_addr = map_physical_memory(phys_addr, len) ; return MAP_FAILED == virt_addr ? NULL : virt_addr; }
@@ -83,17 +100,10 @@ { void *virt_addr;
- if (-1 == fd_mem_cached) { - /* Open the memory device CACHED. */ - if (-1 == (fd_mem_cached = open(MEM_DEV, O_RDWR))) { - perror("Critical error: open(" MEM_DEV ")"); - exit(2); - } - }
- virt_addr = mmap(0, len, PROT_READ, MAP_SHARED, - fd_mem_cached, (off_t)phys_addr); + virt_addr = map_physical_memory(phys_addr, len) ; return MAP_FAILED == virt_addr ? NULL : virt_addr; + }
void physunmap(void *virt_addr, size_t len) @@ -103,7 +113,7 @@ return; } - munmap(virt_addr, len); +// munmap(virt_addr, len); } #endif
Index: pci/pci.h =================================================================== --- pci/pci.h (revision 0) +++ pci/pci.h (revision 0) @@ -0,0 +1,240 @@ +/* + * The PCI Library + * + * Copyright (c) 1997--2009 Martin Mares mj@ucw.cz + * + * Can be freely distributed and used under the terms of the GNU GPL. + */ + +#ifndef _PCI_LIB_H +#define _PCI_LIB_H + +#ifndef PCI_CONFIG_H +#include "config.h" +#endif + +#include "header.h" +#include "types.h" + +#define PCI_LIB_VERSION 0x030100 + +#ifndef PCI_ABI +#define PCI_ABI +#endif + +/* + * PCI Access Structure + */ + +struct pci_methods; + +enum pci_access_type { + /* Known access methods, remember to update access.c as well */ + PCI_ACCESS_AUTO, /* Autodetection */ + PCI_ACCESS_SYS_BUS_PCI, /* Linux /sys/bus/pci */ + PCI_ACCESS_PROC_BUS_PCI, /* Linux /proc/bus/pci */ + PCI_ACCESS_I386_TYPE1, /* i386 ports, type 1 */ + PCI_ACCESS_I386_TYPE2, /* i386 ports, type 2 */ + PCI_ACCESS_FBSD_DEVICE, /* FreeBSD /dev/pci */ + PCI_ACCESS_AIX_DEVICE, /* /dev/pci0, /dev/bus0, etc. */ + PCI_ACCESS_NBSD_LIBPCI, /* NetBSD libpci */ + PCI_ACCESS_OBSD_DEVICE, /* OpenBSD /dev/pci */ + PCI_ACCESS_DUMP, /* Dump file */ + PCI_ACCESS_MAX +}; + +struct pci_access { + /* Options you can change: */ + unsigned int method; /* Access method */ + int writeable; /* Open in read/write mode */ + int buscentric; /* Bus-centric view of the world */ + + char *id_file_name; /* Name of ID list file (use pci_set_name_list_path()) */ + int free_id_name; /* Set if id_file_name is malloced */ + int numeric_ids; /* Enforce PCI_LOOKUP_NUMERIC (>1 => PCI_LOOKUP_MIXED) */ + + unsigned int id_lookup_mode; /* pci_lookup_mode flags which are set automatically */ + /* Default: PCI_LOOKUP_CACHE */ + + int debugging; /* Turn on debugging messages */ + + /* Functions you can override: */ + void (*error)(char *msg, ...) PCI_PRINTF(1,2); /* Write error message and quit */ + void (*warning)(char *msg, ...) PCI_PRINTF(1,2); /* Write a warning message */ + void (*debug)(char *msg, ...) PCI_PRINTF(1,2); /* Write a debugging message */ + + struct pci_dev *devices; /* Devices found on this bus */ + + /* Fields used internally: */ + struct pci_methods *methods; + struct pci_param *params; + struct id_entry **id_hash; /* names.c */ + struct id_bucket *current_id_bucket; + int id_load_failed; + int id_cache_status; /* 0=not read, 1=read, 2=dirty */ + int fd; /* proc/sys: fd for config space */ + int fd_rw; /* proc/sys: fd opened read-write */ + int fd_pos; /* proc/sys: current position */ + int fd_vpd; /* sys: fd for VPD */ + struct pci_dev *cached_dev; /* proc/sys: device the fds are for */ +}; + +/* Initialize PCI access */ +struct pci_access *pci_alloc(void) PCI_ABI; +void pci_init(struct pci_access *) PCI_ABI; +void pci_cleanup(struct pci_access *) PCI_ABI; + +/* Scanning of devices */ +void pci_scan_bus(struct pci_access *acc) PCI_ABI; +struct pci_dev *pci_get_dev(struct pci_access *acc, int domain, int bus, int dev, int func) PCI_ABI; /* Raw access to specified device */ +void pci_free_dev(struct pci_dev *) PCI_ABI; + +/* Names of access methods */ +int pci_lookup_method(char *name) PCI_ABI; /* Returns -1 if not found */ +char *pci_get_method_name(int index) PCI_ABI; /* Returns "" if unavailable, NULL if index out of range */ + +/* + * Named parameters + */ + +struct pci_param { + struct pci_param *next; /* Please use pci_walk_params() for traversing the list */ + char *param; /* Name of the parameter */ + char *value; /* Value of the parameter */ + int value_malloced; /* used internally */ + char *help; /* Explanation of the parameter */ +}; + +char *pci_get_param(struct pci_access *acc, char *param) PCI_ABI; +int pci_set_param(struct pci_access *acc, char *param, char *value) PCI_ABI; /* 0 on success, -1 if no such parameter */ +/* To traverse the list, call pci_walk_params repeatedly, first with prev=NULL, and do not modify the parameters during traversal. */ +struct pci_param *pci_walk_params(struct pci_access *acc, struct pci_param *prev) PCI_ABI; + +/* + * Devices + */ + +struct pci_dev { + struct pci_dev *next; /* Next device in the chain */ + u16 domain; /* PCI domain (host bridge) */ + u8 bus, dev, func; /* Bus inside domain, device and function */ + + /* These fields are set by pci_fill_info() */ + int known_fields; /* Set of info fields already known */ + u16 vendor_id, device_id; /* Identity of the device */ + u16 device_class; /* PCI device class */ + int irq; /* IRQ number */ + pciaddr_t base_addr[6]; /* Base addresses including flags in lower bits */ + pciaddr_t size[6]; /* Region sizes */ + pciaddr_t rom_base_addr; /* Expansion ROM base address */ + pciaddr_t rom_size; /* Expansion ROM size */ + struct pci_cap *first_cap; /* List of capabilities */ + char *phy_slot; /* Physical slot */ + + /* Fields used internally: */ + struct pci_access *access; + struct pci_methods *methods; + u8 *cache; /* Cached config registers */ + int cache_len; + int hdrtype; /* Cached low 7 bits of header type, -1 if unknown */ + void *aux; /* Auxillary data */ +}; + +#define PCI_ADDR_IO_MASK (~(pciaddr_t) 0x3) +#define PCI_ADDR_MEM_MASK (~(pciaddr_t) 0xf) +#define PCI_ADDR_FLAG_MASK 0xf + +u8 pci_read_byte(struct pci_dev *, int pos) PCI_ABI; /* Access to configuration space */ +u16 pci_read_word(struct pci_dev *, int pos) PCI_ABI; +u32 pci_read_long(struct pci_dev *, int pos) PCI_ABI; +int pci_read_block(struct pci_dev *, int pos, u8 *buf, int len) PCI_ABI; +int pci_read_vpd(struct pci_dev *d, int pos, u8 *buf, int len) PCI_ABI; +int pci_write_byte(struct pci_dev *, int pos, u8 data) PCI_ABI; +int pci_write_word(struct pci_dev *, int pos, u16 data) PCI_ABI; +int pci_write_long(struct pci_dev *, int pos, u32 data) PCI_ABI; +int pci_write_block(struct pci_dev *, int pos, u8 *buf, int len) PCI_ABI; + +int pci_fill_info(struct pci_dev *, int flags) PCI_ABI; /* Fill in device information */ + +#define PCI_FILL_IDENT 1 +#define PCI_FILL_IRQ 2 +#define PCI_FILL_BASES 4 +#define PCI_FILL_ROM_BASE 8 +#define PCI_FILL_SIZES 16 +#define PCI_FILL_CLASS 32 +#define PCI_FILL_CAPS 64 +#define PCI_FILL_EXT_CAPS 128 +#define PCI_FILL_PHYS_SLOT 256 +#define PCI_FILL_RESCAN 0x10000 + +void pci_setup_cache(struct pci_dev *, u8 *cache, int len) PCI_ABI; + +/* + * Capabilities + */ + +struct pci_cap { + struct pci_cap *next; + u16 id; /* PCI_CAP_ID_xxx */ + u16 type; /* PCI_CAP_xxx */ + unsigned int addr; /* Position in the config space */ +}; + +#define PCI_CAP_NORMAL 1 /* Traditional PCI capabilities */ +#define PCI_CAP_EXTENDED 2 /* PCIe extended capabilities */ + +struct pci_cap *pci_find_cap(struct pci_dev *, unsigned int id, unsigned int type) PCI_ABI; + +/* + * Filters + */ + +struct pci_filter { + int domain, bus, slot, func; /* -1 = ANY */ + int vendor, device; +}; + +void pci_filter_init(struct pci_access *, struct pci_filter *) PCI_ABI; +char *pci_filter_parse_slot(struct pci_filter *, char *) PCI_ABI; +char *pci_filter_parse_id(struct pci_filter *, char *) PCI_ABI; +int pci_filter_match(struct pci_filter *, struct pci_dev *) PCI_ABI; + +/* + * Conversion of PCI ID's to names (according to the pci.ids file) + * + * Call pci_lookup_name() to identify different types of ID's: + * + * VENDOR (vendorID) -> vendor + * DEVICE (vendorID, deviceID) -> device + * VENDOR | DEVICE (vendorID, deviceID) -> combined vendor and device + * SUBSYSTEM | VENDOR (subvendorID) -> subsystem vendor + * SUBSYSTEM | DEVICE (vendorID, deviceID, subvendorID, subdevID) -> subsystem device + * SUBSYSTEM | VENDOR | DEVICE (vendorID, deviceID, subvendorID, subdevID) -> combined subsystem v+d + * SUBSYSTEM | ... (-1, -1, subvendorID, subdevID) -> generic subsystem + * CLASS (classID) -> class + * PROGIF (classID, progif) -> programming interface + */ + +char *pci_lookup_name(struct pci_access *a, char *buf, int size, int flags, ...) PCI_ABI; + +int pci_load_name_list(struct pci_access *a) PCI_ABI; /* Called automatically by pci_lookup_*() when needed; returns success */ +void pci_free_name_list(struct pci_access *a) PCI_ABI; /* Called automatically by pci_cleanup() */ +void pci_set_name_list_path(struct pci_access *a, char *name, int to_be_freed) PCI_ABI; +void pci_id_cache_flush(struct pci_access *a) PCI_ABI; + +enum pci_lookup_mode { + PCI_LOOKUP_VENDOR = 1, /* Vendor name (args: vendorID) */ + PCI_LOOKUP_DEVICE = 2, /* Device name (args: vendorID, deviceID) */ + PCI_LOOKUP_CLASS = 4, /* Device class (args: classID) */ + PCI_LOOKUP_SUBSYSTEM = 8, + PCI_LOOKUP_PROGIF = 16, /* Programming interface (args: classID, prog_if) */ + PCI_LOOKUP_NUMERIC = 0x10000, /* Want only formatted numbers; default if access->numeric_ids is set */ + PCI_LOOKUP_NO_NUMBERS = 0x20000, /* Return NULL if not found in the database; default is to print numerically */ + PCI_LOOKUP_MIXED = 0x40000, /* Include both numbers and names */ + PCI_LOOKUP_NETWORK = 0x80000, /* Try to resolve unknown ID's by DNS */ + PCI_LOOKUP_SKIP_LOCAL = 0x100000, /* Do not consult local database */ + PCI_LOOKUP_CACHE = 0x200000, /* Consult the local cache before using DNS */ + PCI_LOOKUP_REFRESH_CACHE = 0x400000, /* Forget all previously cached entries, but still allow updating the cache */ +}; + +#endif Index: pci/types.h =================================================================== --- pci/types.h (revision 0) +++ pci/types.h (revision 0) @@ -0,0 +1,65 @@ +/* + * The PCI Library -- Types and Format Strings + * + * Copyright (c) 1997--2008 Martin Mares mj@ucw.cz + * + * Can be freely distributed and used under the terms of the GNU GPL. + */ + +#include <sys/types.h> + +#ifndef PCI_HAVE_Uxx_TYPES + +#ifdef PCI_OS_WINDOWS +#include <windef.h> +typedef BYTE u8; +typedef WORD u16; +typedef DWORD u32; +#elif defined(PCI_HAVE_STDINT_H) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) +#include <stdint.h> +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +#else +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int u32; +#endif + +#ifdef PCI_HAVE_64BIT_ADDRESS +#include <limits.h> +#if ULONG_MAX > 0xffffffff +typedef unsigned long u64; +#define PCI_U64_FMT "l" +#else +typedef unsigned long long u64; +#define PCI_U64_FMT "ll" +#endif +#endif + +#endif /* PCI_HAVE_Uxx_TYPES */ + +#ifdef PCI_HAVE_64BIT_ADDRESS +typedef u64 pciaddr_t; +#define PCIADDR_T_FMT "%08" PCI_U64_FMT "x" +#define PCIADDR_PORT_FMT "%04" PCI_U64_FMT "x" +#else +typedef u32 pciaddr_t; +#define PCIADDR_T_FMT "%08x" +#define PCIADDR_PORT_FMT "%04x" +#endif + +#ifdef PCI_ARCH_SPARC64 +/* On sparc64 Linux the kernel reports remapped port addresses and IRQ numbers */ +#undef PCIADDR_PORT_FMT +#define PCIADDR_PORT_FMT PCIADDR_T_FMT +#define PCIIRQ_FMT "%08x" +#else +#define PCIIRQ_FMT "%d" +#endif + +#ifdef __GNUC__ +#define PCI_PRINTF(x,y) __attribute__((format(printf, x, y))) +#else +#define PCI_PRINTF(x,y) +#endif Index: pci/config.h =================================================================== --- pci/config.h (revision 0) +++ pci/config.h (revision 0) @@ -0,0 +1,3 @@ +#define PCI_CONFIG_H +#define PCI_ARCH_SOLARISxI386 +#define PCI_OS_SOLARISxI386 Index: pci/header.h =================================================================== --- pci/header.h (revision 0) +++ pci/header.h (revision 0) @@ -0,0 +1,1175 @@ +/* + * The PCI Library -- PCI Header Structure (based on <linux/pci.h>) + * + * Copyright (c) 1997--2010 Martin Mares mj@ucw.cz + * + * Can be freely distributed and used under the terms of the GNU GPL. + */ + +/* + * Under PCI, each device has 256 bytes of configuration address space, + * of which the first 64 bytes are standardized as follows: + */ +#define PCI_VENDOR_ID 0x00 /* 16 bits */ +#define PCI_DEVICE_ID 0x02 /* 16 bits */ +#define PCI_COMMAND 0x04 /* 16 bits */ +#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ +#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ +#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ +#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ +#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ +#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ +#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ +#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ +#define PCI_COMMAND_SERR 0x100 /* Enable SERR */ +#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ +#define PCI_COMMAND_DISABLE_INTx 0x400 /* PCIE: Disable INTx interrupts */ + +#define PCI_STATUS 0x06 /* 16 bits */ +#define PCI_STATUS_INTx 0x08 /* PCIE: INTx interrupt pending */ +#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ +#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ +#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ +#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ +#define PCI_STATUS_PARITY 0x100 /* Detected parity error */ +#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ +#define PCI_STATUS_DEVSEL_FAST 0x000 +#define PCI_STATUS_DEVSEL_MEDIUM 0x200 +#define PCI_STATUS_DEVSEL_SLOW 0x400 +#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ +#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ +#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ +#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ +#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ + +#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 + revision */ +#define PCI_REVISION_ID 0x08 /* Revision ID */ +#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ +#define PCI_CLASS_DEVICE 0x0a /* Device class */ + +#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ +#define PCI_LATENCY_TIMER 0x0d /* 8 bits */ +#define PCI_HEADER_TYPE 0x0e /* 8 bits */ +#define PCI_HEADER_TYPE_NORMAL 0 +#define PCI_HEADER_TYPE_BRIDGE 1 +#define PCI_HEADER_TYPE_CARDBUS 2 + +#define PCI_BIST 0x0f /* 8 bits */ +#define PCI_BIST_CODE_MASK 0x0f /* Return result */ +#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ +#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ + +/* + * Base addresses specify locations in memory or I/O space. + * Decoded size can be determined by writing a value of + * 0xffffffff to the register, and reading it back. Only + * 1 bits are decoded. + */ +#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ +#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ +#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ +#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ +#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ +#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ +#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ +#define PCI_BASE_ADDRESS_SPACE_IO 0x01 +#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 +#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 +#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ +#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ +#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ +#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ +#define PCI_BASE_ADDRESS_MEM_MASK (~(pciaddr_t)0x0f) +#define PCI_BASE_ADDRESS_IO_MASK (~(pciaddr_t)0x03) +/* bit 1 is reserved if address_space = 1 */ + +/* Header type 0 (normal devices) */ +#define PCI_CARDBUS_CIS 0x28 +#define PCI_SUBSYSTEM_VENDOR_ID 0x2c +#define PCI_SUBSYSTEM_ID 0x2e +#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ +#define PCI_ROM_ADDRESS_ENABLE 0x01 +#define PCI_ROM_ADDRESS_MASK (~(pciaddr_t)0x7ff) + +#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ + +/* 0x35-0x3b are reserved */ +#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ +#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ +#define PCI_MIN_GNT 0x3e /* 8 bits */ +#define PCI_MAX_LAT 0x3f /* 8 bits */ + +/* Header type 1 (PCI-to-PCI bridges) */ +#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ +#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ +#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ +#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ +#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ +#define PCI_IO_LIMIT 0x1d +#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ +#define PCI_IO_RANGE_TYPE_16 0x00 +#define PCI_IO_RANGE_TYPE_32 0x01 +#define PCI_IO_RANGE_MASK ~0x0f +#define PCI_SEC_STATUS 0x1e /* Secondary status register */ +#define PCI_MEMORY_BASE 0x20 /* Memory range behind */ +#define PCI_MEMORY_LIMIT 0x22 +#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f +#define PCI_MEMORY_RANGE_MASK ~0x0f +#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ +#define PCI_PREF_MEMORY_LIMIT 0x26 +#define PCI_PREF_RANGE_TYPE_MASK 0x0f +#define PCI_PREF_RANGE_TYPE_32 0x00 +#define PCI_PREF_RANGE_TYPE_64 0x01 +#define PCI_PREF_RANGE_MASK ~0x0f +#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ +#define PCI_PREF_LIMIT_UPPER32 0x2c +#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ +#define PCI_IO_LIMIT_UPPER16 0x32 +/* 0x34 same as for htype 0 */ +/* 0x35-0x3b is reserved */ +#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ +/* 0x3c-0x3d are same as for htype 0 */ +#define PCI_BRIDGE_CONTROL 0x3e +#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ +#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ +#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ +#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ +#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ +#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ +#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ +#define PCI_BRIDGE_CTL_PRI_DISCARD_TIMER 0x100 /* PCI-X? */ +#define PCI_BRIDGE_CTL_SEC_DISCARD_TIMER 0x200 /* PCI-X? */ +#define PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS 0x400 /* PCI-X? */ +#define PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN 0x800 /* PCI-X? */ + +/* Header type 2 (CardBus bridges) */ +/* 0x14-0x15 reserved */ +#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ +#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ +#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ +#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ +#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ +#define PCI_CB_MEMORY_BASE_0 0x1c +#define PCI_CB_MEMORY_LIMIT_0 0x20 +#define PCI_CB_MEMORY_BASE_1 0x24 +#define PCI_CB_MEMORY_LIMIT_1 0x28 +#define PCI_CB_IO_BASE_0 0x2c +#define PCI_CB_IO_BASE_0_HI 0x2e +#define PCI_CB_IO_LIMIT_0 0x30 +#define PCI_CB_IO_LIMIT_0_HI 0x32 +#define PCI_CB_IO_BASE_1 0x34 +#define PCI_CB_IO_BASE_1_HI 0x36 +#define PCI_CB_IO_LIMIT_1 0x38 +#define PCI_CB_IO_LIMIT_1_HI 0x3a +#define PCI_CB_IO_RANGE_MASK ~0x03 +/* 0x3c-0x3d are same as for htype 0 */ +#define PCI_CB_BRIDGE_CONTROL 0x3e +#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ +#define PCI_CB_BRIDGE_CTL_SERR 0x02 +#define PCI_CB_BRIDGE_CTL_ISA 0x04 +#define PCI_CB_BRIDGE_CTL_VGA 0x08 +#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 +#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ +#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ +#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ +#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 +#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 +#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 +#define PCI_CB_SUBSYSTEM_ID 0x42 +#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ +/* 0x48-0x7f reserved */ + +/* Capability lists */ + +#define PCI_CAP_LIST_ID 0 /* Capability ID */ +#define PCI_CAP_ID_PM 0x01 /* Power Management */ +#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ +#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ +#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ +#define PCI_CAP_ID_MSI 0x05 /* Message Signaled Interrupts */ +#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ +#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ +#define PCI_CAP_ID_HT 0x08 /* HyperTransport */ +#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */ +#define PCI_CAP_ID_DBG 0x0A /* Debug port */ +#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ +#define PCI_CAP_ID_HOTPLUG 0x0C /* PCI hot-plug */ +#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ +#define PCI_CAP_ID_AGP3 0x0E /* AGP 8x */ +#define PCI_CAP_ID_SECURE 0x0F /* Secure device (?) */ +#define PCI_CAP_ID_EXP 0x10 /* PCI Express */ +#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ +#define PCI_CAP_ID_SATA 0x12 /* Serial-ATA HBA */ +#define PCI_CAP_ID_AF 0x13 /* Advanced features of PCI devices integrated in PCIe root cplx */ +#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ +#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ +#define PCI_CAP_SIZEOF 4 + +/* Capabilities residing in the PCI Express extended configuration space */ + +#define PCI_EXT_CAP_ID_AER 0x01 /* Advanced Error Reporting */ +#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */ +#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ +#define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */ +#define PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */ +#define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */ +#define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */ +#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */ +#define PCI_EXT_CAP_ID_VC2 0x09 /* Virtual Channel (2nd ID) */ +#define PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */ +#define PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */ +#define PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */ +#define PCI_EXT_CAP_ID_ARI 0x0e /* Alternative Routing-ID Interpretation */ +#define PCI_EXT_CAP_ID_ATS 0x0f /* Address Translation Service */ +#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ + +/*** Definitions of capabilities ***/ + +/* Power Management Registers */ + +#define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */ +#define PCI_PM_CAP_PME_CLOCK 0x0008 /* Clock required for PME generation */ +#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization required */ +#define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D3cold */ +#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ +#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ +#define PCI_PM_CAP_PME_D0 0x0800 /* PME can be asserted from D0 */ +#define PCI_PM_CAP_PME_D1 0x1000 /* PME can be asserted from D1 */ +#define PCI_PM_CAP_PME_D2 0x2000 /* PME can be asserted from D2 */ +#define PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME can be asserted from D3hot */ +#define PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME can be asserted from D3cold */ +#define PCI_PM_CTRL 4 /* PM control and status register */ +#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ +#define PCI_PM_CTRL_NO_SOFT_RST 0x0008 /* No Soft Reset from D3hot to D0 */ +#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ +#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* PM table data index */ +#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* PM table data scaling factor */ +#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ +#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions */ +#define PCI_PM_PPB_B2_B3 0x40 /* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */ +#define PCI_PM_BPCC_ENABLE 0x80 /* Secondary bus is power managed */ +#define PCI_PM_DATA_REGISTER 7 /* PM table contents read here */ +#define PCI_PM_SIZEOF 8 + +/* AGP registers */ + +#define PCI_AGP_VERSION 2 /* BCD version number */ +#define PCI_AGP_RFU 3 /* Rest of capability flags */ +#define PCI_AGP_STATUS 4 /* Status register */ +#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ +#define PCI_AGP_STATUS_ISOCH 0x10000 /* Isochronous transactions supported */ +#define PCI_AGP_STATUS_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */ +#define PCI_AGP_STATUS_CAL_MASK 0x1c00 /* Calibration cycle timing */ +#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ +#define PCI_AGP_STATUS_ITA_COH 0x0100 /* In-aperture accesses always coherent */ +#define PCI_AGP_STATUS_GART64 0x0080 /* 64-bit GART entries supported */ +#define PCI_AGP_STATUS_HTRANS 0x0040 /* If 0, core logic can xlate host CPU accesses thru aperture */ +#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing cycles supported */ +#define PCI_AGP_STATUS_FW 0x0010 /* Fast write transfers supported */ +#define PCI_AGP_STATUS_AGP3 0x0008 /* AGP3 mode supported */ +#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported (RFU in AGP3 mode) */ +#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported (8x in AGP3 mode) */ +#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported (4x in AGP3 mode) */ +#define PCI_AGP_COMMAND 8 /* Control register */ +#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ +#define PCI_AGP_COMMAND_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */ +#define PCI_AGP_COMMAND_CAL_MASK 0x1c00 /* Calibration cycle timing */ +#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ +#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ +#define PCI_AGP_COMMAND_GART64 0x0080 /* 64-bit GART entries enabled */ +#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow generation of 64-bit addr cycles */ +#define PCI_AGP_COMMAND_FW 0x0010 /* Enable FW transfers */ +#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate (RFU in AGP3 mode) */ +#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate (8x in AGP3 mode) */ +#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate (4x in AGP3 mode) */ +#define PCI_AGP_SIZEOF 12 + +/* Vital Product Data */ + +#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */ +#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */ +#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */ +#define PCI_VPD_DATA 4 /* 32-bits of data returned here */ + +/* Slot Identification */ + +#define PCI_SID_ESR 2 /* Expansion Slot Register */ +#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ +#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ +#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ + +/* Message Signaled Interrupts registers */ + +#define PCI_MSI_FLAGS 2 /* Various flags */ +#define PCI_MSI_FLAGS_MASK_BIT 0x100 /* interrupt masking & reporting supported */ +#define PCI_MSI_FLAGS_64BIT 0x080 /* 64-bit addresses allowed */ +#define PCI_MSI_FLAGS_QSIZE 0x070 /* Message queue size configured */ +#define PCI_MSI_FLAGS_QMASK 0x00e /* Maximum queue size available */ +#define PCI_MSI_FLAGS_ENABLE 0x001 /* MSI feature enabled */ +#define PCI_MSI_RFU 3 /* Rest of capability flags */ +#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ +#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ +#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ +#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ +#define PCI_MSI_MASK_BIT_32 12 /* per-vector masking for 32-bit devices */ +#define PCI_MSI_MASK_BIT_64 16 /* per-vector masking for 64-bit devices */ +#define PCI_MSI_PENDING_32 16 /* per-vector interrupt pending for 32-bit devices */ +#define PCI_MSI_PENDING_64 20 /* per-vector interrupt pending for 64-bit devices */ + +/* PCI-X */ +#define PCI_PCIX_COMMAND 2 /* Command register offset */ +#define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */ +#define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ +#define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */ +#define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070 +#define PCI_PCIX_COMMAND_RESERVED 0xf80 +#define PCI_PCIX_STATUS 4 /* Status register offset */ +#define PCI_PCIX_STATUS_FUNCTION 0x00000007 +#define PCI_PCIX_STATUS_DEVICE 0x000000f8 +#define PCI_PCIX_STATUS_BUS 0x0000ff00 +#define PCI_PCIX_STATUS_64BIT 0x00010000 +#define PCI_PCIX_STATUS_133MHZ 0x00020000 +#define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */ +#define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */ +#define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */ +#define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */ +#define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000 +#define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000 +#define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */ +#define PCI_PCIX_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ +#define PCI_PCIX_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ +#define PCI_PCIX_SIZEOF 4 + +/* PCI-X Bridges */ +#define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */ +#define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001 +#define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002 +#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */ +#define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */ +#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */ +#define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020 +#define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0 +#define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00 +#define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */ +#define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007 +#define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8 +#define PCI_PCIX_BRIDGE_STATUS_BUS 0x0000ff00 +#define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000 +#define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000 +#define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */ +#define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */ +#define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */ +#define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000 +#define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000 +#define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */ +#define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */ +#define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff +#define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000 +#define PCI_PCIX_BRIDGE_SIZEOF 12 + +/* HyperTransport (as of spec rev. 2.00) */ +#define PCI_HT_CMD 2 /* Command Register */ +#define PCI_HT_CMD_TYP_HI 0xe000 /* Capability Type high part */ +#define PCI_HT_CMD_TYP_HI_PRI 0x0000 /* Slave or Primary Interface */ +#define PCI_HT_CMD_TYP_HI_SEC 0x2000 /* Host or Secondary Interface */ +#define PCI_HT_CMD_TYP 0xf800 /* Capability Type */ +#define PCI_HT_CMD_TYP_SW 0x4000 /* Switch */ +#define PCI_HT_CMD_TYP_IDC 0x8000 /* Interrupt Discovery and Configuration */ +#define PCI_HT_CMD_TYP_RID 0x8800 /* Revision ID */ +#define PCI_HT_CMD_TYP_UIDC 0x9000 /* UnitID Clumping */ +#define PCI_HT_CMD_TYP_ECSA 0x9800 /* Extended Configuration Space Access */ +#define PCI_HT_CMD_TYP_AM 0xa000 /* Address Mapping */ +#define PCI_HT_CMD_TYP_MSIM 0xa800 /* MSI Mapping */ +#define PCI_HT_CMD_TYP_DR 0xb000 /* DirectRoute */ +#define PCI_HT_CMD_TYP_VCS 0xb800 /* VCSet */ +#define PCI_HT_CMD_TYP_RM 0xc000 /* Retry Mode */ +#define PCI_HT_CMD_TYP_X86 0xc800 /* X86 (reserved) */ + + /* Link Control Register */ +#define PCI_HT_LCTR_CFLE 0x0002 /* CRC Flood Enable */ +#define PCI_HT_LCTR_CST 0x0004 /* CRC Start Test */ +#define PCI_HT_LCTR_CFE 0x0008 /* CRC Force Error */ +#define PCI_HT_LCTR_LKFAIL 0x0010 /* Link Failure */ +#define PCI_HT_LCTR_INIT 0x0020 /* Initialization Complete */ +#define PCI_HT_LCTR_EOC 0x0040 /* End of Chain */ +#define PCI_HT_LCTR_TXO 0x0080 /* Transmitter Off */ +#define PCI_HT_LCTR_CRCERR 0x0f00 /* CRC Error */ +#define PCI_HT_LCTR_ISOCEN 0x1000 /* Isochronous Flow Control Enable */ +#define PCI_HT_LCTR_LSEN 0x2000 /* LDTSTOP# Tristate Enable */ +#define PCI_HT_LCTR_EXTCTL 0x4000 /* Extended CTL Time */ +#define PCI_HT_LCTR_64B 0x8000 /* 64-bit Addressing Enable */ + + /* Link Configuration Register */ +#define PCI_HT_LCNF_MLWI 0x0007 /* Max Link Width In */ +#define PCI_HT_LCNF_LW_8B 0x0 /* Link Width 8 bits */ +#define PCI_HT_LCNF_LW_16B 0x1 /* Link Width 16 bits */ +#define PCI_HT_LCNF_LW_32B 0x3 /* Link Width 32 bits */ +#define PCI_HT_LCNF_LW_2B 0x4 /* Link Width 2 bits */ +#define PCI_HT_LCNF_LW_4B 0x5 /* Link Width 4 bits */ +#define PCI_HT_LCNF_LW_NC 0x7 /* Link physically not connected */ +#define PCI_HT_LCNF_DFI 0x0008 /* Doubleword Flow Control In */ +#define PCI_HT_LCNF_MLWO 0x0070 /* Max Link Width Out */ +#define PCI_HT_LCNF_DFO 0x0080 /* Doubleword Flow Control Out */ +#define PCI_HT_LCNF_LWI 0x0700 /* Link Width In */ +#define PCI_HT_LCNF_DFIE 0x0800 /* Doubleword Flow Control In Enable */ +#define PCI_HT_LCNF_LWO 0x7000 /* Link Width Out */ +#define PCI_HT_LCNF_DFOE 0x8000 /* Doubleword Flow Control Out Enable */ + + /* Revision ID Register */ +#define PCI_HT_RID_MIN 0x1f /* Minor Revision */ +#define PCI_HT_RID_MAJ 0xe0 /* Major Revision */ + + /* Link Frequency/Error Register */ +#define PCI_HT_LFRER_FREQ 0x0f /* Transmitter Clock Frequency */ +#define PCI_HT_LFRER_200 0x00 /* 200MHz */ +#define PCI_HT_LFRER_300 0x01 /* 300MHz */ +#define PCI_HT_LFRER_400 0x02 /* 400MHz */ +#define PCI_HT_LFRER_500 0x03 /* 500MHz */ +#define PCI_HT_LFRER_600 0x04 /* 600MHz */ +#define PCI_HT_LFRER_800 0x05 /* 800MHz */ +#define PCI_HT_LFRER_1000 0x06 /* 1.0GHz */ +#define PCI_HT_LFRER_1200 0x07 /* 1.2GHz */ +#define PCI_HT_LFRER_1400 0x08 /* 1.4GHz */ +#define PCI_HT_LFRER_1600 0x09 /* 1.6GHz */ +#define PCI_HT_LFRER_VEND 0x0f /* Vendor-Specific */ +#define PCI_HT_LFRER_ERR 0xf0 /* Link Error */ +#define PCI_HT_LFRER_PROT 0x10 /* Protocol Error */ +#define PCI_HT_LFRER_OV 0x20 /* Overflow Error */ +#define PCI_HT_LFRER_EOC 0x40 /* End of Chain Error */ +#define PCI_HT_LFRER_CTLT 0x80 /* CTL Timeout */ + + /* Link Frequency Capability Register */ +#define PCI_HT_LFCAP_200 0x0001 /* 200MHz */ +#define PCI_HT_LFCAP_300 0x0002 /* 300MHz */ +#define PCI_HT_LFCAP_400 0x0004 /* 400MHz */ +#define PCI_HT_LFCAP_500 0x0008 /* 500MHz */ +#define PCI_HT_LFCAP_600 0x0010 /* 600MHz */ +#define PCI_HT_LFCAP_800 0x0020 /* 800MHz */ +#define PCI_HT_LFCAP_1000 0x0040 /* 1.0GHz */ +#define PCI_HT_LFCAP_1200 0x0080 /* 1.2GHz */ +#define PCI_HT_LFCAP_1400 0x0100 /* 1.4GHz */ +#define PCI_HT_LFCAP_1600 0x0200 /* 1.6GHz */ +#define PCI_HT_LFCAP_VEND 0x8000 /* Vendor-Specific */ + + /* Feature Register */ +#define PCI_HT_FTR_ISOCFC 0x0001 /* Isochronous Flow Control Mode */ +#define PCI_HT_FTR_LDTSTOP 0x0002 /* LDTSTOP# Supported */ +#define PCI_HT_FTR_CRCTM 0x0004 /* CRC Test Mode */ +#define PCI_HT_FTR_ECTLT 0x0008 /* Extended CTL Time Required */ +#define PCI_HT_FTR_64BA 0x0010 /* 64-bit Addressing */ +#define PCI_HT_FTR_UIDRD 0x0020 /* UnitID Reorder Disable */ + + /* Error Handling Register */ +#define PCI_HT_EH_PFLE 0x0001 /* Protocol Error Flood Enable */ +#define PCI_HT_EH_OFLE 0x0002 /* Overflow Error Flood Enable */ +#define PCI_HT_EH_PFE 0x0004 /* Protocol Error Fatal Enable */ +#define PCI_HT_EH_OFE 0x0008 /* Overflow Error Fatal Enable */ +#define PCI_HT_EH_EOCFE 0x0010 /* End of Chain Error Fatal Enable */ +#define PCI_HT_EH_RFE 0x0020 /* Response Error Fatal Enable */ +#define PCI_HT_EH_CRCFE 0x0040 /* CRC Error Fatal Enable */ +#define PCI_HT_EH_SERRFE 0x0080 /* System Error Fatal Enable (B */ +#define PCI_HT_EH_CF 0x0100 /* Chain Fail */ +#define PCI_HT_EH_RE 0x0200 /* Response Error */ +#define PCI_HT_EH_PNFE 0x0400 /* Protocol Error Nonfatal Enable */ +#define PCI_HT_EH_ONFE 0x0800 /* Overflow Error Nonfatal Enable */ +#define PCI_HT_EH_EOCNFE 0x1000 /* End of Chain Error Nonfatal Enable */ +#define PCI_HT_EH_RNFE 0x2000 /* Response Error Nonfatal Enable */ +#define PCI_HT_EH_CRCNFE 0x4000 /* CRC Error Nonfatal Enable */ +#define PCI_HT_EH_SERRNFE 0x8000 /* System Error Nonfatal Enable */ + +/* HyperTransport: Slave or Primary Interface */ +#define PCI_HT_PRI_CMD 2 /* Command Register */ +#define PCI_HT_PRI_CMD_BUID 0x001f /* Base UnitID */ +#define PCI_HT_PRI_CMD_UC 0x03e0 /* Unit Count */ +#define PCI_HT_PRI_CMD_MH 0x0400 /* Master Host */ +#define PCI_HT_PRI_CMD_DD 0x0800 /* Default Direction */ +#define PCI_HT_PRI_CMD_DUL 0x1000 /* Drop on Uninitialized Link */ + +#define PCI_HT_PRI_LCTR0 4 /* Link Control 0 Register */ +#define PCI_HT_PRI_LCNF0 6 /* Link Config 0 Register */ +#define PCI_HT_PRI_LCTR1 8 /* Link Control 1 Register */ +#define PCI_HT_PRI_LCNF1 10 /* Link Config 1 Register */ +#define PCI_HT_PRI_RID 12 /* Revision ID Register */ +#define PCI_HT_PRI_LFRER0 13 /* Link Frequency/Error 0 Register */ +#define PCI_HT_PRI_LFCAP0 14 /* Link Frequency Capability 0 Register */ +#define PCI_HT_PRI_FTR 16 /* Feature Register */ +#define PCI_HT_PRI_LFRER1 17 /* Link Frequency/Error 1 Register */ +#define PCI_HT_PRI_LFCAP1 18 /* Link Frequency Capability 1 Register */ +#define PCI_HT_PRI_ES 20 /* Enumeration Scratchpad Register */ +#define PCI_HT_PRI_EH 22 /* Error Handling Register */ +#define PCI_HT_PRI_MBU 24 /* Memory Base Upper Register */ +#define PCI_HT_PRI_MLU 25 /* Memory Limit Upper Register */ +#define PCI_HT_PRI_BN 26 /* Bus Number Register */ +#define PCI_HT_PRI_SIZEOF 28 + +/* HyperTransport: Host or Secondary Interface */ +#define PCI_HT_SEC_CMD 2 /* Command Register */ +#define PCI_HT_SEC_CMD_WR 0x0001 /* Warm Reset */ +#define PCI_HT_SEC_CMD_DE 0x0002 /* Double-Ended */ +#define PCI_HT_SEC_CMD_DN 0x0076 /* Device Number */ +#define PCI_HT_SEC_CMD_CS 0x0080 /* Chain Side */ +#define PCI_HT_SEC_CMD_HH 0x0100 /* Host Hide */ +#define PCI_HT_SEC_CMD_AS 0x0400 /* Act as Slave */ +#define PCI_HT_SEC_CMD_HIECE 0x0800 /* Host Inbound End of Chain Error */ +#define PCI_HT_SEC_CMD_DUL 0x1000 /* Drop on Uninitialized Link */ + +#define PCI_HT_SEC_LCTR 4 /* Link Control Register */ +#define PCI_HT_SEC_LCNF 6 /* Link Config Register */ +#define PCI_HT_SEC_RID 8 /* Revision ID Register */ +#define PCI_HT_SEC_LFRER 9 /* Link Frequency/Error Register */ +#define PCI_HT_SEC_LFCAP 10 /* Link Frequency Capability Register */ +#define PCI_HT_SEC_FTR 12 /* Feature Register */ +#define PCI_HT_SEC_FTR_EXTRS 0x0100 /* Extended Register Set */ +#define PCI_HT_SEC_FTR_UCNFE 0x0200 /* Upstream Configuration Enable */ +#define PCI_HT_SEC_ES 16 /* Enumeration Scratchpad Register */ +#define PCI_HT_SEC_EH 18 /* Error Handling Register */ +#define PCI_HT_SEC_MBU 20 /* Memory Base Upper Register */ +#define PCI_HT_SEC_MLU 21 /* Memory Limit Upper Register */ +#define PCI_HT_SEC_SIZEOF 24 + +/* HyperTransport: Switch */ +#define PCI_HT_SW_CMD 2 /* Switch Command Register */ +#define PCI_HT_SW_CMD_VIBERR 0x0080 /* VIB Error */ +#define PCI_HT_SW_CMD_VIBFL 0x0100 /* VIB Flood */ +#define PCI_HT_SW_CMD_VIBFT 0x0200 /* VIB Fatal */ +#define PCI_HT_SW_CMD_VIBNFT 0x0400 /* VIB Nonfatal */ +#define PCI_HT_SW_PMASK 4 /* Partition Mask Register */ +#define PCI_HT_SW_SWINF 8 /* Switch Info Register */ +#define PCI_HT_SW_SWINF_DP 0x0000001f /* Default Port */ +#define PCI_HT_SW_SWINF_EN 0x00000020 /* Enable Decode */ +#define PCI_HT_SW_SWINF_CR 0x00000040 /* Cold Reset */ +#define PCI_HT_SW_SWINF_PCIDX 0x00000f00 /* Performance Counter Index */ +#define PCI_HT_SW_SWINF_BLRIDX 0x0003f000 /* Base/Limit Range Index */ +#define PCI_HT_SW_SWINF_SBIDX 0x00002000 /* Secondary Base Range Index */ +#define PCI_HT_SW_SWINF_HP 0x00040000 /* Hot Plug */ +#define PCI_HT_SW_SWINF_HIDE 0x00080000 /* Hide Port */ +#define PCI_HT_SW_PCD 12 /* Performance Counter Data Register */ +#define PCI_HT_SW_BLRD 16 /* Base/Limit Range Data Register */ +#define PCI_HT_SW_SBD 20 /* Secondary Base Data Register */ +#define PCI_HT_SW_SIZEOF 24 + + /* Counter indices */ +#define PCI_HT_SW_PC_PCR 0x0 /* Posted Command Receive */ +#define PCI_HT_SW_PC_NPCR 0x1 /* Nonposted Command Receive */ +#define PCI_HT_SW_PC_RCR 0x2 /* Response Command Receive */ +#define PCI_HT_SW_PC_PDWR 0x3 /* Posted DW Receive */ +#define PCI_HT_SW_PC_NPDWR 0x4 /* Nonposted DW Receive */ +#define PCI_HT_SW_PC_RDWR 0x5 /* Response DW Receive */ +#define PCI_HT_SW_PC_PCT 0x6 /* Posted Command Transmit */ +#define PCI_HT_SW_PC_NPCT 0x7 /* Nonposted Command Transmit */ +#define PCI_HT_SW_PC_RCT 0x8 /* Response Command Transmit */ +#define PCI_HT_SW_PC_PDWT 0x9 /* Posted DW Transmit */ +#define PCI_HT_SW_PC_NPDWT 0xa /* Nonposted DW Transmit */ +#define PCI_HT_SW_PC_RDWT 0xb /* Response DW Transmit */ + + /* Base/Limit Range indices */ +#define PCI_HT_SW_BLR_BASE0_LO 0x0 /* Base 0[31:1], Enable */ +#define PCI_HT_SW_BLR_BASE0_HI 0x1 /* Base 0 Upper */ +#define PCI_HT_SW_BLR_LIM0_LO 0x2 /* Limit 0 Lower */ +#define PCI_HT_SW_BLR_LIM0_HI 0x3 /* Limit 0 Upper */ + + /* Secondary Base indices */ +#define PCI_HT_SW_SB_LO 0x0 /* Secondary Base[31:1], Enable */ +#define PCI_HT_SW_S0_HI 0x1 /* Secondary Base Upper */ + +/* HyperTransport: Interrupt Discovery and Configuration */ +#define PCI_HT_IDC_IDX 2 /* Index Register */ +#define PCI_HT_IDC_DATA 4 /* Data Register */ +#define PCI_HT_IDC_SIZEOF 8 + + /* Register indices */ +#define PCI_HT_IDC_IDX_LINT 0x01 /* Last Interrupt Register */ +#define PCI_HT_IDC_LINT 0x00ff0000 /* Last interrupt definition */ +#define PCI_HT_IDC_IDX_IDR 0x10 /* Interrupt Definition Registers */ + /* Low part (at index) */ +#define PCI_HT_IDC_IDR_MASK 0x10000001 /* Mask */ +#define PCI_HT_IDC_IDR_POL 0x10000002 /* Polarity */ +#define PCI_HT_IDC_IDR_II_2 0x1000001c /* IntrInfo[4:2]: Message Type */ +#define PCI_HT_IDC_IDR_II_5 0x10000020 /* IntrInfo[5]: Request EOI */ +#define PCI_HT_IDC_IDR_II_6 0x00ffffc0 /* IntrInfo[23:6] */ +#define PCI_HT_IDC_IDR_II_24 0xff000000 /* IntrInfo[31:24] */ + /* High part (at index + 1) */ +#define PCI_HT_IDC_IDR_II_32 0x00ffffff /* IntrInfo[55:32] */ +#define PCI_HT_IDC_IDR_PASSPW 0x40000000 /* PassPW setting for messages */ +#define PCI_HT_IDC_IDR_WEOI 0x80000000 /* Waiting for EOI */ + +/* HyperTransport: Revision ID */ +#define PCI_HT_RID_RID 2 /* Revision Register */ +#define PCI_HT_RID_SIZEOF 4 + +/* HyperTransport: UnitID Clumping */ +#define PCI_HT_UIDC_CS 4 /* Clumping Support Register */ +#define PCI_HT_UIDC_CE 8 /* Clumping Enable Register */ +#define PCI_HT_UIDC_SIZEOF 12 + +/* HyperTransport: Extended Configuration Space Access */ +#define PCI_HT_ECSA_ADDR 4 /* Configuration Address Register */ +#define PCI_HT_ECSA_ADDR_REG 0x00000ffc /* Register */ +#define PCI_HT_ECSA_ADDR_FUN 0x00007000 /* Function */ +#define PCI_HT_ECSA_ADDR_DEV 0x000f1000 /* Device */ +#define PCI_HT_ECSA_ADDR_BUS 0x0ff00000 /* Bus Number */ +#define PCI_HT_ECSA_ADDR_TYPE 0x10000000 /* Access Type */ +#define PCI_HT_ECSA_DATA 8 /* Configuration Data Register */ +#define PCI_HT_ECSA_SIZEOF 12 + +/* HyperTransport: Address Mapping */ +#define PCI_HT_AM_CMD 2 /* Command Register */ +#define PCI_HT_AM_CMD_NDMA 0x000f /* Number of DMA Mappings */ +#define PCI_HT_AM_CMD_IOSIZ 0x01f0 /* I/O Size */ +#define PCI_HT_AM_CMD_MT 0x0600 /* Map Type */ +#define PCI_HT_AM_CMD_MT_40B 0x0000 /* 40-bit */ +#define PCI_HT_AM_CMD_MT_64B 0x0200 /* 64-bit */ + + /* Window Control Register bits */ +#define PCI_HT_AM_SBW_CTR_COMP 0x1 /* Compat */ +#define PCI_HT_AM_SBW_CTR_NCOH 0x2 /* NonCoherent */ +#define PCI_HT_AM_SBW_CTR_ISOC 0x4 /* Isochronous */ +#define PCI_HT_AM_SBW_CTR_EN 0x8 /* Enable */ + +/* HyperTransport: 40-bit Address Mapping */ +#define PCI_HT_AM40_SBNPW 4 /* Secondary Bus Non-Prefetchable Window Register */ +#define PCI_HT_AM40_SBW_BASE 0x000fffff /* Window Base */ +#define PCI_HT_AM40_SBW_CTR 0xf0000000 /* Window Control */ +#define PCI_HT_AM40_SBPW 8 /* Secondary Bus Prefetchable Window Register */ +#define PCI_HT_AM40_DMA_PBASE0 12 /* DMA Window Primary Base 0 Register */ +#define PCI_HT_AM40_DMA_CTR0 15 /* DMA Window Control 0 Register */ +#define PCI_HT_AM40_DMA_CTR_CTR 0xf0 /* Window Control */ +#define PCI_HT_AM40_DMA_SLIM0 16 /* DMA Window Secondary Limit 0 Register */ +#define PCI_HT_AM40_DMA_SBASE0 18 /* DMA Window Secondary Base 0 Register */ +#define PCI_HT_AM40_SIZEOF 12 /* size is variable: 12 + 8 * NDMA */ + +/* HyperTransport: 64-bit Address Mapping */ +#define PCI_HT_AM64_IDX 4 /* Index Register */ +#define PCI_HT_AM64_DATA_LO 8 /* Data Lower Register */ +#define PCI_HT_AM64_DATA_HI 12 /* Data Upper Register */ +#define PCI_HT_AM64_SIZEOF 16 + + /* Register indices */ +#define PCI_HT_AM64_IDX_SBNPW 0x00 /* Secondary Bus Non-Prefetchable Window Register */ +#define PCI_HT_AM64_W_BASE_LO 0xfff00000 /* Window Base Lower */ +#define PCI_HT_AM64_W_CTR 0x0000000f /* Window Control */ +#define PCI_HT_AM64_IDX_SBPW 0x01 /* Secondary Bus Prefetchable Window Register */ +#define PCI_HT_AM64_IDX_PBNPW 0x02 /* Primary Bus Non-Prefetchable Window Register */ +#define PCI_HT_AM64_IDX_DMAPB0 0x04 /* DMA Window Primary Base 0 Register */ +#define PCI_HT_AM64_IDX_DMASB0 0x05 /* DMA Window Secondary Base 0 Register */ +#define PCI_HT_AM64_IDX_DMASL0 0x06 /* DMA Window Secondary Limit 0 Register */ + +/* HyperTransport: MSI Mapping */ +#define PCI_HT_MSIM_CMD 2 /* Command Register */ +#define PCI_HT_MSIM_CMD_EN 0x0001 /* Mapping Active */ +#define PCI_HT_MSIM_CMD_FIXD 0x0002 /* MSI Mapping Address Fixed */ +#define PCI_HT_MSIM_ADDR_LO 4 /* MSI Mapping Address Lower Register */ +#define PCI_HT_MSIM_ADDR_HI 8 /* MSI Mapping Address Upper Register */ +#define PCI_HT_MSIM_SIZEOF 12 + +/* HyperTransport: DirectRoute */ +#define PCI_HT_DR_CMD 2 /* Command Register */ +#define PCI_HT_DR_CMD_NDRS 0x000f /* Number of DirectRoute Spaces */ +#define PCI_HT_DR_CMD_IDX 0x01f0 /* Index */ +#define PCI_HT_DR_EN 4 /* Enable Vector Register */ +#define PCI_HT_DR_DATA 8 /* Data Register */ +#define PCI_HT_DR_SIZEOF 12 + + /* Register indices */ +#define PCI_HT_DR_IDX_BASE_LO 0x00 /* DirectRoute Base Lower Register */ +#define PCI_HT_DR_OTNRD 0x00000001 /* Opposite to Normal Request Direction */ +#define PCI_HT_DR_BL_LO 0xffffff00 /* Base/Limit Lower */ +#define PCI_HT_DR_IDX_BASE_HI 0x01 /* DirectRoute Base Upper Register */ +#define PCI_HT_DR_IDX_LIMIT_LO 0x02 /* DirectRoute Limit Lower Register */ +#define PCI_HT_DR_IDX_LIMIT_HI 0x03 /* DirectRoute Limit Upper Register */ + +/* HyperTransport: VCSet */ +#define PCI_HT_VCS_SUP 4 /* VCSets Supported Register */ +#define PCI_HT_VCS_L1EN 5 /* Link 1 VCSets Enabled Register */ +#define PCI_HT_VCS_L0EN 6 /* Link 0 VCSets Enabled Register */ +#define PCI_HT_VCS_SBD 8 /* Stream Bucket Depth Register */ +#define PCI_HT_VCS_SINT 9 /* Stream Interval Register */ +#define PCI_HT_VCS_SSUP 10 /* Number of Streaming VCs Supported Register */ +#define PCI_HT_VCS_SSUP_0 0x00 /* Streaming VC 0 */ +#define PCI_HT_VCS_SSUP_3 0x01 /* Streaming VCs 0-3 */ +#define PCI_HT_VCS_SSUP_15 0x02 /* Streaming VCs 0-15 */ +#define PCI_HT_VCS_NFCBD 12 /* Non-FC Bucket Depth Register */ +#define PCI_HT_VCS_NFCINT 13 /* Non-FC Bucket Interval Register */ +#define PCI_HT_VCS_SIZEOF 16 + +/* HyperTransport: Retry Mode */ +#define PCI_HT_RM_CTR0 4 /* Control 0 Register */ +#define PCI_HT_RM_CTR_LRETEN 0x01 /* Link Retry Enable */ +#define PCI_HT_RM_CTR_FSER 0x02 /* Force Single Error */ +#define PCI_HT_RM_CTR_ROLNEN 0x04 /* Rollover Nonfatal Enable */ +#define PCI_HT_RM_CTR_FSS 0x08 /* Force Single Stomp */ +#define PCI_HT_RM_CTR_RETNEN 0x10 /* Retry Nonfatal Enable */ +#define PCI_HT_RM_CTR_RETFEN 0x20 /* Retry Fatal Enable */ +#define PCI_HT_RM_CTR_AA 0xc0 /* Allowed Attempts */ +#define PCI_HT_RM_STS0 5 /* Status 0 Register */ +#define PCI_HT_RM_STS_RETSNT 0x01 /* Retry Sent */ +#define PCI_HT_RM_STS_CNTROL 0x02 /* Count Rollover */ +#define PCI_HT_RM_STS_SRCV 0x04 /* Stomp Received */ +#define PCI_HT_RM_CTR1 6 /* Control 1 Register */ +#define PCI_HT_RM_STS1 7 /* Status 1 Register */ +#define PCI_HT_RM_CNT0 8 /* Retry Count 0 Register */ +#define PCI_HT_RM_CNT1 10 /* Retry Count 1 Register */ +#define PCI_HT_RM_SIZEOF 12 + +/* Vendor-Specific Capability (see PCI_EVNDR_xxx for the PCIe version) */ +#define PCI_VNDR_LENGTH 2 /* Length byte */ + +/* PCI Express */ +#define PCI_EXP_FLAGS 0x2 /* Capabilities register */ +#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ +#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ +#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ +#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ +#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ +#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ +#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ +#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */ +#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */ +#define PCI_EXP_TYPE_ROOT_INT_EP 0x9 /* Root Complex Integrated Endpoint */ +#define PCI_EXP_TYPE_ROOT_EC 0xa /* Root Complex Event Collector */ +#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ +#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ +#define PCI_EXP_DEVCAP 0x4 /* Device capabilities */ +#define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */ +#define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */ +#define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */ +#define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */ +#define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */ +#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */ +#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */ +#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ +#define PCI_EXP_DEVCAP_RBE 0x8000 /* Role-Based Error Reporting */ +#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ +#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ +#define PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset */ +#define PCI_EXP_DEVCTL 0x8 /* Device Control */ +#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ +#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ +#define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */ +#define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */ +#define PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering */ +#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ +#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ +#define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */ +#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ +#define PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */ +#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ +#define PCI_EXP_DEVCTL_BCRE 0x8000 /* Bridge Configuration Retry Enable */ +#define PCI_EXP_DEVCTL_FLRESET 0x8000 /* Function-Level Reset [bit shared with BCRE] */ +#define PCI_EXP_DEVSTA 0xa /* Device Status */ +#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */ +#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */ +#define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */ +#define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */ +#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ +#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ +#define PCI_EXP_LNKCAP 0xc /* Link Capabilities */ +#define PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */ +#define PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */ +#define PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */ +#define PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */ +#define PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */ +#define PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */ +#define PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */ +#define PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting */ +#define PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */ +#define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */ +#define PCI_EXP_LNKCTL 0x10 /* Link Control */ +#define PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */ +#define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ +#define PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */ +#define PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */ +#define PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */ +#define PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */ +#define PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */ +#define PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */ +#define PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable */ +#define PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt Interrupt Enable */ +#define PCI_EXP_LNKSTA 0x12 /* Link Status */ +#define PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */ +#define PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */ +#define PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error (obsolete) */ +#define PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */ +#define PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */ +#define PCI_EXP_LNKSTA_DL_ACT 0x2000 /* Data Link Layer in DL_Active State */ +#define PCI_EXP_LNKSTA_BWMGMT 0x4000 /* Bandwidth Mgmt Status */ +#define PCI_EXP_LNKSTA_AUTBW 0x8000 /* Autonomous Bandwidth Mgmt Status */ +#define PCI_EXP_SLTCAP 0x14 /* Slot Capabilities */ +#define PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */ +#define PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */ +#define PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */ +#define PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */ +#define PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */ +#define PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */ +#define PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */ +#define PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */ +#define PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */ +#define PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */ +#define PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */ +#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ +#define PCI_EXP_SLTCTL 0x18 /* Slot Control */ +#define PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */ +#define PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */ +#define PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */ +#define PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */ +#define PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enable */ +#define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */ +#define PCI_EXP_SLTCTL_ATNI 0x00c0 /* Attention Indicator Control */ +#define PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */ +#define PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */ +#define PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */ +#define PCI_EXP_SLTCTL_LLCHG 0x1000 /* Data Link Layer State Changed Enable */ +#define PCI_EXP_SLTSTA 0x1a /* Slot Status */ +#define PCI_EXP_SLTSTA_ATNB 0x0001 /* Attention Button Pressed */ +#define PCI_EXP_SLTSTA_PWRF 0x0002 /* Power Fault Detected */ +#define PCI_EXP_SLTSTA_MRLS 0x0004 /* MRL Sensor Changed */ +#define PCI_EXP_SLTSTA_PRSD 0x0008 /* Presence Detect Changed */ +#define PCI_EXP_SLTSTA_CMDC 0x0010 /* Command Completed */ +#define PCI_EXP_SLTSTA_MRL_ST 0x0020 /* MRL Sensor State */ +#define PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */ +#define PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */ +#define PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */ +#define PCI_EXP_RTCTL 0x1c /* Root Control */ +#define PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */ +#define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */ +#define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */ +#define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */ +#define PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */ +#define PCI_EXP_RTCAP 0x1e /* Root Capabilities */ +#define PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */ +#define PCI_EXP_RTSTA 0x20 /* Root Status */ +#define PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */ +#define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */ +#define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */ +#define PCI_EXP_DEVCAP2 0x24 /* Device capabilities 2 */ +#define PCI_EXP_DEVCTL2 0x28 /* Device Control */ +#define PCI_EXP_DEV2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ranges Supported */ +#define PCI_EXP_DEV2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Value */ +#define PCI_EXP_DEV2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disable Supported */ +#define PCI_EXP_DEV2_ARI 0x0020 /* ARI Forwarding */ +#define PCI_EXP_DEVSTA2 0x2a /* Device Status */ +#define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities */ +#define PCI_EXP_LNKCTL2 0x30 /* Link Control */ +#define PCI_EXP_LNKCTL2_SPEED(x) ((x) & 0xf) /* Target Link Speed */ +#define PCI_EXP_LNKCTL2_CMPLNC 0x0010 /* Enter Compliance */ +#define PCI_EXP_LNKCTL2_SPEED_DIS 0x0020 /* Hardware Autonomous Speed Disable */ +#define PCI_EXP_LNKCTL2_DEEMPHASIS(x) (((x) >> 6) & 1) /* Selectable De-emphasis */ +#define PCI_EXP_LNKCTL2_MARGIN(x) (((x) >> 7) & 7) /* Transmit Margin */ +#define PCI_EXP_LNKCTL2_MOD_CMPLNC 0x0400 /* Enter Modified Compliance */ +#define PCI_EXP_LNKCTL2_CMPLNC_SOS 0x0800 /* Compliance SOS */ +#define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 1) /* Compliance De-emphasis */ +#define PCI_EXP_LNKSTA2 0x32 /* Link Status */ +#define PCI_EXP_LINKSTA2_DEEMPHASIS(x) ((x) & 1) /* Current De-emphasis Level */ +#define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities */ +#define PCI_EXP_SLTCTL2 0x38 /* Slot Control */ +#define PCI_EXP_SLTSTA2 0x3a /* Slot Status */ + +/* MSI-X */ +#define PCI_MSIX_ENABLE 0x8000 +#define PCI_MSIX_MASK 0x4000 +#define PCI_MSIX_TABSIZE 0x07ff +#define PCI_MSIX_TABLE 4 +#define PCI_MSIX_PBA 8 +#define PCI_MSIX_BIR 0x7 + +/* Subsystem vendor/device ID for PCI bridges */ +#define PCI_SSVID_VENDOR 4 +#define PCI_SSVID_DEVICE 6 + +/* PCI Advanced Features */ +#define PCI_AF_CAP 3 +#define PCI_AF_CAP_TP 0x01 +#define PCI_AF_CAP_FLR 0x02 +#define PCI_AF_CTRL 4 +#define PCI_AF_CTRL_FLR 0x01 +#define PCI_AF_STATUS 5 +#define PCI_AF_STATUS_TP 0x01 + +/* SATA Host Bus Adapter */ +#define PCI_SATA_HBA_BARS 4 +#define PCI_SATA_HBA_REG0 8 + +/*** Definitions of extended capabilities ***/ + +/* Advanced Error Reporting */ +#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ +#define PCI_ERR_UNC_TRAIN 0x00000001 /* Undefined in PCIe rev1.1 & 2.0 spec */ +#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ +#define PCI_ERR_UNC_SDES 0x00000020 /* Surprise Down Error */ +#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ +#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ +#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ +#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */ +#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */ +#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */ +#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ +#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ +#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ +#define PCI_ERR_UNC_ACS_VIOL 0x00200000 /* ACS Violation */ +#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */ + /* Same bits as above */ +#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */ + /* Same bits as above */ +#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */ +#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */ +#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */ +#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ +#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ +#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ +#define PCI_ERR_COR_REP_ANFE 0x00002000 /* Advisory Non-Fatal Error */ +#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */ + /* Same bits as above */ +#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */ +#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */ +#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */ +#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */ +#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */ +#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ +#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */ +#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */ +#define PCI_ERR_ROOT_STATUS 48 +#define PCI_ERR_ROOT_COR_SRC 52 +#define PCI_ERR_ROOT_SRC 54 + +/* Virtual Channel */ +#define PCI_VC_PORT_REG1 4 +#define PCI_VC_PORT_REG2 8 +#define PCI_VC_PORT_CTRL 12 +#define PCI_VC_PORT_STATUS 14 +#define PCI_VC_RES_CAP 16 +#define PCI_VC_RES_CTRL 20 +#define PCI_VC_RES_STATUS 26 + +/* Power Budgeting */ +#define PCI_PWR_DSR 4 /* Data Select Register */ +#define PCI_PWR_DATA 8 /* Data Register */ +#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ +#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ +#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ +#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ +#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ +#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ +#define PCI_PWR_CAP 12 /* Capability */ +#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ + +/* Root Complex Link */ +#define PCI_RCLINK_ESD 4 /* Element Self Description */ +#define PCI_RCLINK_LINK1 16 /* First Link Entry */ +#define PCI_RCLINK_LINK_DESC 0 /* Link Entry: Description */ +#define PCI_RCLINK_LINK_ADDR 8 /* Link Entry: Address (64-bit) */ +#define PCI_RCLINK_LINK_SIZE 16 /* Link Entry: sizeof */ + +/* PCIe Vendor-Specific Capability */ +#define PCI_EVNDR_HEADER 4 /* Vendor-Specific Header */ +#define PCI_EVNDR_REGISTERS 8 /* Vendor-Specific Registers */ + +/* Access Control Services */ +#define PCI_ACS_CAP 0x04 /* ACS Capability Register */ +#define PCI_ACS_CAP_VALID 0x0001 /* ACS Source Validation */ +#define PCI_ACS_CAP_BLOCK 0x0002 /* ACS Translation Blocking */ +#define PCI_ACS_CAP_REQ_RED 0x0004 /* ACS P2P Request Redirect */ +#define PCI_ACS_CAP_CMPLT_RED 0x0008 /* ACS P2P Completion Redirect */ +#define PCI_ACS_CAP_FORWARD 0x0010 /* ACS Upstream Forwarding */ +#define PCI_ACS_CAP_EGRESS 0x0020 /* ACS P2P Egress Control */ +#define PCI_ACS_CAP_TRANS 0x0040 /* ACS Direct Translated P2P */ +#define PCI_ACS_CAP_VECTOR(x) (((x) >> 8) & 0xff) /* Egress Control Vector Size */ +#define PCI_ACS_CTRL 0x06 /* ACS Control Register */ +#define PCI_ACS_CTRL_VALID 0x0001 /* ACS Source Validation Enable */ +#define PCI_ACS_CTRL_BLOCK 0x0002 /* ACS Translation Blocking Enable */ +#define PCI_ACS_CTRL_REQ_RED 0x0004 /* ACS P2P Request Redirect Enable */ +#define PCI_ACS_CTRL_CMPLT_RED 0x0008 /* ACS P2P Completion Redirect Enable */ +#define PCI_ACS_CTRL_FORWARD 0x0010 /* ACS Upstream Forwarding Enable */ +#define PCI_ACS_CTRL_EGRESS 0x0020 /* ACS P2P Egress Control Enable */ +#define PCI_ACS_CTRL_TRANS 0x0040 /* ACS Direct Translated P2P Enable */ +#define PCI_ACS_EGRESS_CTRL 0x08 /* Egress Control Vector */ + +/* Alternative Routing-ID Interpretation */ +#define PCI_ARI_CAP 0x04 /* ARI Capability Register */ +#define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */ +#define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */ +#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */ +#define PCI_ARI_CTRL 0x06 /* ARI Control Register */ +#define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */ +#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ +#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ + +/* Address Translation Service */ +#define PCI_ATS_CAP 0x04 /* ATS Capability Register */ +#define PCI_ATS_CAP_IQD(x) ((x) & 0x1f) /* Invalidate Queue Depth */ +#define PCI_ATS_CTRL 0x06 /* ATS Control Register */ +#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */ +#define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */ + +/* Single Root I/O Virtualization */ +#define PCI_IOV_CAP 0x04 /* SR-IOV Capability Register */ +#define PCI_IOV_CAP_VFM 0x00000001 /* VF Migration Capable */ +#define PCI_IOV_CAP_IMN(x) ((x) >> 21) /* VF Migration Interrupt Message Number */ +#define PCI_IOV_CTRL 0x08 /* SR-IOV Control Register */ +#define PCI_IOV_CTRL_VFE 0x0001 /* VF Enable */ +#define PCI_IOV_CTRL_VFME 0x0002 /* VF Migration Enable */ +#define PCI_IOV_CTRL_VFMIE 0x0004 /* VF Migration Interrupt Enable */ +#define PCI_IOV_CTRL_MSE 0x0008 /* VF MSE */ +#define PCI_IOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */ +#define PCI_IOV_STATUS 0x0a /* SR-IOV Status Register */ +#define PCI_IOV_STATUS_MS 0x0001 /* VF Migration Status */ +#define PCI_IOV_INITIALVF 0x0c /* Number of VFs that are initially associated */ +#define PCI_IOV_TOTALVF 0x0e /* Maximum number of VFs that could be associated */ +#define PCI_IOV_NUMVF 0x10 /* Number of VFs that are available */ +#define PCI_IOV_FDL 0x12 /* Function Dependency Link */ +#define PCI_IOV_OFFSET 0x14 /* First VF Offset */ +#define PCI_IOV_STRIDE 0x16 /* Routing ID offset from one VF to the next one */ +#define PCI_IOV_DID 0x1a /* VF Device ID */ +#define PCI_IOV_SUPPS 0x1c /* Supported Page Sizes */ +#define PCI_IOV_SYSPS 0x20 /* System Page Size */ +#define PCI_IOV_BAR_BASE 0x24 /* VF BAR0, VF BAR1, ... VF BAR5 */ +#define PCI_IOV_NUM_BAR 6 /* Number of VF BARs */ +#define PCI_IOV_MSAO 0x3c /* VF Migration State Array Offset */ +#define PCI_IOV_MSA_BIR(x) ((x) & 7) /* VF Migration State BIR */ +#define PCI_IOV_MSA_OFFSET(x) ((x) & 0xfffffff8) /* VF Migration State Offset */ + +/* + * The PCI interface treats multi-function devices as independent + * devices. The slot/function address of each device is encoded + * in a single byte as follows: + * + * 7:3 = slot + * 2:0 = function + */ +#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) +#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) +#define PCI_FUNC(devfn) ((devfn) & 0x07) + +/* Device classes and subclasses */ + +#define PCI_CLASS_NOT_DEFINED 0x0000 +#define PCI_CLASS_NOT_DEFINED_VGA 0x0001 + +#define PCI_BASE_CLASS_STORAGE 0x01 +#define PCI_CLASS_STORAGE_SCSI 0x0100 +#define PCI_CLASS_STORAGE_IDE 0x0101 +#define PCI_CLASS_STORAGE_FLOPPY 0x0102 +#define PCI_CLASS_STORAGE_IPI 0x0103 +#define PCI_CLASS_STORAGE_RAID 0x0104 +#define PCI_CLASS_STORAGE_ATA 0x0105 +#define PCI_CLASS_STORAGE_SATA 0x0106 +#define PCI_CLASS_STORAGE_SAS 0x0107 +#define PCI_CLASS_STORAGE_OTHER 0x0180 + +#define PCI_BASE_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x0200 +#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 +#define PCI_CLASS_NETWORK_FDDI 0x0202 +#define PCI_CLASS_NETWORK_ATM 0x0203 +#define PCI_CLASS_NETWORK_ISDN 0x0204 +#define PCI_CLASS_NETWORK_OTHER 0x0280 + +#define PCI_BASE_CLASS_DISPLAY 0x03 +#define PCI_CLASS_DISPLAY_VGA 0x0300 +#define PCI_CLASS_DISPLAY_XGA 0x0301 +#define PCI_CLASS_DISPLAY_3D 0x0302 +#define PCI_CLASS_DISPLAY_OTHER 0x0380 + +#define PCI_BASE_CLASS_MULTIMEDIA 0x04 +#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 +#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 +#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 +#define PCI_CLASS_MULTIMEDIA_AUDIO_DEV 0x0403 +#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 + +#define PCI_BASE_CLASS_MEMORY 0x05 +#define PCI_CLASS_MEMORY_RAM 0x0500 +#define PCI_CLASS_MEMORY_FLASH 0x0501 +#define PCI_CLASS_MEMORY_OTHER 0x0580 + +#define PCI_BASE_CLASS_BRIDGE 0x06 +#define PCI_CLASS_BRIDGE_HOST 0x0600 +#define PCI_CLASS_BRIDGE_ISA 0x0601 +#define PCI_CLASS_BRIDGE_EISA 0x0602 +#define PCI_CLASS_BRIDGE_MC 0x0603 +#define PCI_CLASS_BRIDGE_PCI 0x0604 +#define PCI_CLASS_BRIDGE_PCMCIA 0x0605 +#define PCI_CLASS_BRIDGE_NUBUS 0x0606 +#define PCI_CLASS_BRIDGE_CARDBUS 0x0607 +#define PCI_CLASS_BRIDGE_RACEWAY 0x0608 +#define PCI_CLASS_BRIDGE_PCI_SEMI 0x0609 +#define PCI_CLASS_BRIDGE_IB_TO_PCI 0x060a +#define PCI_CLASS_BRIDGE_OTHER 0x0680 + +#define PCI_BASE_CLASS_COMMUNICATION 0x07 +#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 +#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 +#define PCI_CLASS_COMMUNICATION_MSERIAL 0x0702 +#define PCI_CLASS_COMMUNICATION_MODEM 0x0703 +#define PCI_CLASS_COMMUNICATION_OTHER 0x0780 + +#define PCI_BASE_CLASS_SYSTEM 0x08 +#define PCI_CLASS_SYSTEM_PIC 0x0800 +#define PCI_CLASS_SYSTEM_DMA 0x0801 +#define PCI_CLASS_SYSTEM_TIMER 0x0802 +#define PCI_CLASS_SYSTEM_RTC 0x0803 +#define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 +#define PCI_CLASS_SYSTEM_OTHER 0x0880 + +#define PCI_BASE_CLASS_INPUT 0x09 +#define PCI_CLASS_INPUT_KEYBOARD 0x0900 +#define PCI_CLASS_INPUT_PEN 0x0901 +#define PCI_CLASS_INPUT_MOUSE 0x0902 +#define PCI_CLASS_INPUT_SCANNER 0x0903 +#define PCI_CLASS_INPUT_GAMEPORT 0x0904 +#define PCI_CLASS_INPUT_OTHER 0x0980 + +#define PCI_BASE_CLASS_DOCKING 0x0a +#define PCI_CLASS_DOCKING_GENERIC 0x0a00 +#define PCI_CLASS_DOCKING_OTHER 0x0a80 + +#define PCI_BASE_CLASS_PROCESSOR 0x0b +#define PCI_CLASS_PROCESSOR_386 0x0b00 +#define PCI_CLASS_PROCESSOR_486 0x0b01 +#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 +#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 +#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 +#define PCI_CLASS_PROCESSOR_MIPS 0x0b30 +#define PCI_CLASS_PROCESSOR_CO 0x0b40 + +#define PCI_BASE_CLASS_SERIAL 0x0c +#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 +#define PCI_CLASS_SERIAL_ACCESS 0x0c01 +#define PCI_CLASS_SERIAL_SSA 0x0c02 +#define PCI_CLASS_SERIAL_USB 0x0c03 +#define PCI_CLASS_SERIAL_FIBER 0x0c04 +#define PCI_CLASS_SERIAL_SMBUS 0x0c05 +#define PCI_CLASS_SERIAL_INFINIBAND 0x0c06 + +#define PCI_BASE_CLASS_WIRELESS 0x0d +#define PCI_CLASS_WIRELESS_IRDA 0x0d00 +#define PCI_CLASS_WIRELESS_CONSUMER_IR 0x0d01 +#define PCI_CLASS_WIRELESS_RF 0x0d10 +#define PCI_CLASS_WIRELESS_OTHER 0x0d80 + +#define PCI_BASE_CLASS_INTELLIGENT 0x0e +#define PCI_CLASS_INTELLIGENT_I2O 0x0e00 + +#define PCI_BASE_CLASS_SATELLITE 0x0f +#define PCI_CLASS_SATELLITE_TV 0x0f00 +#define PCI_CLASS_SATELLITE_AUDIO 0x0f01 +#define PCI_CLASS_SATELLITE_VOICE 0x0f03 +#define PCI_CLASS_SATELLITE_DATA 0x0f04 + +#define PCI_BASE_CLASS_CRYPT 0x10 +#define PCI_CLASS_CRYPT_NETWORK 0x1000 +#define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1010 +#define PCI_CLASS_CRYPT_OTHER 0x1080 + +#define PCI_BASE_CLASS_SIGNAL 0x11 +#define PCI_CLASS_SIGNAL_DPIO 0x1100 +#define PCI_CLASS_SIGNAL_PERF_CTR 0x1101 +#define PCI_CLASS_SIGNAL_SYNCHRONIZER 0x1110 +#define PCI_CLASS_SIGNAL_OTHER 0x1180 + +#define PCI_CLASS_OTHERS 0xff + +/* Several ID's we need in the library */ + +#define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_VENDOR_ID_COMPAQ 0x0e11 Index: Makefile =================================================================== --- Makefile (revision 927) +++ Makefile (working copy) @@ -19,13 +19,13 @@
PROGRAM = flashrom
-CC ?= gcc -STRIP = strip +CC = i586-pc-msdosdjgpp-gcc +STRIP = i586-pc-msdosdjgpp-strip INSTALL = install DIFF = diff PREFIX ?= /usr/local MANDIR ?= $(PREFIX)/share/man -CFLAGS ?= -Os -Wall -Werror -Wshadow +CFLAGS ?= -Os -Wall -Wshadow -I. EXPORTDIR ?= .
OS_ARCH = $(shell uname) @@ -43,7 +43,7 @@
CHIP_OBJS = jedec.o stm50flw0x0x.o w39v040c.o w39v080fa.o sharplhf00l04.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ - sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o + sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o getopt.o
LIB_OBJS = layout.o
@@ -69,7 +69,7 @@ CONFIG_INTERNAL ?= yes
# Always enable serprog for now. Needs to be disabled on Windows. -CONFIG_SERPROG ?= yes +CONFIG_SERPROG = no
# Bitbanging SPI infrastructure is not used yet. CONFIG_BITBANG_SPI ?= no @@ -97,7 +97,7 @@ CONFIG_DRKAISER ?= yes
# Always enable Bus Pirate SPI for now. -CONFIG_BUSPIRATESPI ?= yes +CONFIG_BUSPIRATESPI ?=no
# Disable Dediprog SF100 until support is complete and tested. CONFIG_DEDIPROG ?= no @@ -188,7 +188,8 @@ endif
ifeq ($(NEED_PCI), yes) -LIBS += -lpci +LIBS += libpci.a +#-lpci FEATURE_CFLAGS += -D'NEED_PCI=1' PROGRAMMER_OBJS += pcidev.o physmap.o hwaccess.o ifeq ($(OS_ARCH), NetBSD) @@ -239,8 +240,9 @@ rm -f .test.c .test; exit 1) @rm -f .test.c .test
-ifeq ($(NEED_PCI), yes) +ifeq ($(NEED_PCI), xxx) pciutils: compiler + @printf "Checking for libpci headers... " @$(shell ( echo "#include <pci/pci.h>"; \ echo "struct pci_access *pacc;"; \
On 09.03.2010 21:06, Carl-Daniel Hailfinger wrote:
Review follows. If anyone feels up to the task, just repost the code with the requested changes.
This needs to be
#elif defined (__MSDOS__) if (0) { #else if (iopl(3) != 0) { #endif
Use #elif defined (__MSDOS__) for all changes in this file.
Use #if defined (__MSDOS__) for all changes in this file.
Comments should use /**/ instead of //
+void *map_physical_memory(uint32_t phys_base, uint32_t size) // phys_base must be page aligned +{ // size will be aligned automatically
Explanations for phys_base and size should be in a doxygen comment above the function.
Comments above each line, not to the right of the code.
Please use msg_perr instead of printf, try to keep the 80 column limit by breaking the string apart. gcc can handle stuff like below without problems:
msg_perr("ERROR: foo bar " "baz bang\n");
msg_perr instead of printf, 80 column limit.
A copy of the getopt header. If anything, this needs to be merged separately, but it would be preferable to just pick it up from some generic include path.
A copy of the important libpci headers. If anything, this needs to be merged separately, but it would be preferable to just pick it up from some generic include path.
Superseded by my Makefile patch.
Regards, Carl-Daniel
On 09.03.2010 21:06, Carl-Daniel Hailfinger wrote:
The tarball is now available at another location thanks to Danny (last name unknown): http://cswise.com/flashrom/DOS.tar.gz
SHA1: 3d3396c5a75cad448f264f0d85328b73d0f8bf89 DOS.tar.gz
MD5: f5b76b34a8ca8e71fb2f796ad826b32a DOS.tar.gz
Regards, Carl-Daniel
-
Carl-Daniel Hailfinger