Uprgrae SPIROM for Skylake-D platform

[HubertLin]

Hi,

I would like to use flashrom to upgrade BIOS on Skylake-D platform.

I have done some work to unlock ME and fill W25Q256JVFIQ table in
flashschips.c.

But there still have some opcode problem.

Have you try flashrom on Skylake-D platform before?

Is there any temporary patch for Skylake-D platform after v1.2 version.

I would like to try it, may you please help me?

The problem I meet as below,

1.     ich_spi_send_command: Internal command size error for opcode 0xe9,
got writecnt=1, want >=4

2.     Probing for Winbond W25Q256JVFIQ, 32768 kB: Invalid OPCODE 0x9f, will
not execut

3.     Probing for Winbond W25Q256JVFIQ, 32768 kB: probe_spi_rdid_generic:
id1 0xf7, id

Thank you

BR, Hubert.lin

[David Hendricks]

Hello Hubert,
There was some discussion about Skylake-D a few months ago:
https://www.mail-archive.com/[e-mail]/msg14426.html .
There were some PCI IDs which were added
(https://review.coreboot.org/c/flashrom/+/39780) after flashrom-v1.2

The problems you describe are strange, indeed... Can send a verbose
log using `-V`? The W25Q256JVFIQ is also in the table already (as
W25Q256.V), so I'm curious why you needed to add another chip entry.

On Mon, Jun 1, 2020 at 5:10 PM HubertLin  wrote:
> Hi,
>
> I would like to use flashrom to upgrade BIOS on Skylake-D platform.
>
> I have done some work to unlock ME and fill W25Q256JVFIQ table in flashschips.c.
>
> But there still have some opcode problem.
>
> Have you try flashrom on Skylake-D platform before?
>
> Is there any temporary patch for Skylake-D platform after v1.2 version.
>
> I would like to try it, may you please help me?
>
> The problem I meet as below,
> ich_spi_send_command: Internal command size error for opcode 0xe9, got writecnt=1, want >=4
>
> Probing for Winbond W25Q256JVFIQ, 32768 kB: Invalid OPCODE 0x9f, will not execut
>
> Probing for Winbond W25Q256JVFIQ, 32768 kB: probe_spi_rdid_generic: id1 0xf7, id
>
>
>
> Thank you
>
> BR, Hubert.lin
>
> flashrom mailing list -- [e-mail]
> To unsubscribe send an email to [e-mail]

[HubertLin]

Hi David,

Flashrom upgrade full log as below, may you please guide me how should I do? Thank you.

root@ubuntu:~/hubert/bios# ./flashrom -p internal:boardmismatch=force -l allregion.xml -i bios -w Lightning_R01.0.9_test.bin -c W25Q256.V -V -N
flashrom v1.2-55-gc7e9a6e-dirty on Linux 4.15.18 (x86_64)
flashrom is free software, get the source code at https://flashrom.org

flashrom was built with libpci 3.5.2, GCC 7.4.0, little endian
Command line (12 args): ./flashrom -p internal:boardmismatch=force -l allregion.xml -i bios -w Lightning_R01.0.9_test.bin -c W25Q256.V -V -N
romlayout 00000000 - 01ffffff named bios
Using region: "bios".
Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
Initializing internal programmer
/sys/class/mtd/mtd0 does not exist
No coreboot table found.
Using Internal DMI decoder.
DMI string chassis-type: "Desktop"
DMI string system-manufacturer: "Ufi Space"
DMI string system-product-name: "Default string"
DMI string system-version: "Default string"
DMI string baseboard-manufacturer: "Ufi Space"
DMI string baseboard-product-name: "Default string"
DMI string baseboard-version: "Default string"
Found chipset "Intel C620 Series Chipset (QS/PRQ)" with PCI ID 8086:a1c8.
This chipset is marked as untested. If you are using an up-to-date version
of flashrom *and* were (not) able to successfully update your firmware with it,
then please email a report to [e-mail] including a verbose (-V) log.
Thank you!
Enabling flash write... BIOS_SPI_BC = 0x888: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (SPI)
Top Swap: not enabled
SPI Read Configuration: prefetching enabled, caching enabled,
BIOS_CNTL = 0x89: BIOS Lock Enable: disabled, BIOS Write Enable: enabled
SPIBAR = 0x00007fb8e4b4a000 (phys = 0xfe010000)
0x04: 0x6800 (HSFS)
HSFS: FDONE=0, FCERR=0, AEL=0, SCIP=0, PRR34_LOCKDN=0, WRSDIS=1, FDOPSS=1, FDV=1, FLOCKDN=0
Programming OPCODES... done
0x06: 0x0010 (HSFC)
HSFC: FGO=0, HSFC=8, WET=0, FDBC=0, SME=0
0x0c: 0x00000000 (DLOCK)
DLOCK: BMWAG_LOCKDN=0, BMRAG_LOCKDN=0, SBMWAG_LOCKDN=0, SBMRAG_LOCKDN=0,
       PR0_LOCKDN=0, PR1_LOCKDN=0, PR2_LOCKDN=0, PR3_LOCKDN=0, PR4_LOCKDN=0,
       SSEQ_LOCKDN=0
0x50: 0x00005edf (FRAP)
BMWAG 0x00, BMRAG 0x00, BRWA 0x5e, BRRA 0xdf
0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only.
0x58: 0x1fff1000 FREG1: BIOS region (0x01000000-0x01ffffff) is read-write.
0x5C: 0x0a350001 FREG2: Management Engine region (0x00001000-0x00a35fff) is read-write.
0x80: 0x0fef0a36 FREG11: unknown region (0x00a36000-0x00feffff) has unknown permissions.
Not all flash regions are freely accessible by flashrom. This is most likely
due to an active ME. Please see https://flashrom.org/ME for details.
At least some flash regions are write protected. For write operations,
you should use a flash layout and include only writable regions. See
manpage for more details.
0xa0: 0xc0 (SSFS)
SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0
0xa1: 0xfe0000 (SSFC)
SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=6
0xa4: 0x5006     (PREOP)
0xa6: 0x463b     (OPTYPE)
0xa8: 0x05200302 (OPMENU)
0xac: 0xc79f0190 (OPMENU+4)
0xc4: 0xf1d82084 (LVSCC)
LVSCC: BES=0x0, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1
0xc8: 0x00002000 (UVSCC)
UVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x20
OK.
The following protocols are supported: Parallel, LPC, FWH, SPI.
Probing for Winbond W25Q256.V, 32768 kB: probe_spi_rdid_generic: id1 0xf7, id2 0xa00c
No EEPROM/flash device found.
Note: flashrom can never write if the flash chip isn't found automatically.
Restoring MMIO space at 0x7fb8e4b4a0ac
Restoring MMIO space at 0x7fb8e4b4a0a8
Restoring MMIO space at 0x7fb8e4b4a0a6
Restoring MMIO space at 0x7fb8e4b4a0a4
Restoring PCI config space for 00:1f:5 reg 0xdc

Thank you
BR, Hubert.lin

-----Original Message-----
From: David Hendricks [mailto:[e-mail]] 
Sent: Wednesday, June 03, 2020 5:30 AM
To: HubertLin
Cc: flashrom
Subject: Re: [flashrom] Uprgrae SPIROM for Skylake-D platform

Hello Hubert,
There was some discussion about Skylake-D a few months ago:
https://www.mail-archive.com/[e-mail]/msg14426.html .
There were some PCI IDs which were added
(https://review.coreboot.org/c/flashrom/+/39780) after flashrom-v1.2

The problems you describe are strange, indeed... Can send a verbose log using `-V`? The W25Q256JVFIQ is also in the table already (as W25Q256.V), so I'm curious why you needed to add another chip entry.

On Mon, Jun 1, 2020 at 5:10 PM HubertLin  wrote:
> Hi,
>
> I would like to use flashrom to upgrade BIOS on Skylake-D platform.
>
> I have done some work to unlock ME and fill W25Q256JVFIQ table in flashschips.c.
>
> But there still have some opcode problem.
>
> Have you try flashrom on Skylake-D platform before?
>
> Is there any temporary patch for Skylake-D platform after v1.2 version.
>
> I would like to try it, may you please help me?
>
> The problem I meet as below,
> ich_spi_send_command: Internal command size error for opcode 0xe9, got writecnt=1, want >=4
>
> Probing for Winbond W25Q256JVFIQ, 32768 kB: Invalid OPCODE 0x9f, will not execut
>
> Probing for Winbond W25Q256JVFIQ, 32768 kB: probe_spi_rdid_generic: id1 0xf7, id
>
>
>
> Thank you
>
> BR, Hubert.lin
>
> flashrom mailing list -- [e-mail] To unsubscribe send an 
> email to [e-mail]

[HubertLin]

Hi David,

After I correct BIOS VSCC setting, RIDI data seems normally(probe_spi_rdid_generic: id1 0xef, id2 0x4019), 
But I still get " Invalid OPCODE 0x06" issue in the end, may you please help on this? 
Thank you.

root@ubuntu:~/hubert#
l -i bios -w Lightning_R01.0.9_test.bin -c W25Q256.V -V -N=force -l allregion.xml
flashrom unknown on Linux 4.15.0-20-generic (x86_64)
flashrom is free software, get the source code at https://flashrom.org

flashrom was built with libpci 3.5.2, GCC 7.3.0, little endian
Command line (12 args): ./flashrom -p internal:boardmismatch=force -l allregion.xml -i bios -w Lightning_R01.0.9_test.bin -c W25Q256.V -V -N
romlayout 01000000 - 01ffffff named bios
Using region: "bios".
Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
Initializing internal programmer
/sys/class/mtd/mtd0 does not exist
No coreboot table found.
Using Internal DMI decoder.
DMI string chassis-type: "Desktop"
DMI string system-manufacturer: "Ufi Space"
DMI string system-product-name: "Default string"
DMI string system-version: "Default string"
DMI string baseboard-manufacturer: "Ufi Space"
DMI string baseboard-product-name: "Default string"
DMI string baseboard-version: "Default string"
Found chipset "Intel C620 Series Chipset (QS/PRQ)" with PCI ID 8086:a1c8.
This chipset is marked as untested. If you are using an up-to-date version
of flashrom *and* were (not) able to successfully update your firmware with it,
then please email a report to [e-mail] including a verbose (-V) log.
Thank you!
Enabling flash write... BIOS_SPI_BC = 0x888: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (SPI)
Top Swap: not enabled
SPI Read Configuration: prefetching enabled, caching enabled,
BIOS_CNTL = 0x89: BIOS Lock Enable: disabled, BIOS Write Enable: enabled
SPIBAR = 0x00007feb19741000 (phys = 0xfe010000)
0x04: 0xe800 (HSFS)
HSFS: FDONE=0, FCERR=0, AEL=0, SCIP=0, PRR34_LOCKDN=0, WRSDIS=1, FDOPSS=1, FDV=1, FLOCKDN=1
SPI Configuration is locked down.
Reading OPCODES... done
0x06: 0x0010 (HSFC)
HSFC: FGO=0, HSFC=8, WET=0, FDBC=0, SME=0
0x0c: 0x00000000 (DLOCK)
DLOCK: BMWAG_LOCKDN=0, BMRAG_LOCKDN=0, SBMWAG_LOCKDN=0, SBMRAG_LOCKDN=0,
       PR0_LOCKDN=0, PR1_LOCKDN=0, PR2_LOCKDN=0, PR3_LOCKDN=0, PR4_LOCKDN=0,
       SSEQ_LOCKDN=0
0x50: 0x00005edf (FRAP)
BMWAG 0x00, BMRAG 0x00, BRWA 0x5e, BRRA 0xdf
0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only.
0x58: 0x1fff1000 FREG1: BIOS region (0x01000000-0x01ffffff) is read-write.
0x5C: 0x0a350001 FREG2: Management Engine region (0x00001000-0x00a35fff) is read-write.
0x80: 0x0fef0a36 FREG11: unknown region (0x00a36000-0x00feffff) has unknown permissions.
Not all flash regions are freely accessible by flashrom. This is most likely
due to an active ME. Please see https://flashrom.org/ME for details.
At least some flash regions are write protected. For write operations,
you should use a flash layout and include only writable regions. See
manpage for more details.
0xa0: 0xc0 (SSFS)
SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0
0xa1: 0xfe0000 (SSFC)
SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=6
0xa4: 0x0006     (PREOP)
0xa6: 0x803b     (OPTYPE)
0xa8: 0x05200302 (OPMENU)
0xac: 0x5a009f9f (OPMENU+4)
0xc4: 0xf1d82085 (LVSCC)
LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1
0xc8: 0x20252025 (UVSCC)
UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20
OK.
The following protocols are supported: Parallel, LPC, FWH, SPI.
Probing for Winbond W25Q256.V, 32768 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4019
Found Winbond flash chip "W25Q256.V" (32768 kB, SPI) mapped at physical address 0x00000000fe000000.
Chip status register is 0x00.
This chip may contain one-time programmable memory. flashrom cannot read
and may never be able to write it, hence it may not be able to completely
clone the contents of this chip (see man page for details).
Flash image seems to be a legacy BIOS. Disabling coreboot-related checks.
Invalid OPCODE 0x06, will not execute.
spi_simple_write_cmd failed during command execution
Failed to set correct 4BA mode! Aborting.
Restoring PCI config space for 00:1f:5 reg 0xdc
root@ubuntu:~/hubert#

Thank you
BR, Hubert.lin

-----Original Message-----
From: HubertLin [mailto:[e-mail]] 
Sent: Friday, June 05, 2020 8:58 AM
To: 'David Hendricks'
Cc: 'flashrom'
Subject: RE: [flashrom] Uprgrae SPIROM for Skylake-D platform

Hi David,

Flashrom upgrade full log as below, may you please guide me how should I do? Thank you.

root@ubuntu:~/hubert/bios# ./flashrom -p internal:boardmismatch=force -l allregion.xml -i bios -w Lightning_R01.0.9_test.bin -c W25Q256.V -V -N flashrom v1.2-55-gc7e9a6e-dirty on Linux 4.15.18 (x86_64) flashrom is free software, get the source code at https://flashrom.org

flashrom was built with libpci 3.5.2, GCC 7.4.0, little endian Command line (12 args): ./flashrom -p internal:boardmismatch=force -l allregion.xml -i bios -w Lightning_R01.0.9_test.bin -c W25Q256.V -V -N romlayout 00000000 - 01ffffff named bios Using region: "bios".
Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
Initializing internal programmer
/sys/class/mtd/mtd0 does not exist
No coreboot table found.
Using Internal DMI decoder.
DMI string chassis-type: "Desktop"
DMI string system-manufacturer: "Ufi Space"
DMI string system-product-name: "Default string"
DMI string system-version: "Default string"
DMI string baseboard-manufacturer: "Ufi Space"
DMI string baseboard-product-name: "Default string"
DMI string baseboard-version: "Default string"
Found chipset "Intel C620 Series Chipset (QS/PRQ)" with PCI ID 8086:a1c8.
This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to [e-mail] including a verbose (-V) log.
Thank you!
Enabling flash write... BIOS_SPI_BC = 0x888: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (SPI) Top Swap: not enabled SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x89: BIOS Lock Enable: disabled, BIOS Write Enable: enabled SPIBAR = 0x00007fb8e4b4a000 (phys = 0xfe010000)
0x04: 0x6800 (HSFS)
HSFS: FDONE=0, FCERR=0, AEL=0, SCIP=0, PRR34_LOCKDN=0, WRSDIS=1, FDOPSS=1, FDV=1, FLOCKDN=0 Programming OPCODES... done
0x06: 0x0010 (HSFC)
HSFC: FGO=0, HSFC=8, WET=0, FDBC=0, SME=0
0x0c: 0x00000000 (DLOCK)
DLOCK: BMWAG_LOCKDN=0, BMRAG_LOCKDN=0, SBMWAG_LOCKDN=0, SBMRAG_LOCKDN=0,
       PR0_LOCKDN=0, PR1_LOCKDN=0, PR2_LOCKDN=0, PR3_LOCKDN=0, PR4_LOCKDN=0,
       SSEQ_LOCKDN=0
0x50: 0x00005edf (FRAP)
BMWAG 0x00, BMRAG 0x00, BRWA 0x5e, BRRA 0xdf
0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only.
0x58: 0x1fff1000 FREG1: BIOS region (0x01000000-0x01ffffff) is read-write.
0x5C: 0x0a350001 FREG2: Management Engine region (0x00001000-0x00a35fff) is read-write.
0x80: 0x0fef0a36 FREG11: unknown region (0x00a36000-0x00feffff) has unknown permissions.
Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see https://flashrom.org/ME for details.
At least some flash regions are write protected. For write operations, you should use a flash layout and include only writable regions. See manpage for more details.
0xa0: 0xc0 (SSFS)
SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0
0xa1: 0xfe0000 (SSFC)
SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=6
0xa4: 0x5006     (PREOP)
0xa6: 0x463b     (OPTYPE)
0xa8: 0x05200302 (OPMENU)
0xac: 0xc79f0190 (OPMENU+4)
0xc4: 0xf1d82084 (LVSCC)
LVSCC: BES=0x0, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1
0xc8: 0x00002000 (UVSCC)
UVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x20 OK.
The following protocols are supported: Parallel, LPC, FWH, SPI.
Probing for Winbond W25Q256.V, 32768 kB: probe_spi_rdid_generic: id1 0xf7, id2 0xa00c No EEPROM/flash device found.
Note: flashrom can never write if the flash chip isn't found automatically.
Restoring MMIO space at 0x7fb8e4b4a0ac
Restoring MMIO space at 0x7fb8e4b4a0a8
Restoring MMIO space at 0x7fb8e4b4a0a6
Restoring MMIO space at 0x7fb8e4b4a0a4
Restoring PCI config space for 00:1f:5 reg 0xdc

Thank you
BR, Hubert.lin

-----Original Message-----
From: David Hendricks [mailto:[e-mail]]
Sent: Wednesday, June 03, 2020 5:30 AM
To: HubertLin
Cc: flashrom
Subject: Re: [flashrom] Uprgrae SPIROM for Skylake-D platform

Hello Hubert,
There was some discussion about Skylake-D a few months ago:
https://www.mail-archive.com/[e-mail]/msg14426.html .
There were some PCI IDs which were added
(https://review.coreboot.org/c/flashrom/+/39780) after flashrom-v1.2

The problems you describe are strange, indeed... Can send a verbose log using `-V`? The W25Q256JVFIQ is also in the table already (as W25Q256.V), so I'm curious why you needed to add another chip entry.

On Mon, Jun 1, 2020 at 5:10 PM HubertLin  wrote:
> Hi,
>
> I would like to use flashrom to upgrade BIOS on Skylake-D platform.
>
> I have done some work to unlock ME and fill W25Q256JVFIQ table in flashschips.c.
>
> But there still have some opcode problem.
>
> Have you try flashrom on Skylake-D platform before?
>
> Is there any temporary patch for Skylake-D platform after v1.2 version.
>
> I would like to try it, may you please help me?
>
> The problem I meet as below,
> ich_spi_send_command: Internal command size error for opcode 0xe9, got writecnt=1, want >=4
>
> Probing for Winbond W25Q256JVFIQ, 32768 kB: Invalid OPCODE 0x9f, will not execut
>
> Probing for Winbond W25Q256JVFIQ, 32768 kB: probe_spi_rdid_generic: id1 0xf7, id
>
>
>
> Thank you
>
> BR, Hubert.lin
>
> flashrom mailing list -- [e-mail] To unsubscribe send an 
> email to [e-mail]

[David Hendricks]

Hi Hubert,
What happens if you add "ich_spi_mode=hwseq" to your programmer
parameters, i.e. "-p internal:boardmismatch=force,ich_spi_mode=hwseq"
?

On Tue, Jun 9, 2020 at 4:04 AM HubertLin  wrote:
> Hi David,
>
> After I correct BIOS VSCC setting, RIDI data seems normally(probe_spi_rdid_generic: id1 0xef, id2 0x4019),
> But I still get " Invalid OPCODE 0x06" issue in the end, may you please help on this?
> Thank you.
>
> root@ubuntu:~/hubert#
> l -i bios -w Lightning_R01.0.9_test.bin -c W25Q256.V -V -N=force -l allregion.xml
> flashrom unknown on Linux 4.15.0-20-generic (x86_64)
> flashrom is free software, get the source code at https://flashrom.org
>
> flashrom was built with libpci 3.5.2, GCC 7.3.0, little endian
> Command line (12 args): ./flashrom -p internal:boardmismatch=force -l allregion.xml -i bios -w Lightning_R01.0.9_test.bin -c W25Q256.V -V -N
> romlayout 01000000 - 01ffffff named bios
> Using region: "bios".
> Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
> Initializing internal programmer
> /sys/class/mtd/mtd0 does not exist
> No coreboot table found.
> Using Internal DMI decoder.
> DMI string chassis-type: "Desktop"
> DMI string system-manufacturer: "Ufi Space"
> DMI string system-product-name: "Default string"
> DMI string system-version: "Default string"
> DMI string baseboard-manufacturer: "Ufi Space"
> DMI string baseboard-product-name: "Default string"
> DMI string baseboard-version: "Default string"
> Found chipset "Intel C620 Series Chipset (QS/PRQ)" with PCI ID 8086:a1c8.
> This chipset is marked as untested. If you are using an up-to-date version
> of flashrom *and* were (not) able to successfully update your firmware with it,
> then please email a report to [e-mail] including a verbose (-V) log.
> Thank you!
> Enabling flash write... BIOS_SPI_BC = 0x888: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (SPI)
> Top Swap: not enabled
> SPI Read Configuration: prefetching enabled, caching enabled,
> BIOS_CNTL = 0x89: BIOS Lock Enable: disabled, BIOS Write Enable: enabled
> SPIBAR = 0x00007feb19741000 (phys = 0xfe010000)
> 0x04: 0xe800 (HSFS)
> HSFS: FDONE=0, FCERR=0, AEL=0, SCIP=0, PRR34_LOCKDN=0, WRSDIS=1, FDOPSS=1, FDV=1, FLOCKDN=1
> SPI Configuration is locked down.
> Reading OPCODES... done
> 0x06: 0x0010 (HSFC)
> HSFC: FGO=0, HSFC=8, WET=0, FDBC=0, SME=0
> 0x0c: 0x00000000 (DLOCK)
> DLOCK: BMWAG_LOCKDN=0, BMRAG_LOCKDN=0, SBMWAG_LOCKDN=0, SBMRAG_LOCKDN=0,
>        PR0_LOCKDN=0, PR1_LOCKDN=0, PR2_LOCKDN=0, PR3_LOCKDN=0, PR4_LOCKDN=0,
>        SSEQ_LOCKDN=0
> 0x50: 0x00005edf (FRAP)
> BMWAG 0x00, BMRAG 0x00, BRWA 0x5e, BRRA 0xdf
> 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only.
> 0x58: 0x1fff1000 FREG1: BIOS region (0x01000000-0x01ffffff) is read-write.
> 0x5C: 0x0a350001 FREG2: Management Engine region (0x00001000-0x00a35fff) is read-write.
> 0x80: 0x0fef0a36 FREG11: unknown region (0x00a36000-0x00feffff) has unknown permissions.
> Not all flash regions are freely accessible by flashrom. This is most likely
> due to an active ME. Please see https://flashrom.org/ME for details.
> At least some flash regions are write protected. For write operations,
> you should use a flash layout and include only writable regions. See
> manpage for more details.
> 0xa0: 0xc0 (SSFS)
> SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0
> 0xa1: 0xfe0000 (SSFC)
> SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=6
> 0xa4: 0x0006     (PREOP)
> 0xa6: 0x803b     (OPTYPE)
> 0xa8: 0x05200302 (OPMENU)
> 0xac: 0x5a009f9f (OPMENU+4)
> 0xc4: 0xf1d82085 (LVSCC)
> LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1
> 0xc8: 0x20252025 (UVSCC)
> UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20
> OK.
> The following protocols are supported: Parallel, LPC, FWH, SPI.
> Probing for Winbond W25Q256.V, 32768 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4019
> Found Winbond flash chip "W25Q256.V" (32768 kB, SPI) mapped at physical address 0x00000000fe000000.
> Chip status register is 0x00.
> This chip may contain one-time programmable memory. flashrom cannot read
> and may never be able to write it, hence it may not be able to completely
> clone the contents of this chip (see man page for details).
> Flash image seems to be a legacy BIOS. Disabling coreboot-related checks.
> Invalid OPCODE 0x06, will not execute.
> spi_simple_write_cmd failed during command execution
> Failed to set correct 4BA mode! Aborting.
> Restoring PCI config space for 00:1f:5 reg 0xdc
> root@ubuntu:~/hubert#
>
> Thank you
> BR, Hubert.lin
>
> -----Original Message-----
> From: HubertLin [mailto:[e-mail]]
> Sent: Friday, June 05, 2020 8:58 AM
> To: 'David Hendricks'
> Cc: 'flashrom'
> Subject: RE: [flashrom] Uprgrae SPIROM for Skylake-D platform
>
> Hi David,
>
> Flashrom upgrade full log as below, may you please guide me how should I do? Thank you.
>
> root@ubuntu:~/hubert/bios# ./flashrom -p internal:boardmismatch=force -l allregion.xml -i bios -w Lightning_R01.0.9_test.bin -c W25Q256.V -V -N flashrom v1.2-55-gc7e9a6e-dirty on Linux 4.15.18 (x86_64) flashrom is free software, get the source code at https://flashrom.org
>
> flashrom was built with libpci 3.5.2, GCC 7.4.0, little endian Command line (12 args): ./flashrom -p internal:boardmismatch=force -l allregion.xml -i bios -w Lightning_R01.0.9_test.bin -c W25Q256.V -V -N romlayout 00000000 - 01ffffff named bios Using region: "bios".
> Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
> Initializing internal programmer
> /sys/class/mtd/mtd0 does not exist
> No coreboot table found.
> Using Internal DMI decoder.
> DMI string chassis-type: "Desktop"
> DMI string system-manufacturer: "Ufi Space"
> DMI string system-product-name: "Default string"
> DMI string system-version: "Default string"
> DMI string baseboard-manufacturer: "Ufi Space"
> DMI string baseboard-product-name: "Default string"
> DMI string baseboard-version: "Default string"
> Found chipset "Intel C620 Series Chipset (QS/PRQ)" with PCI ID 8086:a1c8.
> This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to [e-mail] including a verbose (-V) log.
> Thank you!
> Enabling flash write... BIOS_SPI_BC = 0x888: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (SPI) Top Swap: not enabled SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x89: BIOS Lock Enable: disabled, BIOS Write Enable: enabled SPIBAR = 0x00007fb8e4b4a000 (phys = 0xfe010000)
> 0x04: 0x6800 (HSFS)
> HSFS: FDONE=0, FCERR=0, AEL=0, SCIP=0, PRR34_LOCKDN=0, WRSDIS=1, FDOPSS=1, FDV=1, FLOCKDN=0 Programming OPCODES... done
> 0x06: 0x0010 (HSFC)
> HSFC: FGO=0, HSFC=8, WET=0, FDBC=0, SME=0
> 0x0c: 0x00000000 (DLOCK)
> DLOCK: BMWAG_LOCKDN=0, BMRAG_LOCKDN=0, SBMWAG_LOCKDN=0, SBMRAG_LOCKDN=0,
>        PR0_LOCKDN=0, PR1_LOCKDN=0, PR2_LOCKDN=0, PR3_LOCKDN=0, PR4_LOCKDN=0,
>        SSEQ_LOCKDN=0
> 0x50: 0x00005edf (FRAP)
> BMWAG 0x00, BMRAG 0x00, BRWA 0x5e, BRRA 0xdf
> 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only.
> 0x58: 0x1fff1000 FREG1: BIOS region (0x01000000-0x01ffffff) is read-write.
> 0x5C: 0x0a350001 FREG2: Management Engine region (0x00001000-0x00a35fff) is read-write.
> 0x80: 0x0fef0a36 FREG11: unknown region (0x00a36000-0x00feffff) has unknown permissions.
> Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see https://flashrom.org/ME for details.
> At least some flash regions are write protected. For write operations, you should use a flash layout and include only writable regions. See manpage for more details.
> 0xa0: 0xc0 (SSFS)
> SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0
> 0xa1: 0xfe0000 (SSFC)
> SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=6
> 0xa4: 0x5006     (PREOP)
> 0xa6: 0x463b     (OPTYPE)
> 0xa8: 0x05200302 (OPMENU)
> 0xac: 0xc79f0190 (OPMENU+4)
> 0xc4: 0xf1d82084 (LVSCC)
> LVSCC: BES=0x0, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1
> 0xc8: 0x00002000 (UVSCC)
> UVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x20 OK.
> The following protocols are supported: Parallel, LPC, FWH, SPI.
> Probing for Winbond W25Q256.V, 32768 kB: probe_spi_rdid_generic: id1 0xf7, id2 0xa00c No EEPROM/flash device found.
> Note: flashrom can never write if the flash chip isn't found automatically.
> Restoring MMIO space at 0x7fb8e4b4a0ac
> Restoring MMIO space at 0x7fb8e4b4a0a8
> Restoring MMIO space at 0x7fb8e4b4a0a6
> Restoring MMIO space at 0x7fb8e4b4a0a4
> Restoring PCI config space for 00:1f:5 reg 0xdc
>
> Thank you
> BR, Hubert.lin
>
> -----Original Message-----
> From: David Hendricks [mailto:[e-mail]]
> Sent: Wednesday, June 03, 2020 5:30 AM
> To: HubertLin
> Cc: flashrom
> Subject: Re: [flashrom] Uprgrae SPIROM for Skylake-D platform
>
> Hello Hubert,
> There was some discussion about Skylake-D a few months ago:
> https://www.mail-archive.com/[e-mail]/msg14426.html .
> There were some PCI IDs which were added
> (https://review.coreboot.org/c/flashrom/+/39780) after flashrom-v1.2
>
> The problems you describe are strange, indeed... Can send a verbose log using `-V`? The W25Q256JVFIQ is also in the table already (as W25Q256.V), so I'm curious why you needed to add another chip entry.
>
> On Mon, Jun 1, 2020 at 5:10 PM HubertLin  wrote:
> > Hi,
> >
> > I would like to use flashrom to upgrade BIOS on Skylake-D platform.
> >
> > I have done some work to unlock ME and fill W25Q256JVFIQ table in flashschips.c.
> >
> > But there still have some opcode problem.
> >
> > Have you try flashrom on Skylake-D platform before?
> >
> > Is there any temporary patch for Skylake-D platform after v1.2 version.
> >
> > I would like to try it, may you please help me?
> >
> > The problem I meet as below,
> > ich_spi_send_command: Internal command size error for opcode 0xe9, got writecnt=1, want >=4
> >
> > Probing for Winbond W25Q256JVFIQ, 32768 kB: Invalid OPCODE 0x9f, will not execut
> >
> > Probing for Winbond W25Q256JVFIQ, 32768 kB: probe_spi_rdid_generic: id1 0xf7, id
> >
> >
> >
> > Thank you
> >
> > BR, Hubert.lin
> >
> > flashrom mailing list -- [e-mail] To unsubscribe send an
> > email to [e-mail]

[HubertLin]

Hi David,

I have modified OPTYPE and OPMENU to support OPCODE 0x20 sector erase, but it still failed.
//===========================================================
Running OPCODE 0x20 failed at address 0x000000 (payload length was 0).
spi_write_cmd failed during command execution at address 0x1000000
//===========================================================

I also try your suggestion and it also failed.
//===========================================================
The following protocols are supported: Parallel, LPC, FWH, Programmer-specific.
No EEPROM/flash device found.
Note: flashrom can never write if the flash chip isn't found automatically.
//===========================================================

Full log as below:

Command line (12 args): ./flashrom -p internal:boardmismatch=force -l allregion.xml -i bios -w Lightning_R01.2_test.bin -c W25Q256.V -V -N
romlayout 01000000 - 01007fff named bios
Using region: "bios".
Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
Initializing internal programmer
/sys/class/mtd/mtd0 does not exist
No coreboot table found.
Using Internal DMI decoder.
DMI string chassis-type: "Desktop"
DMI string system-manufacturer: "Ufi Space"
DMI string system-product-name: "Default string"
DMI string system-version: "Default string"
DMI string baseboard-manufacturer: "Ufi Space"
DMI string baseboard-product-name: "Default string"
DMI string baseboard-version: "Default string"
Found chipset "Intel C620 Series Chipset (QS/PRQ)" with PCI ID 8086:a1c8.
This chipset is marked as untested. If you are using an up-to-date version
of flashrom *and* were (not) able to successfully update your firmware with it,
then please email a report to [e-mail] including a verbose (-V) log.
Thank you!
Enabling flash write... BIOS_SPI_BC = 0x889: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (SPI)
Top Swap: not enabled
SPI Read Configuration: prefetching enabled, caching enabled,
BIOS_CNTL = 0x89: BIOS Lock Enable: disabled, BIOS Write Enable: enabled
SPIBAR = 0x00007f2bbde94000 (phys = 0xfe010000)
0x04: 0xe800 (HSFS)
HSFS: FDONE=0, FCERR=0, AEL=0, SCIP=0, PRR34_LOCKDN=0, WRSDIS=1, FDOPSS=1, FDV=1, FLOCKDN=1
SPI Configuration is locked down.
Reading OPCODES... done
0x06: 0x0010 (HSFC)
HSFC: FGO=0, HSFC=8, WET=0, FDBC=0, SME=0
0x0c: 0x00000000 (DLOCK)
DLOCK: BMWAG_LOCKDN=0, BMRAG_LOCKDN=0, SBMWAG_LOCKDN=0, SBMRAG_LOCKDN=0,
       PR0_LOCKDN=0, PR1_LOCKDN=0, PR2_LOCKDN=0, PR3_LOCKDN=0, PR4_LOCKDN=0,
       SSEQ_LOCKDN=0
0x50: 0x00005edf (FRAP)
BMWAG 0x00, BMRAG 0x00, BRWA 0x5e, BRRA 0xdf
0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only.
0x58: 0x1fff1000 FREG1: BIOS region (0x01000000-0x01ffffff) is read-write.
0x5C: 0x0a350001 FREG2: Management Engine region (0x00001000-0x00a35fff) is read-write.
0x80: 0x0fef0a36 FREG11: unknown region (0x00a36000-0x00feffff) has unknown permissions.
Not all flash regions are freely accessible by flashrom. This is most likely
due to an active ME. Please see https://flashrom.org/ME for details.
At least some flash regions are write protected. For write operations,
you should use a flash layout and include only writable regions. See
manpage for more details.
0xa0: 0xc4 (SSFS)
SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0
0xa1: 0xfe7f10 (SSFC)
SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=6
0xa4: 0x0006     (PREOP)
0xa6: 0x5438     (OPTYPE)
0xa8: 0x05200300 (OPMENU)
0xac: 0x06e9c59f (OPMENU+4)
0xc4: 0xf1d82085 (LVSCC)
LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1
0xc8: 0x20252025 (UVSCC)
UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20
OK.
The following protocols are supported: Parallel, LPC, FWH, SPI.
Probing for Winbond W25Q256.V, 32768 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4019
Found Winbond flash chip "W25Q256.V" (32768 kB, SPI) mapped at physical address 0x00000000fe000000.
Chip status register is 0x00.
This chip may contain one-time programmable memory. flashrom cannot read
and may never be able to write it, hence it may not be able to completely
clone the contents of this chip (see man page for details).
Flash image seems to be a legacy BIOS. Disabling coreboot-related checks.
Reading old flash chip contents... done.
Erasing and writing flash chip... Trying erase function 0... 0x1000000-0x1000fff:ETransaction error!
SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0
SSFC: SCGO=0, ACS=1, SPOP=0, COP=2, DBC=0, SME=0, SCF=6
Running OPCODE 0x20 failed at address 0x000000 (payload length was 0).
spi_write_cmd failed during command execution at address 0x1000000
Reading current flash chip contents... done. Looking for another erase function.
Trying erase function 1... 0x1000000-0x1007fff:EInvalid OPCODE 0x52, will not execute.
spi_write_cmd failed during command execution at address 0x1000000
Reading current flash chip contents... done. Looking for another erase function.
Trying erase function 2... 0x1000000-0x100ffff:RREInvalid OPCODE 0xd8, will not execute.
spi_write_cmd failed during command execution at address 0x1000000
Reading current flash chip contents... done. Looking for another erase function.
Trying erase function 3... 0x000000-0x1ffffff:R^C
root@ubuntu:~/hubert#

Command line (12 args): ./flashrom -p internal:boardmismatch=force,ich_spi_mode=hwseq -l allregion.xml -i bios -w Lightning_R01.2_test.bin -c W25Q256.V -V -N
romlayout 01000000 - 01007fff named bios
Using region: "bios".
Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
Initializing internal programmer
/sys/class/mtd/mtd0 does not exist
No coreboot table found.
Using Internal DMI decoder.
DMI string chassis-type: "Desktop"
DMI string system-manufacturer: "Ufi Space"
DMI string system-product-name: "Default string"
DMI string system-version: "Default string"
DMI string baseboard-manufacturer: "Ufi Space"
DMI string baseboard-product-name: "Default string"
DMI string baseboard-version: "Default string"
Found chipset "Intel C620 Series Chipset (QS/PRQ)" with PCI ID 8086:a1c8.
This chipset is marked as untested. If you are using an up-to-date version
of flashrom *and* were (not) able to successfully update your firmware with it,
then please email a report to [e-mail] including a verbose (-V) log.
Thank you!
Enabling flash write... BIOS_SPI_BC = 0x889: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (SPI)
Top Swap: not enabled
SPI Read Configuration: prefetching enabled, caching enabled,
BIOS_CNTL = 0x89: BIOS Lock Enable: disabled, BIOS Write Enable: enabled
SPIBAR = 0x00007fb5c0ff7000 (phys = 0xfe010000)
0x04: 0xe800 (HSFS)
HSFS: FDONE=0, FCERR=0, AEL=0, SCIP=0, PRR34_LOCKDN=0, WRSDIS=1, FDOPSS=1, FDV=1, FLOCKDN=1
SPI Configuration is locked down.
Reading OPCODES... done
0x06: 0x0010 (HSFC)
HSFC: FGO=0, HSFC=8, WET=0, FDBC=0, SME=0
0x0c: 0x00000000 (DLOCK)
DLOCK: BMWAG_LOCKDN=0, BMRAG_LOCKDN=0, SBMWAG_LOCKDN=0, SBMRAG_LOCKDN=0,
       PR0_LOCKDN=0, PR1_LOCKDN=0, PR2_LOCKDN=0, PR3_LOCKDN=0, PR4_LOCKDN=0,
       SSEQ_LOCKDN=0
0x50: 0x00005edf (FRAP)
BMWAG 0x00, BMRAG 0x00, BRWA 0x5e, BRRA 0xdf
0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only.
0x58: 0x1fff1000 FREG1: BIOS region (0x01000000-0x01ffffff) is read-write.
0x5C: 0x0a350001 FREG2: Management Engine region (0x00001000-0x00a35fff) is read-write.
0x80: 0x0fef0a36 FREG11: unknown region (0x00a36000-0x00feffff) has unknown permissions.
Not all flash regions are freely accessible by flashrom. This is most likely
due to an active ME. Please see https://flashrom.org/ME for details.
At least some flash regions are write protected. For write operations,
you should use a flash layout and include only writable regions. See
manpage for more details.
0xa0: 0xc4 (SSFS)
SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0
0xa1: 0xfe7f10 (SSFC)
SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=6
0xa4: 0x0006     (PREOP)
0xa6: 0x5438     (OPTYPE)
0xa8: 0x05200300 (OPMENU)
0xac: 0x06e9c59f (OPMENU+4)
0xc4: 0xf1d82085 (LVSCC)
LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1
0xc8: 0x20252025 (UVSCC)
UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20
OK.
The following protocols are supported: Parallel, LPC, FWH, Programmer-specific.
No EEPROM/flash device found.
Note: flashrom can never write if the flash chip isn't found automatically.
root@ubuntu:~/hubert#

Thank you
BR, Hubert.lin

-----Original Message-----
From: David Hendricks [mailto:[e-mail]] 
Sent: Thursday, June 11, 2020 8:56 AM
To: HubertLin
Cc: flashrom
Subject: Re: [flashrom] Uprgrae SPIROM for Skylake-D platform

Hi Hubert,
What happens if you add "ich_spi_mode=hwseq" to your programmer parameters, i.e. "-p internal:boardmismatch=force,ich_spi_mode=hwseq"
?

On Tue, Jun 9, 2020 at 4:04 AM HubertLin  wrote:
> Hi David,
>
> After I correct BIOS VSCC setting, RIDI data seems 
> normally(probe_spi_rdid_generic: id1 0xef, id2 0x4019), But I still get " Invalid OPCODE 0x06" issue in the end, may you please help on this?
> Thank you.
>
> root@ubuntu:~/hubert#
> l -i bios -w Lightning_R01.0.9_test.bin -c W25Q256.V -V -N=force -l 
> allregion.xml flashrom unknown on Linux 4.15.0-20-generic (x86_64) 
> flashrom is free software, get the source code at https://flashrom.org
>
> flashrom was built with libpci 3.5.2, GCC 7.3.0, little endian Command 
> line (12 args): ./flashrom -p internal:boardmismatch=force -l 
> allregion.xml -i bios -w Lightning_R01.0.9_test.bin -c W25Q256.V -V -N 
> romlayout 01000000 - 01ffffff named bios Using region: "bios".
> Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
> Initializing internal programmer
> /sys/class/mtd/mtd0 does not exist
> No coreboot table found.
> Using Internal DMI decoder.
> DMI string chassis-type: "Desktop"
> DMI string system-manufacturer: "Ufi Space"
> DMI string system-product-name: "Default string"
> DMI string system-version: "Default string"
> DMI string baseboard-manufacturer: "Ufi Space"
> DMI string baseboard-product-name: "Default string"
> DMI string baseboard-version: "Default string"
> Found chipset "Intel C620 Series Chipset (QS/PRQ)" with PCI ID 8086:a1c8.
> This chipset is marked as untested. If you are using an up-to-date 
> version of flashrom *and* were (not) able to successfully update your 
> firmware with it, then please email a report to [e-mail] including a verbose (-V) log.
> Thank you!
> Enabling flash write... BIOS_SPI_BC = 0x888: BIOS Interface Lock-Down: 
> enabled, Boot BIOS Straps: 0x0 (SPI) Top Swap: not enabled SPI Read 
> Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x89: 
> BIOS Lock Enable: disabled, BIOS Write Enable: enabled SPIBAR = 
> 0x00007feb19741000 (phys = 0xfe010000)
> 0x04: 0xe800 (HSFS)
> HSFS: FDONE=0, FCERR=0, AEL=0, SCIP=0, PRR34_LOCKDN=0, WRSDIS=1, 
> FDOPSS=1, FDV=1, FLOCKDN=1 SPI Configuration is locked down.
> Reading OPCODES... done
> 0x06: 0x0010 (HSFC)
> HSFC: FGO=0, HSFC=8, WET=0, FDBC=0, SME=0
> 0x0c: 0x00000000 (DLOCK)
> DLOCK: BMWAG_LOCKDN=0, BMRAG_LOCKDN=0, SBMWAG_LOCKDN=0, SBMRAG_LOCKDN=0,
>        PR0_LOCKDN=0, PR1_LOCKDN=0, PR2_LOCKDN=0, PR3_LOCKDN=0, PR4_LOCKDN=0,
>        SSEQ_LOCKDN=0
> 0x50: 0x00005edf (FRAP)
> BMWAG 0x00, BMRAG 0x00, BRWA 0x5e, BRRA 0xdf
> 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only.
> 0x58: 0x1fff1000 FREG1: BIOS region (0x01000000-0x01ffffff) is read-write.
> 0x5C: 0x0a350001 FREG2: Management Engine region (0x00001000-0x00a35fff) is read-write.
> 0x80: 0x0fef0a36 FREG11: unknown region (0x00a36000-0x00feffff) has unknown permissions.
> Not all flash regions are freely accessible by flashrom. This is most 
> likely due to an active ME. Please see https://flashrom.org/ME for details.
> At least some flash regions are write protected. For write operations, 
> you should use a flash layout and include only writable regions. See 
> manpage for more details.
> 0xa0: 0xc0 (SSFS)
> SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0
> 0xa1: 0xfe0000 (SSFC)
> SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=6
> 0xa4: 0x0006     (PREOP)
> 0xa6: 0x803b     (OPTYPE)
> 0xa8: 0x05200302 (OPMENU)
> 0xac: 0x5a009f9f (OPMENU+4)
> 0xc4: 0xf1d82085 (LVSCC)
> LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1
> 0xc8: 0x20252025 (UVSCC)
> UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 OK.
> The following protocols are supported: Parallel, LPC, FWH, SPI.
> Probing for Winbond W25Q256.V, 32768 kB: probe_spi_rdid_generic: id1 
> 0xef, id2 0x4019 Found Winbond flash chip "W25Q256.V" (32768 kB, SPI) mapped at physical address 0x00000000fe000000.
> Chip status register is 0x00.
> This chip may contain one-time programmable memory. flashrom cannot 
> read and may never be able to write it, hence it may not be able to 
> completely clone the contents of this chip (see man page for details).
> Flash image seems to be a legacy BIOS. Disabling coreboot-related checks.
> Invalid OPCODE 0x06, will not execute.
> spi_simple_write_cmd failed during command execution Failed to set 
> correct 4BA mode! Aborting.
> Restoring PCI config space for 00:1f:5 reg 0xdc root@ubuntu:~/hubert#
>
> Thank you
> BR, Hubert.lin
>
> -----Original Message-----
> From: HubertLin [mailto:[e-mail]]
> Sent: Friday, June 05, 2020 8:58 AM
> To: 'David Hendricks'
> Cc: 'flashrom'
> Subject: RE: [flashrom] Uprgrae SPIROM for Skylake-D platform
>
> Hi David,
>
> Flashrom upgrade full log as below, may you please guide me how should I do? Thank you.
>
> root@ubuntu:~/hubert/bios# ./flashrom -p internal:boardmismatch=force 
> -l allregion.xml -i bios -w Lightning_R01.0.9_test.bin -c W25Q256.V -V 
> -N flashrom v1.2-55-gc7e9a6e-dirty on Linux 4.15.18 (x86_64) flashrom 
> is free software, get the source code at https://flashrom.org
>
> flashrom was built with libpci 3.5.2, GCC 7.4.0, little endian Command line (12 args): ./flashrom -p internal:boardmismatch=force -l allregion.xml -i bios -w Lightning_R01.0.9_test.bin -c W25Q256.V -V -N romlayout 00000000 - 01ffffff named bios Using region: "bios".
> Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
> Initializing internal programmer
> /sys/class/mtd/mtd0 does not exist
> No coreboot table found.
> Using Internal DMI decoder.
> DMI string chassis-type: "Desktop"
> DMI string system-manufacturer: "Ufi Space"
> DMI string system-product-name: "Default string"
> DMI string system-version: "Default string"
> DMI string baseboard-manufacturer: "Ufi Space"
> DMI string baseboard-product-name: "Default string"
> DMI string baseboard-version: "Default string"
> Found chipset "Intel C620 Series Chipset (QS/PRQ)" with PCI ID 8086:a1c8.
> This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to [e-mail] including a verbose (-V) log.
> Thank you!
> Enabling flash write... BIOS_SPI_BC = 0x888: BIOS Interface Lock-Down: 
> enabled, Boot BIOS Straps: 0x0 (SPI) Top Swap: not enabled SPI Read 
> Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x89: 
> BIOS Lock Enable: disabled, BIOS Write Enable: enabled SPIBAR = 
> 0x00007fb8e4b4a000 (phys = 0xfe010000)
> 0x04: 0x6800 (HSFS)
> HSFS: FDONE=0, FCERR=0, AEL=0, SCIP=0, PRR34_LOCKDN=0, WRSDIS=1, 
> FDOPSS=1, FDV=1, FLOCKDN=0 Programming OPCODES... done
> 0x06: 0x0010 (HSFC)
> HSFC: FGO=0, HSFC=8, WET=0, FDBC=0, SME=0
> 0x0c: 0x00000000 (DLOCK)
> DLOCK: BMWAG_LOCKDN=0, BMRAG_LOCKDN=0, SBMWAG_LOCKDN=0, SBMRAG_LOCKDN=0,
>        PR0_LOCKDN=0, PR1_LOCKDN=0, PR2_LOCKDN=0, PR3_LOCKDN=0, PR4_LOCKDN=0,
>        SSEQ_LOCKDN=0
> 0x50: 0x00005edf (FRAP)
> BMWAG 0x00, BMRAG 0x00, BRWA 0x5e, BRRA 0xdf
> 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only.
> 0x58: 0x1fff1000 FREG1: BIOS region (0x01000000-0x01ffffff) is read-write.
> 0x5C: 0x0a350001 FREG2: Management Engine region (0x00001000-0x00a35fff) is read-write.
> 0x80: 0x0fef0a36 FREG11: unknown region (0x00a36000-0x00feffff) has unknown permissions.
> Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see https://flashrom.org/ME for details.
> At least some flash regions are write protected. For write operations, you should use a flash layout and include only writable regions. See manpage for more details.
> 0xa0: 0xc0 (SSFS)
> SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0
> 0xa1: 0xfe0000 (SSFC)
> SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=6
> 0xa4: 0x5006     (PREOP)
> 0xa6: 0x463b     (OPTYPE)
> 0xa8: 0x05200302 (OPMENU)
> 0xac: 0xc79f0190 (OPMENU+4)
> 0xc4: 0xf1d82084 (LVSCC)
> LVSCC: BES=0x0, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1
> 0xc8: 0x00002000 (UVSCC)
> UVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x20 OK.
> The following protocols are supported: Parallel, LPC, FWH, SPI.
> Probing for Winbond W25Q256.V, 32768 kB: probe_spi_rdid_generic: id1 0xf7, id2 0xa00c No EEPROM/flash device found.
> Note: flashrom can never write if the flash chip isn't found automatically.
> Restoring MMIO space at 0x7fb8e4b4a0ac Restoring MMIO space at 
> 0x7fb8e4b4a0a8 Restoring MMIO space at 0x7fb8e4b4a0a6 Restoring MMIO 
> space at 0x7fb8e4b4a0a4 Restoring PCI config space for 00:1f:5 reg 
> 0xdc
>
> Thank you
> BR, Hubert.lin
>
> -----Original Message-----
> From: David Hendricks [mailto:[e-mail]]
> Sent: Wednesday, June 03, 2020 5:30 AM
> To: HubertLin
> Cc: flashrom
> Subject: Re: [flashrom] Uprgrae SPIROM for Skylake-D platform
>
> Hello Hubert,
> There was some discussion about Skylake-D a few months ago:
> https://www.mail-archive.com/[e-mail]/msg14426.html .
> There were some PCI IDs which were added
> (https://review.coreboot.org/c/flashrom/+/39780) after flashrom-v1.2
>
> The problems you describe are strange, indeed... Can send a verbose log using `-V`? The W25Q256JVFIQ is also in the table already (as W25Q256.V), so I'm curious why you needed to add another chip entry.
>
> On Mon, Jun 1, 2020 at 5:10 PM HubertLin  wrote:
> > Hi,
> >
> > I would like to use flashrom to upgrade BIOS on Skylake-D platform.
> >
> > I have done some work to unlock ME and fill W25Q256JVFIQ table in flashschips.c.
> >
> > But there still have some opcode problem.
> >
> > Have you try flashrom on Skylake-D platform before?
> >
> > Is there any temporary patch for Skylake-D platform after v1.2 version.
> >
> > I would like to try it, may you please help me?
> >
> > The problem I meet as below,
> > ich_spi_send_command: Internal command size error for opcode 0xe9, got writecnt=1, want >=4
> >
> > Probing for Winbond W25Q256JVFIQ, 32768 kB: Invalid OPCODE 0x9f, will not execut
> >
> > Probing for Winbond W25Q256JVFIQ, 32768 kB: probe_spi_rdid_generic: id1 0xf7, id
> >
> >
> >
> > Thank you
> >
> > BR, Hubert.lin
> >
> > flashrom mailing list -- [e-mail] To unsubscribe send 
> > an email to [e-mail]

[David Hendricks]

Hi Hubert,
> I have modified OPTYPE and OPMENU to support OPCODE 0x20 sector erase, but it still failed.
> //===========================================================
> Running OPCODE 0x20 failed at address 0x000000 (payload length was 0).
> spi_write_cmd failed during command execution at address 0x1000000
> //===========================================================

Opcode 0x20 takes a 3-byte address and 0x1000000 is a 4-byte address,
so this failure makes sense. You either need to use opcode 0x21 which
is 4KiB erase with 4-byte address, or use the extended address
register in the flash chip. I'm not sure how to do that (or if it's
possible) with software sequencing on Skylake-D though...
> I also try your suggestion and it also failed.
> //===========================================================
> The following protocols are supported: Parallel, LPC, FWH, Programmer-specific.
> No EEPROM/flash device found.
> Note: flashrom can never write if the flash chip isn't found automatically.
> //===========================================================

I forgot to mention that for hardware sequencing you should either
omit the chip option or set it to "Opaque flash chip", i.e.
"./flashrom -p internal:boardmismatch=force,ich_spi_mode=hwseq -l
allregion.xml -i bios -w Lightning_R01.2_test.bin -c "Opaque flash
chip" -V -N"

[HubertLin]

Hi David,

Thanks for your help, I finally able to upgrade BIOS and Intel ME with "-c "Opaque flash chip"" parameter.
But I can't find description of "Opaque flash chip" on flashrom wiki, may you please help to explain what is this parameter used for? 
Or guide us where can I find the document.

Thank you
BR, Hubert.lin

-----Original Message-----
From: David Hendricks [mailto:[e-mail]] 
Sent: Saturday, June 13, 2020 2:39 AM
To: HubertLin
Cc: flashrom
Subject: Re: [flashrom] Uprgrae SPIROM for Skylake-D platform

Hi Hubert,
> I have modified OPTYPE and OPMENU to support OPCODE 0x20 sector erase, but it still failed.
> //===========================================================
> Running OPCODE 0x20 failed at address 0x000000 (payload length was 0).
> spi_write_cmd failed during command execution at address 0x1000000 
> //===========================================================

Opcode 0x20 takes a 3-byte address and 0x1000000 is a 4-byte address, so this failure makes sense. You either need to use opcode 0x21 which is 4KiB erase with 4-byte address, or use the extended address register in the flash chip. I'm not sure how to do that (or if it's
possible) with software sequencing on Skylake-D though...
> I also try your suggestion and it also failed.
> //===========================================================
> The following protocols are supported: Parallel, LPC, FWH, Programmer-specific.
> No EEPROM/flash device found.
> Note: flashrom can never write if the flash chip isn't found automatically.
> //===========================================================

I forgot to mention that for hardware sequencing you should either omit the chip option or set it to "Opaque flash chip", i.e.
"./flashrom -p internal:boardmismatch=force,ich_spi_mode=hwseq -l allregion.xml -i bios -w Lightning_R01.2_test.bin -c "Opaque flash chip" -V -N"

[David Hendricks]

Hello Hubert,

Thanks for your help, I finally able to upgrade BIOS and Intel ME with "-c
> "Opaque flash chip"" parameter.

I'm glad you got it working! For what it's worth you probably don't even
need to use the '-c' option when using hardware sequencing.
> But I can't find description of "Opaque flash chip" on flashrom wiki, may
> you please help to explain what is this parameter used for?
> Or guide us where can I find the document.

That is a great question. I took a stab at adding a brief explanation here:
https://review.coreboot.org/c/flashrom/+/42485. Let me know if that
explanation is helpful and feel free to chime in on that patch with
suggestions.

For more details, Stefan Tauner also wrote a blog post about it here:
https://blogs.coreboot.org/blog/2011/06/11/gsoc-2011-flashrom-part-1