This kind of chip seems to be behind Altera's EPCQ16 that is used to store configuration of FPGAs on some boards. No official datasheet matching the chip is available. The chip definition bases on the datasheet of the EPCQ16 and other Micron chips of the same familiy.
Its existence and functionality via SFDP was reported by Peter Ma.
Signed-off-by: Stefan Tauner stefan.tauner@alumni.tuwien.ac.at
On Thu, 28 Jul 2016 19:59:59 +0000 "Ma, Peter" peter.ma@intel.com wrote:
I just received a new set of boards with the Altera EPCQ16 that we discussed before. Something odd happened: I would use flashrom and it would do the usual "SFDP-capable chip" (2048 kB, SPI).
But on subsequent tries (even after re-boots), flashrom is coming back with: Found ST flash chip "unknown ST SPI chip" (0 kB, SPI)
Have any idea as to what could be going wrong?
Not exactly, no. Apparently something you did changed the chip's reaction to the SFDP query opcode or something similar. You could try lowering the SPI frequency and look for a changed behavior while probing for SFDP. If that fails you could also try the attached patch that adds a chip definition that should work for your variation as well.
--- flashchips.c | 39 ++++++++++++++++++++++++++++++++++++++- flashchips.h | 2 ++ 2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/flashchips.c b/flashchips.c index 40b6b8e..30c50ca 100644 --- a/flashchips.c +++ b/flashchips.c @@ -9505,7 +9505,7 @@ const struct flashchip flashchips[] = {
{ .vendor = "Micron/Numonyx/ST", - .name = "N25Q016", + .name = "N25Q016..1E", .bustype = BUS_SPI, .manufacture_id = ST_ID, .model_id = ST_N25Q016__1E, @@ -9542,6 +9542,43 @@ const struct flashchip flashchips[] = {
{ .vendor = "Micron/Numonyx/ST", + .name = "N25Q016..3E", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q016__3E, + .total_size = 2048, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron/Numonyx/ST", .name = "N25Q032..1E", .bustype = BUS_SPI, .manufacture_id = ST_ID, diff --git a/flashchips.h b/flashchips.h index 9ffb30f..7dfe985 100644 --- a/flashchips.h +++ b/flashchips.h @@ -839,6 +839,8 @@ #define ST_MT28GU256___2 0x8904 #define ST_MT28GU512___1 0x887E #define ST_MT28GU512___2 0x8881 +/* The N25Q family is also used by Altera in its EPCQ series. */ +#define ST_N25Q016__3E 0xBA15 /* N25Q016, 3.0V, (uniform sectors expected) */ #define ST_N25Q016__1E 0xBB15 /* N25Q016, 1.8V, (uniform sectors expected) */ #define ST_N25Q032__3E 0xBA16 /* N25Q032, 3.0V, (uniform sectors expected) */ #define ST_N25Q032__1E 0xBB16 /* N25Q032, 1.8V, (uniform sectors expected) */
Hi, Stefan...
Nevermind, I think I know what happened: previous to the CPU accessing this SPI Flash, the FPGA attempted to load from it in QSPI mode. So that implies that the FPGA set the QE bit, which keeps it stuck at QSPI mode...
Regards, --------------------------------------------------------- Peter Ma | email: peter.ma@intel.com Senior Design Engineer | tel: +1 (604) 742 5778 Intel of Canada, Ltd. | fax: +1 (604) 639 1185 #688 - 1333 West Broadway, Vancouver, BC, Canada, V6H 4C1
-----Original Message----- From: Stefan Tauner [mailto:stefan.tauner@alumni.tuwien.ac.at] Sent: Thursday, July 28, 2016 3:36 PM To: Ma, Peter peter.ma@intel.com Cc: flashrom@flashrom.org; Stefan Tauner stefan.tauner@alumni.tuwien.ac.at Subject: [PATCH] Add support for Micron N25Q016..3E
This kind of chip seems to be behind Altera's EPCQ16 that is used to store configuration of FPGAs on some boards. No official datasheet matching the chip is available. The chip definition bases on the datasheet of the EPCQ16 and other Micron chips of the same familiy.
Its existence and functionality via SFDP was reported by Peter Ma.
Signed-off-by: Stefan Tauner stefan.tauner@alumni.tuwien.ac.at
On Thu, 28 Jul 2016 19:59:59 +0000 "Ma, Peter" peter.ma@intel.com wrote:
I just received a new set of boards with the Altera EPCQ16 that we discussed before. Something odd happened: I would use flashrom and it would do the usual "SFDP-capable chip" (2048 kB, SPI).
But on subsequent tries (even after re-boots), flashrom is coming back with: Found ST flash chip "unknown ST SPI chip" (0 kB, SPI)
Have any idea as to what could be going wrong?
Not exactly, no. Apparently something you did changed the chip's reaction to the SFDP query opcode or something similar. You could try lowering the SPI frequency and look for a changed behavior while probing for SFDP. If that fails you could also try the attached patch that adds a chip definition that should work for your variation as well.
--- flashchips.c | 39 ++++++++++++++++++++++++++++++++++++++- flashchips.h | 2 ++ 2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/flashchips.c b/flashchips.c index 40b6b8e..30c50ca 100644 --- a/flashchips.c +++ b/flashchips.c @@ -9505,7 +9505,7 @@ const struct flashchip flashchips[] = {
{ .vendor = "Micron/Numonyx/ST", - .name = "N25Q016", + .name = "N25Q016..1E", .bustype = BUS_SPI, .manufacture_id = ST_ID, .model_id = ST_N25Q016__1E, @@ -9542,6 +9542,43 @@ const struct flashchip flashchips[] = {
{ .vendor = "Micron/Numonyx/ST", + .name = "N25Q016..3E", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q016__3E, + .total_size = 2048, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron/Numonyx/ST", .name = "N25Q032..1E", .bustype = BUS_SPI, .manufacture_id = ST_ID, diff --git a/flashchips.h b/flashchips.h index 9ffb30f..7dfe985 100644 --- a/flashchips.h +++ b/flashchips.h @@ -839,6 +839,8 @@ #define ST_MT28GU256___2 0x8904 #define ST_MT28GU512___1 0x887E #define ST_MT28GU512___2 0x8881 +/* The N25Q family is also used by Altera in its EPCQ series. */ +#define ST_N25Q016__3E 0xBA15 /* N25Q016, 3.0V, (uniform sectors expected) */ #define ST_N25Q016__1E 0xBB15 /* N25Q016, 1.8V, (uniform sectors expected) */ #define ST_N25Q032__3E 0xBA16 /* N25Q032, 3.0V, (uniform sectors expected) */ #define ST_N25Q032__1E 0xBB16 /* N25Q032, 1.8V, (uniform sectors expected) */ -- Kind regards, Stefan Tauner
-
Ma, Peter -
Stefan Tauner