[PATCH] ft2232_spi.c: Added MPSSE controller reset

[Boris Baykov]

Added MPSSE reset according to FTDI Application Notes AN114.

Signed-off-by: Boris Baykov 
---
diff -U 5 -N ./flashrom/ft2232_spi.c ./flashrom.ftdi_mpsse_init/ft2232_spi.c
--- ./flashrom/ft2232_spi.c     2015-01-25 10:16:05.372174400 +0300
+++ ./flashrom.ftdi_mpsse_init/ft2232_spi.c     2015-01-25 10:17:50.000000000 +0300
@@ -75,10 +75,11 @@
        {0},
 };

#define DEFAULT_DIVISOR 2

+#define BITMODE_BITBANG_RESET  0
 #define BITMODE_BITBANG_NORMAL 1
 #define BITMODE_BITBANG_SPI    2

/* The variables cs_bits and pindir store the values for the "set data bits low byte" MPSSE command that
  * sets the initial state and the direction of the I/O pins. The pin offsets are as follows:
@@ -352,10 +353,14 @@

if (ftdi_write_data_set_chunksize(ftdic, 256)) {
                msg_perr("Unable to set chunk size (%s).\n", ftdi_get_error_string(ftdic));
        }

+       if (ftdi_set_bitmode(ftdic, 0x00, BITMODE_BITBANG_RESET) < 0) {
+               msg_perr("Unable to reset MPSSE controller (%s).\n", ftdi_get_error_string(ftdic));
+       }
+
        if (ftdi_set_bitmode(ftdic, 0x00, BITMODE_BITBANG_SPI) < 0) {
                msg_perr("Unable to set bitmode to SPI (%s).\n", ftdi_get_error_string(ftdic));
        }

if (clock_5x) {

[Stefan Tauner]

On Sun, 25 Jan 2015 10:33:41 +0300
Boris Baykov  wrote:
> Added MPSSE reset according to FTDI Application Notes AN114.
> Signed-off-by: Boris Baykov
>
> diff -U 5 -N ./flashrom/ft2232_spi.c ./flashrom.ftdi_mpsse_init/ft2232_spi.c
> --- ./flashrom/ft2232_spi.c     2015-01-25 10:16:05.372174400 +0300
> +++ ./flashrom.ftdi_mpsse_init/ft2232_spi.c     2015-01-25 10:17:50.000000000 +0300
> @@ -75,10 +75,11 @@
>         {0},
>  };
>
> #define DEFAULT_DIVISOR 2
>
> +#define BITMODE_BITBANG_RESET  0
>  #define BITMODE_BITBANG_NORMAL 1
>  #define BITMODE_BITBANG_SPI    2
>
> /* The variables cs_bits and pindir store the values for the "set data bits low byte" MPSSE command that
> sets the initial state and the direction of the I/O pins. The pin offsets are as follows:
>
> @@ -352,10 +353,14 @@
>     if (ftdi_write_data_set_chunksize(ftdic, 256)) {
>             msg_perr("Unable to set chunk size (%s).\n", ftdi_get_error_string(ftdic));
>     }
>
>   if (ftdi_set_bitmode(ftdic, 0x00, BITMODE_BITBANG_RESET) < 0) {
>           msg_perr("Unable to reset MPSSE controller (%s).\n", ftdi_get_error_string(ftdic));
>   }
>   if (ftdi_set_bitmode(ftdic, 0x00, BITMODE_BITBANG_SPI) < 0) {
>           msg_perr("Unable to set bitmode to SPI (%s).\n", ftdi_get_error_string(ftdic));
>   }
>
>   if (clock_5x) {

Yes, that's probably a good idea, thank you.
For *H devices we should also disable three-phase data clocking (0x8D)
and adaptive clocking (0x97). It's probably overkill but it shouldn't
hurt either I guess (and it is recommended by the docs). That said, I
don't want to commit that before the imminent 0.9.8 release. I will
commit it (a refined version with the additional disables) shortly
after release.