Info for supermicro x7dw-n

[Michael Melcher]

# ../flashrom/flashrom -w real.rom    
flashrom v0.9.0-r653
No coreboot table found.
Found chipset "Intel 631xESB/632xESB/3100", enabling flash write... OK.
This chipset supports the following protocols: Non-SPI.
Calibrating delay loop... OK.
Found chip "SST SST49LF016C" (2048 KB, FWH) at physical address
0xffe00000.
Flash image seems to be a legacy BIOS. Disabling checks.
Writing flash chip... Programming page: ERASE FAILED at 0x00000000!
Expected=0xff, Read=0x80
ERASE FAILED!
ERASE FAILED!
Verifying flash... VERIFY FAILED at 0x00000000! Expected=0xf8, Read=0x80

[PATCH] Reset SST49LF016C after erase

[Carl-Daniel Hailfinger]

Reset SST49LF016C after erase to exit the read status register mode.
Without this, all reads after erase will return 0x80 instead of the real
memory contents.

Signed-off-by: Carl-Daniel Hailfinger

Index: flashrom-sst49lf016c_reset_after_erase/sst49lfxxxc.c
===================================================================
--- flashrom-sst49lf016c_reset_after_erase/sst49lfxxxc.c	(Revision 653)
+++ flashrom-sst49lf016c_reset_after_erase/sst49lfxxxc.c	(Arbeitskopie)
@@ -91,6 +91,7 @@
    		return (-1);
    	}
    } while (!(status & STATUS_WSMS));
+	chip_writeb(RESET, bios);

if (check_erased_range(flash, address, sector_size)) {
    	fprintf(stderr, "ERASE FAILED!\n");

[PATCH] Reset SST49LF016C after erase

[Luc Verhaegen]

On Mon, Jul 20, 2009 at 04:57:56PM +0200, Carl-Daniel Hailfinger wrote:
> Reset SST49LF016C after erase to exit the read status register mode.
> Without this, all reads after erase will return 0x80 instead of the real
> memory contents.
>
> Signed-off-by: Carl-Daniel Hailfinger

Since Michael Melcher tested this successfully on irc:

Acked-by: Luc Verhaegen

Luc Verhaegen.