Using my GPIO finder posted earlier, I have the gpio needed to enable flashing on the dell. I would like to get a patch together but have not done this mainboard enable thing. I would like to do this in the most-approved manner.
Basically need to match the dell mainboard, find the 8086:24d0 bridge, look up a BAR, and twiddle one little gpio line.
The northbridge looks like this: 00:00.0 Host bridge: Intel Corporation E7520 Memory Controller Hub (rev 09) 00: 86 80 90 35 46 01 90 00 09 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 6c 01 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 41 10 00 00 00 00 00 00 00 00 00 00 00 50: 0c 20 4a 00 00 00 00 00 00 10 11 11 01 00 00 10 60: 10 10 10 10 20 20 30 30 00 00 00 00 00 00 00 00 70: 0a 00 0a 0a 00 00 00 00 44 11 5e 55 1e 02 20 2c 80: 41 28 41 00 00 00 00 00 80 01 00 f0 88 00 00 00 90: 00 00 00 00 00 aa 04 39 aa aa 0c 30 75 08 12 07 a0: 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 b0: cc 00 99 55 00 00 00 00 00 00 00 00 00 00 00 00 c0: 44 c0 50 33 00 e0 60 00 67 00 28 00 30 00 00 e0 d0: 02 28 00 0e 03 00 00 00 00 00 93 b5 00 00 00 00 e0: 00 00 00 00 00 00 00 00 34 3e 00 00 00 00 00 00 f0: 00 00 00 00 10 01 02 00 80 0f 0c 00 00 00 00 00
suggestions welcome.
ron
Hi Ron,
here's an incomplete patch. Is is missing the exact GPIO number, but the datasheet is clear that the GPIO must be between 16 and 31 (inclusive). GPIOs below 16 are input only and thus unusable for flash write enables.
Please send complete output of "lspci -nnvvxxx" so I can find a suitable set of PCI devices to match on for the board_enable array.
On 18.09.2009 23:27, ron minnich wrote:
Using my GPIO finder posted earlier, I have the gpio needed to enable flashing on the dell. I would like to get a patch together but have not done this mainboard enable thing. I would like to do this in the most-approved manner.
As stated above, the patch is missing PCI IDs for the board enable array and the exact GPIO number (XX). That's it.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Index: flashrom-boardenable_cleanup_arima_hdama/board_enable.c =================================================================== --- flashrom-boardenable_cleanup_arima_hdama/board_enable.c (Revision 725) +++ flashrom-boardenable_cleanup_arima_hdama/board_enable.c (Arbeitskopie) @@ -569,6 +569,17 @@ }
/** + * Suited for the Dell S1850. All parameters except the last one are documented + * in the public Intel 82801EB ICH5 / 82801ER ICH5R Datasheet. The last + * parameter (GPIO number) has to be in the range [16,31] according to said + * Intel Datasheet and can be found by exhaustive search. + */ +static int ich5_gpioXX_raise(const char *name) +{ + return ich_gpio_raise(name, 0x8086, 0x24d0, 0x58, 0x0c, 0xffc0, XX); +} + +/** * Suited for MSI MS-7046. */ static int ich6_gpio19_raise(const char *name)
here's the lspci
thanks!
ron
On 19.09.2009 02:04, ron minnich wrote:
here's the lspci
Thanks. To be honest, I think our PCI ID tables need a lot more IDs to be accurate, but for now I picked the following devices as trigger: Intel E7520 Memory Controller Hub (with Dell subsystem) LSI/symbios/NCR 53c1030 PCI-X Fusion-MPT Dual Ultra320 SCSI (with Dell subsystem) If you think other dell boards may have these devices as well, we probably have to kill the subsystem ID for one of them to disable automatic matching.
The only thing left to do is to replace XX with the correct GPIO number (between 16 and 31). After that it should work. I couldn't find the GPIO number in any of your mails, but you said you used the GPIO finder program, so a dump/output from that program would help me pick the correct number.
I picked "dell","s1850" as coreboot IDs for now. However, please note that the dell/s1850 target in the coreboot v2 tree has completely incorrect IDs which should be fixed: default CONFIG_MAINBOARD_PART_NUMBER="X6DHR" default CONFIG_MAINBOARD_VENDOR= "Supermicro" default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Index: flashrom-boardenable_dell_s1850/board_enable.c =================================================================== --- flashrom-boardenable_dell_s1850/board_enable.c (Revision 725) +++ flashrom-boardenable_dell_s1850/board_enable.c (Arbeitskopie) @@ -569,6 +569,17 @@ }
/** + * Suited for the Dell S1850. All parameters except the last one are documented + * in the public Intel 82801EB ICH5 / 82801ER ICH5R Datasheet. The last + * parameter (GPIO number) has to be in the range [16,31] according to said + * Intel Datasheet and can be found by exhaustive search. + */ +static int ich5_gpioXX_raise(const char *name) +{ + return ich_gpio_raise(name, 0x8086, 0x24d0, 0x58, 0x0c, 0xffc0, XX); +} + +/** * Suited for MSI MS-7046. */ static int ich6_gpio19_raise(const char *name) @@ -992,6 +1003,7 @@ {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", board_asus_p4p800}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, + {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, "dell", "s1850", "Dell", "S1850", ich5_gpioXX_raise}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3},
On 19.09.2009 16:40, Carl-Daniel Hailfinger wrote:
Thanks. To be honest, I think our PCI ID tables need a lot more IDs to be accurate, but for now I picked the following devices as trigger: Intel E7520 Memory Controller Hub (with Dell subsystem) LSI/symbios/NCR 53c1030 PCI-X Fusion-MPT Dual Ultra320 SCSI (with Dell subsystem) If you think other dell boards may have these devices as well, we probably have to kill the subsystem ID for one of them to disable automatic matching.
For the record, here's my annotated version of the lspci from Ron: 00:00.0 8086:3590 "Intel E7520 Memory Controller Hub" Subsystem: 1028:016c 00:02.0 8086:3595 00:04.0 8086:3597 00:05.0 8086:3598 00:06.0 8086:3599 00:1e.0 8086:244e 00:1f.0 8086:24d0 01:00.0 8086:0330 01:00.2 8086:0332 02:05.0 1000:0030 "LSI Fusion-MPT Dual Ultra320 SCSI" Subsystem: 1028:016c 04:00.0 15b3:6282 "Mellanox InfiniHost III Ex" Subsystem: 15b3:6282 05:00.0 8086:0329 05:00.2 8086:032a 06:07.0 8086:1076 "Intel Gigabit Ethernet" Subsystem: 1028:016d 07:08.0 8086:1076 "Intel Gigabit Ethernet" Subsystem: 1028:016d 08:00.0 1425:0030 "Chelsio T310 10GbE Single Port" Subsystem: 1425:0001 09:0d.0 1002:5159 "ATI Radeon RV100 QY" Subsystem: 1028:016c
All devices without subsystem ID are useless (could be any board). All plugged in devices are useless as well because they could be absent in other boards of the same type. That leaves only very few devices. Now if we had the ability to store full lspci IDs in our board enable structures, we could match with better accuracy.
Regards, Carl-Daniel
A working patch for the s1850 is attached.
ron
On 20.09.2009 06:04, ron minnich wrote:
A working patch for the s1850 is attached.
Thanks. I changed one bitmask and some whitespace. New patch follows for reference.
This enables flashing the Dell S1850 under Linux. This code has been tested.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net Acked-by: Ronald G. Minnich rminnich@gmail.com
Index: flashrom-boardenable_dell_s1850/board_enable.c =================================================================== --- flashrom-boardenable_dell_s1850/board_enable.c (Revision 727) +++ flashrom-boardenable_dell_s1850/board_enable.c (Arbeitskopie) @@ -569,6 +569,17 @@ }
/** + * Suited for the Dell S1850. All parameters except the last one are documented + * in the public Intel 82801EB ICH5 / 82801ER ICH5R Datasheet. The last + * parameter (GPIO number) has to be in the range [16,31] according to said + * Intel Datasheet and was found by exhaustive search. + */ +static int ich5_gpio23_raise(const char *name) +{ + return ich_gpio_raise(name, 0x8086, 0x24d0, 0x58, 0x0c, 0xffc0, 23); +} + +/** * Suited for MSI MS-7046. */ static int ich6_gpio19_raise(const char *name) @@ -992,6 +1003,7 @@ {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", board_asus_p4p800}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, + {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "S1850", ich5_gpio23_raise}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3},
On 23.09.2009 03:58, Carl-Daniel Hailfinger wrote:
On 20.09.2009 06:04, ron minnich wrote:
A working patch for the s1850 is attached.
Thanks. I changed one bitmask and some whitespace. New patch follows for reference.
This enables flashing the Dell S1850 under Linux. This code has been tested.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net Acked-by: Ronald G. Minnich rminnich@gmail.com
And committed in r728. Thanks to Ron for testing and designing the GPIO finder.
Regards, Carl-Daniel
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Carl-Daniel Hailfinger -
ron minnich