Re: [flashrom] FAILED: Adlink NanoX-TC

[Stefan Tauner]

On Wed, 13 Aug 2014 16:24:43 -0300
Ricardo Menzer  wrote:
> I have also found that if I probe the chip three times, it will work
> only once. I mean, if I probe for the chip and it is found, the next
> two probes will fail. The third will work, and the next two will fail
> again, and so on.
> I'm attaching the logs for three consecutive probes and also the
> output of lspci -vvxxxnn.

Hi, the logs look really weird. Is it possible that the boot* SPI bus is
shared with something else? The block diagram in the datasheet does not
look very detailed. *IIRC that SoC has more than one SPI master.

FAILED: Adlink NanoX-TC

[Ricardo Menzer]

Hi Stefan.
I think there's no other device on the SPI bus. Is there a software
way to verify that?
On the baseboard i'm sure there's not (I have the schematics), but I
don't know about the module itself.
The design guide for COM Express
(http://www.picmg.org/openstandards/com-express/) recommends using SPI
only for BIOS. From page 118:
"The SPI interface is defined in this specification to service as an
off-module option for BIOS
storage. [...] Many current chipsets only specify SPI for
BIOS/Firmware storage usage, so the COM.0
specification is limited to that connectivity use-case to enable
maximum compatibility across
Modules and silicon platforms. Additional features, such as SPI-based
Trusted Platform Module
support might be added to a given carrier design, but compatibility is
not guaranteed across
Modules."

Ricardo Menzer
[e-mail]
(32)8865-8805

On Wed, Aug 13, 2014 at 8:08 PM, Stefan Tauner
 wrote:
> On Wed, 13 Aug 2014 16:24:43 -0300
> Ricardo Menzer  wrote:
> > I have also found that if I probe the chip three times, it will work
> > only once. I mean, if I probe for the chip and it is found, the next
> > two probes will fail. The third will work, and the next two will fail
> > again, and so on.
> > I'm attaching the logs for three consecutive probes and also the
> > output of lspci -vvxxxnn.
>
> Hi, the logs look really weird. Is it possible that the boot* SPI bus is
> shared with something else? The block diagram in the datasheet does not
> look very detailed. *IIRC that SoC has more than one SPI master.