[PATCH] Add Spi interface support for Tunnel Creek chipset (3)

[Feldschmid, Ingo]

Hi,

Last changes I submitted have been vs. trunk 1424. Since there is a new
version out, I will resubmit the changes built against the new flashrom
trunk version:

The Intel Tunnel Creek chipset supports both an SPI and an LPC bus. Set
chipset table entry for Tunnel Creek to new function
"enable_flash_tunnelcreek", which will read the hardware straps and
return support for the bus that has been used for booting. This function
uses "ich_init_spi" with ich_generation set to 7 for initializing the
SPI bus if necessary.

SPI functionality tested on actual hardware (see attached file
flashrom.log), Tunnel Creek LPC interface not tested yet (missing
hardware for that).

The attached patch has been created vs. flashrom trunk 1427.

Signed-off-by: Ingo Feldschmid

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[PATCH] Add Spi interface support for Tunnel Creek chipset (3)

[Uwe Hermann]

Hi,

On Mon, Sep 05, 2011 at 09:58:14AM +0200, Feldschmid, Ingo wrote:
> The Intel Tunnel Creek chipset supports both an SPI and an LPC bus.

[...]
> Signed-off-by: Ingo Feldschmid

Thanks a lot for the patch, this is committed with minor changes as r1430.
> /* Enable Flash Writes */
> ret = enable_flash_ich(dev, name, 0xd8);

I added this chunk here, similar to other places which now handle the
return code:

if (ret == ERROR_FATAL)
                return ret;
> /* this adds BUS_SPI */
> buses_supported = BUS_SPI;
> if (ich_init_spi(dev, tmp, rcrb, 7) != 0) {
> if (!ret)
> 	ret = ERROR_NONFATAL;
>    }
>    return ret;

Here we some small whitespace inconsistencies (usage of spaces instead
of one tab for indentation), I fixed those.

Some of the code looks very similar to the one in other functions, maybe
there's some potential for refactoring there, I didn't check closely. If
yes, that can be done in a follow-up patch though.

Cheers, Uwe.

[PATCH] Add Spi interface support for Tunnel Creek chipset (3)

[Stefan Tauner]

hello ingo,

i am trying to refactor your patch and merge it with the poulsbo enable
(something i wanted to do before merging your patch, but uwe was faster
with committing back then...).

i noticed that you try to disable the prefetching and i wonder why. did
you have any problems with it? we dont do this for any other intel
chipset afaics and i would rather leave it alone/use it.

On Mon, 5 Sep 2011 09:58:14 +0200
"Feldschmid, Ingo"  wrote:
> /* Make sure BIOS prefetch mechanism is disabled */
> old = pci_read_byte(dev, 0xd9);
> msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis");
> new = old & ~1;
> if (new != old)
> rpci_write_byte(dev, 0xd9, new);

[Feldschmid, Ingo]

Hi,

Actually, I have taken the Poulsbo function as source for the tunnel creek support function. AFAIK, disabling the prefetch mechanism should make sure we always get the correct values when reading status registers or flash data for verify.

If that's any help, I have taken our board and tested flashrom with and without clearing prefetch, and both versions seem to work.

Best regards,
Ingo

Es gelten unsere Allgemeinen Leistungsbedingungen die 
unter http://www.msc-ge.com/alb abrufbar sind.

Our standard terms and conditions apply which are 
available under http://www.msc-ge.com/alb .

MSC Vertriebs GmbH

Sitz der Gesellschaft:	Industriestrasse 16, 76297 Stutensee 
Handelsregister: 	Mannheim, HRB Nr. 10 3631
Geschäftsführung: 	Lothar Kümmerlin, Rüdiger Kuhn, Silvano Geissler, Johannes Alberti
Umsatzsteuer ID Nr.: 	DE 143 585 507
WEEE Reg. Nr. :		DE 31011852

Gleichmann & Co. Electronics GmbH

Sitz der Gesellschaft:	Schraderstrasse 44, 67227 Frankenthal 
Handelsregister:	Ludwigshafen, HRB Nr. 21305
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-----Ursprüngliche Nachricht-----
Von: Stefan Tauner [mailto:[e-mail]] 
Gesendet: Freitag, 24. August 2012 03:54
An: Feldschmid, Ingo
Cc: [e-mail]
Betreff: Re: [flashrom] [PATCH] Add Spi interface support for Tunnel Creek chipset (3)

hello ingo,

i am trying to refactor your patch and merge it with the poulsbo enable (something i wanted to do before merging your patch, but uwe was faster with committing back then...).

i noticed that you try to disable the prefetching and i wonder why. did you have any problems with it? we dont do this for any other intel chipset afaics and i would rather leave it alone/use it.

On Mon, 5 Sep 2011 09:58:14 +0200
"Feldschmid, Ingo"  wrote:
> /* Make sure BIOS prefetch mechanism is disabled */
> old = pci_read_byte(dev, 0xd9);
> msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis");
> new = old & ~1;
> if (new != old)
> rpci_write_byte(dev, 0xd9, new);