On Fri, Jan 6, 2012 at 5:12 AM, Raghuramchary Jallipalli < Raghuramchary.Jallipalli@lntinfotech.com> wrote:
There is a high likelihood that either the Management Engine (ME) or embedded controller (EC) is interfering with Flashrom operation.
One concern is that flashrom does not appear to set the op.atomic field properly: 0x94: 0x0606 (PREOP) 0x96: 0x0be4 (OPTYPE) 0x98: 0x02030105 (OPMENU) 0x9C: 0xff9f3c20 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xD0: 0x00000000 (FPB) Reading OPCODES... done preop0=0x06, preop1=0x06 op[0]=0x05, 0, 0 op[1]=0x01, 1, 0 op[2]=0x03, 2, 0 op[3]=0x02, 3, 0 op[4]=0x20, 3, 0 op[5]=0x3c, 2, 0 op[6]=0x9f, 0, 0 op[7]=0xff, 0, 0
The third column shows that none of the opcodes are configured as atomic cycles. Thus, Flashrom does not know to set the SPIC_ACS bit ( http://flashrom.org/trac/flashrom/browser/trunk/ichspi.c#L782) when processing these opcodes.
If the "atomic" field is not set properly, then it is possible for ME or EC to interfere with flashrom in between write enable (WREN) opcodes such as block erase and program page.
On Fri, Jan 6, 2012 at 5:12 AM, Raghuramchary Jallipalli < Raghuramchary.Jallipalli@lntinfotech.com> wrote:
Are both ROMs logically present? Or will the jumper only enable one ROM at a given time?
If there are multiple ROMs present, then Flashrom use the "Hardware Sequencing" method of flashing when it detects the "Number of Components" (NC) > 0 in the flash descriptor region: http://flashrom.org/trac/flashrom/browser/trunk/ichspi.c#L1742
See FLMAP0 in the Intel documentation for more details, and ensure the NC field is programmed appropriately for your mainboard configuration.
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David Hendricks