Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- rayer_spi.c | 106 ++++++++++++++++++++++++++++++++++-------------------------- 1 file changed, 61 insertions(+), 45 deletions(-)
diff --git a/rayer_spi.c b/rayer_spi.c index b312610..b4ef205 100644 --- a/rayer_spi.c +++ b/rayer_spi.c @@ -37,21 +37,48 @@ #include "programmer.h" #include "hwaccess.h"
-enum rayer_type { - TYPE_RAYER, - TYPE_XILINX_DLC5, -}; - /* We have two sets of pins, out and in. The numbers for both sets are * independent and are bitshift values, not real pin numbers. * Default settings are for the RayeR hardware. */ -/* Pins for master->slave direction */ -static int rayer_cs_bit = 5; -static int rayer_sck_bit = 6; -static int rayer_mosi_bit = 7; -/* Pins for slave->master direction */ -static int rayer_miso_bit = 6; + +struct rayer_programmer { + const char * type; + const enum test_state status; + const char * description; + const void * private; +}; + +struct rayer_pinout { + int cs_bit; + int sck_bit; + int mosi_bit; + int miso_bit; + void (*preinit)(void *); + int (*shutdown)(void *); +}; + +static struct rayer_pinout rayer_spipgm = { + .cs_bit = 5, + .sck_bit = 6, + .mosi_bit = 7, + .miso_bit = 6, +}; + +static struct rayer_pinout xilinx_dlc5 = { + .cs_bit = 2, + .sck_bit = 1, + .mosi_bit = 0, + .miso_bit = 4, +}; + +struct rayer_programmer rayer_spi_types[] = { + {"rayer", NT, "RayeR SPIPGM", &rayer_spipgm}, + {"xilinx", NT, "Xilinx Parallel Cable III (DLC 5)", &xilinx_dlc5}, + {0}, +}; + +struct rayer_pinout *pinout = NULL;
static uint16_t lpt_iobase;
@@ -60,22 +87,22 @@ static uint8_t lpt_outbyte;
static void rayer_bitbang_set_cs(int val) { - lpt_outbyte &= ~(1 << rayer_cs_bit); - lpt_outbyte |= (val << rayer_cs_bit); + lpt_outbyte &= ~(1 << pinout->cs_bit); + lpt_outbyte |= (val << pinout->cs_bit); OUTB(lpt_outbyte, lpt_iobase); }
static void rayer_bitbang_set_sck(int val) { - lpt_outbyte &= ~(1 << rayer_sck_bit); - lpt_outbyte |= (val << rayer_sck_bit); + lpt_outbyte &= ~(1 << pinout->sck_bit); + lpt_outbyte |= (val << pinout->sck_bit); OUTB(lpt_outbyte, lpt_iobase); }
static void rayer_bitbang_set_mosi(int val) { - lpt_outbyte &= ~(1 << rayer_mosi_bit); - lpt_outbyte |= (val << rayer_mosi_bit); + lpt_outbyte &= ~(1 << pinout->mosi_bit); + lpt_outbyte |= (val << pinout->mosi_bit); OUTB(lpt_outbyte, lpt_iobase); }
@@ -83,8 +110,8 @@ static int rayer_bitbang_get_miso(void) { uint8_t tmp;
- tmp = INB(lpt_iobase + 1); - tmp = (tmp >> rayer_miso_bit) & 0x1; + tmp = INB(lpt_iobase + 1) ^ 0x80; // bit.7 inverted + tmp = (tmp >> pinout->miso_bit) & 0x1; return tmp; }
@@ -99,8 +126,8 @@ static const struct bitbang_spi_master bitbang_spi_master_rayer = {
int rayer_spi_init(void) { + struct rayer_programmer *prog = rayer_spi_types; char *arg = NULL; - enum rayer_type rayer_type = TYPE_RAYER;
/* Non-default port requested? */ arg = extract_programmer_param("iobase"); @@ -138,36 +165,20 @@ int rayer_spi_init(void)
arg = extract_programmer_param("type"); if (arg) { - if (!strcasecmp(arg, "rayer")) { - rayer_type = TYPE_RAYER; - } else if (!strcasecmp(arg, "xilinx")) { - rayer_type = TYPE_XILINX_DLC5; - } else { + for (; prog->type; ++prog) { + if (! strcasecmp (arg, prog->type)) { + break; + } + } + if(! prog->type) { msg_perr("Error: Invalid device type specified.\n"); free(arg); return 1; } + free(arg); } - free(arg); - switch (rayer_type) { - case TYPE_RAYER: - msg_pdbg("Using RayeR SPIPGM pinout.\n"); - /* Bits for master->slave direction */ - rayer_cs_bit = 5; - rayer_sck_bit = 6; - rayer_mosi_bit = 7; - /* Bits for slave->master direction */ - rayer_miso_bit = 6; - break; - case TYPE_XILINX_DLC5: - msg_pdbg("Using Xilinx Parallel Cable III (DLC 5) pinout.\n"); - /* Bits for master->slave direction */ - rayer_cs_bit = 2; - rayer_sck_bit = 1; - rayer_mosi_bit = 0; - /* Bits for slave->master direction */ - rayer_miso_bit = 4; - } + msg_pinfo("Using %s pinout.\n", prog->description); + pinout = (struct rayer_pinout *) prog->private;
if (rget_io_perms()) return 1; @@ -175,6 +186,11 @@ int rayer_spi_init(void) /* Get the initial value before writing to any line. */ lpt_outbyte = INB(lpt_iobase);
+ if (pinout->shutdown) + register_shutdown(pinout->shutdown, (void*)pinout); + if (pinout->preinit) + pinout->preinit(pinout); + if (bitbang_spi_init(&bitbang_spi_master_rayer)) return 1;
Pin 6 on LPT controls a pulldown on MISO/TDO signal.
Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- rayer_spi.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
diff --git a/rayer_spi.c b/rayer_spi.c index b4ef205..dfa093d 100644 --- a/rayer_spi.c +++ b/rayer_spi.c @@ -72,9 +72,22 @@ static struct rayer_pinout xilinx_dlc5 = { .miso_bit = 4, };
+static void dlc5b_preinit(void *); +static int dlc5b_shutdown(void *); + +static struct rayer_pinout xilinx_dlc5b = { + .cs_bit = 2, + .sck_bit = 1, + .mosi_bit = 0, + .miso_bit = 4, + .preinit = dlc5b_preinit, + .shutdown = dlc5b_shutdown, +}; + struct rayer_programmer rayer_spi_types[] = { {"rayer", NT, "RayeR SPIPGM", &rayer_spipgm}, {"xilinx", NT, "Xilinx Parallel Cable III (DLC 5)", &xilinx_dlc5}, + {"dlc-5b", NT, "Xilinx Parallel Cable III (DLC 5) (buffered)", &xilinx_dlc5b}, {0}, };
@@ -197,6 +210,21 @@ int rayer_spi_init(void) return 0; }
+static void dlc5b_preinit(void * data) { + msg_pdbg("dlc5b_preinit\n"); + /* Assert pin 6 to receive MISO. */ + lpt_outbyte |= (1<<4); + OUTB(lpt_outbyte, lpt_iobase); +} + +static int dlc5b_shutdown(void * data) { + msg_pdbg("dlc5b_shutdown\n"); + /* De-assert pin 6 to force MISO low. */ + lpt_outbyte &= ~(1<<4); + OUTB(lpt_outbyte, lpt_iobase); + return 0; +} + #else #error PCI port I/O access is not supported on this architecture yet. #endif
From: "mmcx@mail.ru" mmcx@mail.ru
Signed-off-by: Maksim Kuleshov mmcx@mail.ru Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- rayer_spi.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)
diff --git a/rayer_spi.c b/rayer_spi.c index dfa093d..a2338b6 100644 --- a/rayer_spi.c +++ b/rayer_spi.c @@ -84,10 +84,23 @@ static struct rayer_pinout xilinx_dlc5b = { .shutdown = dlc5b_shutdown, };
+static void byteblaster_preinit(void *); +static int byteblaster_shutdown(void *); + +static struct rayer_pinout altera_byteblaster = { + .cs_bit = 1, + .sck_bit = 0, + .mosi_bit = 6, + .miso_bit = 7, + .preinit = byteblaster_preinit, + .shutdown = byteblaster_shutdown, +}; + struct rayer_programmer rayer_spi_types[] = { {"rayer", NT, "RayeR SPIPGM", &rayer_spipgm}, {"xilinx", NT, "Xilinx Parallel Cable III (DLC 5)", &xilinx_dlc5}, {"dlc-5b", NT, "Xilinx Parallel Cable III (DLC 5) (buffered)", &xilinx_dlc5b}, + {"byteblaster", NT, "Altera ByteBlaster", &altera_byteblaster}, {0}, };
@@ -225,6 +238,19 @@ static int dlc5b_shutdown(void * data) { return 0; }
+static void byteblaster_preinit(void * data){ + msg_pdbg("byteblaster_preinit\n"); + /* Assert #EN signal. */ + OUTB(2, lpt_iobase + 2 ); +} + +static int byteblaster_shutdown(void * data){ + msg_pdbg("byteblaster_shutdown\n"); + /* De-Assert #EN signal. */ + OUTB(0, lpt_iobase + 2 ); + return 0; +} + #else #error PCI port I/O access is not supported on this architecture yet. #endif
From: "mmcx@mail.ru" mmcx@mail.ru
Signed-off-by: Maksim Kuleshov mmcx@mail.ru Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- rayer_spi.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
diff --git a/rayer_spi.c b/rayer_spi.c index a2338b6..a705aad 100644 --- a/rayer_spi.c +++ b/rayer_spi.c @@ -96,11 +96,24 @@ static struct rayer_pinout altera_byteblaster = { .shutdown = byteblaster_shutdown, };
+static void stk200_preinit(void *); +static int stk200_shutdown(void *); + +static struct rayer_pinout atmel_stk200 = { + .cs_bit = 7, + .sck_bit = 4, + .mosi_bit = 5, + .miso_bit = 6, + .preinit = stk200_preinit, + .shutdown = stk200_shutdown, +}; + struct rayer_programmer rayer_spi_types[] = { {"rayer", NT, "RayeR SPIPGM", &rayer_spipgm}, {"xilinx", NT, "Xilinx Parallel Cable III (DLC 5)", &xilinx_dlc5}, {"dlc-5b", NT, "Xilinx Parallel Cable III (DLC 5) (buffered)", &xilinx_dlc5b}, {"byteblaster", NT, "Altera ByteBlaster", &altera_byteblaster}, + {"stk200", NT, "Atmel STK200/300 adapter", &atmel_stk200}, {0}, };
@@ -251,6 +264,21 @@ static int byteblaster_shutdown(void * data){ return 0; }
+static void stk200_preinit(void *data) { + msg_pdbg("stk200_init\n"); + /* Assert #EN signals, set LED signal. */ + lpt_outbyte = (1 << 6) ; + OUTB(lpt_outbyte, lpt_iobase); +} + +static int stk200_shutdown(void *data) { + msg_pdbg("stk200_shutdown\n"); + /* Assert #EN signals, clear LED signal. */ + lpt_outbyte = (1 << 2) | (1 << 3); + OUTB(lpt_outbyte, lpt_iobase); + return 0; +} + #else #error PCI port I/O access is not supported on this architecture yet. #endif
From: "mmcx@mail.ru" mmcx@mail.ru
Signed-off-by: Maksim Kuleshov mmcx@mail.ru Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- rayer_spi.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/rayer_spi.c b/rayer_spi.c index a705aad..61f1ca6 100644 --- a/rayer_spi.c +++ b/rayer_spi.c @@ -108,12 +108,20 @@ static struct rayer_pinout atmel_stk200 = { .shutdown = stk200_shutdown, };
+static struct rayer_pinout wiggler_lpt = { + .cs_bit = 1, + .sck_bit = 2, + .mosi_bit = 3, + .miso_bit = 7, +}; + struct rayer_programmer rayer_spi_types[] = { {"rayer", NT, "RayeR SPIPGM", &rayer_spipgm}, {"xilinx", NT, "Xilinx Parallel Cable III (DLC 5)", &xilinx_dlc5}, {"dlc-5b", NT, "Xilinx Parallel Cable III (DLC 5) (buffered)", &xilinx_dlc5b}, {"byteblaster", NT, "Altera ByteBlaster", &altera_byteblaster}, {"stk200", NT, "Atmel STK200/300 adapter", &atmel_stk200}, + {"wiggler", NT, "Wiggler LPT", &wiggler_lpt}, {0}, };
Hi
It would be great if you can test the updated patchset with new rayer_spi pinouts on actual hardware.
https://bitbucket.org/kmalkki/flashrom/get/rayer_spi.tar.bz2
or
git clone -b rayer_spi https://bitbucket.org/kmalkki/flashrom.git
Thanks, Kyösti
Hi.
1. Byteblaster tested OK. Logs attached. https://bitbucket.org/mmcx/flashrom/commits/ef9639ee291a4b07e139a2afbf218635...
2. Added ppdev support. ppdev tested OK. Logs attached. https://bitbucket.org/mmcx/flashrom/commits/f7a71bb359245c79826061aa054c547e... https://bitbucket.org/mmcx/flashrom/commits/fee6601e451c7b1576af862c94df4495...
-----Original Message----- Date: Thu, 07 Mar 2013 18:19:17 +0200 From: Kyösti Mälkki kyosti.malkki@gmail.com To: flashrom flashrom@flashrom.org Subject: Re: [PATCH 1/5] rayer_spi: Create list of programmer types
Hi
It would be great if you can test the updated patchset with new rayer_spi pinouts on actual hardware.
https://bitbucket.org/kmalkki/flashrom/get/rayer_spi.tar.bz2
or
git clone -b rayer_spi https://bitbucket.org/kmalkki/flashrom.git
Thanks, Kyösti
Hi
It might take quite a bit of time for those patches to move forward and get merged. It helps if you can test the other pinouts too, and please send those acked-by replies to the list.
I don't know how portable ppdev is, that part is likely to get completely ignored.
KM
On Wed, 2013-03-13 at 18:08 +0400, mmcx@mail.ru wrote:
Hi.
- Byteblaster tested OK. Logs attached.
https://bitbucket.org/mmcx/flashrom/commits/ef9639ee291a4b07e139a2afbf218635...
- Added ppdev support. ppdev tested OK. Logs attached.
https://bitbucket.org/mmcx/flashrom/commits/f7a71bb359245c79826061aa054c547e... https://bitbucket.org/mmcx/flashrom/commits/fee6601e451c7b1576af862c94df4495...
-----Original Message----- Date: Thu, 07 Mar 2013 18:19:17 +0200 From: Kyösti Mälkki kyosti.malkki@gmail.com To: flashrom flashrom@flashrom.org Subject: Re: [PATCH 1/5] rayer_spi: Create list of programmer types
Hi
It would be great if you can test the updated patchset with new rayer_spi pinouts on actual hardware.
https://bitbucket.org/kmalkki/flashrom/get/rayer_spi.tar.bz2
or
git clone -b rayer_spi https://bitbucket.org/kmalkki/flashrom.git
Thanks, Kyösti
Hi.
Tested: byteblaster - OK wiggler - OK rayer - BAD, maybe cable too long
I broke rayer_spi.c on lpt_bitbang_spi.c and lpt_io.c. lpt_io.c - LPT support functions for different methods of input-output. lpt_bitbang_spi.c - Support rayer, xilinx, byteblaster, stk200, wiggler, willem etc. I also added the patch "[PATCH 0/3] rayer_spi: Add support for Willem EPROM programmer SPI" from Ondrej Zary Sat Mar 16 23:42:50 CET 2013 Please see https://bitbucket.org/mmcx/flashrom/commits/branch/lpt_bitbang_spi
-----Original Message----- Date: Wed, 13 Mar 2013 20:33:12 +0200 From: Kyösti Mälkki kyosti.malkki@gmail.com To: mmcx@mail.ru, flashrom flashrom@flashrom.org Subject: Re: [PATCH 1/5] rayer_spi: Create list of programmer types
Hi
It might take quite a bit of time for those patches to move forward and get merged. It helps if you can test the other pinouts too, and please send those acked-by replies to the list.
I don't know how portable ppdev is, that part is likely to get completely ignored.
KM
On Wed, 2013-03-13 at 18:08 +0400, mmcx@mail.ru wrote:
Hi.
- Byteblaster tested OK. Logs attached.
https://bitbucket.org/mmcx/flashrom/commits/ef9639ee291a4b07e139a2afbf218635...
- Added ppdev support. ppdev tested OK. Logs attached.
https://bitbucket.org/mmcx/flashrom/commits/f7a71bb359245c79826061aa054c547e... https://bitbucket.org/mmcx/flashrom/commits/fee6601e451c7b1576af862c94df4495...
-----Original Message----- Date: Thu, 07 Mar 2013 18:19:17 +0200 From: Kyösti Mälkki kyosti.malkki@gmail.com To: flashrom flashrom@flashrom.org Subject: Re: [PATCH 1/5] rayer_spi: Create list of programmer types
Hi
It would be great if you can test the updated patchset with new rayer_spi pinouts on actual hardware.
https://bitbucket.org/kmalkki/flashrom/get/rayer_spi.tar.bz2
or
git clone -b rayer_spi https://bitbucket.org/kmalkki/flashrom.git
Thanks, Kyösti
On Sun, 2013-03-31 at 19:40 +0400, Maksim Kuleshov wrote:
Hi.
Tested: byteblaster - OK wiggler - OK rayer - BAD, maybe cable too long
I broke rayer_spi.c on lpt_bitbang_spi.c and lpt_io.c. lpt_io.c - LPT support functions for different methods of input-output. lpt_bitbang_spi.c - Support rayer, xilinx, byteblaster, stk200, wiggler, willem etc. I also added the patch "[PATCH 0/3] rayer_spi: Add support for Willem EPROM programmer SPI" from Ondrej Zary Sat Mar 16 23:42:50 CET 2013 Please see https://bitbucket.org/mmcx/flashrom/commits/branch/lpt_bitbang_spi
Hi
Please come and discuss such (massive) rewrites on #flashrom or the mailing list. I like most approaches you had handling the parallel port, but we need to coordinate changes to avoid duplicate work with the Willem FWH/LPC programmer device.
Can you confirm "byteblaster" and "wiggler" to work with patches applied upto this: http://patchwork.coreboot.org/patch/3880/
Should we use "byteblastermv" and "Altera ByteBlasterMV" ?
My plan was to have that set of patches merged as the first step. Keeping these simple increases chances of getting a review and merge.
Handling parallel port with either direct IO or ppdev must be independent of using SPI, there are FWH/LPC/parallel flash programmers. And parallel port code needs to be portable to different OS too. I did not look thoroughly, maybe these requirements were taken care of already.
Thanks, Kyösti
Hi.
Sorry. I don't speak English.
Please come and discuss such (massive) rewrites on #flashrom or the mailing list. I like most approaches you had handling the parallel port, but we need to coordinate changes to avoid duplicate work with the Willem FWH/LPC programmer device.
First thing is to get rid of direct calls INB () and OUTB (). Because difficult to recognize that OUTB (0x12, 0xDC02) is lpt_write_control (0x12), and INB (0xDB01) is lpt_read_status (). Now appeared in the mailing list patches for Willem and they also use OUTB (), INB (). In Linux INB () and OUTB () call iopl () or ioperm (), and iopl () requires a UID == 0. In Windows INB () and OUTB () are available only after dancing with a tambourine. For Windows, I wrote code to use InpOut32.dll ( http://www.highrez.co.uk/Downloads/InpOut32/default.htm ), but have not tested, because I do not use Windows. See: https://bitbucket.org/mmcx/flashrom/commits/fc684370fba426db678691ab9f5b6486...
Can you confirm "byteblaster" and "wiggler" to work with patches applied upto this: http://patchwork.coreboot.org/patch/3880/
I confirm "byteblaster" and "wiggler" is OK with http://patchwork.coreboot.org/patch/3880/.
Should we use "byteblastermv" and "Altera ByteBlasterMV" ?
Altera has two adapters for LPT: ByteBlaster II and ByteBlasterMV. They differ in polarity signal OE. "ByteBlasterMV" a jumper between pins 7 and 10 of LPT. "ByteBlaster II" has a jumper between pins 6 and 10 LPT. I use a clone ByteBlasterMV. Possible it is necessary to add a method "probe()" to determine whether the adapter connected.
My plan was to have that set of patches merged as the first step. Keeping these simple increases chances of getting a review and merge. Handling parallel port with either direct IO or ppdev must be independent of using SPI, there are FWH/LPC/parallel flash programmers. And parallel port code needs to be portable to different OS too. I did not look thoroughly, maybe these requirements were taken care of already.
In previous patches for each adapter appear almost identical methods init () and shutdown (). The difference is only able to pin "to programming" and "after the programming" for different adapters. I think it is better to use bitmaps to describe the state of pins. I also think that it is more convenient to use the pin numbers LPT, what number of bits in the registers. One more thing: LPT-port has an internal inversion on pines 11, 14, 17 (so-called "bit 7 hack"). I think that this inversion has no place in the description of adapters.
Maksim
On Mon, 1 Apr 2013 21:12:03 +0400 Maksim Kuleshov mmcx@mail.ru wrote:
Altera has two adapters for LPT: ByteBlaster II and ByteBlasterMV. They differ in polarity signal OE. "ByteBlasterMV" a jumper between pins 7 and 10 of LPT. "ByteBlaster II" has a jumper between pins 6 and 10 LPT.
exactly, I verified both with the public schematics. they are not trivial to find, so for further reference:
http://www.altera.co.jp/literature/ds/dsbytemv.pdf http://www.altera.com/literature/ug/ug_bbii.pdf
NB: the MV user guide does not have the schematic.