[PATCH] Try to handle non-x86 sanely

[Carl-Daniel Hailfinger]

flashrom is very x86 centric. It does work on other architectures if you
get it to compile. Try to fix the worst compile errors on non-x86 for a
full build.

Should work in theory with a default build if you exclude nic3com.
Will pretty sure break compilation on Alpha.

Signed-off-by: Carl-Daniel Hailfinger

Index: flashrom-ioport_x86_only/hwaccess.c
===================================================================
--- flashrom-ioport_x86_only/hwaccess.c	(Revision 984)
+++ flashrom-ioport_x86_only/hwaccess.c	(Arbeitskopie)
@@ -26,6 +26,8 @@
 #include <errno.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 #if defined(__FreeBSD__) || defined(__DragonFly__)
 int io_fd;
 #endif
@@ -54,6 +56,22 @@
 #endif
 }

+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+void get_io_perms(void)
+{
+}
+
+void release_io_perms(void)
+{
+}
+
+#else
+
+#error Unknown architecture
+
+#endif
+
 #ifdef __DJGPP__

extern unsigned short  segFS;
Index: flashrom-ioport_x86_only/hwaccess.h
===================================================================
--- flashrom-ioport_x86_only/hwaccess.h	(Revision 984)
+++ flashrom-ioport_x86_only/hwaccess.h	(Arbeitskopie)
@@ -31,6 +31,8 @@
 #include <pci/pci.h>
 #endif

+#if defined(__i386__) || defined(__x86_64__)
+
 /* for iopl and outb under Solaris */
 #if defined (__sun) && (defined(__i386) || defined(__amd64))
 #include <strings.h>
@@ -162,4 +164,11 @@
 int freebsd_wrmsr(int addr, msr_t msr);
 #endif

+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+/* Port I/O is not available on PowerPC. */
+
+#else
+#error Unknown architecture
+#endif
+
 #endif /* !__HWACCESS_H__ */
Index: flashrom-ioport_x86_only/it87spi.c
===================================================================
--- flashrom-ioport_x86_only/it87spi.c	(Revision 984)
+++ flashrom-ioport_x86_only/it87spi.c	(Arbeitskopie)
@@ -29,6 +29,8 @@
 #include "chipdrivers.h"
 #include "spi.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 #define ITE_SUPERIO_PORT1	0x2e
 #define ITE_SUPERIO_PORT2	0x4e

@@ -347,3 +349,5 @@

return 0;
 }
+
+#endif
Index: flashrom-ioport_x86_only/physmap.c
===================================================================
--- flashrom-ioport_x86_only/physmap.c	(Revision 984)
+++ flashrom-ioport_x86_only/physmap.c	(Arbeitskopie)
@@ -238,6 +238,8 @@
    return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO);
 }

+#if defined(__i386__) || defined(__x86_64__)
+
 #ifdef __linux__
 /*
  * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr,
@@ -455,4 +457,6 @@
 #endif
 #endif
 #endif
-
+#else
+/* Does MSR exist on non-x86 architectures? */
+#endif
Index: flashrom-ioport_x86_only/nic3com.c
===================================================================
--- flashrom-ioport_x86_only/nic3com.c	(Revision 984)
+++ flashrom-ioport_x86_only/nic3com.c	(Arbeitskopie)
@@ -23,6 +23,8 @@
 #include <sys/types.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 #define BIOS_ROM_ADDR		0x04
 #define BIOS_ROM_DATA		0x08
 #define INT_STATUS		0x0e
@@ -112,3 +114,7 @@
    OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
    return INB(io_base_addr + BIOS_ROM_DATA);
 }
+
+#else
+#error Unknown architecture
+#endif
Index: flashrom-ioport_x86_only/wbsio_spi.c
===================================================================
--- flashrom-ioport_x86_only/wbsio_spi.c	(Revision 984)
+++ flashrom-ioport_x86_only/wbsio_spi.c	(Arbeitskopie)
@@ -23,6 +23,8 @@
 #include "chipdrivers.h"
 #include "spi.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 #define WBSIO_PORT1	0x2e
 #define WBSIO_PORT2	0x4e

@@ -199,3 +201,5 @@

return spi_chip_write_1(flash, buf);
 }
+
+#endif
Index: flashrom-ioport_x86_only/chipset_enable.c
===================================================================
--- flashrom-ioport_x86_only/chipset_enable.c	(Revision 984)
+++ flashrom-ioport_x86_only/chipset_enable.c	(Arbeitskopie)
@@ -34,6 +34,8 @@
 #include <fcntl.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 extern int ichspi_lock;

static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
@@ -1285,8 +1287,11 @@
    return 0;
 }

+#endif
+
 /* Please keep this list alphabetically sorted by vendor/device. */
 const struct penable chipset_enables[] = {
+#if defined(__i386__) || defined(__x86_64__)
    {0x10B9, 0x1533, OK, "ALi", "M1533",		enable_flash_ali_m1533},
    {0x1022, 0x7440, OK, "AMD", "AMD-768",		enable_flash_amd8111},
    {0x1022, 0x7468, OK, "AMD", "AMD8111",		enable_flash_amd8111},
@@ -1417,7 +1422,7 @@
    {0x1106, 0x0596, OK, "VIA", "VT82C596",		enable_flash_amd8111},
    {0x1106, 0x0586, OK, "VIA", "VT82C586A/B",	enable_flash_amd8111},
    {0x1106, 0x0686, NT, "VIA", "VT82C686A/B",	enable_flash_amd8111},
-
+#endif
    {},
 };

Index: flashrom-ioport_x86_only/board_enable.c
===================================================================
--- flashrom-ioport_x86_only/board_enable.c	(Revision 984)
+++ flashrom-ioport_x86_only/board_enable.c	(Arbeitskopie)
@@ -28,6 +28,7 @@
 #include <fcntl.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
 /*
  * Helper functions for many Winbond Super I/Os of the W836xx range.
  */
@@ -1299,6 +1300,8 @@
    return it8712f_gpio_set(32, 1);
 }

+#endif
+
 /**
  * Below is the list of boards which need a special "board enable" code in
  * flashrom before their ROM chip can be accessed/written to.
@@ -1342,6 +1345,7 @@
 struct board_pciid_enable board_pciid_enables[] = {

/* first pci-id set [4],          second pci-id set [4],          dmi identifier coreboot id [2],             vendor name    board name       max_rom_...  OK? flash enable */
+#if defined(__i386__) || defined(__x86_64__)
    {0x10DE, 0x0547, 0x147B, 0x1C2F,  0x10DE, 0x0548, 0x147B, 0x1C2F, NULL,          NULL,         NULL,          "Abit",        "AN-M2",                 0,   NT, nvidia_mcp_gpio2_raise},
    {0x8086, 0x2926, 0x147b, 0x1084,  0x11ab, 0x4364, 0x147b, 0x1084, NULL,          NULL,         NULL,          "Abit",        "IP35",                  0,   OK, intel_ich_gpio16_raise},
    {0x8086, 0x2930, 0x147b, 0x1083,  0x10ec, 0x8167, 0x147b, 0x1083, NULL,          NULL,         NULL,          "Abit",        "IP35 Pro",              0,   OK, intel_ich_gpio16_raise},
@@ -1407,7 +1411,7 @@
    {0x1106, 0x3123, 0x1106, 0x3123,  0x1106, 0x3059, 0x1106, 0x4161, NULL,          NULL,         NULL,          "Termtek",     "TK-3370 (Rev:2.5B)",    0,   OK, w836xx_memw_enable_4e},
    {0x1106, 0x3177, 0x1106, 0xAA01,  0x1106, 0x3123, 0x1106, 0xAA01, NULL,          NULL,         NULL,          "VIA",         "EPIA M/MII/...",        0,   OK, via_vt823x_gpio15_raise},
    {0x1106, 0x0259, 0x1106, 0x3227,  0x1106, 0x3065, 0x1106, 0x3149, NULL,          NULL,         NULL,          "VIA",         "EPIA-N/NL",             0,   OK, via_vt823x_gpio9_raise},
-
+#endif
    {     0,      0,      0,      0,       0,      0,      0,      0, NULL,          NULL,         NULL,          NULL,          NULL,                    0,   NT, NULL}, /* end marker */
 };

[Carl-Daniel Hailfinger]

Misha Manulis asked for satasii support on PPC and on IRC we gave him
some hints to hack up something that works for ppc only and satasii
only. His patch can be found here: http://coreboot.pastebin.com/fuLk1FCA

Here is a patch which does everything The Right Way (TM) and uses proper
abstraction for satasii and compiles all x86 specific stuff only on x86.

Huge thanks go to Segher Boessenkool who provided valuable info about
all the endianness trickery (especially preprocessor macros) and tested
8 iterations of the code on Linux/PPC.

On 26.03.2010 01:51, Carl-Daniel Hailfinger wrote:
> flashrom is very x86 centric. It does work on other architectures if you
> get it to compile. Try to fix the all errors on ppc for a
> full build.
>
> Should work in theory with a default build if you exclude nic3com.
> Will pretty sure break compilation on Alpha.

This one should compile on ppc, I even expect it to work for satasii on ppc.
AFAICS all programmer drivers except nic3com should work.
Compile with
make distclean
make NIC3COM=no

Known bugs:

x86 is broken by this patch because the Makefile excludes the x86
specific internal files. If you want to test this patch on x86 (to make
sure I didn't break everything), change
#PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o
to
PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o

boards_ok and boards_bad has no x86 guard yet and will end up in
flashrom -L output.

Signed-off-by: Carl-Daniel Hailfinger

Index: flashrom-ioport_x86_only/hwaccess.c
===================================================================
--- flashrom-ioport_x86_only/hwaccess.c	(Revision 984)
+++ flashrom-ioport_x86_only/hwaccess.c	(Arbeitskopie)
@@ -26,6 +26,8 @@
 #include <errno.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 #if defined(__FreeBSD__) || defined(__DragonFly__)
 int io_fd;
 #endif
@@ -54,6 +56,22 @@
 #endif
 }

+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+void get_io_perms(void)
+{
+}
+
+void release_io_perms(void)
+{
+}
+
+#else
+
+#error Unknown architecture
+
+#endif
+
 #ifdef __DJGPP__

extern unsigned short  segFS;
@@ -122,3 +140,33 @@
    return *(volatile uint32_t *) addr;
 }
 #endif
+
+void mmio_le_writeb(uint8_t val, void *addr)
+{
+	mmio_writeb(cpu_to_le8(val), addr);
+}
+
+void mmio_le_writew(uint16_t val, void *addr)
+{
+	mmio_writeb(cpu_to_le16(val), addr);
+}
+
+void mmio_le_writel(uint32_t val, void *addr)
+{
+	mmio_writeb(cpu_to_le32(val), addr);
+}
+
+uint8_t mmio_le_readb(void *addr)
+{
+	return le_to_cpu8(mmio_readb(addr));
+}
+
+uint16_t mmio_le_readw(void *addr)
+{
+	return le_to_cpu16(mmio_readw(addr));
+}
+
+uint32_t mmio_le_readl(void *addr)
+{
+	return le_to_cpu32(mmio_readl(addr));
+}
Index: flashrom-ioport_x86_only/flash.h
===================================================================
--- flashrom-ioport_x86_only/flash.h	(Revision 984)
+++ flashrom-ioport_x86_only/flash.h	(Arbeitskopie)
@@ -59,8 +59,10 @@
    PROGRAMMER_ATAHPT,
 #endif
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    PROGRAMMER_IT87SPI,
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    PROGRAMMER_FT2232SPI,
 #endif
@@ -402,6 +404,12 @@
 uint8_t mmio_readb(void *addr);
 uint16_t mmio_readw(void *addr);
 uint32_t mmio_readl(void *addr);
+void mmio_le_writeb(uint8_t val, void *addr);
+void mmio_le_writew(uint16_t val, void *addr);
+void mmio_le_writel(uint32_t val, void *addr);
+uint8_t mmio_le_readb(void *addr);
+uint16_t mmio_le_readw(void *addr);
+uint32_t mmio_le_readl(void *addr);

/* programmer.c */
 int noop_shutdown(void);
@@ -585,6 +593,7 @@
 enum spi_controller {
    SPI_CONTROLLER_NONE,
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    SPI_CONTROLLER_ICH7,
    SPI_CONTROLLER_ICH9,
    SPI_CONTROLLER_IT87XX,
@@ -592,6 +601,7 @@
    SPI_CONTROLLER_VIA,
    SPI_CONTROLLER_WBSIO,
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    SPI_CONTROLLER_FT2232,
 #endif
Index: flashrom-ioport_x86_only/spi25.c
===================================================================
--- flashrom-ioport_x86_only/spi25.c	(Revision 984)
+++ flashrom-ioport_x86_only/spi25.c	(Arbeitskopie)
@@ -172,12 +172,14 @@
    /* only some SPI chipsets support 4 bytes commands */
    switch (spi_controller) {
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    case SPI_CONTROLLER_ICH7:
    case SPI_CONTROLLER_ICH9:
    case SPI_CONTROLLER_VIA:
    case SPI_CONTROLLER_SB600:
    case SPI_CONTROLLER_WBSIO:
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    case SPI_CONTROLLER_FT2232:
 #endif
@@ -950,11 +952,13 @@

switch (spi_controller) {
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    case SPI_CONTROLLER_WBSIO:
    	msg_cerr("%s: impossible with Winbond SPI masters,"
    			" degrading to byte program\n", __func__);
    	return spi_chip_write_1(flash, buf);
 #endif
+#endif
    default:
    	break;
    }
Index: flashrom-ioport_x86_only/hwaccess.h
===================================================================
--- flashrom-ioport_x86_only/hwaccess.h	(Revision 984)
+++ flashrom-ioport_x86_only/hwaccess.h	(Arbeitskopie)
@@ -24,13 +24,88 @@
 #ifndef __HWACCESS_H__
 #define __HWACCESS_H__ 1

+#if defined (__i386__) || defined (__x86_64__)
 #if defined(__GLIBC__)
 #include <sys/io.h>
 #endif
+#endif
+
 #if NEED_PCI == 1
 #include <pci/pci.h>
 #endif

+#define ___constant_swab8(x) ((uint8_t)(				\
+	(((uint8_t)(x) & (uint8_t)0xffU))))
+
+#define ___constant_swab16(x) ((uint16_t)(				\
+	(((uint16_t)(x) & (uint16_t)0x00ffU) << 8) |			\
+	(((uint16_t)(x) & (uint16_t)0xff00U) >> 8)))
+
+#define ___constant_swab32(x) ((uint32_t)(				\
+	(((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) |		\
+	(((uint32_t)(x) & (uint32_t)0x0000ff00UL) <<  8) |		\
+	(((uint32_t)(x) & (uint32_t)0x00ff0000UL) >>  8) |		\
+	(((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24)))
+
+#define ___constant_swab64(x) ((uint64_t)(				\
+	(((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) |	\
+	(((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) |	\
+	(((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) |	\
+	(((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) <<  8) |	\
+	(((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >>  8) |	\
+	(((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) |	\
+	(((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) |	\
+	(((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56)))
+
+#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__)
+
+#define cpu_to_le(bits)							\
+static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val)	\
+{									\
+	return ___constant_swab##bits(val);				\
+}
+
+cpu_to_le(8)
+cpu_to_le(16)
+cpu_to_le(32)
+cpu_to_le(64)
+
+#define cpu_to_be8
+#define cpu_to_be16
+#define cpu_to_be32
+#define cpu_to_be64
+
+#else
+
+#define cpu_to_be(bits)							\
+static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val)	\
+{									\
+	return ___constant_swab##bits(val);				\
+}
+
+cpu_to_be(8)
+cpu_to_be(16)
+cpu_to_be(32)
+cpu_to_be(64)
+
+#define cpu_to_le8
+#define cpu_to_le16
+#define cpu_to_le32
+#define cpu_to_le64
+
+#endif
+
+#define be_to_cpu8 cpu_to_be8
+#define be_to_cpu16 cpu_to_be16
+#define be_to_cpu32 cpu_to_be32
+#define be_to_cpu64 cpu_to_be64
+#define le_to_cpu8 cpu_to_le8
+#define le_to_cpu16 cpu_to_le16
+#define le_to_cpu32 cpu_to_le32
+#define le_to_cpu64 cpu_to_le64
+
+#if defined (__i386__) || defined (__x86_64__)
+
 /* for iopl and outb under Solaris */
 #if defined (__sun) && (defined(__i386) || defined(__amd64))
 #include <strings.h>
@@ -162,4 +237,11 @@
 int freebsd_wrmsr(int addr, msr_t msr);
 #endif

+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+/* Port I/O is not available on PowerPC. */
+
+#else
+#error Unknown architecture
+#endif
+
 #endif /* !__HWACCESS_H__ */
Index: flashrom-ioport_x86_only/physmap.c
===================================================================
--- flashrom-ioport_x86_only/physmap.c	(Revision 984)
+++ flashrom-ioport_x86_only/physmap.c	(Arbeitskopie)
@@ -238,6 +238,8 @@
    return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO);
 }

+#if defined(__i386__) || defined(__x86_64__)
+
 #ifdef __linux__
 /*
  * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr,
@@ -455,4 +457,6 @@
 #endif
 #endif
 #endif
-
+#else
+/* Does MSR exist on non-x86 architectures? */
+#endif
Index: flashrom-ioport_x86_only/spi.c
===================================================================
--- flashrom-ioport_x86_only/spi.c	(Revision 984)
+++ flashrom-ioport_x86_only/spi.c	(Arbeitskopie)
@@ -42,6 +42,7 @@
    },

#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    { /* SPI_CONTROLLER_ICH7 */
    	.command = ich_spi_send_command,
    	.multicommand = ich_spi_send_multicommand,
@@ -84,6 +85,7 @@
    	.write_256 = wbsio_spi_write_1,
    },
 #endif
+#endif

#if FT2232_SPI_SUPPORT == 1
    { /* SPI_CONTROLLER_FT2232 */
Index: flashrom-ioport_x86_only/nic3com.c
===================================================================
--- flashrom-ioport_x86_only/nic3com.c	(Revision 984)
+++ flashrom-ioport_x86_only/nic3com.c	(Arbeitskopie)
@@ -23,6 +23,8 @@
 #include <sys/types.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 #define BIOS_ROM_ADDR		0x04
 #define BIOS_ROM_DATA		0x08
 #define INT_STATUS		0x0e
@@ -112,3 +114,7 @@
    OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
    return INB(io_base_addr + BIOS_ROM_DATA);
 }
+
+#else
+#error Unknown architecture
+#endif
Index: flashrom-ioport_x86_only/Makefile
===================================================================
--- flashrom-ioport_x86_only/Makefile	(Revision 984)
+++ flashrom-ioport_x86_only/Makefile	(Arbeitskopie)
@@ -121,7 +121,8 @@

ifeq ($(CONFIG_INTERNAL), yes)
 FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1'
-PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o
+PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o
+#PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o
 NEED_PCI := yes
 endif

@@ -253,7 +254,7 @@
    rm -f .dependencies .features .libdeps

dep:
-	@$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies
+	@$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies

strip: $(PROGRAM)
    $(STRIP) $(STRIP_ARGS) $(PROGRAM)
Index: flashrom-ioport_x86_only/satasii.c
===================================================================
--- flashrom-ioport_x86_only/satasii.c	(Revision 984)
+++ flashrom-ioport_x86_only/satasii.c	(Arbeitskopie)
@@ -62,7 +62,7 @@
    sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset;

/* Check if ROM cycle are OK. */
-	if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26))))
+	if ((id != 0x0680) && (!(mmio_le_readl(sii_bar) & (1 << 26))))
    	msg_pinfo("Warning: Flash seems unconnected.\n");

buses_supported = CHIP_BUSTYPE_PARALLEL;
@@ -82,32 +82,32 @@
 {
    uint32_t ctrl_reg, data_reg;

-	while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;
+	while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ;

/* Mask out unused/reserved bits, set writes and start transaction. */
    ctrl_reg &= 0xfcf80000;
    ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff);

-	data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val;
-	mmio_writel(data_reg, (sii_bar + 4));
-	mmio_writel(ctrl_reg, sii_bar);
+	data_reg = (mmio_le_readl((sii_bar + 4)) & ~0xff) | val;
+	mmio_le_writel(data_reg, (sii_bar + 4));
+	mmio_le_writel(ctrl_reg, sii_bar);

-	while (mmio_readl(sii_bar) & (1 << 25)) ;
+	while (mmio_le_readl(sii_bar) & (1 << 25)) ;
 }

uint8_t satasii_chip_readb(const chipaddr addr)
 {
    uint32_t ctrl_reg;

-	while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;
+	while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ;

/* Mask out unused/reserved bits, set reads and start transaction. */
    ctrl_reg &= 0xfcf80000;
    ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff);

-	mmio_writel(ctrl_reg, sii_bar);
+	mmio_le_writel(ctrl_reg, sii_bar);

-	while (mmio_readl(sii_bar) & (1 << 25)) ;
+	while (mmio_le_readl(sii_bar) & (1 << 25)) ;

-	return (mmio_readl(sii_bar + 4)) & 0xff;
+	return (mmio_le_readl(sii_bar + 4)) & 0xff;
 }
Index: flashrom-ioport_x86_only/chipset_enable.c
===================================================================
--- flashrom-ioport_x86_only/chipset_enable.c	(Revision 984)
+++ flashrom-ioport_x86_only/chipset_enable.c	(Arbeitskopie)
@@ -34,6 +34,8 @@
 #include <fcntl.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 extern int ichspi_lock;

static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
@@ -1285,8 +1287,11 @@
    return 0;
 }

+#endif
+
 /* Please keep this list alphabetically sorted by vendor/device. */
 const struct penable chipset_enables[] = {
+#if defined(__i386__) || defined(__x86_64__)
    {0x10B9, 0x1533, OK, "ALi", "M1533",		enable_flash_ali_m1533},
    {0x1022, 0x7440, OK, "AMD", "AMD-768",		enable_flash_amd8111},
    {0x1022, 0x7468, OK, "AMD", "AMD8111",		enable_flash_amd8111},
@@ -1417,7 +1422,7 @@
    {0x1106, 0x0596, OK, "VIA", "VT82C596",		enable_flash_amd8111},
    {0x1106, 0x0586, OK, "VIA", "VT82C586A/B",	enable_flash_amd8111},
    {0x1106, 0x0686, NT, "VIA", "VT82C686A/B",	enable_flash_amd8111},
-
+#endif
    {},
 };

Index: flashrom-ioport_x86_only/flashrom.c
===================================================================
--- flashrom-ioport_x86_only/flashrom.c	(Revision 984)
+++ flashrom-ioport_x86_only/flashrom.c	(Arbeitskopie)
@@ -233,6 +233,7 @@
 #endif

#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    {
    	.name			= "it87spi",
    	.init			= it87spi_init,
@@ -250,6 +251,7 @@
    	.delay			= internal_delay,
    },
 #endif
+#endif

#if FT2232_SPI_SUPPORT == 1
    {
Index: flashrom-ioport_x86_only/internal.c
===================================================================
--- flashrom-ioport_x86_only/internal.c	(Revision 984)
+++ flashrom-ioport_x86_only/internal.c	(Arbeitskopie)
@@ -99,9 +99,11 @@
 #endif

#if INTERNAL_SUPPORT == 1
-struct superio superio = {};
 int force_boardenable = 0;

+#if defined(__i386__) || defined(__x86_64__)
+struct superio superio = {};
+
 void probe_superio(void)
 {
    superio = probe_superio_ite();
@@ -111,8 +113,9 @@
    	superio = probe_superio_winbond();
 #endif
 }
+#endif

-int is_laptop;
+int is_laptop = 0;

int internal_init(void)
 {
@@ -149,10 +152,13 @@
     * mainboard specific flash enable sequence.
     */
    coreboot_init();
+
+#if defined(__i386__) || defined(__x86_64__)
    dmi_init();

/* Probe for the Super I/O chip and fill global struct superio. */
    probe_superio();
+#endif

/* Warn if a laptop is detected. */
    if (is_laptop)
@@ -173,8 +179,10 @@
    	       "will most likely fail.\n");
    }

+#if defined(__i386__) || defined(__x86_64__)
    /* Probe for IT87* LPC->SPI translation unconditionally. */
    it87xx_probe_spi_flash(NULL);
+#endif

board_flash_enable(lb_vendor, lb_part);

Index: flashrom-ioport_x86_only/board_enable.c
===================================================================
--- flashrom-ioport_x86_only/board_enable.c	(Revision 984)
+++ flashrom-ioport_x86_only/board_enable.c	(Arbeitskopie)
@@ -28,6 +28,7 @@
 #include <fcntl.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
 /*
  * Helper functions for many Winbond Super I/Os of the W836xx range.
  */
@@ -1299,6 +1300,8 @@
    return it8712f_gpio_set(32, 1);
 }

+#endif
+
 /**
  * Below is the list of boards which need a special "board enable" code in
  * flashrom before their ROM chip can be accessed/written to.
@@ -1342,6 +1345,7 @@
 struct board_pciid_enable board_pciid_enables[] = {

/* first pci-id set [4],          second pci-id set [4],          dmi identifier coreboot id [2],             vendor name    board name       max_rom_...  OK? flash enable */
+#if defined(__i386__) || defined(__x86_64__)
    {0x10DE, 0x0547, 0x147B, 0x1C2F,  0x10DE, 0x0548, 0x147B, 0x1C2F, NULL,          NULL,         NULL,          "Abit",        "AN-M2",                 0,   NT, nvidia_mcp_gpio2_raise},
    {0x8086, 0x2926, 0x147b, 0x1084,  0x11ab, 0x4364, 0x147b, 0x1084, NULL,          NULL,         NULL,          "Abit",        "IP35",                  0,   OK, intel_ich_gpio16_raise},
    {0x8086, 0x2930, 0x147b, 0x1083,  0x10ec, 0x8167, 0x147b, 0x1083, NULL,          NULL,         NULL,          "Abit",        "IP35 Pro",              0,   OK, intel_ich_gpio16_raise},
@@ -1407,7 +1411,7 @@
    {0x1106, 0x3123, 0x1106, 0x3123,  0x1106, 0x3059, 0x1106, 0x4161, NULL,          NULL,         NULL,          "Termtek",     "TK-3370 (Rev:2.5B)",    0,   OK, w836xx_memw_enable_4e},
    {0x1106, 0x3177, 0x1106, 0xAA01,  0x1106, 0x3123, 0x1106, 0xAA01, NULL,          NULL,         NULL,          "VIA",         "EPIA M/MII/...",        0,   OK, via_vt823x_gpio15_raise},
    {0x1106, 0x0259, 0x1106, 0x3227,  0x1106, 0x3065, 0x1106, 0x3149, NULL,          NULL,         NULL,          "VIA",         "EPIA-N/NL",             0,   OK, via_vt823x_gpio9_raise},
-
+#endif
    {     0,      0,      0,      0,       0,      0,      0,      0, NULL,          NULL,         NULL,          NULL,          NULL,                    0,   NT, NULL}, /* end marker */
 };

[Carl-Daniel Hailfinger]

On 26.03.2010 05:13, Carl-Daniel Hailfinger wrote:
> Misha Manulis asked for satasii support on PPC and on IRC we gave him
> some hints to hack up something that works for ppc only and satasii
> only. His patch can be found here: http://coreboot.pastebin.com/fuLk1FCA
>
> Here is a patch which does everything The Right Way (TM) and uses proper
> abstraction for satasii and compiles all x86 specific stuff only on x86.
>
> Huge thanks go to Segher Boessenkool who provided valuable info about
> all the endianness trickery (especially preprocessor macros) and tested
> 8 iterations of the code on Linux/PPC.
>
> On 26.03.2010 01:51, Carl-Daniel Hailfinger wrote:
> > flashrom is very x86 centric. It does work on other architectures if you
> > get it to compile. Try to fix the all errors on ppc for a
> > full build.
> >
> > Should work in theory with a default build if you exclude nic3com.
> > Will pretty sure break compilation on Alpha.
>
> This one should compile on ppc, I even expect it to work for satasii on ppc.
> AFAICS all programmer drivers except nic3com should work.
> Compile with
> make distclean
> make NIC3COM=no
>
> Known bugs:
>
> x86 is broken by this patch because the Makefile excludes the x86
> specific internal files. If you want to test this patch on x86 (to make
> sure I didn't break everything), change
> #PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o
> to
> PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o
>
> boards_ok and boards_bad has no x86 guard yet and will end up in
> flashrom -L output.

Misha Manulis tested the patch and it didn't work. I found a typo which
truncated all 16 bit and 32 bit LE write accesses to 8 bit.

New version, should work fine with the x86/nic3com exceptions mentioned
above.

Signed-off-by: Carl-Daniel Hailfinger

Index: flashrom-ioport_x86_only/hwaccess.c
===================================================================
--- flashrom-ioport_x86_only/hwaccess.c	(Revision 984)
+++ flashrom-ioport_x86_only/hwaccess.c	(Arbeitskopie)
@@ -26,6 +26,8 @@
 #include <errno.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 #if defined(__FreeBSD__) || defined(__DragonFly__)
 int io_fd;
 #endif
@@ -54,6 +56,22 @@
 #endif
 }

+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+void get_io_perms(void)
+{
+}
+
+void release_io_perms(void)
+{
+}
+
+#else
+
+#error Unknown architecture
+
+#endif
+
 #ifdef __DJGPP__

extern unsigned short  segFS;
@@ -122,3 +140,33 @@
    return *(volatile uint32_t *) addr;
 }
 #endif
+
+void mmio_le_writeb(uint8_t val, void *addr)
+{
+	mmio_writeb(cpu_to_le8(val), addr);
+}
+
+void mmio_le_writew(uint16_t val, void *addr)
+{
+	mmio_writew(cpu_to_le16(val), addr);
+}
+
+void mmio_le_writel(uint32_t val, void *addr)
+{
+	mmio_writel(cpu_to_le32(val), addr);
+}
+
+uint8_t mmio_le_readb(void *addr)
+{
+	return le_to_cpu8(mmio_readb(addr));
+}
+
+uint16_t mmio_le_readw(void *addr)
+{
+	return le_to_cpu16(mmio_readw(addr));
+}
+
+uint32_t mmio_le_readl(void *addr)
+{
+	return le_to_cpu32(mmio_readl(addr));
+}
Index: flashrom-ioport_x86_only/flash.h
===================================================================
--- flashrom-ioport_x86_only/flash.h	(Revision 984)
+++ flashrom-ioport_x86_only/flash.h	(Arbeitskopie)
@@ -59,8 +59,10 @@
    PROGRAMMER_ATAHPT,
 #endif
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    PROGRAMMER_IT87SPI,
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    PROGRAMMER_FT2232SPI,
 #endif
@@ -402,6 +404,12 @@
 uint8_t mmio_readb(void *addr);
 uint16_t mmio_readw(void *addr);
 uint32_t mmio_readl(void *addr);
+void mmio_le_writeb(uint8_t val, void *addr);
+void mmio_le_writew(uint16_t val, void *addr);
+void mmio_le_writel(uint32_t val, void *addr);
+uint8_t mmio_le_readb(void *addr);
+uint16_t mmio_le_readw(void *addr);
+uint32_t mmio_le_readl(void *addr);

/* programmer.c */
 int noop_shutdown(void);
@@ -585,6 +593,7 @@
 enum spi_controller {
    SPI_CONTROLLER_NONE,
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    SPI_CONTROLLER_ICH7,
    SPI_CONTROLLER_ICH9,
    SPI_CONTROLLER_IT87XX,
@@ -592,6 +601,7 @@
    SPI_CONTROLLER_VIA,
    SPI_CONTROLLER_WBSIO,
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    SPI_CONTROLLER_FT2232,
 #endif
Index: flashrom-ioport_x86_only/spi25.c
===================================================================
--- flashrom-ioport_x86_only/spi25.c	(Revision 984)
+++ flashrom-ioport_x86_only/spi25.c	(Arbeitskopie)
@@ -172,12 +172,14 @@
    /* only some SPI chipsets support 4 bytes commands */
    switch (spi_controller) {
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    case SPI_CONTROLLER_ICH7:
    case SPI_CONTROLLER_ICH9:
    case SPI_CONTROLLER_VIA:
    case SPI_CONTROLLER_SB600:
    case SPI_CONTROLLER_WBSIO:
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    case SPI_CONTROLLER_FT2232:
 #endif
@@ -950,11 +952,13 @@

switch (spi_controller) {
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    case SPI_CONTROLLER_WBSIO:
    	msg_cerr("%s: impossible with Winbond SPI masters,"
    			" degrading to byte program\n", __func__);
    	return spi_chip_write_1(flash, buf);
 #endif
+#endif
    default:
    	break;
    }
Index: flashrom-ioport_x86_only/hwaccess.h
===================================================================
--- flashrom-ioport_x86_only/hwaccess.h	(Revision 984)
+++ flashrom-ioport_x86_only/hwaccess.h	(Arbeitskopie)
@@ -24,13 +24,88 @@
 #ifndef __HWACCESS_H__
 #define __HWACCESS_H__ 1

+#if defined (__i386__) || defined (__x86_64__)
 #if defined(__GLIBC__)
 #include <sys/io.h>
 #endif
+#endif
+
 #if NEED_PCI == 1
 #include <pci/pci.h>
 #endif

+#define ___constant_swab8(x) ((uint8_t)(				\
+	(((uint8_t)(x) & (uint8_t)0xffU))))
+
+#define ___constant_swab16(x) ((uint16_t)(				\
+	(((uint16_t)(x) & (uint16_t)0x00ffU) << 8) |			\
+	(((uint16_t)(x) & (uint16_t)0xff00U) >> 8)))
+
+#define ___constant_swab32(x) ((uint32_t)(				\
+	(((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) |		\
+	(((uint32_t)(x) & (uint32_t)0x0000ff00UL) <<  8) |		\
+	(((uint32_t)(x) & (uint32_t)0x00ff0000UL) >>  8) |		\
+	(((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24)))
+
+#define ___constant_swab64(x) ((uint64_t)(				\
+	(((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) |	\
+	(((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) |	\
+	(((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) |	\
+	(((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) <<  8) |	\
+	(((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >>  8) |	\
+	(((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) |	\
+	(((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) |	\
+	(((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56)))
+
+#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__)
+
+#define cpu_to_le(bits)							\
+static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val)	\
+{									\
+	return ___constant_swab##bits(val);				\
+}
+
+cpu_to_le(8)
+cpu_to_le(16)
+cpu_to_le(32)
+cpu_to_le(64)
+
+#define cpu_to_be8
+#define cpu_to_be16
+#define cpu_to_be32
+#define cpu_to_be64
+
+#else
+
+#define cpu_to_be(bits)							\
+static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val)	\
+{									\
+	return ___constant_swab##bits(val);				\
+}
+
+cpu_to_be(8)
+cpu_to_be(16)
+cpu_to_be(32)
+cpu_to_be(64)
+
+#define cpu_to_le8
+#define cpu_to_le16
+#define cpu_to_le32
+#define cpu_to_le64
+
+#endif
+
+#define be_to_cpu8 cpu_to_be8
+#define be_to_cpu16 cpu_to_be16
+#define be_to_cpu32 cpu_to_be32
+#define be_to_cpu64 cpu_to_be64
+#define le_to_cpu8 cpu_to_le8
+#define le_to_cpu16 cpu_to_le16
+#define le_to_cpu32 cpu_to_le32
+#define le_to_cpu64 cpu_to_le64
+
+#if defined (__i386__) || defined (__x86_64__)
+
 /* for iopl and outb under Solaris */
 #if defined (__sun) && (defined(__i386) || defined(__amd64))
 #include <strings.h>
@@ -162,4 +237,11 @@
 int freebsd_wrmsr(int addr, msr_t msr);
 #endif

+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+/* Port I/O is not available on PowerPC. */
+
+#else
+#error Unknown architecture
+#endif
+
 #endif /* !__HWACCESS_H__ */
Index: flashrom-ioport_x86_only/physmap.c
===================================================================
--- flashrom-ioport_x86_only/physmap.c	(Revision 984)
+++ flashrom-ioport_x86_only/physmap.c	(Arbeitskopie)
@@ -238,6 +238,8 @@
    return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO);
 }

+#if defined(__i386__) || defined(__x86_64__)
+
 #ifdef __linux__
 /*
  * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr,
@@ -455,4 +457,6 @@
 #endif
 #endif
 #endif
-
+#else
+/* Does MSR exist on non-x86 architectures? */
+#endif
Index: flashrom-ioport_x86_only/spi.c
===================================================================
--- flashrom-ioport_x86_only/spi.c	(Revision 984)
+++ flashrom-ioport_x86_only/spi.c	(Arbeitskopie)
@@ -42,6 +42,7 @@
    },

#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    { /* SPI_CONTROLLER_ICH7 */
    	.command = ich_spi_send_command,
    	.multicommand = ich_spi_send_multicommand,
@@ -84,6 +85,7 @@
    	.write_256 = wbsio_spi_write_1,
    },
 #endif
+#endif

#if FT2232_SPI_SUPPORT == 1
    { /* SPI_CONTROLLER_FT2232 */
Index: flashrom-ioport_x86_only/nic3com.c
===================================================================
--- flashrom-ioport_x86_only/nic3com.c	(Revision 984)
+++ flashrom-ioport_x86_only/nic3com.c	(Arbeitskopie)
@@ -23,6 +23,8 @@
 #include <sys/types.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 #define BIOS_ROM_ADDR		0x04
 #define BIOS_ROM_DATA		0x08
 #define INT_STATUS		0x0e
@@ -112,3 +114,7 @@
    OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
    return INB(io_base_addr + BIOS_ROM_DATA);
 }
+
+#else
+#error Unknown architecture
+#endif
Index: flashrom-ioport_x86_only/Makefile
===================================================================
--- flashrom-ioport_x86_only/Makefile	(Revision 984)
+++ flashrom-ioport_x86_only/Makefile	(Arbeitskopie)
@@ -121,7 +121,8 @@

ifeq ($(CONFIG_INTERNAL), yes)
 FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1'
-PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o
+PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o
+#PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o
 NEED_PCI := yes
 endif

@@ -253,7 +254,7 @@
    rm -f .dependencies .features .libdeps

dep:
-	@$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies
+	@$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies

strip: $(PROGRAM)
    $(STRIP) $(STRIP_ARGS) $(PROGRAM)
Index: flashrom-ioport_x86_only/satasii.c
===================================================================
--- flashrom-ioport_x86_only/satasii.c	(Revision 984)
+++ flashrom-ioport_x86_only/satasii.c	(Arbeitskopie)
@@ -62,7 +62,7 @@
    sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset;

/* Check if ROM cycle are OK. */
-	if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26))))
+	if ((id != 0x0680) && (!(mmio_le_readl(sii_bar) & (1 << 26))))
    	msg_pinfo("Warning: Flash seems unconnected.\n");

buses_supported = CHIP_BUSTYPE_PARALLEL;
@@ -82,32 +82,32 @@
 {
    uint32_t ctrl_reg, data_reg;

-	while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;
+	while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ;

/* Mask out unused/reserved bits, set writes and start transaction. */
    ctrl_reg &= 0xfcf80000;
    ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff);

-	data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val;
-	mmio_writel(data_reg, (sii_bar + 4));
-	mmio_writel(ctrl_reg, sii_bar);
+	data_reg = (mmio_le_readl((sii_bar + 4)) & ~0xff) | val;
+	mmio_le_writel(data_reg, (sii_bar + 4));
+	mmio_le_writel(ctrl_reg, sii_bar);

-	while (mmio_readl(sii_bar) & (1 << 25)) ;
+	while (mmio_le_readl(sii_bar) & (1 << 25)) ;
 }

uint8_t satasii_chip_readb(const chipaddr addr)
 {
    uint32_t ctrl_reg;

-	while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;
+	while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ;

/* Mask out unused/reserved bits, set reads and start transaction. */
    ctrl_reg &= 0xfcf80000;
    ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff);

-	mmio_writel(ctrl_reg, sii_bar);
+	mmio_le_writel(ctrl_reg, sii_bar);

-	while (mmio_readl(sii_bar) & (1 << 25)) ;
+	while (mmio_le_readl(sii_bar) & (1 << 25)) ;

-	return (mmio_readl(sii_bar + 4)) & 0xff;
+	return (mmio_le_readl(sii_bar + 4)) & 0xff;
 }
Index: flashrom-ioport_x86_only/chipset_enable.c
===================================================================
--- flashrom-ioport_x86_only/chipset_enable.c	(Revision 984)
+++ flashrom-ioport_x86_only/chipset_enable.c	(Arbeitskopie)
@@ -34,6 +34,8 @@
 #include <fcntl.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 extern int ichspi_lock;

static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
@@ -1285,8 +1287,11 @@
    return 0;
 }

+#endif
+
 /* Please keep this list alphabetically sorted by vendor/device. */
 const struct penable chipset_enables[] = {
+#if defined(__i386__) || defined(__x86_64__)
    {0x10B9, 0x1533, OK, "ALi", "M1533",		enable_flash_ali_m1533},
    {0x1022, 0x7440, OK, "AMD", "AMD-768",		enable_flash_amd8111},
    {0x1022, 0x7468, OK, "AMD", "AMD8111",		enable_flash_amd8111},
@@ -1417,7 +1422,7 @@
    {0x1106, 0x0596, OK, "VIA", "VT82C596",		enable_flash_amd8111},
    {0x1106, 0x0586, OK, "VIA", "VT82C586A/B",	enable_flash_amd8111},
    {0x1106, 0x0686, NT, "VIA", "VT82C686A/B",	enable_flash_amd8111},
-
+#endif
    {},
 };

Index: flashrom-ioport_x86_only/flashrom.c
===================================================================
--- flashrom-ioport_x86_only/flashrom.c	(Revision 984)
+++ flashrom-ioport_x86_only/flashrom.c	(Arbeitskopie)
@@ -233,6 +233,7 @@
 #endif

#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    {
    	.name			= "it87spi",
    	.init			= it87spi_init,
@@ -250,6 +251,7 @@
    	.delay			= internal_delay,
    },
 #endif
+#endif

#if FT2232_SPI_SUPPORT == 1
    {
Index: flashrom-ioport_x86_only/internal.c
===================================================================
--- flashrom-ioport_x86_only/internal.c	(Revision 984)
+++ flashrom-ioport_x86_only/internal.c	(Arbeitskopie)
@@ -99,9 +99,11 @@
 #endif

#if INTERNAL_SUPPORT == 1
-struct superio superio = {};
 int force_boardenable = 0;

+#if defined(__i386__) || defined(__x86_64__)
+struct superio superio = {};
+
 void probe_superio(void)
 {
    superio = probe_superio_ite();
@@ -111,8 +113,9 @@
    	superio = probe_superio_winbond();
 #endif
 }
+#endif

-int is_laptop;
+int is_laptop = 0;

int internal_init(void)
 {
@@ -149,10 +152,13 @@
     * mainboard specific flash enable sequence.
     */
    coreboot_init();
+
+#if defined(__i386__) || defined(__x86_64__)
    dmi_init();

/* Probe for the Super I/O chip and fill global struct superio. */
    probe_superio();
+#endif

/* Warn if a laptop is detected. */
    if (is_laptop)
@@ -173,8 +179,10 @@
    	       "will most likely fail.\n");
    }

+#if defined(__i386__) || defined(__x86_64__)
    /* Probe for IT87* LPC->SPI translation unconditionally. */
    it87xx_probe_spi_flash(NULL);
+#endif

board_flash_enable(lb_vendor, lb_part);

Index: flashrom-ioport_x86_only/board_enable.c
===================================================================
--- flashrom-ioport_x86_only/board_enable.c	(Revision 984)
+++ flashrom-ioport_x86_only/board_enable.c	(Arbeitskopie)
@@ -28,6 +28,7 @@
 #include <fcntl.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
 /*
  * Helper functions for many Winbond Super I/Os of the W836xx range.
  */
@@ -1299,6 +1300,8 @@
    return it8712f_gpio_set(32, 1);
 }

+#endif
+
 /**
  * Below is the list of boards which need a special "board enable" code in
  * flashrom before their ROM chip can be accessed/written to.
@@ -1342,6 +1345,7 @@
 struct board_pciid_enable board_pciid_enables[] = {

/* first pci-id set [4],          second pci-id set [4],          dmi identifier coreboot id [2],             vendor name    board name       max_rom_...  OK? flash enable */
+#if defined(__i386__) || defined(__x86_64__)
    {0x10DE, 0x0547, 0x147B, 0x1C2F,  0x10DE, 0x0548, 0x147B, 0x1C2F, NULL,          NULL,         NULL,          "Abit",        "AN-M2",                 0,   NT, nvidia_mcp_gpio2_raise},
    {0x8086, 0x2926, 0x147b, 0x1084,  0x11ab, 0x4364, 0x147b, 0x1084, NULL,          NULL,         NULL,          "Abit",        "IP35",                  0,   OK, intel_ich_gpio16_raise},
    {0x8086, 0x2930, 0x147b, 0x1083,  0x10ec, 0x8167, 0x147b, 0x1083, NULL,          NULL,         NULL,          "Abit",        "IP35 Pro",              0,   OK, intel_ich_gpio16_raise},
@@ -1407,7 +1411,7 @@
    {0x1106, 0x3123, 0x1106, 0x3123,  0x1106, 0x3059, 0x1106, 0x4161, NULL,          NULL,         NULL,          "Termtek",     "TK-3370 (Rev:2.5B)",    0,   OK, w836xx_memw_enable_4e},
    {0x1106, 0x3177, 0x1106, 0xAA01,  0x1106, 0x3123, 0x1106, 0xAA01, NULL,          NULL,         NULL,          "VIA",         "EPIA M/MII/...",        0,   OK, via_vt823x_gpio15_raise},
    {0x1106, 0x0259, 0x1106, 0x3227,  0x1106, 0x3065, 0x1106, 0x3149, NULL,          NULL,         NULL,          "VIA",         "EPIA-N/NL",             0,   OK, via_vt823x_gpio9_raise},
-
+#endif
    {     0,      0,      0,      0,       0,      0,      0,      0, NULL,          NULL,         NULL,          NULL,          NULL,                    0,   NT, NULL}, /* end marker */
 };

[Michael Manulis]

I tested the changes on my system.  The system is a CurtisWright Raptor
board with a single PowerPC 7457 processor.  It has a daughter-board from
TechnoBox 5575 PCI-over-PMC SATA adapter.  The daughter-board has onboard
BIOS (AMD flash chip) and EEPROM.

I was able to read, write and erase both chips using satasii programmer.

I did encounter an issue when my rootfs is mounted over NFS.  When writing
data back onto flash, the data came back in reverse endianness from the
original.  This was only an issue with NFS-mounted rootfs.  When I tested
the same procedure with the rootfs mounted from the internal SATA drive,
everything was consistent.

My test procedure was as follows:

1. Run flashrom to detect the flah chips
    flashrom -p satasii
2. Got the contents of the flash chips and diff-ed the hexdump of the
contents against a known good image which came back with no differences
        flashrom -p satasii -r current_contents.img
3. Erased the contents of flash.  Dumped the contents of the flash after
erase and verified that it is all zeros (0)
        flashrom -p satasii -E
4. Flashed the contents of the known good image
    flashrom -p satasii -w original.img
5. Dumped the new contents and verified the hexdump against the known good
image again

Log of the steps and their result:

vsm:~# ./flashrom -p satasii
flashrom v0.9.1-r985
Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF
00:0a.0).
===
This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output
to [e-mail] if it works for you. Thank you for your help!
===
Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100.
Warning: Flash seems unconnected.
Calibrating delay loop... OK.
Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address
0xfff80000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to [e-mail] if any of the above
operations
work correctly for you with this flash part. Please include the flashrom
output with the additional -V option for all operations you tested (-V, -rV,
-wV, -EV), and mention which mainboard or programmer you tested.
Thanks for your help!
===
No operations were specified.
vsm:~# ./flashrom -p satasii -r current_contents.img
flashrom v0.9.1-r985
Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF
00:0a.0).
===
This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output
to [e-mail] if it works for you. Thank you for your help!
===
Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100.
Warning: Flash seems unconnected.
Calibrating delay loop... OK.
Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address
0xfff80000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to [e-mail] if any of the above
operations
work correctly for you with this flash part. Please include the flashrom
output with the additional -V option for all operations you tested (-V, -rV,
-wV, -EV), and mention which mainboard or programmer you tested.
Thanks for your help!
===
Reading flash... done.
vsm:~# hexdump current_contents.img > current_contents.hex
vsm:~# diff sii.hex current_contents.hex
vsm:~# ./flashrom -p satasii -E
flashrom v0.9.1-r985
Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF
00:0a.0).
===
This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output
to [e-mail] if it works for you. Thank you for your help!
===
Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100.
Warning: Flash seems unconnected.
Calibrating delay loop... OK.
Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address
0xfff80000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to [e-mail] if any of the above
operations
work correctly for you with this flash part. Please include the flashrom
output with the additional -V option for all operations you tested (-V, -rV,
-wV, -EV), and mention which mainboard or programmer you tested.
Thanks for your help!
===
Erasing flash chip... SUCCESS.
vsm:~# ./flashrom -p satasii -r empty.img
flashrom v0.9.1-r985
Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF
00:0a.0).
===
This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output
to [e-mail] if it works for you. Thank you for your help!
===
Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100.
Warning: Flash seems unconnected.
Calibrating delay loop... OK.
Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address
0xfff80000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to [e-mail] if any of the above
operations
work correctly for you with this flash part. Please include the flashrom
output with the additional -V option for all operations you tested (-V, -rV,
-wV, -EV), and mention which mainboard or programmer you tested.
Thanks for your help!
===
Reading flash... done.
vsm:~# hexdump empty.img
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0080000
vsm:~# ./flashrom -p satasii -w sii.
sii.dump  sii.hex
vsm:~# ./flashrom -p satasii -w sii.dump
flashrom v0.9.1-r985
Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF
00:0a.0).
===
This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output
to [e-mail] if it works for you. Thank you for your help!
===
Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100.
Warning: Flash seems unconnected.
Calibrating delay loop... OK.
Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address
0xfff80000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to [e-mail] if any of the above
operations
work correctly for you with this flash part. Please include the flashrom
output with the additional -V option for all operations you tested (-V, -rV,
-wV, -EV), and mention which mainboard or programmer you tested.
Thanks for your help!
===
Flash image seems to be a legacy BIOS. Disabling checks.
Writing flash chip... Erasing flash chip... SUCCESS.
Programming page: DONE!ss: 0x0007f000
COMPLETE.
Verifying flash... VERIFIED.
vsm:~# ./flashrom -p satasii -r new.img
flashrom v0.9.1-r985
Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF
00:0a.0).
===
This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output
to [e-mail] if it works for you. Thank you for your help!
===
Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100.
Warning: Flash seems unconnected.
Calibrating delay loop... OK.
Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address
0xfff80000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to [e-mail] if any of the above
operations
work correctly for you with this flash part. Please include the flashrom
output with the additional -V option for all operations you tested (-V, -rV,
-wV, -EV), and mention which mainboard or programmer you tested.
Thanks for your help!
===
Reading flash... done.
vsm:~# hexdump new.img > new.hex
vsm:~# diff new.hex sii.hex

All these steps were completed successfully

Thank you everyone for your help

Acked-by: Misha Manulis

On Fri, Mar 26, 2010 at 9:42 AM, Carl-Daniel Hailfinger <
[e-mail]> wrote:
> On 26.03.2010 05:13, Carl-Daniel Hailfinger wrote:
> > Misha Manulis asked for satasii support on PPC and on IRC we gave him
> > some hints to hack up something that works for ppc only and satasii
> > only. His patch can be found here: http://coreboot.pastebin.com/fuLk1FCA
> >
> > Here is a patch which does everything The Right Way (TM) and uses proper
> > abstraction for satasii and compiles all x86 specific stuff only on x86.
> >
> > Huge thanks go to Segher Boessenkool who provided valuable info about
> > all the endianness trickery (especially preprocessor macros) and tested
> > 8 iterations of the code on Linux/PPC.
> >
> > On 26.03.2010 01:51, Carl-Daniel Hailfinger wrote:
> > > flashrom is very x86 centric. It does work on other architectures if you
> > > get it to compile. Try to fix the all errors on ppc for a
> > > full build.
> > >
> > > Should work in theory with a default build if you exclude nic3com.
> > > Will pretty sure break compilation on Alpha.
> >
> > This one should compile on ppc, I even expect it to work for satasii on
>
> ppc.
> > AFAICS all programmer drivers except nic3com should work.
> > Compile with
> > make distclean
> > make NIC3COM=no
> >
> > Known bugs:
> >
> > x86 is broken by this patch because the Makefile excludes the x86
> > specific internal files. If you want to test this patch on x86 (to make
> > sure I didn't break everything), change
> > #PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o
> > to
> > PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o
> >
> > boards_ok and boards_bad has no x86 guard yet and will end up in
> > flashrom -L output.
>
> Misha Manulis tested the patch and it didn't work. I found a typo which
> truncated all 16 bit and 32 bit LE write accesses to 8 bit.
>
> New version, should work fine with the x86/nic3com exceptions mentioned
> above.
>
> Signed-off-by: Carl-Daniel Hailfinger
> Index: flashrom-ioport_x86_only/hwaccess.c
>
> --- flashrom-ioport_x86_only/hwaccess.c (Revision 984)
> +++ flashrom-ioport_x86_only/hwaccess.c (Arbeitskopie)
> @@ -26,6 +26,8 @@
>  #include <errno.h>
>  #include "flash.h"
>
> +#if defined(__i386__) || defined(__x86_64__)
>
> #if defined(__FreeBSD__) || defined(__DragonFly__)
>  int io_fd;
>  #endif
> @@ -54,6 +56,22 @@
>  #endif
>  }
>
> +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__)
> || defined(__ppc64__)
>
> +void get_io_perms(void)
> +{
> +}
>
> +void release_io_perms(void)
> +{
> +}
>
> +#else
>
> +#error Unknown architecture
>
> +#endif
>
> #ifdef __DJGPP__
>
> extern unsigned short  segFS;
> @@ -122,3 +140,33 @@
>        return *(volatile uint32_t *) addr;
>  }
>  #endif
>
> +void mmio_le_writeb(uint8_t val, void *addr)
> +{
>   mmio_writeb(cpu_to_le8(val), addr);
>
> +}
>
> +void mmio_le_writew(uint16_t val, void *addr)
> +{
>   mmio_writew(cpu_to_le16(val), addr);
>
> +}
>
> +void mmio_le_writel(uint32_t val, void *addr)
> +{
>   mmio_writel(cpu_to_le32(val), addr);
>
> +}
>
> +uint8_t mmio_le_readb(void *addr)
> +{
>   return le_to_cpu8(mmio_readb(addr));
>
> +}
>
> +uint16_t mmio_le_readw(void *addr)
> +{
>   return le_to_cpu16(mmio_readw(addr));
>
> +}
>
> +uint32_t mmio_le_readl(void *addr)
> +{
>   return le_to_cpu32(mmio_readl(addr));
>
> +}
> Index: flashrom-ioport_x86_only/flash.h
> ===================================================================
> --- flashrom-ioport_x86_only/flash.h    (Revision 984)
> +++ flashrom-ioport_x86_only/flash.h    (Arbeitskopie)
> @@ -59,8 +59,10 @@
>        PROGRAMMER_ATAHPT,
>  #endif
>  #if INTERNAL_SUPPORT == 1
> +#if defined(__i386__) || defined(__x86_64__)
>        PROGRAMMER_IT87SPI,
>  #endif
> +#endif
>  #if FT2232_SPI_SUPPORT == 1
>        PROGRAMMER_FT2232SPI,
>  #endif
> @@ -402,6 +404,12 @@
>  uint8_t mmio_readb(void *addr);
>  uint16_t mmio_readw(void *addr);
>  uint32_t mmio_readl(void *addr);
> +void mmio_le_writeb(uint8_t val, void *addr);
> +void mmio_le_writew(uint16_t val, void *addr);
> +void mmio_le_writel(uint32_t val, void *addr);
> +uint8_t mmio_le_readb(void *addr);
> +uint16_t mmio_le_readw(void *addr);
> +uint32_t mmio_le_readl(void *addr);
>
> /* programmer.c */
>  int noop_shutdown(void);
> @@ -585,6 +593,7 @@
>  enum spi_controller {
>        SPI_CONTROLLER_NONE,
>  #if INTERNAL_SUPPORT == 1
> +#if defined(__i386__) || defined(__x86_64__)
>        SPI_CONTROLLER_ICH7,
>        SPI_CONTROLLER_ICH9,
>        SPI_CONTROLLER_IT87XX,
> @@ -592,6 +601,7 @@
>        SPI_CONTROLLER_VIA,
>        SPI_CONTROLLER_WBSIO,
>  #endif
> +#endif
>  #if FT2232_SPI_SUPPORT == 1
>        SPI_CONTROLLER_FT2232,
>  #endif
> Index: flashrom-ioport_x86_only/spi25.c
> ===================================================================
> --- flashrom-ioport_x86_only/spi25.c    (Revision 984)
> +++ flashrom-ioport_x86_only/spi25.c    (Arbeitskopie)
> @@ -172,12 +172,14 @@
>        /* only some SPI chipsets support 4 bytes commands */
>        switch (spi_controller) {
>  #if INTERNAL_SUPPORT == 1
> +#if defined(__i386__) || defined(__x86_64__)
>        case SPI_CONTROLLER_ICH7:
>        case SPI_CONTROLLER_ICH9:
>        case SPI_CONTROLLER_VIA:
>        case SPI_CONTROLLER_SB600:
>        case SPI_CONTROLLER_WBSIO:
>  #endif
> +#endif
>  #if FT2232_SPI_SUPPORT == 1
>        case SPI_CONTROLLER_FT2232:
>  #endif
> @@ -950,11 +952,13 @@
>    switch (spi_controller) {
>
> #if INTERNAL_SUPPORT == 1
> +#if defined(__i386__) || defined(__x86_64__)
>        case SPI_CONTROLLER_WBSIO:
>                msg_cerr("%s: impossible with Winbond SPI masters,"
>                                " degrading to byte program\n", __func__);
>                return spi_chip_write_1(flash, buf);
>  #endif
> +#endif
>        default:
>                break;
>        }
> Index: flashrom-ioport_x86_only/hwaccess.h
> ===================================================================
> --- flashrom-ioport_x86_only/hwaccess.h (Revision 984)
> +++ flashrom-ioport_x86_only/hwaccess.h (Arbeitskopie)
> @@ -24,13 +24,88 @@
>  #ifndef __HWACCESS_H__
>  #define __HWACCESS_H__ 1
>
> +#if defined (__i386__) || defined (__x86_64__)
>  #if defined(__GLIBC__)
>  #include <sys/io.h>
>  #endif
> +#endif
>
> #if NEED_PCI == 1
>  #include <pci/pci.h>
>  #endif
>
> +#define ___constant_swab8(x) ((uint8_t)(                               \
>   (((uint8_t)(x) & (uint8_t)0xffU))))
>
> +#define ___constant_swab16(x) ((uint16_t)(                             \
>   (((uint16_t)(x) & (uint16_t)0x00ffU) << 8) |                    \
>   (((uint16_t)(x) & (uint16_t)0xff00U) >> 8)))
>
> +#define ___constant_swab32(x) ((uint32_t)(                             \
>   (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) |              \
>   (((uint32_t)(x) & (uint32_t)0x0000ff00UL) <<  8) |              \
>   (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >>  8) |              \
>   (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24)))
>
> +#define ___constant_swab64(x) ((uint64_t)(                             \
>   (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) |     \
>   (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) |     \
>   (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) |     \
>   (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) <<  8) |     \
>   (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >>  8) |     \
>   (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) |     \
>   (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) |     \
>   (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56)))
>
> +#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__)
>
> +#define cpu_to_le(bits)
>      \
> +static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val)       \
> +{                                                                      \
>   return ___constant_swab##bits(val);                             \
>
> +}
>
> +cpu_to_le(8)
> +cpu_to_le(16)
> +cpu_to_le(32)
> +cpu_to_le(64)
>
> +#define cpu_to_be8
> +#define cpu_to_be16
> +#define cpu_to_be32
> +#define cpu_to_be64
>
> +#else
>
> +#define cpu_to_be(bits)
>      \
> +static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val)       \
> +{                                                                      \
>   return ___constant_swab##bits(val);                             \
>
> +}
>
> +cpu_to_be(8)
> +cpu_to_be(16)
> +cpu_to_be(32)
> +cpu_to_be(64)
>
> +#define cpu_to_le8
> +#define cpu_to_le16
> +#define cpu_to_le32
> +#define cpu_to_le64
>
> +#endif
>
> +#define be_to_cpu8 cpu_to_be8
> +#define be_to_cpu16 cpu_to_be16
> +#define be_to_cpu32 cpu_to_be32
> +#define be_to_cpu64 cpu_to_be64
> +#define le_to_cpu8 cpu_to_le8
> +#define le_to_cpu16 cpu_to_le16
> +#define le_to_cpu32 cpu_to_le32
> +#define le_to_cpu64 cpu_to_le64
>
> +#if defined (__i386__) || defined (__x86_64__)
>
> /* for iopl and outb under Solaris */
>  #if defined (__sun) && (defined(__i386) || defined(__amd64))
>  #include <strings.h>
> @@ -162,4 +237,11 @@
>  int freebsd_wrmsr(int addr, msr_t msr);
>  #endif
>
> +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__)
> || defined(__ppc64__)
> +/* Port I/O is not available on PowerPC. */
>
> +#else
> +#error Unknown architecture
> +#endif
>
> #endif /* !__HWACCESS_H__ */
> Index: flashrom-ioport_x86_only/physmap.c
> ===================================================================
> --- flashrom-ioport_x86_only/physmap.c  (Revision 984)
> +++ flashrom-ioport_x86_only/physmap.c  (Arbeitskopie)
> @@ -238,6 +238,8 @@
>        return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL,
> PHYSMAP_RO);
>  }
>
> +#if defined(__i386__) || defined(__x86_64__)
>
> #ifdef __linux__
>  /*
> Reading and writing to MSRs, however requires instructions rdmsr/wrmsr,
>
> @@ -455,4 +457,6 @@
>  #endif
>  #endif
>  #endif
>
> +#else
> +/* Does MSR exist on non-x86 architectures? */
> +#endif
> Index: flashrom-ioport_x86_only/spi.c
> ===================================================================
> --- flashrom-ioport_x86_only/spi.c      (Revision 984)
> +++ flashrom-ioport_x86_only/spi.c      (Arbeitskopie)
> @@ -42,6 +42,7 @@
>        },
>
> #if INTERNAL_SUPPORT == 1
> +#if defined(__i386__) || defined(__x86_64__)
>        { /* SPI_CONTROLLER_ICH7 */
>                .command = ich_spi_send_command,
>                .multicommand = ich_spi_send_multicommand,
> @@ -84,6 +85,7 @@
>                .write_256 = wbsio_spi_write_1,
>        },
>  #endif
> +#endif
>
> #if FT2232_SPI_SUPPORT == 1
>        { /* SPI_CONTROLLER_FT2232 */
> Index: flashrom-ioport_x86_only/nic3com.c
> ===================================================================
> --- flashrom-ioport_x86_only/nic3com.c  (Revision 984)
> +++ flashrom-ioport_x86_only/nic3com.c  (Arbeitskopie)
> @@ -23,6 +23,8 @@
>  #include <sys/types.h>
>  #include "flash.h"
>
> +#if defined(__i386__) || defined(__x86_64__)
>
> #define BIOS_ROM_ADDR          0x04
>  #define BIOS_ROM_DATA          0x08
>  #define INT_STATUS             0x0e
> @@ -112,3 +114,7 @@
>        OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
>        return INB(io_base_addr + BIOS_ROM_DATA);
>  }
>
> +#else
> +#error Unknown architecture
> +#endif
> Index: flashrom-ioport_x86_only/Makefile
> ===================================================================
> --- flashrom-ioport_x86_only/Makefile   (Revision 984)
> +++ flashrom-ioport_x86_only/Makefile   (Arbeitskopie)
> @@ -121,7 +121,8 @@
>
> ifeq ($(CONFIG_INTERNAL), yes)
>  FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1'
> -PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o
> it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o
> +PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o
> internal.o
> +#PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o
>  NEED_PCI := yes
>  endif
>
> @@ -253,7 +254,7 @@
>        rm -f .dependencies .features .libdeps
>
> dep:
>   @$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies
>   @$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies
>
> strip: $(PROGRAM)
>        $(STRIP) $(STRIP_ARGS) $(PROGRAM)
> Index: flashrom-ioport_x86_only/satasii.c
> ===================================================================
> --- flashrom-ioport_x86_only/satasii.c  (Revision 984)
> +++ flashrom-ioport_x86_only/satasii.c  (Arbeitskopie)
> @@ -62,7 +62,7 @@
>        sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset;
>    /* Check if ROM cycle are OK. */
>   if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26))))
>   if ((id != 0x0680) && (!(mmio_le_readl(sii_bar) & (1 << 26))))
>          msg_pinfo("Warning: Flash seems unconnected.\n");
>
>  buses_supported = CHIP_BUSTYPE_PARALLEL;
>
> @@ -82,32 +82,32 @@
>  {
>        uint32_t ctrl_reg, data_reg;
>   while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;
>   while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ;
>
>  /* Mask out unused/reserved bits, set writes and start transaction.
>
> */
>        ctrl_reg &= 0xfcf80000;
>        ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff);
>   data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val;
>   mmio_writel(data_reg, (sii_bar + 4));
>   mmio_writel(ctrl_reg, sii_bar);
>   data_reg = (mmio_le_readl((sii_bar + 4)) & ~0xff) | val;
>   mmio_le_writel(data_reg, (sii_bar + 4));
>   mmio_le_writel(ctrl_reg, sii_bar);
>
>   while (mmio_readl(sii_bar) & (1 << 25)) ;
>   while (mmio_le_readl(sii_bar) & (1 << 25)) ;
>
> }
>
> uint8_t satasii_chip_readb(const chipaddr addr)
>  {
>        uint32_t ctrl_reg;
>   while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;
>   while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ;
>
>  /* Mask out unused/reserved bits, set reads and start transaction.
>
> */
>        ctrl_reg &= 0xfcf80000;
>        ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff);
>   mmio_writel(ctrl_reg, sii_bar);
>   mmio_le_writel(ctrl_reg, sii_bar);
>
>   while (mmio_readl(sii_bar) & (1 << 25)) ;
>   while (mmio_le_readl(sii_bar) & (1 << 25)) ;
>
>   return (mmio_readl(sii_bar + 4)) & 0xff;
>   return (mmio_le_readl(sii_bar + 4)) & 0xff;
>
> }
> Index: flashrom-ioport_x86_only/chipset_enable.c
> ===================================================================
> --- flashrom-ioport_x86_only/chipset_enable.c   (Revision 984)
> +++ flashrom-ioport_x86_only/chipset_enable.c   (Arbeitskopie)
> @@ -34,6 +34,8 @@
>  #include <fcntl.h>
>  #include "flash.h"
>
> +#if defined(__i386__) || defined(__x86_64__)
>
> extern int ichspi_lock;
>
> static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
> @@ -1285,8 +1287,11 @@
>        return 0;
>  }
>
> +#endif
>
> /* Please keep this list alphabetically sorted by vendor/device. */
>  const struct penable chipset_enables[] = {
> +#if defined(__i386__) || defined(__x86_64__)
>        {0x10B9, 0x1533, OK, "ALi", "M1533",
>  enable_flash_ali_m1533},
>        {0x1022, 0x7440, OK, "AMD", "AMD-768",
>  enable_flash_amd8111},
>        {0x1022, 0x7468, OK, "AMD", "AMD8111",
>  enable_flash_amd8111},
> @@ -1417,7 +1422,7 @@
>        {0x1106, 0x0596, OK, "VIA", "VT82C596",
> enable_flash_amd8111},
>        {0x1106, 0x0586, OK, "VIA", "VT82C586A/B",
>  enable_flash_amd8111},
>        {0x1106, 0x0686, NT, "VIA", "VT82C686A/B",
>  enable_flash_amd8111},
>
> +#endif
>        {},
>  };
> Index: flashrom-ioport_x86_only/flashrom.c
>
> --- flashrom-ioport_x86_only/flashrom.c (Revision 984)
> +++ flashrom-ioport_x86_only/flashrom.c (Arbeitskopie)
> @@ -233,6 +233,7 @@
>  #endif
>
> #if INTERNAL_SUPPORT == 1
> +#if defined(__i386__) || defined(__x86_64__)
>        {
>                .name                   = "it87spi",
>                .init                   = it87spi_init,
> @@ -250,6 +251,7 @@
>                .delay                  = internal_delay,
>        },
>  #endif
> +#endif
>
> #if FT2232_SPI_SUPPORT == 1
>        {
> Index: flashrom-ioport_x86_only/internal.c
> ===================================================================
> --- flashrom-ioport_x86_only/internal.c (Revision 984)
> +++ flashrom-ioport_x86_only/internal.c (Arbeitskopie)
> @@ -99,9 +99,11 @@
>  #endif
>
> #if INTERNAL_SUPPORT == 1
> -struct superio superio = {};
>  int force_boardenable = 0;
>
> +#if defined(__i386__) || defined(__x86_64__)
> +struct superio superio = {};
>
> void probe_superio(void)
>  {
>        superio = probe_superio_ite();
> @@ -111,8 +113,9 @@
>                superio = probe_superio_winbond();
>  #endif
>  }
> +#endif
>
> -int is_laptop;
> +int is_laptop = 0;
>
> int internal_init(void)
>  {
> @@ -149,10 +152,13 @@
>         * mainboard specific flash enable sequence.
>         */
>        coreboot_init();
>
> +#if defined(__i386__) || defined(__x86_64__)
>        dmi_init();
>    /* Probe for the Super I/O chip and fill global struct superio. */
>    probe_superio();
>
> +#endif
>    /* Warn if a laptop is detected. */
>    if (is_laptop)
>
> @@ -173,8 +179,10 @@
>                       "will most likely fail.\n");
>        }
>
> +#if defined(__i386__) || defined(__x86_64__)
>        /* Probe for IT87* LPC->SPI translation unconditionally. */
>        it87xx_probe_spi_flash(NULL);
> +#endif
>    board_flash_enable(lb_vendor, lb_part);
>
> Index: flashrom-ioport_x86_only/board_enable.c
>
> --- flashrom-ioport_x86_only/board_enable.c     (Revision 984)
> +++ flashrom-ioport_x86_only/board_enable.c     (Arbeitskopie)
> @@ -28,6 +28,7 @@
>  #include <fcntl.h>
>  #include "flash.h"
>
> +#if defined(__i386__) || defined(__x86_64__)
>  /*
> Helper functions for many Winbond Super I/Os of the W836xx range.
>
> */
> @@ -1299,6 +1300,8 @@
>        return it8712f_gpio_set(32, 1);
>  }
>
> +#endif
>
> /**
> Below is the list of boards which need a special "board enable" code in
> flashrom before their ROM chip can be accessed/written to.
>
> @@ -1342,6 +1345,7 @@
>  struct board_pciid_enable board_pciid_enables[] = {
>    /* first pci-id set [4],          second pci-id set [4],
>
> dmi identifier coreboot id [2],             vendor name    board name
> max_rom_...  OK? flash enable */
> +#if defined(__i386__) || defined(__x86_64__)
>        {0x10DE, 0x0547, 0x147B, 0x1C2F,  0x10DE, 0x0548, 0x147B, 0x1C2F,
> NULL,          NULL,         NULL,          "Abit",        "AN-M2",
>         0,   NT, nvidia_mcp_gpio2_raise},
>        {0x8086, 0x2926, 0x147b, 0x1084,  0x11ab, 0x4364, 0x147b, 0x1084,
> NULL,          NULL,         NULL,          "Abit",        "IP35",
>        0,   OK, intel_ich_gpio16_raise},
>        {0x8086, 0x2930, 0x147b, 0x1083,  0x10ec, 0x8167, 0x147b, 0x1083,
> NULL,          NULL,         NULL,          "Abit",        "IP35 Pro",
>        0,   OK, intel_ich_gpio16_raise},
> @@ -1407,7 +1411,7 @@
>        {0x1106, 0x3123, 0x1106, 0x3123,  0x1106, 0x3059, 0x1106, 0x4161,
> NULL,          NULL,         NULL,          "Termtek",     "TK-3370
> (Rev:2.5B)",    0,   OK, w836xx_memw_enable_4e},
>        {0x1106, 0x3177, 0x1106, 0xAA01,  0x1106, 0x3123, 0x1106, 0xAA01,
> NULL,          NULL,         NULL,          "VIA",         "EPIA M/MII/...",
>        0,   OK, via_vt823x_gpio15_raise},
>        {0x1106, 0x0259, 0x1106, 0x3227,  0x1106, 0x3065, 0x1106, 0x3149,
> NULL,          NULL,         NULL,          "VIA",         "EPIA-N/NL",
>         0,   OK, via_vt823x_gpio9_raise},
>
> +#endif
>        {     0,      0,      0,      0,       0,      0,      0,      0,
> NULL,          NULL,         NULL,          NULL,          NULL,
>        0,   NT, NULL}, /* end marker */
>  };

[Carl-Daniel Hailfinger]

On 26.03.2010 19:13, Michael Manulis wrote:
> I tested the changes on my system.  The system is a CurtisWright Raptor
> board with a single PowerPC 7457 processor.  It has a daughter-board from
> TechnoBox 5575 PCI-over-PMC SATA adapter.  The daughter-board has onboard
> BIOS (AMD flash chip) and EEPROM.
>
> I was able to read, write and erase both chips using satasii programmer.
>
> I did encounter an issue when my rootfs is mounted over NFS.  When writing
> data back onto flash, the data came back in reverse endianness from the
> original.  This was only an issue with NFS-mounted rootfs.  When I tested
> the same procedure with the rootfs mounted from the internal SATA drive,
> everything was consistent.
> [...]
>
> vsm:~# ./flashrom -p satasii
> flashrom v0.9.1-r985
> Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF
> 00:0a.0).
> ===
> This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output
> to [e-mail] if it works for you. Thank you for your help!
> ===
> Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100.
> Warning: Flash seems unconnected.
> Calibrating delay loop... OK.
> Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address
> 0xfff80000.
>
> Acked-by: Misha Manulis
>
> On Fri, Mar 26, 2010 at 9:42 AM, Carl-Daniel Hailfinger <
> [e-mail]> wrote:
> > On 26.03.2010 05:13, Carl-Daniel Hailfinger wrote:
> > > Misha Manulis asked for satasii support on PPC and on IRC we gave him
> > > some hints to hack up something that works for ppc only and satasii
> > > only. His patch can be found here: http://coreboot.pastebin.com/fuLk1FCA
> > >
> > > Here is a patch which does everything The Right Way (TM) and uses proper
> > > abstraction for satasii and compiles all x86 specific stuff only on x86.
> > >
> > > Huge thanks go to Segher Boessenkool who provided valuable info about
> > > all the endianness trickery (especially preprocessor macros) and tested
> > > 8 iterations of the code on Linux/PPC.

All programmers except nic3com should be compilable with this new patch.
The satasii programmer should work on PowerPC.

make distclean
make CONFIG_NIC3COM=no

Please report any compilation issues to the mailing list.

Signed-off-by: Carl-Daniel Hailfinger

Index: flashrom-arch_abstraction/hwaccess.c
===================================================================
--- flashrom-arch_abstraction/hwaccess.c	(Revision 1008)
+++ flashrom-arch_abstraction/hwaccess.c	(Arbeitskopie)
@@ -26,6 +26,8 @@
 #include <errno.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 #if defined(__FreeBSD__) || defined(__DragonFly__)
 int io_fd;
 #endif
@@ -54,6 +56,22 @@
 #endif
 }

+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+void get_io_perms(void)
+{
+}
+
+void release_io_perms(void)
+{
+}
+
+#else
+
+#error Unknown architecture
+
+#endif
+
 void mmio_writeb(uint8_t val, void *addr)
 {
    *(volatile uint8_t *) addr = val;
@@ -83,3 +101,33 @@
 {
    return *(volatile uint32_t *) addr;
 }
+
+void mmio_le_writeb(uint8_t val, void *addr)
+{
+	mmio_writeb(cpu_to_le8(val), addr);
+}
+
+void mmio_le_writew(uint16_t val, void *addr)
+{
+	mmio_writew(cpu_to_le16(val), addr);
+}
+
+void mmio_le_writel(uint32_t val, void *addr)
+{
+	mmio_writel(cpu_to_le32(val), addr);
+}
+
+uint8_t mmio_le_readb(void *addr)
+{
+	return le_to_cpu8(mmio_readb(addr));
+}
+
+uint16_t mmio_le_readw(void *addr)
+{
+	return le_to_cpu16(mmio_readw(addr));
+}
+
+uint32_t mmio_le_readl(void *addr)
+{
+	return le_to_cpu32(mmio_readl(addr));
+}
Index: flashrom-arch_abstraction/flash.h
===================================================================
--- flashrom-arch_abstraction/flash.h	(Revision 1008)
+++ flashrom-arch_abstraction/flash.h	(Arbeitskopie)
@@ -63,8 +63,10 @@
    PROGRAMMER_ATAHPT,
 #endif
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    PROGRAMMER_IT87SPI,
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    PROGRAMMER_FT2232SPI,
 #endif
@@ -407,6 +409,12 @@
 uint8_t mmio_readb(void *addr);
 uint16_t mmio_readw(void *addr);
 uint32_t mmio_readl(void *addr);
+void mmio_le_writeb(uint8_t val, void *addr);
+void mmio_le_writew(uint16_t val, void *addr);
+void mmio_le_writel(uint32_t val, void *addr);
+uint8_t mmio_le_readb(void *addr);
+uint16_t mmio_le_readw(void *addr);
+uint32_t mmio_le_readl(void *addr);

/* programmer.c */
 int noop_shutdown(void);
@@ -603,6 +611,7 @@
 enum spi_controller {
    SPI_CONTROLLER_NONE,
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    SPI_CONTROLLER_ICH7,
    SPI_CONTROLLER_ICH9,
    SPI_CONTROLLER_IT87XX,
@@ -610,6 +619,7 @@
    SPI_CONTROLLER_VIA,
    SPI_CONTROLLER_WBSIO,
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    SPI_CONTROLLER_FT2232,
 #endif
Index: flashrom-arch_abstraction/spi25.c
===================================================================
--- flashrom-arch_abstraction/spi25.c	(Revision 1008)
+++ flashrom-arch_abstraction/spi25.c	(Arbeitskopie)
@@ -172,12 +172,14 @@
    /* only some SPI chipsets support 4 bytes commands */
    switch (spi_controller) {
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    case SPI_CONTROLLER_ICH7:
    case SPI_CONTROLLER_ICH9:
    case SPI_CONTROLLER_VIA:
    case SPI_CONTROLLER_SB600:
    case SPI_CONTROLLER_WBSIO:
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    case SPI_CONTROLLER_FT2232:
 #endif
@@ -996,11 +998,13 @@

switch (spi_controller) {
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    case SPI_CONTROLLER_WBSIO:
    	msg_cerr("%s: impossible with Winbond SPI masters,"
    			" degrading to byte program\n", __func__);
    	return spi_chip_write_1(flash, buf);
 #endif
+#endif
    default:
    	break;
    }
Index: flashrom-arch_abstraction/hwaccess.h
===================================================================
--- flashrom-arch_abstraction/hwaccess.h	(Revision 1008)
+++ flashrom-arch_abstraction/hwaccess.h	(Arbeitskopie)
@@ -24,13 +24,88 @@
 #ifndef __HWACCESS_H__
 #define __HWACCESS_H__ 1

+#if defined (__i386__) || defined (__x86_64__)
 #if defined(__GLIBC__)
 #include <sys/io.h>
 #endif
+#endif
+
 #if NEED_PCI == 1
 #include <pci/pci.h>
 #endif

+#define ___constant_swab8(x) ((uint8_t)(				\
+	(((uint8_t)(x) & (uint8_t)0xffU))))
+
+#define ___constant_swab16(x) ((uint16_t)(				\
+	(((uint16_t)(x) & (uint16_t)0x00ffU) << 8) |			\
+	(((uint16_t)(x) & (uint16_t)0xff00U) >> 8)))
+
+#define ___constant_swab32(x) ((uint32_t)(				\
+	(((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) |		\
+	(((uint32_t)(x) & (uint32_t)0x0000ff00UL) <<  8) |		\
+	(((uint32_t)(x) & (uint32_t)0x00ff0000UL) >>  8) |		\
+	(((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24)))
+
+#define ___constant_swab64(x) ((uint64_t)(				\
+	(((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) |	\
+	(((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) |	\
+	(((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) |	\
+	(((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) <<  8) |	\
+	(((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >>  8) |	\
+	(((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) |	\
+	(((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) |	\
+	(((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56)))
+
+#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__)
+
+#define cpu_to_le(bits)							\
+static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val)	\
+{									\
+	return ___constant_swab##bits(val);				\
+}
+
+cpu_to_le(8)
+cpu_to_le(16)
+cpu_to_le(32)
+cpu_to_le(64)
+
+#define cpu_to_be8
+#define cpu_to_be16
+#define cpu_to_be32
+#define cpu_to_be64
+
+#else
+
+#define cpu_to_be(bits)							\
+static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val)	\
+{									\
+	return ___constant_swab##bits(val);				\
+}
+
+cpu_to_be(8)
+cpu_to_be(16)
+cpu_to_be(32)
+cpu_to_be(64)
+
+#define cpu_to_le8
+#define cpu_to_le16
+#define cpu_to_le32
+#define cpu_to_le64
+
+#endif
+
+#define be_to_cpu8 cpu_to_be8
+#define be_to_cpu16 cpu_to_be16
+#define be_to_cpu32 cpu_to_be32
+#define be_to_cpu64 cpu_to_be64
+#define le_to_cpu8 cpu_to_le8
+#define le_to_cpu16 cpu_to_le16
+#define le_to_cpu32 cpu_to_le32
+#define le_to_cpu64 cpu_to_le64
+
+#if defined (__i386__) || defined (__x86_64__)
+
 /* for iopl and outb under Solaris */
 #if defined (__sun) && (defined(__i386) || defined(__amd64))
 #include <strings.h>
@@ -162,4 +237,11 @@
 int freebsd_wrmsr(int addr, msr_t msr);
 #endif

+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+/* Port I/O is not available on PowerPC. */
+
+#else
+#error Unknown architecture
+#endif
+
 #endif /* !__HWACCESS_H__ */
Index: flashrom-arch_abstraction/it87spi.c
===================================================================
--- flashrom-arch_abstraction/it87spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/it87spi.c	(Arbeitskopie)
@@ -23,6 +23,8 @@
  * Contains the ITE IT87* SPI specific routines
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include <stdlib.h>
 #include "flash.h"
@@ -351,3 +353,5 @@

return 0;
 }
+
+#endif
Index: flashrom-arch_abstraction/physmap.c
===================================================================
--- flashrom-arch_abstraction/physmap.c	(Revision 1008)
+++ flashrom-arch_abstraction/physmap.c	(Arbeitskopie)
@@ -241,6 +241,8 @@
    return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO);
 }

+#if defined(__i386__) || defined(__x86_64__)
+
 #ifdef __linux__
 /*
  * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr,
@@ -462,4 +464,6 @@
 #endif
 #endif
 #endif
-
+#else
+/* Does MSR exist on non-x86 architectures? */
+#endif
Index: flashrom-arch_abstraction/nic3com.c
===================================================================
--- flashrom-arch_abstraction/nic3com.c	(Revision 1008)
+++ flashrom-arch_abstraction/nic3com.c	(Arbeitskopie)
@@ -23,6 +23,8 @@
 #include <sys/types.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 #define BIOS_ROM_ADDR		0x04
 #define BIOS_ROM_DATA		0x08
 #define INT_STATUS		0x0e
@@ -112,3 +114,7 @@
    OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
    return INB(io_base_addr + BIOS_ROM_DATA);
 }
+
+#else
+#error Unknown architecture
+#endif
Index: flashrom-arch_abstraction/spi.c
===================================================================
--- flashrom-arch_abstraction/spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/spi.c	(Arbeitskopie)
@@ -42,6 +42,7 @@
    },

#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    { /* SPI_CONTROLLER_ICH7 */
    	.command = ich_spi_send_command,
    	.multicommand = ich_spi_send_multicommand,
@@ -84,6 +85,7 @@
    	.write_256 = wbsio_spi_write_1,
    },
 #endif
+#endif

#if FT2232_SPI_SUPPORT == 1
    { /* SPI_CONTROLLER_FT2232 */
Index: flashrom-arch_abstraction/Makefile
===================================================================
--- flashrom-arch_abstraction/Makefile	(Revision 1008)
+++ flashrom-arch_abstraction/Makefile	(Arbeitskopie)
@@ -124,7 +124,9 @@

ifeq ($(CONFIG_INTERNAL), yes)
 FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1'
-PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o
+PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o
+# FIXME: The PROGRAMMER_OBJS below should only be included on x86.
+PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o
 NEED_PCI := yes
 endif

@@ -260,7 +262,7 @@
    rm -f .dependencies .features .libdeps

dep:
-	@$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies
+	@$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies

strip: $(PROGRAM)
    $(STRIP) $(STRIP_ARGS) $(PROGRAM)
Index: flashrom-arch_abstraction/satasii.c
===================================================================
--- flashrom-arch_abstraction/satasii.c	(Revision 1008)
+++ flashrom-arch_abstraction/satasii.c	(Arbeitskopie)
@@ -62,7 +62,7 @@
    sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset;

/* Check if ROM cycle are OK. */
-	if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26))))
+	if ((id != 0x0680) && (!(mmio_le_readl(sii_bar) & (1 << 26))))
    	msg_pinfo("Warning: Flash seems unconnected.\n");

buses_supported = CHIP_BUSTYPE_PARALLEL;
@@ -82,32 +82,32 @@
 {
    uint32_t ctrl_reg, data_reg;

-	while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;
+	while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ;

/* Mask out unused/reserved bits, set writes and start transaction. */
    ctrl_reg &= 0xfcf80000;
    ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff);

-	data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val;
-	mmio_writel(data_reg, (sii_bar + 4));
-	mmio_writel(ctrl_reg, sii_bar);
+	data_reg = (mmio_le_readl((sii_bar + 4)) & ~0xff) | val;
+	mmio_le_writel(data_reg, (sii_bar + 4));
+	mmio_le_writel(ctrl_reg, sii_bar);

-	while (mmio_readl(sii_bar) & (1 << 25)) ;
+	while (mmio_le_readl(sii_bar) & (1 << 25)) ;
 }

uint8_t satasii_chip_readb(const chipaddr addr)
 {
    uint32_t ctrl_reg;

-	while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;
+	while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ;

/* Mask out unused/reserved bits, set reads and start transaction. */
    ctrl_reg &= 0xfcf80000;
    ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff);

-	mmio_writel(ctrl_reg, sii_bar);
+	mmio_le_writel(ctrl_reg, sii_bar);

-	while (mmio_readl(sii_bar) & (1 << 25)) ;
+	while (mmio_le_readl(sii_bar) & (1 << 25)) ;

-	return (mmio_readl(sii_bar + 4)) & 0xff;
+	return (mmio_le_readl(sii_bar + 4)) & 0xff;
 }
Index: flashrom-arch_abstraction/wbsio_spi.c
===================================================================
--- flashrom-arch_abstraction/wbsio_spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/wbsio_spi.c	(Arbeitskopie)
@@ -18,6 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include "flash.h"
 #include "chipdrivers.h"
@@ -199,3 +201,5 @@

return spi_chip_write_1(flash, buf);
 }
+
+#endif
Index: flashrom-arch_abstraction/chipset_enable.c
===================================================================
--- flashrom-arch_abstraction/chipset_enable.c	(Revision 1008)
+++ flashrom-arch_abstraction/chipset_enable.c	(Arbeitskopie)
@@ -34,6 +34,8 @@
 #include <fcntl.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 extern int ichspi_lock;

static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
@@ -1285,8 +1287,11 @@
    return 0;
 }

+#endif
+
 /* Please keep this list alphabetically sorted by vendor/device. */
 const struct penable chipset_enables[] = {
+#if defined(__i386__) || defined(__x86_64__)
    {0x10B9, 0x1533, OK, "ALi", "M1533",		enable_flash_ali_m1533},
    {0x1022, 0x7440, OK, "AMD", "AMD-768",		enable_flash_amd8111},
    {0x1022, 0x7468, OK, "AMD", "AMD8111",		enable_flash_amd8111},
@@ -1425,7 +1430,7 @@
    {0x1106, 0x0596, OK, "VIA", "VT82C596",		enable_flash_amd8111},
    {0x1106, 0x0586, OK, "VIA", "VT82C586A/B",	enable_flash_amd8111},
    {0x1106, 0x0686, NT, "VIA", "VT82C686A/B",	enable_flash_amd8111},
-
+#endif
    {},
 };

Index: flashrom-arch_abstraction/sb600spi.c
===================================================================
--- flashrom-arch_abstraction/sb600spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/sb600spi.c	(Arbeitskopie)
@@ -21,6 +21,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include "flash.h"
 #include "chipdrivers.h"
@@ -166,3 +168,5 @@

return 0;
 }
+
+#endif
Index: flashrom-arch_abstraction/flashrom.c
===================================================================
--- flashrom-arch_abstraction/flashrom.c	(Revision 1008)
+++ flashrom-arch_abstraction/flashrom.c	(Arbeitskopie)
@@ -276,6 +276,7 @@
 #endif

#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    {
    	.name			= "it87spi",
    	.init			= it87spi_init,
@@ -293,6 +294,7 @@
    	.delay			= internal_delay,
    },
 #endif
+#endif

#if FT2232_SPI_SUPPORT == 1
    {
Index: flashrom-arch_abstraction/internal.c
===================================================================
--- flashrom-arch_abstraction/internal.c	(Revision 1008)
+++ flashrom-arch_abstraction/internal.c	(Arbeitskopie)
@@ -99,10 +99,12 @@
 #endif

#if INTERNAL_SUPPORT == 1
-struct superio superio = {};
 int force_boardenable = 0;
 int force_boardmismatch = 0;

+#if defined(__i386__) || defined(__x86_64__)
+struct superio superio = {};
+
 void probe_superio(void)
 {
    superio = probe_superio_ite();
@@ -112,8 +114,9 @@
    	superio = probe_superio_winbond();
 #endif
 }
+#endif

-int is_laptop;
+int is_laptop = 0;

int internal_init(void)
 {
@@ -166,10 +169,13 @@
     * mainboard specific flash enable sequence.
     */
    coreboot_init();
+
+#if defined(__i386__) || defined(__x86_64__)
    dmi_init();

/* Probe for the Super I/O chip and fill global struct superio. */
    probe_superio();
+#endif

/* Warn if a laptop is detected. */
    if (is_laptop) {
@@ -203,8 +209,10 @@
    		 "will most likely fail.\n");
    }

+#if defined(__i386__) || defined(__x86_64__)
    /* Probe for IT87* LPC->SPI translation unconditionally. */
    it87xx_probe_spi_flash(NULL);
+#endif

board_flash_enable(lb_vendor, lb_part);

Index: flashrom-arch_abstraction/ichspi.c
===================================================================
--- flashrom-arch_abstraction/ichspi.c	(Revision 1008)
+++ flashrom-arch_abstraction/ichspi.c	(Arbeitskopie)
@@ -33,6 +33,8 @@
  *
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include "flash.h"
 #include "chipdrivers.h"
@@ -832,3 +834,5 @@
    }
    return ret;
 }
+
+#endif
Index: flashrom-arch_abstraction/print_wiki.c
===================================================================
--- flashrom-arch_abstraction/print_wiki.c	(Revision 1008)
+++ flashrom-arch_abstraction/print_wiki.c	(Arbeitskopie)
@@ -104,6 +104,7 @@
 /* Please keep these lists alphabetically ordered by vendor/board. */
 const struct board_info_url boards_url[] = {
    /* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"AX8",			"http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=Y..." },
    { "Abit",		"Fatal1ty F-I90HD",	"http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NAM..." },
    { "Advantech",		"PCM-5820", 		"http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" },
@@ -279,8 +280,10 @@
    { "VIA",		"EPIA-N/NL",		"http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&a..." }, /* EPIA-N link for now */
    { "VIA",		"EPIA SP",		"http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&a..." },
    { "VIA",		"PC3500G",		"http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp" },
+#endif

/* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"IS-10",		"http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NAM..." },
    { "ASRock",		"K7VT4A+",		"http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=" },
    { "ASUS",		"MEW-AM",		"ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/" },
@@ -298,18 +301,23 @@
    { "Sun",		"Fire x4150",		"http://www.sun.com/servers/x64/x4150/" },
    { "Sun",		"Fire x4200",		"http://www.sun.com/servers/entry/x4200/" },
    { "Sun",		"Fire x4600",		"http://www.sun.com/servers/x64/x4600/" },
+#endif

/* Verified working laptops. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire 1520",		"http://support.acer.com/us/en/acerpanam/notebook/0000/Acer/Aspire1520/Aspire..." },
    { "Lenovo",		"3000 V100 TF05Cxx",	"http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Leno..." },
+#endif

/* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One",		NULL },
    { "ASUS",		"Eee PC 701 4G",	"http://www.asus.com/product.aspx?P_ID=h6SPd3tEzLEsrEiS" },
    { "Dell",		"Latitude CPi A366XT",	"http://www.coreboot.org/Dell_Latitude_CPi_A366XT" },
    { "HP/Compaq",		"nx9010",		"http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc..." },
    { "IBM/Lenovo",		"Thinkpad T40p",	"http://www.thinkwiki.org/wiki/Category:T40p" },
    { "IBM/Lenovo",		"240",			"http://www.stanford.edu/~bresnan//tp240.html" },
+#endif

{ NULL,			NULL,			0 },
 };
@@ -317,6 +325,7 @@
 /* Please keep these lists alphabetically ordered by vendor/board. */
 const struct board_info_notes boards_notes[] = {
    /* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "ASI",		"MB-5BLMP",		"Used in the IGEL WinNET III thin client." },
    { "ASRock",		"K8S8X",		"The Super I/O isn't found on this board. See http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html." },
    { "ASUS",		"A8V-E SE",		"See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." },
@@ -324,23 +333,30 @@
    { "BCOM",		"WinNET100",		"Used in the IGEL-316 thin client." },
    { "GIGABYTE",		"GA-7ZM",		"Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option." },
    { "ASUS",		"M2N-E",		"If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html" },
+#endif

/* Verified working boards that DO need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One",		"See http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html." },
+#endif

/* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "MSI",		"MS-6178",		"Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot." },
    { "MSI",		"MS-7260 (K9N Neo)",	"Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot." },
+#endif

/* Verified working laptops. */
    /* None which need comments, yet... */

/* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One",		"http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html" },
    { "ASUS",		"Eee PC 701 4G",	"It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)." },
    { "Dell",		"Latitude CPi A366XT",	"The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop." },
    { "HP/Compaq",		"nx9010",		"Hangs upon '''flashrom -V''' (needs hard power-cycle then)." },
    { "IBM/Lenovo",		"Thinkpad T40p",	"Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later." },
+#endif

{ NULL,			NULL,			0 },
 };
Index: flashrom-arch_abstraction/print.c
===================================================================
--- flashrom-arch_abstraction/print.c	(Revision 1008)
+++ flashrom-arch_abstraction/print.c	(Arbeitskopie)
@@ -257,6 +257,7 @@
 /* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info boards_ok[] = {
    /* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"AX8", },
    { "Abit",		"Fatal1ty F-I90HD", },
    { "Advantech",		"PCM-5820", },
@@ -377,13 +378,14 @@
    { "VIA",		"pc2500e", },
    { "VIA",		"PC3500G", },
    { "VIA",		"VB700X", },
-
+#endif
    {},
 };

/* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info boards_bad[] = {
    /* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"IS-10", },
    { "ASRock",		"K7VT4A+", },
    { "ASUS",		"MEW-AM", },
@@ -401,29 +403,31 @@
    { "Sun",		"Fire x4200", },
    { "Sun",		"Fire x4540", },
    { "Sun",		"Fire x4600", },
-
+#endif
    {},
 };

/* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info laptops_ok[] = {
    /* Verified working laptops. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Lenovo",		"3000 V100 TF05Cxx", },
    { "Acer",               "Aspire 1520", },
-
+#endif
    {},
 };

/* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info laptops_bad[] = {
    /* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One", },
    { "ASUS",		"Eee PC 701 4G", },
    { "Dell",		"Latitude CPi A366XT", },
    { "HP/Compaq",		"nx9010", },
    { "IBM/Lenovo",		"Thinkpad T40p", },
    { "IBM/Lenovo",		"240", },
-
+#endif
    {},
 };
 #endif
Index: flashrom-arch_abstraction/board_enable.c
===================================================================
--- flashrom-arch_abstraction/board_enable.c	(Revision 1008)
+++ flashrom-arch_abstraction/board_enable.c	(Arbeitskopie)
@@ -28,6 +28,7 @@
 #include <fcntl.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
 /*
  * Helper functions for many Winbond Super I/Os of the W836xx range.
  */
@@ -1306,6 +1307,8 @@
    return it8712f_gpio_set(32, 1);
 }

+#endif
+
 /**
  * Below is the list of boards which need a special "board enable" code in
  * flashrom before their ROM chip can be accessed/written to.
@@ -1349,6 +1352,7 @@
 struct board_pciid_enable board_pciid_enables[] = {

/* first pci-id set [4],          second pci-id set [4],          dmi identifier coreboot id [2],             vendor name    board name       max_rom_...  OK? flash enable */
+#if defined(__i386__) || defined(__x86_64__)
    {0x10DE, 0x0547, 0x147B, 0x1C2F,  0x10DE, 0x0548, 0x147B, 0x1C2F, NULL,          NULL,         NULL,          "Abit",        "AN-M2",                 0,   NT, nvidia_mcp_gpio2_raise},
    {0x8086, 0x2926, 0x147b, 0x1084,  0x11ab, 0x4364, 0x147b, 0x1084, NULL,          NULL,         NULL,          "Abit",        "IP35",                  0,   OK, intel_ich_gpio16_raise},
    {0x8086, 0x2930, 0x147b, 0x1083,  0x10ec, 0x8167, 0x147b, 0x1083, NULL,          NULL,         NULL,          "Abit",        "IP35 Pro",              0,   OK, intel_ich_gpio16_raise},
@@ -1415,7 +1419,7 @@
    {0x1106, 0x3123, 0x1106, 0x3123,  0x1106, 0x3059, 0x1106, 0x4161, NULL,          NULL,         NULL,          "Termtek",     "TK-3370 (Rev:2.5B)",    0,   OK, w836xx_memw_enable_4e},
    {0x1106, 0x3177, 0x1106, 0xAA01,  0x1106, 0x3123, 0x1106, 0xAA01, NULL,          NULL,         NULL,          "VIA",         "EPIA M/MII/...",        0,   OK, via_vt823x_gpio15_raise},
    {0x1106, 0x0259, 0x1106, 0x3227,  0x1106, 0x3065, 0x1106, 0x3149, NULL,          NULL,         NULL,          "VIA",         "EPIA-N/NL",             0,   OK, via_vt823x_gpio9_raise},
-
+#endif
    {     0,      0,      0,      0,       0,      0,      0,      0, NULL,          NULL,         NULL,          NULL,          NULL,                    0,   NT, NULL}, /* end marker */
 };

[Carl-Daniel Hailfinger]

On 22.05.2010 23:56, Carl-Daniel Hailfinger wrote:
> On 26.03.2010 19:13, Michael Manulis wrote:
> > I tested the changes on my system.  The system is a CurtisWright Raptor
> > board with a single PowerPC 7457 processor.  It has a daughter-board from
> > TechnoBox 5575 PCI-over-PMC SATA adapter.  The daughter-board has onboard
> > BIOS (AMD flash chip) and EEPROM.
> >
> > I was able to read, write and erase both chips using satasii programmer.
> >
> > I did encounter an issue when my rootfs is mounted over NFS.  When writing
> > data back onto flash, the data came back in reverse endianness from the
> > original.  This was only an issue with NFS-mounted rootfs.  When I tested
> > the same procedure with the rootfs mounted from the internal SATA drive,
> > everything was consistent.
> > [...]
> >
> > vsm:~# ./flashrom -p satasii
> > flashrom v0.9.1-r985
> > Found "Silicon Image SiI 3512 [SATALink/SATARaid] SATA Ctrl" (1095:3512, BDF
> > 00:0a.0).
> > ===
> > This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output
> > to [e-mail] if it works for you. Thank you for your help!
> > ===
> > Mapping SATA SIL registers at 0xf0000000, unaligned size 0x100.
> > Warning: Flash seems unconnected.
> > Calibrating delay loop... OK.
> > Found chip "AMD Am29LV040B" (512 KB, Parallel) at physical address
> > 0xfff80000.
> >
> > Acked-by: Misha Manulis
> >
> > On Fri, Mar 26, 2010 at 9:42 AM, Carl-Daniel Hailfinger <
> > [e-mail]> wrote:
> > > On 26.03.2010 05:13, Carl-Daniel Hailfinger wrote:
> > > > Misha Manulis asked for satasii support on PPC and on IRC we gave him
> > > > some hints to hack up something that works for ppc only and satasii
> > > > only. His patch can be found here: http://coreboot.pastebin.com/fuLk1FCA
> > > >
> > > > Here is a patch which does everything The Right Way (TM) and uses proper
> > > > abstraction for satasii and compiles all x86 specific stuff only on x86.
> > > >
> > > > Huge thanks go to Segher Boessenkool who provided valuable info about
> > > > all the endianness trickery (especially preprocessor macros) and tested
> > > > 8 iterations of the code on Linux/PPC.
>
> All programmers except nic3com should be compilable with this new patch.
> The satasii programmer should work on PowerPC.
>
> make distclean
> make CONFIG_NIC3COM=no
>
> Please report any issues to the mailing list.

Signed-off-by: Carl-Daniel Hailfinger

Index: flashrom-arch_abstraction/hwaccess.c
===================================================================
--- flashrom-arch_abstraction/hwaccess.c	(Revision 1008)
+++ flashrom-arch_abstraction/hwaccess.c	(Arbeitskopie)
@@ -26,6 +26,12 @@
 #include <errno.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
+static inline void sync_primitive(void)
+{
+}
+
 #if defined(__FreeBSD__) || defined(__DragonFly__)
 int io_fd;
 #endif
@@ -54,19 +60,43 @@
 #endif
 }

+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+static inline void sync_primitive(void)
+{
+	asm("eieio" : : : "memory")
+}
+
+void get_io_perms(void)
+{
+}
+
+void release_io_perms(void)
+{
+}
+
+#else
+
+#error Unknown architecture
+
+#endif
+
 void mmio_writeb(uint8_t val, void *addr)
 {
    *(volatile uint8_t *) addr = val;
+	sync_primitive();
 }

void mmio_writew(uint16_t val, void *addr)
 {
    *(volatile uint16_t *) addr = val;
+	sync_primitive();
 }

void mmio_writel(uint32_t val, void *addr)
 {
    *(volatile uint32_t *) addr = val;
+	sync_primitive();
 }

uint8_t mmio_readb(void *addr)
@@ -83,3 +113,33 @@
 {
    return *(volatile uint32_t *) addr;
 }
+
+void mmio_le_writeb(uint8_t val, void *addr)
+{
+	mmio_writeb(cpu_to_le8(val), addr);
+}
+
+void mmio_le_writew(uint16_t val, void *addr)
+{
+	mmio_writew(cpu_to_le16(val), addr);
+}
+
+void mmio_le_writel(uint32_t val, void *addr)
+{
+	mmio_writel(cpu_to_le32(val), addr);
+}
+
+uint8_t mmio_le_readb(void *addr)
+{
+	return le_to_cpu8(mmio_readb(addr));
+}
+
+uint16_t mmio_le_readw(void *addr)
+{
+	return le_to_cpu16(mmio_readw(addr));
+}
+
+uint32_t mmio_le_readl(void *addr)
+{
+	return le_to_cpu32(mmio_readl(addr));
+}
Index: flashrom-arch_abstraction/flash.h
===================================================================
--- flashrom-arch_abstraction/flash.h	(Revision 1008)
+++ flashrom-arch_abstraction/flash.h	(Arbeitskopie)
@@ -63,8 +63,10 @@
    PROGRAMMER_ATAHPT,
 #endif
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    PROGRAMMER_IT87SPI,
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    PROGRAMMER_FT2232SPI,
 #endif
@@ -407,6 +409,12 @@
 uint8_t mmio_readb(void *addr);
 uint16_t mmio_readw(void *addr);
 uint32_t mmio_readl(void *addr);
+void mmio_le_writeb(uint8_t val, void *addr);
+void mmio_le_writew(uint16_t val, void *addr);
+void mmio_le_writel(uint32_t val, void *addr);
+uint8_t mmio_le_readb(void *addr);
+uint16_t mmio_le_readw(void *addr);
+uint32_t mmio_le_readl(void *addr);

/* programmer.c */
 int noop_shutdown(void);
@@ -603,6 +611,7 @@
 enum spi_controller {
    SPI_CONTROLLER_NONE,
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    SPI_CONTROLLER_ICH7,
    SPI_CONTROLLER_ICH9,
    SPI_CONTROLLER_IT87XX,
@@ -610,6 +619,7 @@
    SPI_CONTROLLER_VIA,
    SPI_CONTROLLER_WBSIO,
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    SPI_CONTROLLER_FT2232,
 #endif
Index: flashrom-arch_abstraction/spi25.c
===================================================================
--- flashrom-arch_abstraction/spi25.c	(Revision 1008)
+++ flashrom-arch_abstraction/spi25.c	(Arbeitskopie)
@@ -172,12 +172,14 @@
    /* only some SPI chipsets support 4 bytes commands */
    switch (spi_controller) {
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    case SPI_CONTROLLER_ICH7:
    case SPI_CONTROLLER_ICH9:
    case SPI_CONTROLLER_VIA:
    case SPI_CONTROLLER_SB600:
    case SPI_CONTROLLER_WBSIO:
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    case SPI_CONTROLLER_FT2232:
 #endif
@@ -996,11 +998,13 @@

switch (spi_controller) {
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    case SPI_CONTROLLER_WBSIO:
    	msg_cerr("%s: impossible with Winbond SPI masters,"
    			" degrading to byte program\n", __func__);
    	return spi_chip_write_1(flash, buf);
 #endif
+#endif
    default:
    	break;
    }
Index: flashrom-arch_abstraction/hwaccess.h
===================================================================
--- flashrom-arch_abstraction/hwaccess.h	(Revision 1008)
+++ flashrom-arch_abstraction/hwaccess.h	(Arbeitskopie)
@@ -24,13 +24,88 @@
 #ifndef __HWACCESS_H__
 #define __HWACCESS_H__ 1

+#if defined (__i386__) || defined (__x86_64__)
 #if defined(__GLIBC__)
 #include <sys/io.h>
 #endif
+#endif
+
 #if NEED_PCI == 1
 #include <pci/pci.h>
 #endif

+#define ___constant_swab8(x) ((uint8_t)(				\
+	(((uint8_t)(x) & (uint8_t)0xffU))))
+
+#define ___constant_swab16(x) ((uint16_t)(				\
+	(((uint16_t)(x) & (uint16_t)0x00ffU) << 8) |			\
+	(((uint16_t)(x) & (uint16_t)0xff00U) >> 8)))
+
+#define ___constant_swab32(x) ((uint32_t)(				\
+	(((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) |		\
+	(((uint32_t)(x) & (uint32_t)0x0000ff00UL) <<  8) |		\
+	(((uint32_t)(x) & (uint32_t)0x00ff0000UL) >>  8) |		\
+	(((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24)))
+
+#define ___constant_swab64(x) ((uint64_t)(				\
+	(((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) |	\
+	(((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) |	\
+	(((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) |	\
+	(((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) <<  8) |	\
+	(((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >>  8) |	\
+	(((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) |	\
+	(((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) |	\
+	(((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56)))
+
+#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__)
+
+#define cpu_to_le(bits)							\
+static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val)	\
+{									\
+	return ___constant_swab##bits(val);				\
+}
+
+cpu_to_le(8)
+cpu_to_le(16)
+cpu_to_le(32)
+cpu_to_le(64)
+
+#define cpu_to_be8
+#define cpu_to_be16
+#define cpu_to_be32
+#define cpu_to_be64
+
+#else
+
+#define cpu_to_be(bits)							\
+static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val)	\
+{									\
+	return ___constant_swab##bits(val);				\
+}
+
+cpu_to_be(8)
+cpu_to_be(16)
+cpu_to_be(32)
+cpu_to_be(64)
+
+#define cpu_to_le8
+#define cpu_to_le16
+#define cpu_to_le32
+#define cpu_to_le64
+
+#endif
+
+#define be_to_cpu8 cpu_to_be8
+#define be_to_cpu16 cpu_to_be16
+#define be_to_cpu32 cpu_to_be32
+#define be_to_cpu64 cpu_to_be64
+#define le_to_cpu8 cpu_to_le8
+#define le_to_cpu16 cpu_to_le16
+#define le_to_cpu32 cpu_to_le32
+#define le_to_cpu64 cpu_to_le64
+
+#if defined (__i386__) || defined (__x86_64__)
+
 /* for iopl and outb under Solaris */
 #if defined (__sun) && (defined(__i386) || defined(__amd64))
 #include <strings.h>
@@ -162,4 +237,11 @@
 int freebsd_wrmsr(int addr, msr_t msr);
 #endif

+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+/* Port I/O is not available on PowerPC. */
+
+#else
+#error Unknown architecture
+#endif
+
 #endif /* !__HWACCESS_H__ */
Index: flashrom-arch_abstraction/it87spi.c
===================================================================
--- flashrom-arch_abstraction/it87spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/it87spi.c	(Arbeitskopie)
@@ -23,6 +23,8 @@
  * Contains the ITE IT87* SPI specific routines
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include <stdlib.h>
 #include "flash.h"
@@ -351,3 +353,5 @@

return 0;
 }
+
+#endif
Index: flashrom-arch_abstraction/physmap.c
===================================================================
--- flashrom-arch_abstraction/physmap.c	(Revision 1008)
+++ flashrom-arch_abstraction/physmap.c	(Arbeitskopie)
@@ -241,6 +241,8 @@
    return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO);
 }

+#if defined(__i386__) || defined(__x86_64__)
+
 #ifdef __linux__
 /*
  * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr,
@@ -462,4 +464,6 @@
 #endif
 #endif
 #endif
-
+#else
+/* Does MSR exist on non-x86 architectures? */
+#endif
Index: flashrom-arch_abstraction/nic3com.c
===================================================================
--- flashrom-arch_abstraction/nic3com.c	(Revision 1008)
+++ flashrom-arch_abstraction/nic3com.c	(Arbeitskopie)
@@ -23,6 +23,8 @@
 #include <sys/types.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 #define BIOS_ROM_ADDR		0x04
 #define BIOS_ROM_DATA		0x08
 #define INT_STATUS		0x0e
@@ -112,3 +114,7 @@
    OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
    return INB(io_base_addr + BIOS_ROM_DATA);
 }
+
+#else
+#error Unknown architecture
+#endif
Index: flashrom-arch_abstraction/spi.c
===================================================================
--- flashrom-arch_abstraction/spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/spi.c	(Arbeitskopie)
@@ -42,6 +42,7 @@
    },

#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    { /* SPI_CONTROLLER_ICH7 */
    	.command = ich_spi_send_command,
    	.multicommand = ich_spi_send_multicommand,
@@ -84,6 +85,7 @@
    	.write_256 = wbsio_spi_write_1,
    },
 #endif
+#endif

#if FT2232_SPI_SUPPORT == 1
    { /* SPI_CONTROLLER_FT2232 */
Index: flashrom-arch_abstraction/Makefile
===================================================================
--- flashrom-arch_abstraction/Makefile	(Revision 1008)
+++ flashrom-arch_abstraction/Makefile	(Arbeitskopie)
@@ -124,7 +124,9 @@

ifeq ($(CONFIG_INTERNAL), yes)
 FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1'
-PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o
+PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o
+# FIXME: The PROGRAMMER_OBJS below should only be included on x86.
+PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o
 NEED_PCI := yes
 endif

@@ -260,7 +262,7 @@
    rm -f .dependencies .features .libdeps

dep:
-	@$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies
+	@$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies

strip: $(PROGRAM)
    $(STRIP) $(STRIP_ARGS) $(PROGRAM)
Index: flashrom-arch_abstraction/satasii.c
===================================================================
--- flashrom-arch_abstraction/satasii.c	(Revision 1008)
+++ flashrom-arch_abstraction/satasii.c	(Arbeitskopie)
@@ -62,7 +62,7 @@
    sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset;

/* Check if ROM cycle are OK. */
-	if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26))))
+	if ((id != 0x0680) && (!(mmio_le_readl(sii_bar) & (1 << 26))))
    	msg_pinfo("Warning: Flash seems unconnected.\n");

buses_supported = CHIP_BUSTYPE_PARALLEL;
@@ -82,32 +82,32 @@
 {
    uint32_t ctrl_reg, data_reg;

-	while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;
+	while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ;

/* Mask out unused/reserved bits, set writes and start transaction. */
    ctrl_reg &= 0xfcf80000;
    ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff);

-	data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val;
-	mmio_writel(data_reg, (sii_bar + 4));
-	mmio_writel(ctrl_reg, sii_bar);
+	data_reg = (mmio_le_readl((sii_bar + 4)) & ~0xff) | val;
+	mmio_le_writel(data_reg, (sii_bar + 4));
+	mmio_le_writel(ctrl_reg, sii_bar);

-	while (mmio_readl(sii_bar) & (1 << 25)) ;
+	while (mmio_le_readl(sii_bar) & (1 << 25)) ;
 }

uint8_t satasii_chip_readb(const chipaddr addr)
 {
    uint32_t ctrl_reg;

-	while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;
+	while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) ;

/* Mask out unused/reserved bits, set reads and start transaction. */
    ctrl_reg &= 0xfcf80000;
    ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff);

-	mmio_writel(ctrl_reg, sii_bar);
+	mmio_le_writel(ctrl_reg, sii_bar);

-	while (mmio_readl(sii_bar) & (1 << 25)) ;
+	while (mmio_le_readl(sii_bar) & (1 << 25)) ;

-	return (mmio_readl(sii_bar + 4)) & 0xff;
+	return (mmio_le_readl(sii_bar + 4)) & 0xff;
 }
Index: flashrom-arch_abstraction/wbsio_spi.c
===================================================================
--- flashrom-arch_abstraction/wbsio_spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/wbsio_spi.c	(Arbeitskopie)
@@ -18,6 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include "flash.h"
 #include "chipdrivers.h"
@@ -199,3 +201,5 @@

return spi_chip_write_1(flash, buf);
 }
+
+#endif
Index: flashrom-arch_abstraction/chipset_enable.c
===================================================================
--- flashrom-arch_abstraction/chipset_enable.c	(Revision 1008)
+++ flashrom-arch_abstraction/chipset_enable.c	(Arbeitskopie)
@@ -34,6 +34,8 @@
 #include <fcntl.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 extern int ichspi_lock;

static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
@@ -1285,8 +1287,11 @@
    return 0;
 }

+#endif
+
 /* Please keep this list alphabetically sorted by vendor/device. */
 const struct penable chipset_enables[] = {
+#if defined(__i386__) || defined(__x86_64__)
    {0x10B9, 0x1533, OK, "ALi", "M1533",		enable_flash_ali_m1533},
    {0x1022, 0x7440, OK, "AMD", "AMD-768",		enable_flash_amd8111},
    {0x1022, 0x7468, OK, "AMD", "AMD8111",		enable_flash_amd8111},
@@ -1425,7 +1430,7 @@
    {0x1106, 0x0596, OK, "VIA", "VT82C596",		enable_flash_amd8111},
    {0x1106, 0x0586, OK, "VIA", "VT82C586A/B",	enable_flash_amd8111},
    {0x1106, 0x0686, NT, "VIA", "VT82C686A/B",	enable_flash_amd8111},
-
+#endif
    {},
 };

Index: flashrom-arch_abstraction/sb600spi.c
===================================================================
--- flashrom-arch_abstraction/sb600spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/sb600spi.c	(Arbeitskopie)
@@ -21,6 +21,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include "flash.h"
 #include "chipdrivers.h"
@@ -166,3 +168,5 @@

return 0;
 }
+
+#endif
Index: flashrom-arch_abstraction/flashrom.c
===================================================================
--- flashrom-arch_abstraction/flashrom.c	(Revision 1008)
+++ flashrom-arch_abstraction/flashrom.c	(Arbeitskopie)
@@ -276,6 +276,7 @@
 #endif

#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    {
    	.name			= "it87spi",
    	.init			= it87spi_init,
@@ -293,6 +294,7 @@
    	.delay			= internal_delay,
    },
 #endif
+#endif

#if FT2232_SPI_SUPPORT == 1
    {
Index: flashrom-arch_abstraction/internal.c
===================================================================
--- flashrom-arch_abstraction/internal.c	(Revision 1008)
+++ flashrom-arch_abstraction/internal.c	(Arbeitskopie)
@@ -99,10 +99,12 @@
 #endif

#if INTERNAL_SUPPORT == 1
-struct superio superio = {};
 int force_boardenable = 0;
 int force_boardmismatch = 0;

+#if defined(__i386__) || defined(__x86_64__)
+struct superio superio = {};
+
 void probe_superio(void)
 {
    superio = probe_superio_ite();
@@ -112,8 +114,9 @@
    	superio = probe_superio_winbond();
 #endif
 }
+#endif

-int is_laptop;
+int is_laptop = 0;

int internal_init(void)
 {
@@ -166,10 +169,13 @@
     * mainboard specific flash enable sequence.
     */
    coreboot_init();
+
+#if defined(__i386__) || defined(__x86_64__)
    dmi_init();

/* Probe for the Super I/O chip and fill global struct superio. */
    probe_superio();
+#endif

/* Warn if a laptop is detected. */
    if (is_laptop) {
@@ -203,8 +209,10 @@
    		 "will most likely fail.\n");
    }

+#if defined(__i386__) || defined(__x86_64__)
    /* Probe for IT87* LPC->SPI translation unconditionally. */
    it87xx_probe_spi_flash(NULL);
+#endif

board_flash_enable(lb_vendor, lb_part);

Index: flashrom-arch_abstraction/ichspi.c
===================================================================
--- flashrom-arch_abstraction/ichspi.c	(Revision 1008)
+++ flashrom-arch_abstraction/ichspi.c	(Arbeitskopie)
@@ -33,6 +33,8 @@
  *
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include "flash.h"
 #include "chipdrivers.h"
@@ -832,3 +834,5 @@
    }
    return ret;
 }
+
+#endif
Index: flashrom-arch_abstraction/print_wiki.c
===================================================================
--- flashrom-arch_abstraction/print_wiki.c	(Revision 1008)
+++ flashrom-arch_abstraction/print_wiki.c	(Arbeitskopie)
@@ -104,6 +104,7 @@
 /* Please keep these lists alphabetically ordered by vendor/board. */
 const struct board_info_url boards_url[] = {
    /* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"AX8",			"http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=Y..." },
    { "Abit",		"Fatal1ty F-I90HD",	"http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NAM..." },
    { "Advantech",		"PCM-5820", 		"http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" },
@@ -279,8 +280,10 @@
    { "VIA",		"EPIA-N/NL",		"http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&a..." }, /* EPIA-N link for now */
    { "VIA",		"EPIA SP",		"http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&a..." },
    { "VIA",		"PC3500G",		"http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp" },
+#endif

/* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"IS-10",		"http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NAM..." },
    { "ASRock",		"K7VT4A+",		"http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=" },
    { "ASUS",		"MEW-AM",		"ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/" },
@@ -298,18 +301,23 @@
    { "Sun",		"Fire x4150",		"http://www.sun.com/servers/x64/x4150/" },
    { "Sun",		"Fire x4200",		"http://www.sun.com/servers/entry/x4200/" },
    { "Sun",		"Fire x4600",		"http://www.sun.com/servers/x64/x4600/" },
+#endif

/* Verified working laptops. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire 1520",		"http://support.acer.com/us/en/acerpanam/notebook/0000/Acer/Aspire1520/Aspire..." },
    { "Lenovo",		"3000 V100 TF05Cxx",	"http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Leno..." },
+#endif

/* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One",		NULL },
    { "ASUS",		"Eee PC 701 4G",	"http://www.asus.com/product.aspx?P_ID=h6SPd3tEzLEsrEiS" },
    { "Dell",		"Latitude CPi A366XT",	"http://www.coreboot.org/Dell_Latitude_CPi_A366XT" },
    { "HP/Compaq",		"nx9010",		"http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc..." },
    { "IBM/Lenovo",		"Thinkpad T40p",	"http://www.thinkwiki.org/wiki/Category:T40p" },
    { "IBM/Lenovo",		"240",			"http://www.stanford.edu/~bresnan//tp240.html" },
+#endif

{ NULL,			NULL,			0 },
 };
@@ -317,6 +325,7 @@
 /* Please keep these lists alphabetically ordered by vendor/board. */
 const struct board_info_notes boards_notes[] = {
    /* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "ASI",		"MB-5BLMP",		"Used in the IGEL WinNET III thin client." },
    { "ASRock",		"K8S8X",		"The Super I/O isn't found on this board. See http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html." },
    { "ASUS",		"A8V-E SE",		"See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." },
@@ -324,23 +333,30 @@
    { "BCOM",		"WinNET100",		"Used in the IGEL-316 thin client." },
    { "GIGABYTE",		"GA-7ZM",		"Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option." },
    { "ASUS",		"M2N-E",		"If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html" },
+#endif

/* Verified working boards that DO need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One",		"See http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html." },
+#endif

/* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "MSI",		"MS-6178",		"Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot." },
    { "MSI",		"MS-7260 (K9N Neo)",	"Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot." },
+#endif

/* Verified working laptops. */
    /* None which need comments, yet... */

/* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One",		"http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html" },
    { "ASUS",		"Eee PC 701 4G",	"It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)." },
    { "Dell",		"Latitude CPi A366XT",	"The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop." },
    { "HP/Compaq",		"nx9010",		"Hangs upon '''flashrom -V''' (needs hard power-cycle then)." },
    { "IBM/Lenovo",		"Thinkpad T40p",	"Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later." },
+#endif

{ NULL,			NULL,			0 },
 };
Index: flashrom-arch_abstraction/print.c
===================================================================
--- flashrom-arch_abstraction/print.c	(Revision 1008)
+++ flashrom-arch_abstraction/print.c	(Arbeitskopie)
@@ -257,6 +257,7 @@
 /* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info boards_ok[] = {
    /* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"AX8", },
    { "Abit",		"Fatal1ty F-I90HD", },
    { "Advantech",		"PCM-5820", },
@@ -377,13 +378,14 @@
    { "VIA",		"pc2500e", },
    { "VIA",		"PC3500G", },
    { "VIA",		"VB700X", },
-
+#endif
    {},
 };

/* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info boards_bad[] = {
    /* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"IS-10", },
    { "ASRock",		"K7VT4A+", },
    { "ASUS",		"MEW-AM", },
@@ -401,29 +403,31 @@
    { "Sun",		"Fire x4200", },
    { "Sun",		"Fire x4540", },
    { "Sun",		"Fire x4600", },
-
+#endif
    {},
 };

/* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info laptops_ok[] = {
    /* Verified working laptops. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Lenovo",		"3000 V100 TF05Cxx", },
    { "Acer",               "Aspire 1520", },
-
+#endif
    {},
 };

/* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info laptops_bad[] = {
    /* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One", },
    { "ASUS",		"Eee PC 701 4G", },
    { "Dell",		"Latitude CPi A366XT", },
    { "HP/Compaq",		"nx9010", },
    { "IBM/Lenovo",		"Thinkpad T40p", },
    { "IBM/Lenovo",		"240", },
-
+#endif
    {},
 };
 #endif
Index: flashrom-arch_abstraction/board_enable.c
===================================================================
--- flashrom-arch_abstraction/board_enable.c	(Revision 1008)
+++ flashrom-arch_abstraction/board_enable.c	(Arbeitskopie)
@@ -28,6 +28,7 @@
 #include <fcntl.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
 /*
  * Helper functions for many Winbond Super I/Os of the W836xx range.
  */
@@ -1306,6 +1307,8 @@
    return it8712f_gpio_set(32, 1);
 }

+#endif
+
 /**
  * Below is the list of boards which need a special "board enable" code in
  * flashrom before their ROM chip can be accessed/written to.
@@ -1349,6 +1352,7 @@
 struct board_pciid_enable board_pciid_enables[] = {

/* first pci-id set [4],          second pci-id set [4],          dmi identifier coreboot id [2],             vendor name    board name       max_rom_...  OK? flash enable */
+#if defined(__i386__) || defined(__x86_64__)
    {0x10DE, 0x0547, 0x147B, 0x1C2F,  0x10DE, 0x0548, 0x147B, 0x1C2F, NULL,          NULL,         NULL,          "Abit",        "AN-M2",                 0,   NT, nvidia_mcp_gpio2_raise},
    {0x8086, 0x2926, 0x147b, 0x1084,  0x11ab, 0x4364, 0x147b, 0x1084, NULL,          NULL,         NULL,          "Abit",        "IP35",                  0,   OK, intel_ich_gpio16_raise},
    {0x8086, 0x2930, 0x147b, 0x1083,  0x10ec, 0x8167, 0x147b, 0x1083, NULL,          NULL,         NULL,          "Abit",        "IP35 Pro",              0,   OK, intel_ich_gpio16_raise},
@@ -1415,7 +1419,7 @@
    {0x1106, 0x3123, 0x1106, 0x3123,  0x1106, 0x3059, 0x1106, 0x4161, NULL,          NULL,         NULL,          "Termtek",     "TK-3370 (Rev:2.5B)",    0,   OK, w836xx_memw_enable_4e},
    {0x1106, 0x3177, 0x1106, 0xAA01,  0x1106, 0x3123, 0x1106, 0xAA01, NULL,          NULL,         NULL,          "VIA",         "EPIA M/MII/...",        0,   OK, via_vt823x_gpio15_raise},
    {0x1106, 0x0259, 0x1106, 0x3227,  0x1106, 0x3065, 0x1106, 0x3149, NULL,          NULL,         NULL,          "VIA",         "EPIA-N/NL",             0,   OK, via_vt823x_gpio9_raise},
-
+#endif
    {     0,      0,      0,      0,       0,      0,      0,      0, NULL,          NULL,         NULL,          NULL,          NULL,                    0,   NT, NULL}, /* end marker */
 };

[Carl-Daniel Hailfinger]

New patch.

Handle the following architectures in generic flashrom code:
- x86/x86_64 (little endian)
- PowerPC (big endian)
- MIPS (big+little endian)

No changes to programmer specific code. This means any drivers with MMIO
access will _not_ suddenly start working on big endian systems, but with
this patch everything is in place to fix them.

Compilation should work on all architectures listed above for all
drivers except nic3com which requires x86 for now.

To compile without nic3com, run
make distclean
make CONFIG_NIC3COM=no

Signed-off-by: Carl-Daniel Hailfinger

Index: flashrom-arch_abstraction/hwaccess.c
===================================================================
--- flashrom-arch_abstraction/hwaccess.c	(Revision 1008)
+++ flashrom-arch_abstraction/hwaccess.c	(Arbeitskopie)
@@ -26,6 +26,12 @@
 #include <errno.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
+static inline void sync_primitive(void)
+{
+}
+
 #if defined(__FreeBSD__) || defined(__DragonFly__)
 int io_fd;
 #endif
@@ -54,19 +60,58 @@
 #endif
 }

+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+static inline void sync_primitive(void)
+{
+	asm("eieio" : : : "memory")
+}
+
+void get_io_perms(void)
+{
+}
+
+void release_io_perms(void)
+{
+}
+
+#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
+
+/* Not sure about the sync primitive. */
+static inline void sync_primitive(void)
+{
+}
+
+void get_io_perms(void)
+{
+}
+
+void release_io_perms(void)
+{
+}
+
+#else
+
+#error Unknown architecture
+
+#endif
+
 void mmio_writeb(uint8_t val, void *addr)
 {
    *(volatile uint8_t *) addr = val;
+	sync_primitive();
 }

void mmio_writew(uint16_t val, void *addr)
 {
    *(volatile uint16_t *) addr = val;
+	sync_primitive();
 }

void mmio_writel(uint32_t val, void *addr)
 {
    *(volatile uint32_t *) addr = val;
+	sync_primitive();
 }

uint8_t mmio_readb(void *addr)
@@ -83,3 +128,33 @@
 {
    return *(volatile uint32_t *) addr;
 }
+
+void mmio_le_writeb(uint8_t val, void *addr)
+{
+	mmio_writeb(cpu_to_le8(val), addr);
+}
+
+void mmio_le_writew(uint16_t val, void *addr)
+{
+	mmio_writew(cpu_to_le16(val), addr);
+}
+
+void mmio_le_writel(uint32_t val, void *addr)
+{
+	mmio_writel(cpu_to_le32(val), addr);
+}
+
+uint8_t mmio_le_readb(void *addr)
+{
+	return le_to_cpu8(mmio_readb(addr));
+}
+
+uint16_t mmio_le_readw(void *addr)
+{
+	return le_to_cpu16(mmio_readw(addr));
+}
+
+uint32_t mmio_le_readl(void *addr)
+{
+	return le_to_cpu32(mmio_readl(addr));
+}
Index: flashrom-arch_abstraction/flash.h
===================================================================
--- flashrom-arch_abstraction/flash.h	(Revision 1008)
+++ flashrom-arch_abstraction/flash.h	(Arbeitskopie)
@@ -63,8 +63,10 @@
    PROGRAMMER_ATAHPT,
 #endif
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    PROGRAMMER_IT87SPI,
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    PROGRAMMER_FT2232SPI,
 #endif
@@ -407,6 +409,12 @@
 uint8_t mmio_readb(void *addr);
 uint16_t mmio_readw(void *addr);
 uint32_t mmio_readl(void *addr);
+void mmio_le_writeb(uint8_t val, void *addr);
+void mmio_le_writew(uint16_t val, void *addr);
+void mmio_le_writel(uint32_t val, void *addr);
+uint8_t mmio_le_readb(void *addr);
+uint16_t mmio_le_readw(void *addr);
+uint32_t mmio_le_readl(void *addr);

/* programmer.c */
 int noop_shutdown(void);
@@ -603,6 +611,7 @@
 enum spi_controller {
    SPI_CONTROLLER_NONE,
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    SPI_CONTROLLER_ICH7,
    SPI_CONTROLLER_ICH9,
    SPI_CONTROLLER_IT87XX,
@@ -610,6 +619,7 @@
    SPI_CONTROLLER_VIA,
    SPI_CONTROLLER_WBSIO,
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    SPI_CONTROLLER_FT2232,
 #endif
Index: flashrom-arch_abstraction/spi25.c
===================================================================
--- flashrom-arch_abstraction/spi25.c	(Revision 1008)
+++ flashrom-arch_abstraction/spi25.c	(Arbeitskopie)
@@ -172,12 +172,14 @@
    /* only some SPI chipsets support 4 bytes commands */
    switch (spi_controller) {
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    case SPI_CONTROLLER_ICH7:
    case SPI_CONTROLLER_ICH9:
    case SPI_CONTROLLER_VIA:
    case SPI_CONTROLLER_SB600:
    case SPI_CONTROLLER_WBSIO:
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    case SPI_CONTROLLER_FT2232:
 #endif
@@ -996,11 +998,13 @@

switch (spi_controller) {
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    case SPI_CONTROLLER_WBSIO:
    	msg_cerr("%s: impossible with Winbond SPI masters,"
    			" degrading to byte program\n", __func__);
    	return spi_chip_write_1(flash, buf);
 #endif
+#endif
    default:
    	break;
    }
Index: flashrom-arch_abstraction/hwaccess.h
===================================================================
--- flashrom-arch_abstraction/hwaccess.h	(Revision 1008)
+++ flashrom-arch_abstraction/hwaccess.h	(Arbeitskopie)
@@ -24,13 +24,137 @@
 #ifndef __HWACCESS_H__
 #define __HWACCESS_H__ 1

+#if defined (__i386__) || defined (__x86_64__)
 #if defined(__GLIBC__)
 #include <sys/io.h>
 #endif
+#endif
+
 #if NEED_PCI == 1
 #include <pci/pci.h>
 #endif

+#if defined (__i386__) || defined (__x86_64__)
+
+/* All x86 is little-endian. */
+#define __FLASHROM_LITTLE_ENDIAN__ 1
+
+#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
+
+/* MIPS can be either endian. */
+#if defined (__MIPSEL) || defined (__MIPSEL__) || defined (_MIPSEL) || defined (MIPSEL)
+#define __FLASHROM_LITTLE_ENDIAN__ 1
+#elif defined (__MIPSEB) || defined (__MIPSEB__) || defined (_MIPSEB) || defined (MIPSEB)
+#define __FLASHROM_BIG_ENDIAN__ 1
+#endif
+
+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+/* PowerPC can be either endian. */
+#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__)
+#define __FLASHROM_BIG_ENDIAN__ 1
+/* Error checking in case some weird header has #defines for LE as well. */
+#if defined (_LITTLE_ENDIAN) || defined (__LITTLE_ENDIAN__)
+#error Conflicting endianness #define
+#endif
+#else
+#error Little-endian PowerPC #defines are unknown
+#endif
+
+#endif
+
+#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__)
+/* Nonstandard libc-specific macros for determining endianness. */
+#if defined(__GLIBC__)
+#include <endian.h>
+#if BYTE_ORDER == LITTLE_ENDIAN
+#define __FLASHROM_LITTLE_ENDIAN__ 1
+#elif BYTE_ORDER == BIG_ENDIAN
+#define __FLASHROM_BIG_ENDIAN__ 1
+#endif
+#endif
+#endif
+
+#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__)
+#error Can not determine endianness. Please add support for your arch or libc.
+#endif
+
+#define ___constant_swab8(x) ((uint8_t)(				\
+	(((uint8_t)(x) & (uint8_t)0xffU))))
+
+#define ___constant_swab16(x) ((uint16_t)(				\
+	(((uint16_t)(x) & (uint16_t)0x00ffU) << 8) |			\
+	(((uint16_t)(x) & (uint16_t)0xff00U) >> 8)))
+
+#define ___constant_swab32(x) ((uint32_t)(				\
+	(((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) |		\
+	(((uint32_t)(x) & (uint32_t)0x0000ff00UL) <<  8) |		\
+	(((uint32_t)(x) & (uint32_t)0x00ff0000UL) >>  8) |		\
+	(((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24)))
+
+#define ___constant_swab64(x) ((uint64_t)(				\
+	(((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) |	\
+	(((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) |	\
+	(((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) |	\
+	(((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) <<  8) |	\
+	(((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >>  8) |	\
+	(((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) |	\
+	(((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) |	\
+	(((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56)))
+
+#if defined (__FLASHROM_BIG_ENDIAN__)
+
+#define cpu_to_le(bits)							\
+static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val)	\
+{									\
+	return ___constant_swab##bits(val);				\
+}
+
+cpu_to_le(8)
+cpu_to_le(16)
+cpu_to_le(32)
+cpu_to_le(64)
+
+#define cpu_to_be8
+#define cpu_to_be16
+#define cpu_to_be32
+#define cpu_to_be64
+
+#elif defined (__FLASHROM_LITTLE_ENDIAN__)
+
+#define cpu_to_be(bits)							\
+static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val)	\
+{									\
+	return ___constant_swab##bits(val);				\
+}
+
+cpu_to_be(8)
+cpu_to_be(16)
+cpu_to_be(32)
+cpu_to_be(64)
+
+#define cpu_to_le8
+#define cpu_to_le16
+#define cpu_to_le32
+#define cpu_to_le64
+
+#else
+
+#error Could not determine endianness.
+
+#endif
+
+#define be_to_cpu8 cpu_to_be8
+#define be_to_cpu16 cpu_to_be16
+#define be_to_cpu32 cpu_to_be32
+#define be_to_cpu64 cpu_to_be64
+#define le_to_cpu8 cpu_to_le8
+#define le_to_cpu16 cpu_to_le16
+#define le_to_cpu32 cpu_to_le32
+#define le_to_cpu64 cpu_to_le64
+
+#if defined (__i386__) || defined (__x86_64__)
+
 /* for iopl and outb under Solaris */
 #if defined (__sun) && (defined(__i386) || defined(__amd64))
 #include <strings.h>
@@ -162,4 +286,18 @@
 int freebsd_wrmsr(int addr, msr_t msr);
 #endif

+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+/* Port I/O is not available on PowerPC. */
+
+#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
+
+/* Port I/O is not available on MIPS. */
+
+#else
+
+#error Unknown architecture, please check if it supports port IO.
+
+#endif
+
 #endif /* !__HWACCESS_H__ */
Index: flashrom-arch_abstraction/it87spi.c
===================================================================
--- flashrom-arch_abstraction/it87spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/it87spi.c	(Arbeitskopie)
@@ -23,6 +23,8 @@
  * Contains the ITE IT87* SPI specific routines
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include <stdlib.h>
 #include "flash.h"
@@ -351,3 +353,5 @@

return 0;
 }
+
+#endif
Index: flashrom-arch_abstraction/physmap.c
===================================================================
--- flashrom-arch_abstraction/physmap.c	(Revision 1008)
+++ flashrom-arch_abstraction/physmap.c	(Arbeitskopie)
@@ -241,6 +241,8 @@
    return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO);
 }

+#if defined(__i386__) || defined(__x86_64__)
+
 #ifdef __linux__
 /*
  * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr,
@@ -462,4 +464,6 @@
 #endif
 #endif
 #endif
-
+#else
+/* Does MSR exist on non-x86 architectures? */
+#endif
Index: flashrom-arch_abstraction/spi.c
===================================================================
--- flashrom-arch_abstraction/spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/spi.c	(Arbeitskopie)
@@ -42,6 +42,7 @@
    },

#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    { /* SPI_CONTROLLER_ICH7 */
    	.command = ich_spi_send_command,
    	.multicommand = ich_spi_send_multicommand,
@@ -84,6 +85,7 @@
    	.write_256 = wbsio_spi_write_1,
    },
 #endif
+#endif

#if FT2232_SPI_SUPPORT == 1
    { /* SPI_CONTROLLER_FT2232 */
Index: flashrom-arch_abstraction/nic3com.c
===================================================================
--- flashrom-arch_abstraction/nic3com.c	(Revision 1008)
+++ flashrom-arch_abstraction/nic3com.c	(Arbeitskopie)
@@ -23,6 +23,8 @@
 #include <sys/types.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 #define BIOS_ROM_ADDR		0x04
 #define BIOS_ROM_DATA		0x08
 #define INT_STATUS		0x0e
@@ -112,3 +114,7 @@
    OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
    return INB(io_base_addr + BIOS_ROM_DATA);
 }
+
+#else
+#error Unsupported architecture for nic3com. You need a way to emulate port IO access.
+#endif
Index: flashrom-arch_abstraction/Makefile
===================================================================
--- flashrom-arch_abstraction/Makefile	(Revision 1008)
+++ flashrom-arch_abstraction/Makefile	(Arbeitskopie)
@@ -124,7 +124,9 @@

ifeq ($(CONFIG_INTERNAL), yes)
 FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1'
-PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o
+PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o
+# FIXME: The PROGRAMMER_OBJS below should only be included on x86.
+PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o
 NEED_PCI := yes
 endif

@@ -260,7 +262,7 @@
    rm -f .dependencies .features .libdeps

dep:
-	@$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies
+	@$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies

strip: $(PROGRAM)
    $(STRIP) $(STRIP_ARGS) $(PROGRAM)
Index: flashrom-arch_abstraction/wbsio_spi.c
===================================================================
--- flashrom-arch_abstraction/wbsio_spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/wbsio_spi.c	(Arbeitskopie)
@@ -18,6 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include "flash.h"
 #include "chipdrivers.h"
@@ -199,3 +201,5 @@

return spi_chip_write_1(flash, buf);
 }
+
+#endif
Index: flashrom-arch_abstraction/chipset_enable.c
===================================================================
--- flashrom-arch_abstraction/chipset_enable.c	(Revision 1008)
+++ flashrom-arch_abstraction/chipset_enable.c	(Arbeitskopie)
@@ -34,6 +34,8 @@
 #include <fcntl.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 extern int ichspi_lock;

static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
@@ -1285,8 +1287,11 @@
    return 0;
 }

+#endif
+
 /* Please keep this list alphabetically sorted by vendor/device. */
 const struct penable chipset_enables[] = {
+#if defined(__i386__) || defined(__x86_64__)
    {0x10B9, 0x1533, OK, "ALi", "M1533",		enable_flash_ali_m1533},
    {0x1022, 0x7440, OK, "AMD", "AMD-768",		enable_flash_amd8111},
    {0x1022, 0x7468, OK, "AMD", "AMD8111",		enable_flash_amd8111},
@@ -1425,7 +1430,7 @@
    {0x1106, 0x0596, OK, "VIA", "VT82C596",		enable_flash_amd8111},
    {0x1106, 0x0586, OK, "VIA", "VT82C586A/B",	enable_flash_amd8111},
    {0x1106, 0x0686, NT, "VIA", "VT82C686A/B",	enable_flash_amd8111},
-
+#endif
    {},
 };

Index: flashrom-arch_abstraction/sb600spi.c
===================================================================
--- flashrom-arch_abstraction/sb600spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/sb600spi.c	(Arbeitskopie)
@@ -21,6 +21,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include "flash.h"
 #include "chipdrivers.h"
@@ -166,3 +168,5 @@

return 0;
 }
+
+#endif
Index: flashrom-arch_abstraction/flashrom.c
===================================================================
--- flashrom-arch_abstraction/flashrom.c	(Revision 1008)
+++ flashrom-arch_abstraction/flashrom.c	(Arbeitskopie)
@@ -276,6 +276,7 @@
 #endif

#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    {
    	.name			= "it87spi",
    	.init			= it87spi_init,
@@ -293,6 +294,7 @@
    	.delay			= internal_delay,
    },
 #endif
+#endif

#if FT2232_SPI_SUPPORT == 1
    {
Index: flashrom-arch_abstraction/internal.c
===================================================================
--- flashrom-arch_abstraction/internal.c	(Revision 1008)
+++ flashrom-arch_abstraction/internal.c	(Arbeitskopie)
@@ -99,10 +99,12 @@
 #endif

#if INTERNAL_SUPPORT == 1
-struct superio superio = {};
 int force_boardenable = 0;
 int force_boardmismatch = 0;

+#if defined(__i386__) || defined(__x86_64__)
+struct superio superio = {};
+
 void probe_superio(void)
 {
    superio = probe_superio_ite();
@@ -112,8 +114,9 @@
    	superio = probe_superio_winbond();
 #endif
 }
+#endif

-int is_laptop;
+int is_laptop = 0;

int internal_init(void)
 {
@@ -166,10 +169,13 @@
     * mainboard specific flash enable sequence.
     */
    coreboot_init();
+
+#if defined(__i386__) || defined(__x86_64__)
    dmi_init();

/* Probe for the Super I/O chip and fill global struct superio. */
    probe_superio();
+#endif

/* Warn if a laptop is detected. */
    if (is_laptop) {
@@ -203,8 +209,10 @@
    		 "will most likely fail.\n");
    }

+#if defined(__i386__) || defined(__x86_64__)
    /* Probe for IT87* LPC->SPI translation unconditionally. */
    it87xx_probe_spi_flash(NULL);
+#endif

board_flash_enable(lb_vendor, lb_part);

Index: flashrom-arch_abstraction/ichspi.c
===================================================================
--- flashrom-arch_abstraction/ichspi.c	(Revision 1008)
+++ flashrom-arch_abstraction/ichspi.c	(Arbeitskopie)
@@ -33,6 +33,8 @@
  *
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include "flash.h"
 #include "chipdrivers.h"
@@ -832,3 +834,5 @@
    }
    return ret;
 }
+
+#endif
Index: flashrom-arch_abstraction/print_wiki.c
===================================================================
--- flashrom-arch_abstraction/print_wiki.c	(Revision 1008)
+++ flashrom-arch_abstraction/print_wiki.c	(Arbeitskopie)
@@ -104,6 +104,7 @@
 /* Please keep these lists alphabetically ordered by vendor/board. */
 const struct board_info_url boards_url[] = {
    /* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"AX8",			"http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=Y..." },
    { "Abit",		"Fatal1ty F-I90HD",	"http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NAM..." },
    { "Advantech",		"PCM-5820", 		"http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" },
@@ -279,8 +280,10 @@
    { "VIA",		"EPIA-N/NL",		"http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&a..." }, /* EPIA-N link for now */
    { "VIA",		"EPIA SP",		"http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&a..." },
    { "VIA",		"PC3500G",		"http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp" },
+#endif

/* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"IS-10",		"http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NAM..." },
    { "ASRock",		"K7VT4A+",		"http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=" },
    { "ASUS",		"MEW-AM",		"ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/" },
@@ -298,18 +301,23 @@
    { "Sun",		"Fire x4150",		"http://www.sun.com/servers/x64/x4150/" },
    { "Sun",		"Fire x4200",		"http://www.sun.com/servers/entry/x4200/" },
    { "Sun",		"Fire x4600",		"http://www.sun.com/servers/x64/x4600/" },
+#endif

/* Verified working laptops. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire 1520",		"http://support.acer.com/us/en/acerpanam/notebook/0000/Acer/Aspire1520/Aspire..." },
    { "Lenovo",		"3000 V100 TF05Cxx",	"http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Leno..." },
+#endif

/* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One",		NULL },
    { "ASUS",		"Eee PC 701 4G",	"http://www.asus.com/product.aspx?P_ID=h6SPd3tEzLEsrEiS" },
    { "Dell",		"Latitude CPi A366XT",	"http://www.coreboot.org/Dell_Latitude_CPi_A366XT" },
    { "HP/Compaq",		"nx9010",		"http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc..." },
    { "IBM/Lenovo",		"Thinkpad T40p",	"http://www.thinkwiki.org/wiki/Category:T40p" },
    { "IBM/Lenovo",		"240",			"http://www.stanford.edu/~bresnan//tp240.html" },
+#endif

{ NULL,			NULL,			0 },
 };
@@ -317,6 +325,7 @@
 /* Please keep these lists alphabetically ordered by vendor/board. */
 const struct board_info_notes boards_notes[] = {
    /* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "ASI",		"MB-5BLMP",		"Used in the IGEL WinNET III thin client." },
    { "ASRock",		"K8S8X",		"The Super I/O isn't found on this board. See http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html." },
    { "ASUS",		"A8V-E SE",		"See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." },
@@ -324,23 +333,30 @@
    { "BCOM",		"WinNET100",		"Used in the IGEL-316 thin client." },
    { "GIGABYTE",		"GA-7ZM",		"Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option." },
    { "ASUS",		"M2N-E",		"If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html" },
+#endif

/* Verified working boards that DO need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One",		"See http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html." },
+#endif

/* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "MSI",		"MS-6178",		"Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot." },
    { "MSI",		"MS-7260 (K9N Neo)",	"Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot." },
+#endif

/* Verified working laptops. */
    /* None which need comments, yet... */

/* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One",		"http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html" },
    { "ASUS",		"Eee PC 701 4G",	"It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)." },
    { "Dell",		"Latitude CPi A366XT",	"The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop." },
    { "HP/Compaq",		"nx9010",		"Hangs upon '''flashrom -V''' (needs hard power-cycle then)." },
    { "IBM/Lenovo",		"Thinkpad T40p",	"Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later." },
+#endif

{ NULL,			NULL,			0 },
 };
Index: flashrom-arch_abstraction/print.c
===================================================================
--- flashrom-arch_abstraction/print.c	(Revision 1008)
+++ flashrom-arch_abstraction/print.c	(Arbeitskopie)
@@ -257,6 +257,7 @@
 /* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info boards_ok[] = {
    /* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"AX8", },
    { "Abit",		"Fatal1ty F-I90HD", },
    { "Advantech",		"PCM-5820", },
@@ -377,13 +378,14 @@
    { "VIA",		"pc2500e", },
    { "VIA",		"PC3500G", },
    { "VIA",		"VB700X", },
-
+#endif
    {},
 };

/* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info boards_bad[] = {
    /* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"IS-10", },
    { "ASRock",		"K7VT4A+", },
    { "ASUS",		"MEW-AM", },
@@ -401,29 +403,31 @@
    { "Sun",		"Fire x4200", },
    { "Sun",		"Fire x4540", },
    { "Sun",		"Fire x4600", },
-
+#endif
    {},
 };

/* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info laptops_ok[] = {
    /* Verified working laptops. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Lenovo",		"3000 V100 TF05Cxx", },
    { "Acer",               "Aspire 1520", },
-
+#endif
    {},
 };

/* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info laptops_bad[] = {
    /* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One", },
    { "ASUS",		"Eee PC 701 4G", },
    { "Dell",		"Latitude CPi A366XT", },
    { "HP/Compaq",		"nx9010", },
    { "IBM/Lenovo",		"Thinkpad T40p", },
    { "IBM/Lenovo",		"240", },
-
+#endif
    {},
 };
 #endif
Index: flashrom-arch_abstraction/board_enable.c
===================================================================
--- flashrom-arch_abstraction/board_enable.c	(Revision 1008)
+++ flashrom-arch_abstraction/board_enable.c	(Arbeitskopie)
@@ -28,6 +28,7 @@
 #include <fcntl.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
 /*
  * Helper functions for many Winbond Super I/Os of the W836xx range.
  */
@@ -1306,6 +1307,8 @@
    return it8712f_gpio_set(32, 1);
 }

+#endif
+
 /**
  * Below is the list of boards which need a special "board enable" code in
  * flashrom before their ROM chip can be accessed/written to.
@@ -1349,6 +1352,7 @@
 struct board_pciid_enable board_pciid_enables[] = {

/* first pci-id set [4],          second pci-id set [4],          dmi identifier coreboot id [2],             vendor name    board name       max_rom_...  OK? flash enable */
+#if defined(__i386__) || defined(__x86_64__)
    {0x10DE, 0x0547, 0x147B, 0x1C2F,  0x10DE, 0x0548, 0x147B, 0x1C2F, NULL,          NULL,         NULL,          "Abit",        "AN-M2",                 0,   NT, nvidia_mcp_gpio2_raise},
    {0x8086, 0x2926, 0x147b, 0x1084,  0x11ab, 0x4364, 0x147b, 0x1084, NULL,          NULL,         NULL,          "Abit",        "IP35",                  0,   OK, intel_ich_gpio16_raise},
    {0x8086, 0x2930, 0x147b, 0x1083,  0x10ec, 0x8167, 0x147b, 0x1083, NULL,          NULL,         NULL,          "Abit",        "IP35 Pro",              0,   OK, intel_ich_gpio16_raise},
@@ -1415,7 +1419,7 @@
    {0x1106, 0x3123, 0x1106, 0x3123,  0x1106, 0x3059, 0x1106, 0x4161, NULL,          NULL,         NULL,          "Termtek",     "TK-3370 (Rev:2.5B)",    0,   OK, w836xx_memw_enable_4e},
    {0x1106, 0x3177, 0x1106, 0xAA01,  0x1106, 0x3123, 0x1106, 0xAA01, NULL,          NULL,         NULL,          "VIA",         "EPIA M/MII/...",        0,   OK, via_vt823x_gpio15_raise},
    {0x1106, 0x0259, 0x1106, 0x3227,  0x1106, 0x3065, 0x1106, 0x3149, NULL,          NULL,         NULL,          "VIA",         "EPIA-N/NL",             0,   OK, via_vt823x_gpio9_raise},
-
+#endif
    {     0,      0,      0,      0,       0,      0,      0,      0, NULL,          NULL,         NULL,          NULL,          NULL,                    0,   NT, NULL}, /* end marker */
 };

[Carl-Daniel Hailfinger]

Segher: I'd appreciate if you could take a look and ack it if this looks
OK from a PowerPC perspective.

Handle the following architectures in generic flashrom code:
- x86/x86_64 (little endian)
- PowerPC (big endian)
- MIPS (big+little endian)

No changes to programmer specific code. This means any drivers with MMIO
access will _not_ suddenly start working on big endian systems, but with
this patch everything is in place to fix them.

Compilation should work on all architectures listed above for all
drivers except nic3com and nicrealtek which require PCI Port IO which is
x86-only for now.

To compile without nic3com and nicrealtek, run
make distclean
make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no

Signed-off-by: Carl-Daniel Hailfinger

Index: flashrom-arch_abstraction/hwaccess.c
===================================================================
--- flashrom-arch_abstraction/hwaccess.c	(Revision 1008)
+++ flashrom-arch_abstraction/hwaccess.c	(Arbeitskopie)
@@ -26,6 +26,12 @@
 #include <errno.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
+static inline void sync_primitive(void)
+{
+}
+
 #if defined(__FreeBSD__) || defined(__DragonFly__)
 int io_fd;
 #endif
@@ -54,19 +60,62 @@
 #endif
 }

+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+static inline void sync_primitive(void)
+{
+	asm("eieio" : : : "memory")
+}
+
+/* PCI port I/O is not yet implemented on PowerPC. */
+void get_io_perms(void)
+{
+}
+
+/* PCI port I/O is not yet implemented on PowerPC. */
+void release_io_perms(void)
+{
+}
+
+#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
+
+/* Not sure about the sync primitive. */
+static inline void sync_primitive(void)
+{
+}
+
+/* PCI port I/O is not yet implemented on MIPS. */
+void get_io_perms(void)
+{
+}
+
+/* PCI port I/O is not yet implemented on MIPS. */
+void release_io_perms(void)
+{
+}
+
+#else
+
+#error Unknown architecture
+
+#endif
+
 void mmio_writeb(uint8_t val, void *addr)
 {
    *(volatile uint8_t *) addr = val;
+	sync_primitive();
 }

void mmio_writew(uint16_t val, void *addr)
 {
    *(volatile uint16_t *) addr = val;
+	sync_primitive();
 }

void mmio_writel(uint32_t val, void *addr)
 {
    *(volatile uint32_t *) addr = val;
+	sync_primitive();
 }

uint8_t mmio_readb(void *addr)
@@ -83,3 +132,33 @@
 {
    return *(volatile uint32_t *) addr;
 }
+
+void mmio_le_writeb(uint8_t val, void *addr)
+{
+	mmio_writeb(cpu_to_le8(val), addr);
+}
+
+void mmio_le_writew(uint16_t val, void *addr)
+{
+	mmio_writew(cpu_to_le16(val), addr);
+}
+
+void mmio_le_writel(uint32_t val, void *addr)
+{
+	mmio_writel(cpu_to_le32(val), addr);
+}
+
+uint8_t mmio_le_readb(void *addr)
+{
+	return le_to_cpu8(mmio_readb(addr));
+}
+
+uint16_t mmio_le_readw(void *addr)
+{
+	return le_to_cpu16(mmio_readw(addr));
+}
+
+uint32_t mmio_le_readl(void *addr)
+{
+	return le_to_cpu32(mmio_readl(addr));
+}
Index: flashrom-arch_abstraction/flash.h
===================================================================
--- flashrom-arch_abstraction/flash.h	(Revision 1008)
+++ flashrom-arch_abstraction/flash.h	(Arbeitskopie)
@@ -63,8 +63,10 @@
    PROGRAMMER_ATAHPT,
 #endif
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    PROGRAMMER_IT87SPI,
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    PROGRAMMER_FT2232SPI,
 #endif
@@ -407,6 +409,12 @@
 uint8_t mmio_readb(void *addr);
 uint16_t mmio_readw(void *addr);
 uint32_t mmio_readl(void *addr);
+void mmio_le_writeb(uint8_t val, void *addr);
+void mmio_le_writew(uint16_t val, void *addr);
+void mmio_le_writel(uint32_t val, void *addr);
+uint8_t mmio_le_readb(void *addr);
+uint16_t mmio_le_readw(void *addr);
+uint32_t mmio_le_readl(void *addr);

/* programmer.c */
 int noop_shutdown(void);
@@ -603,6 +611,7 @@
 enum spi_controller {
    SPI_CONTROLLER_NONE,
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    SPI_CONTROLLER_ICH7,
    SPI_CONTROLLER_ICH9,
    SPI_CONTROLLER_IT87XX,
@@ -610,6 +619,7 @@
    SPI_CONTROLLER_VIA,
    SPI_CONTROLLER_WBSIO,
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    SPI_CONTROLLER_FT2232,
 #endif
Index: flashrom-arch_abstraction/spi25.c
===================================================================
--- flashrom-arch_abstraction/spi25.c	(Revision 1008)
+++ flashrom-arch_abstraction/spi25.c	(Arbeitskopie)
@@ -172,12 +172,14 @@
    /* only some SPI chipsets support 4 bytes commands */
    switch (spi_controller) {
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    case SPI_CONTROLLER_ICH7:
    case SPI_CONTROLLER_ICH9:
    case SPI_CONTROLLER_VIA:
    case SPI_CONTROLLER_SB600:
    case SPI_CONTROLLER_WBSIO:
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    case SPI_CONTROLLER_FT2232:
 #endif
@@ -996,11 +998,13 @@

switch (spi_controller) {
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    case SPI_CONTROLLER_WBSIO:
    	msg_cerr("%s: impossible with Winbond SPI masters,"
    			" degrading to byte program\n", __func__);
    	return spi_chip_write_1(flash, buf);
 #endif
+#endif
    default:
    	break;
    }
Index: flashrom-arch_abstraction/hwaccess.h
===================================================================
--- flashrom-arch_abstraction/hwaccess.h	(Revision 1008)
+++ flashrom-arch_abstraction/hwaccess.h	(Arbeitskopie)
@@ -24,13 +24,137 @@
 #ifndef __HWACCESS_H__
 #define __HWACCESS_H__ 1

+#if defined (__i386__) || defined (__x86_64__)
 #if defined(__GLIBC__)
 #include <sys/io.h>
 #endif
+#endif
+
 #if NEED_PCI == 1
 #include <pci/pci.h>
 #endif

+#if defined (__i386__) || defined (__x86_64__)
+
+/* All x86 is little-endian. */
+#define __FLASHROM_LITTLE_ENDIAN__ 1
+
+#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
+
+/* MIPS can be either endian. */
+#if defined (__MIPSEL) || defined (__MIPSEL__) || defined (_MIPSEL) || defined (MIPSEL)
+#define __FLASHROM_LITTLE_ENDIAN__ 1
+#elif defined (__MIPSEB) || defined (__MIPSEB__) || defined (_MIPSEB) || defined (MIPSEB)
+#define __FLASHROM_BIG_ENDIAN__ 1
+#endif
+
+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+/* PowerPC can be either endian. */
+#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__)
+#define __FLASHROM_BIG_ENDIAN__ 1
+/* Error checking in case some weird header has #defines for LE as well. */
+#if defined (_LITTLE_ENDIAN) || defined (__LITTLE_ENDIAN__)
+#error Conflicting endianness #define
+#endif
+#else
+#error Little-endian PowerPC #defines are unknown
+#endif
+
+#endif
+
+#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__)
+/* Nonstandard libc-specific macros for determining endianness. */
+#if defined(__GLIBC__)
+#include <endian.h>
+#if BYTE_ORDER == LITTLE_ENDIAN
+#define __FLASHROM_LITTLE_ENDIAN__ 1
+#elif BYTE_ORDER == BIG_ENDIAN
+#define __FLASHROM_BIG_ENDIAN__ 1
+#endif
+#endif
+#endif
+
+#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__)
+#error Unable to determine endianness. Please add support for your arch or libc.
+#endif
+
+#define ___constant_swab8(x) ((uint8_t)(				\
+	(((uint8_t)(x) & (uint8_t)0xffU))))
+
+#define ___constant_swab16(x) ((uint16_t)(				\
+	(((uint16_t)(x) & (uint16_t)0x00ffU) << 8) |			\
+	(((uint16_t)(x) & (uint16_t)0xff00U) >> 8)))
+
+#define ___constant_swab32(x) ((uint32_t)(				\
+	(((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) |		\
+	(((uint32_t)(x) & (uint32_t)0x0000ff00UL) <<  8) |		\
+	(((uint32_t)(x) & (uint32_t)0x00ff0000UL) >>  8) |		\
+	(((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24)))
+
+#define ___constant_swab64(x) ((uint64_t)(				\
+	(((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) |	\
+	(((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) |	\
+	(((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) |	\
+	(((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) <<  8) |	\
+	(((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >>  8) |	\
+	(((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) |	\
+	(((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) |	\
+	(((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56)))
+
+#if defined (__FLASHROM_BIG_ENDIAN__)
+
+#define cpu_to_le(bits)							\
+static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val)	\
+{									\
+	return ___constant_swab##bits(val);				\
+}
+
+cpu_to_le(8)
+cpu_to_le(16)
+cpu_to_le(32)
+cpu_to_le(64)
+
+#define cpu_to_be8
+#define cpu_to_be16
+#define cpu_to_be32
+#define cpu_to_be64
+
+#elif defined (__FLASHROM_LITTLE_ENDIAN__)
+
+#define cpu_to_be(bits)							\
+static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val)	\
+{									\
+	return ___constant_swab##bits(val);				\
+}
+
+cpu_to_be(8)
+cpu_to_be(16)
+cpu_to_be(32)
+cpu_to_be(64)
+
+#define cpu_to_le8
+#define cpu_to_le16
+#define cpu_to_le32
+#define cpu_to_le64
+
+#else
+
+#error Could not determine endianness.
+
+#endif
+
+#define be_to_cpu8 cpu_to_be8
+#define be_to_cpu16 cpu_to_be16
+#define be_to_cpu32 cpu_to_be32
+#define be_to_cpu64 cpu_to_be64
+#define le_to_cpu8 cpu_to_le8
+#define le_to_cpu16 cpu_to_le16
+#define le_to_cpu32 cpu_to_le32
+#define le_to_cpu64 cpu_to_le64
+
+#if defined (__i386__) || defined (__x86_64__)
+
 /* for iopl and outb under Solaris */
 #if defined (__sun) && (defined(__i386) || defined(__amd64))
 #include <strings.h>
@@ -162,4 +286,18 @@
 int freebsd_wrmsr(int addr, msr_t msr);
 #endif

+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+/* PCI port I/O is not yet implemented on PowerPC. */
+
+#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
+
+/* PCI port I/O is not yet implemented on MIPS. */
+
+#else
+
+#error Unknown architecture, please check if it supports PCI port IO.
+
+#endif
+
 #endif /* !__HWACCESS_H__ */
Index: flashrom-arch_abstraction/it87spi.c
===================================================================
--- flashrom-arch_abstraction/it87spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/it87spi.c	(Arbeitskopie)
@@ -23,6 +23,8 @@
  * Contains the ITE IT87* SPI specific routines
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include <stdlib.h>
 #include "flash.h"
@@ -351,3 +353,5 @@

return 0;
 }
+
+#endif
Index: flashrom-arch_abstraction/physmap.c
===================================================================
--- flashrom-arch_abstraction/physmap.c	(Revision 1008)
+++ flashrom-arch_abstraction/physmap.c	(Arbeitskopie)
@@ -241,6 +241,8 @@
    return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO);
 }

+#if defined(__i386__) || defined(__x86_64__)
+
 #ifdef __linux__
 /*
  * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr,
@@ -462,4 +464,6 @@
 #endif
 #endif
 #endif
-
+#else
+/* Does MSR exist on non-x86 architectures? */
+#endif
Index: flashrom-arch_abstraction/spi.c
===================================================================
--- flashrom-arch_abstraction/spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/spi.c	(Arbeitskopie)
@@ -42,6 +42,7 @@
    },

#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    { /* SPI_CONTROLLER_ICH7 */
    	.command = ich_spi_send_command,
    	.multicommand = ich_spi_send_multicommand,
@@ -84,6 +85,7 @@
    	.write_256 = wbsio_spi_write_1,
    },
 #endif
+#endif

#if FT2232_SPI_SUPPORT == 1
    { /* SPI_CONTROLLER_FT2232 */
Index: flashrom-arch_abstraction/nic3com.c
===================================================================
--- flashrom-arch_abstraction/nic3com.c	(Revision 1008)
+++ flashrom-arch_abstraction/nic3com.c	(Arbeitskopie)
@@ -23,6 +23,8 @@
 #include <sys/types.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 #define BIOS_ROM_ADDR		0x04
 #define BIOS_ROM_DATA		0x08
 #define INT_STATUS		0x0e
@@ -112,3 +114,7 @@
    OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
    return INB(io_base_addr + BIOS_ROM_DATA);
 }
+
+#else
+#error Unsupported architecture for nic3com. You need a way to emulate port IO access.
+#endif
Index: flashrom-arch_abstraction/Makefile
===================================================================
--- flashrom-arch_abstraction/Makefile	(Revision 1008)
+++ flashrom-arch_abstraction/Makefile	(Arbeitskopie)
@@ -124,7 +124,9 @@

ifeq ($(CONFIG_INTERNAL), yes)
 FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1'
-PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o
+PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o
+# FIXME: The PROGRAMMER_OBJS below should only be included on x86.
+PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o
 NEED_PCI := yes
 endif

@@ -260,7 +262,7 @@
    rm -f .dependencies .features .libdeps

dep:
-	@$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies
+	@$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies

strip: $(PROGRAM)
    $(STRIP) $(STRIP_ARGS) $(PROGRAM)
Index: flashrom-arch_abstraction/wbsio_spi.c
===================================================================
--- flashrom-arch_abstraction/wbsio_spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/wbsio_spi.c	(Arbeitskopie)
@@ -18,6 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include "flash.h"
 #include "chipdrivers.h"
@@ -199,3 +201,5 @@

return spi_chip_write_1(flash, buf);
 }
+
+#endif
Index: flashrom-arch_abstraction/chipset_enable.c
===================================================================
--- flashrom-arch_abstraction/chipset_enable.c	(Revision 1008)
+++ flashrom-arch_abstraction/chipset_enable.c	(Arbeitskopie)
@@ -34,6 +34,8 @@
 #include <fcntl.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 extern int ichspi_lock;

static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
@@ -1285,8 +1287,11 @@
    return 0;
 }

+#endif
+
 /* Please keep this list alphabetically sorted by vendor/device. */
 const struct penable chipset_enables[] = {
+#if defined(__i386__) || defined(__x86_64__)
    {0x10B9, 0x1533, OK, "ALi", "M1533",		enable_flash_ali_m1533},
    {0x1022, 0x7440, OK, "AMD", "AMD-768",		enable_flash_amd8111},
    {0x1022, 0x7468, OK, "AMD", "AMD8111",		enable_flash_amd8111},
@@ -1425,7 +1430,7 @@
    {0x1106, 0x0596, OK, "VIA", "VT82C596",		enable_flash_amd8111},
    {0x1106, 0x0586, OK, "VIA", "VT82C586A/B",	enable_flash_amd8111},
    {0x1106, 0x0686, NT, "VIA", "VT82C686A/B",	enable_flash_amd8111},
-
+#endif
    {},
 };

Index: flashrom-arch_abstraction/sb600spi.c
===================================================================
--- flashrom-arch_abstraction/sb600spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/sb600spi.c	(Arbeitskopie)
@@ -21,6 +21,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include "flash.h"
 #include "chipdrivers.h"
@@ -166,3 +168,5 @@

return 0;
 }
+
+#endif
Index: flashrom-arch_abstraction/flashrom.c
===================================================================
--- flashrom-arch_abstraction/flashrom.c	(Revision 1008)
+++ flashrom-arch_abstraction/flashrom.c	(Arbeitskopie)
@@ -276,6 +276,7 @@
 #endif

#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    {
    	.name			= "it87spi",
    	.init			= it87spi_init,
@@ -293,6 +294,7 @@
    	.delay			= internal_delay,
    },
 #endif
+#endif

#if FT2232_SPI_SUPPORT == 1
    {
@@ -1208,17 +1210,22 @@
 #endif
 #endif
 #ifdef __clang__
-	msg_ginfo(" LLVM %i/clang %i", __llvm__, __clang__);
+	msg_ginfo(" LLVM %i/clang %i, ", __llvm__, __clang__);
 #elif defined(__GNUC__)
    msg_ginfo(" GCC");
 #ifdef __VERSION__
-	msg_ginfo(" %s", __VERSION__);
+	msg_ginfo(" %s,", __VERSION__);
 #else
-	msg_ginfo(" unknown version");
+	msg_ginfo(" unknown version,");
 #endif
 #else
-	msg_ginfo(" unknown compiler");
+	msg_ginfo(" unknown compiler,");
 #endif
+#if defined (__FLASHROM_LITTLE_ENDIAN__)
+	msg_ginfo(" little endian");
+#else
+	msg_ginfo(" big endian");
+#endif
    msg_ginfo("\n");
 }

Index: flashrom-arch_abstraction/internal.c
===================================================================
--- flashrom-arch_abstraction/internal.c	(Revision 1008)
+++ flashrom-arch_abstraction/internal.c	(Arbeitskopie)
@@ -99,10 +99,12 @@
 #endif

#if INTERNAL_SUPPORT == 1
-struct superio superio = {};
 int force_boardenable = 0;
 int force_boardmismatch = 0;

+#if defined(__i386__) || defined(__x86_64__)
+struct superio superio = {};
+
 void probe_superio(void)
 {
    superio = probe_superio_ite();
@@ -112,8 +114,9 @@
    	superio = probe_superio_winbond();
 #endif
 }
+#endif

-int is_laptop;
+int is_laptop = 0;

int internal_init(void)
 {
@@ -166,10 +169,13 @@
     * mainboard specific flash enable sequence.
     */
    coreboot_init();
+
+#if defined(__i386__) || defined(__x86_64__)
    dmi_init();

/* Probe for the Super I/O chip and fill global struct superio. */
    probe_superio();
+#endif

/* Warn if a laptop is detected. */
    if (is_laptop) {
@@ -203,8 +209,10 @@
    		 "will most likely fail.\n");
    }

+#if defined(__i386__) || defined(__x86_64__)
    /* Probe for IT87* LPC->SPI translation unconditionally. */
    it87xx_probe_spi_flash(NULL);
+#endif

board_flash_enable(lb_vendor, lb_part);

Index: flashrom-arch_abstraction/ichspi.c
===================================================================
--- flashrom-arch_abstraction/ichspi.c	(Revision 1008)
+++ flashrom-arch_abstraction/ichspi.c	(Arbeitskopie)
@@ -33,6 +33,8 @@
  *
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include "flash.h"
 #include "chipdrivers.h"
@@ -832,3 +834,5 @@
    }
    return ret;
 }
+
+#endif
Index: flashrom-arch_abstraction/print_wiki.c
===================================================================
--- flashrom-arch_abstraction/print_wiki.c	(Revision 1008)
+++ flashrom-arch_abstraction/print_wiki.c	(Arbeitskopie)
@@ -104,6 +104,7 @@
 /* Please keep these lists alphabetically ordered by vendor/board. */
 const struct board_info_url boards_url[] = {
    /* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"AX8",			"http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=Y..." },
    { "Abit",		"Fatal1ty F-I90HD",	"http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NAM..." },
    { "Advantech",		"PCM-5820", 		"http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" },
@@ -279,8 +280,10 @@
    { "VIA",		"EPIA-N/NL",		"http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&a..." }, /* EPIA-N link for now */
    { "VIA",		"EPIA SP",		"http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&a..." },
    { "VIA",		"PC3500G",		"http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp" },
+#endif

/* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"IS-10",		"http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NAM..." },
    { "ASRock",		"K7VT4A+",		"http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=" },
    { "ASUS",		"MEW-AM",		"ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/" },
@@ -298,18 +301,23 @@
    { "Sun",		"Fire x4150",		"http://www.sun.com/servers/x64/x4150/" },
    { "Sun",		"Fire x4200",		"http://www.sun.com/servers/entry/x4200/" },
    { "Sun",		"Fire x4600",		"http://www.sun.com/servers/x64/x4600/" },
+#endif

/* Verified working laptops. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire 1520",		"http://support.acer.com/us/en/acerpanam/notebook/0000/Acer/Aspire1520/Aspire..." },
    { "Lenovo",		"3000 V100 TF05Cxx",	"http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Leno..." },
+#endif

/* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One",		NULL },
    { "ASUS",		"Eee PC 701 4G",	"http://www.asus.com/product.aspx?P_ID=h6SPd3tEzLEsrEiS" },
    { "Dell",		"Latitude CPi A366XT",	"http://www.coreboot.org/Dell_Latitude_CPi_A366XT" },
    { "HP/Compaq",		"nx9010",		"http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc..." },
    { "IBM/Lenovo",		"Thinkpad T40p",	"http://www.thinkwiki.org/wiki/Category:T40p" },
    { "IBM/Lenovo",		"240",			"http://www.stanford.edu/~bresnan//tp240.html" },
+#endif

{ NULL,			NULL,			0 },
 };
@@ -317,6 +325,7 @@
 /* Please keep these lists alphabetically ordered by vendor/board. */
 const struct board_info_notes boards_notes[] = {
    /* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "ASI",		"MB-5BLMP",		"Used in the IGEL WinNET III thin client." },
    { "ASRock",		"K8S8X",		"The Super I/O isn't found on this board. See http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html." },
    { "ASUS",		"A8V-E SE",		"See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." },
@@ -324,23 +333,30 @@
    { "BCOM",		"WinNET100",		"Used in the IGEL-316 thin client." },
    { "GIGABYTE",		"GA-7ZM",		"Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option." },
    { "ASUS",		"M2N-E",		"If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html" },
+#endif

/* Verified working boards that DO need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One",		"See http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html." },
+#endif

/* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "MSI",		"MS-6178",		"Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot." },
    { "MSI",		"MS-7260 (K9N Neo)",	"Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot." },
+#endif

/* Verified working laptops. */
    /* None which need comments, yet... */

/* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One",		"http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html" },
    { "ASUS",		"Eee PC 701 4G",	"It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)." },
    { "Dell",		"Latitude CPi A366XT",	"The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop." },
    { "HP/Compaq",		"nx9010",		"Hangs upon '''flashrom -V''' (needs hard power-cycle then)." },
    { "IBM/Lenovo",		"Thinkpad T40p",	"Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later." },
+#endif

{ NULL,			NULL,			0 },
 };
Index: flashrom-arch_abstraction/print.c
===================================================================
--- flashrom-arch_abstraction/print.c	(Revision 1008)
+++ flashrom-arch_abstraction/print.c	(Arbeitskopie)
@@ -257,6 +257,7 @@
 /* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info boards_ok[] = {
    /* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"AX8", },
    { "Abit",		"Fatal1ty F-I90HD", },
    { "Advantech",		"PCM-5820", },
@@ -377,13 +378,14 @@
    { "VIA",		"pc2500e", },
    { "VIA",		"PC3500G", },
    { "VIA",		"VB700X", },
-
+#endif
    {},
 };

/* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info boards_bad[] = {
    /* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"IS-10", },
    { "ASRock",		"K7VT4A+", },
    { "ASUS",		"MEW-AM", },
@@ -401,29 +403,31 @@
    { "Sun",		"Fire x4200", },
    { "Sun",		"Fire x4540", },
    { "Sun",		"Fire x4600", },
-
+#endif
    {},
 };

/* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info laptops_ok[] = {
    /* Verified working laptops. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Lenovo",		"3000 V100 TF05Cxx", },
    { "Acer",               "Aspire 1520", },
-
+#endif
    {},
 };

/* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info laptops_bad[] = {
    /* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One", },
    { "ASUS",		"Eee PC 701 4G", },
    { "Dell",		"Latitude CPi A366XT", },
    { "HP/Compaq",		"nx9010", },
    { "IBM/Lenovo",		"Thinkpad T40p", },
    { "IBM/Lenovo",		"240", },
-
+#endif
    {},
 };
 #endif
Index: flashrom-arch_abstraction/board_enable.c
===================================================================
--- flashrom-arch_abstraction/board_enable.c	(Revision 1008)
+++ flashrom-arch_abstraction/board_enable.c	(Arbeitskopie)
@@ -28,6 +28,7 @@
 #include <fcntl.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
 /*
  * Helper functions for many Winbond Super I/Os of the W836xx range.
  */
@@ -1306,6 +1307,8 @@
    return it8712f_gpio_set(32, 1);
 }

+#endif
+
 /**
  * Below is the list of boards which need a special "board enable" code in
  * flashrom before their ROM chip can be accessed/written to.
@@ -1349,6 +1352,7 @@
 struct board_pciid_enable board_pciid_enables[] = {

/* first pci-id set [4],          second pci-id set [4],          dmi identifier coreboot id [2],             vendor name    board name       max_rom_...  OK? flash enable */
+#if defined(__i386__) || defined(__x86_64__)
    {0x10DE, 0x0547, 0x147B, 0x1C2F,  0x10DE, 0x0548, 0x147B, 0x1C2F, NULL,          NULL,         NULL,          "Abit",        "AN-M2",                 0,   NT, nvidia_mcp_gpio2_raise},
    {0x8086, 0x2926, 0x147b, 0x1084,  0x11ab, 0x4364, 0x147b, 0x1084, NULL,          NULL,         NULL,          "Abit",        "IP35",                  0,   OK, intel_ich_gpio16_raise},
    {0x8086, 0x2930, 0x147b, 0x1083,  0x10ec, 0x8167, 0x147b, 0x1083, NULL,          NULL,         NULL,          "Abit",        "IP35 Pro",              0,   OK, intel_ich_gpio16_raise},
@@ -1415,7 +1419,7 @@
    {0x1106, 0x3123, 0x1106, 0x3123,  0x1106, 0x3059, 0x1106, 0x4161, NULL,          NULL,         NULL,          "Termtek",     "TK-3370 (Rev:2.5B)",    0,   OK, w836xx_memw_enable_4e},
    {0x1106, 0x3177, 0x1106, 0xAA01,  0x1106, 0x3123, 0x1106, 0xAA01, NULL,          NULL,         NULL,          "VIA",         "EPIA M/MII/...",        0,   OK, via_vt823x_gpio15_raise},
    {0x1106, 0x0259, 0x1106, 0x3227,  0x1106, 0x3065, 0x1106, 0x3149, NULL,          NULL,         NULL,          "VIA",         "EPIA-N/NL",             0,   OK, via_vt823x_gpio9_raise},
-
+#endif
    {     0,      0,      0,      0,       0,      0,      0,      0, NULL,          NULL,         NULL,          NULL,          NULL,                    0,   NT, NULL}, /* end marker */
 };

[Vladimir 'φ-coder/phcoder' Serbinenko]

Carl-Daniel Hailfinger wrote:
> Segher: I'd appreciate if you could take a look and ack it if this looks
> OK from a PowerPC perspective.
>
> Handle the following architectures in generic flashrom code:
> x86/x86_64 (little endian)
> PowerPC (big endian)
> MIPS (big+little endian)
>
> No changes to programmer specific code. This means any drivers with MMIO
> access will _not_ suddenly start working on big endian systems, but with
> this patch everything is in place to fix them.
>
> Compilation should work on all architectures listed above for all
> drivers except nic3com and nicrealtek which require PCI Port IO which is
> x86-only for now.
>
> To compile without nic3com and nicrealtek, run
> make distclean
> make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no
>
> Signed-off-by: Carl-Daniel Hailfinger

This patch together with setting flash_base to 0x1fc00000 worked fine on
my yeeloong LM8089 (8.9" version, mipsel (little-endian) ). I attach the
logs of -Vr, -V and -w together with lspci.
Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko

[Carl-Daniel Hailfinger]

On 25.05.2010 04:00, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
> Carl-Daniel Hailfinger wrote:
> > Handle the following architectures in generic flashrom code:
> > x86/x86_64 (little endian)
> > PowerPC (big endian)
> > MIPS (big+little endian)
> >
> > Signed-off-by: Carl-Daniel Hailfinger
>
> This patch together with setting flash_base to 0x1fc00000 worked fine on
> my yeeloong LM8089 (8.9" version, mipsel (little-endian) ). I attach the
> logs of -Vr, -V and -w together with lspci.
>
> Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko

Thanks for the review and thanks for testing.

Is there a way to determine the chipset and/or the board from userspace?
We'll need that to set buses_supported and flash_base correctly.

Regards,
Carl-Daniel

[Vladimir 'φ-coder/phcoder' Serbinenko]

Carl-Daniel Hailfinger wrote:
> On 25.05.2010 04:00, Vladimir 'φ-coder/phcoder' Serbinenko wrote:
> > Carl-Daniel Hailfinger wrote:
> > > Handle the following architectures in generic flashrom code:
> > > x86/x86_64 (little endian)
> > > PowerPC (big endian)
> > > MIPS (big+little endian)
> > >
> > > Signed-off-by: Carl-Daniel Hailfinger
> >
> > This patch together with setting flash_base to 0x1fc00000 worked fine on
> > my yeeloong LM8089 (8.9" version, mipsel (little-endian) ). I attach the
> > logs of -Vr, -V and -w together with lspci.
> >
> > Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko
>
> Thanks for the review and thanks for testing.
>
> Is there a way to determine the chipset and/or the board from userspace?

I don't think it's actualy necessary. The PCI and LIO bus interfaces as
well as address BootROM is mapped to is part of Loongson 2F (CPU)
specification. So it's enough to check CPU model. But if you want to be
on a safe side you can check "system type" in /proc/cpuinfo as well.
> We'll need that to set buses_supported and flash_base correctly.
>
> Regards,
> Carl-Daniel

[Carl-Daniel Hailfinger]

Segher: I'd appreciate if you could take a look and ack it if this looks
OK from a PowerPC perspective.

New patch. Fix compilation on PowerPC.

Handle the following architectures in generic flashrom code:
- x86/x86_64 (little endian)
- PowerPC (big endian)
- MIPS (big+little endian)

No changes to programmer specific code. This means any drivers with MMIO
access will _not_ suddenly start working on big endian systems, but with
this patch everything is in place to fix them.

Compilation should work on all architectures listed above for all
drivers except nic3com and nicrealtek which require PCI Port IO which is
x86-only for now.

To compile without nic3com and nicrealtek, run
make distclean
make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no

Thanks to Vladimir Serbinenko for compile testing on MIPS (little
endian) and PowerPC (big endian) and for runtime testing on MIPS (little
endian).
Thanks to David Daney for compile testing on MIPS (big endian).

DO NOT RUN FLASHROM ON NON-X86 AFTER APPLYING THIS PATCH!

Signed-off-by: Carl-Daniel Hailfinger 
Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko

Index: flashrom-arch_abstraction/hwaccess.c
===================================================================
--- flashrom-arch_abstraction/hwaccess.c	(Revision 1008)
+++ flashrom-arch_abstraction/hwaccess.c	(Arbeitskopie)
@@ -26,6 +26,12 @@
 #include <errno.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
+static inline void sync_primitive(void)
+{
+}
+
 #if defined(__FreeBSD__) || defined(__DragonFly__)
 int io_fd;
 #endif
@@ -54,19 +60,62 @@
 #endif
 }

+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+static inline void sync_primitive(void)
+{
+	asm("eieio" : : : "memory");
+}
+
+/* PCI port I/O is not yet implemented on PowerPC. */
+void get_io_perms(void)
+{
+}
+
+/* PCI port I/O is not yet implemented on PowerPC. */
+void release_io_perms(void)
+{
+}
+
+#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
+
+/* Not sure about the sync primitive. */
+static inline void sync_primitive(void)
+{
+}
+
+/* PCI port I/O is not yet implemented on MIPS. */
+void get_io_perms(void)
+{
+}
+
+/* PCI port I/O is not yet implemented on MIPS. */
+void release_io_perms(void)
+{
+}
+
+#else
+
+#error Unknown architecture
+
+#endif
+
 void mmio_writeb(uint8_t val, void *addr)
 {
    *(volatile uint8_t *) addr = val;
+	sync_primitive();
 }

void mmio_writew(uint16_t val, void *addr)
 {
    *(volatile uint16_t *) addr = val;
+	sync_primitive();
 }

void mmio_writel(uint32_t val, void *addr)
 {
    *(volatile uint32_t *) addr = val;
+	sync_primitive();
 }

uint8_t mmio_readb(void *addr)
@@ -83,3 +132,33 @@
 {
    return *(volatile uint32_t *) addr;
 }
+
+void mmio_le_writeb(uint8_t val, void *addr)
+{
+	mmio_writeb(cpu_to_le8(val), addr);
+}
+
+void mmio_le_writew(uint16_t val, void *addr)
+{
+	mmio_writew(cpu_to_le16(val), addr);
+}
+
+void mmio_le_writel(uint32_t val, void *addr)
+{
+	mmio_writel(cpu_to_le32(val), addr);
+}
+
+uint8_t mmio_le_readb(void *addr)
+{
+	return le_to_cpu8(mmio_readb(addr));
+}
+
+uint16_t mmio_le_readw(void *addr)
+{
+	return le_to_cpu16(mmio_readw(addr));
+}
+
+uint32_t mmio_le_readl(void *addr)
+{
+	return le_to_cpu32(mmio_readl(addr));
+}
Index: flashrom-arch_abstraction/flash.h
===================================================================
--- flashrom-arch_abstraction/flash.h	(Revision 1008)
+++ flashrom-arch_abstraction/flash.h	(Arbeitskopie)
@@ -63,8 +63,10 @@
    PROGRAMMER_ATAHPT,
 #endif
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    PROGRAMMER_IT87SPI,
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    PROGRAMMER_FT2232SPI,
 #endif
@@ -407,6 +409,12 @@
 uint8_t mmio_readb(void *addr);
 uint16_t mmio_readw(void *addr);
 uint32_t mmio_readl(void *addr);
+void mmio_le_writeb(uint8_t val, void *addr);
+void mmio_le_writew(uint16_t val, void *addr);
+void mmio_le_writel(uint32_t val, void *addr);
+uint8_t mmio_le_readb(void *addr);
+uint16_t mmio_le_readw(void *addr);
+uint32_t mmio_le_readl(void *addr);

/* programmer.c */
 int noop_shutdown(void);
@@ -603,6 +611,7 @@
 enum spi_controller {
    SPI_CONTROLLER_NONE,
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    SPI_CONTROLLER_ICH7,
    SPI_CONTROLLER_ICH9,
    SPI_CONTROLLER_IT87XX,
@@ -610,6 +619,7 @@
    SPI_CONTROLLER_VIA,
    SPI_CONTROLLER_WBSIO,
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    SPI_CONTROLLER_FT2232,
 #endif
Index: flashrom-arch_abstraction/spi25.c
===================================================================
--- flashrom-arch_abstraction/spi25.c	(Revision 1008)
+++ flashrom-arch_abstraction/spi25.c	(Arbeitskopie)
@@ -172,12 +172,14 @@
    /* only some SPI chipsets support 4 bytes commands */
    switch (spi_controller) {
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    case SPI_CONTROLLER_ICH7:
    case SPI_CONTROLLER_ICH9:
    case SPI_CONTROLLER_VIA:
    case SPI_CONTROLLER_SB600:
    case SPI_CONTROLLER_WBSIO:
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    case SPI_CONTROLLER_FT2232:
 #endif
@@ -996,11 +998,13 @@

switch (spi_controller) {
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    case SPI_CONTROLLER_WBSIO:
    	msg_cerr("%s: impossible with Winbond SPI masters,"
    			" degrading to byte program\n", __func__);
    	return spi_chip_write_1(flash, buf);
 #endif
+#endif
    default:
    	break;
    }
Index: flashrom-arch_abstraction/hwaccess.h
===================================================================
--- flashrom-arch_abstraction/hwaccess.h	(Revision 1008)
+++ flashrom-arch_abstraction/hwaccess.h	(Arbeitskopie)
@@ -24,13 +24,137 @@
 #ifndef __HWACCESS_H__
 #define __HWACCESS_H__ 1

+#if defined (__i386__) || defined (__x86_64__)
 #if defined(__GLIBC__)
 #include <sys/io.h>
 #endif
+#endif
+
 #if NEED_PCI == 1
 #include <pci/pci.h>
 #endif

+#if defined (__i386__) || defined (__x86_64__)
+
+/* All x86 is little-endian. */
+#define __FLASHROM_LITTLE_ENDIAN__ 1
+
+#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
+
+/* MIPS can be either endian. */
+#if defined (__MIPSEL) || defined (__MIPSEL__) || defined (_MIPSEL) || defined (MIPSEL)
+#define __FLASHROM_LITTLE_ENDIAN__ 1
+#elif defined (__MIPSEB) || defined (__MIPSEB__) || defined (_MIPSEB) || defined (MIPSEB)
+#define __FLASHROM_BIG_ENDIAN__ 1
+#endif
+
+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+/* PowerPC can be either endian. */
+#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__)
+#define __FLASHROM_BIG_ENDIAN__ 1
+/* Error checking in case some weird header has #defines for LE as well. */
+#if defined (_LITTLE_ENDIAN) || defined (__LITTLE_ENDIAN__)
+#error Conflicting endianness #define
+#endif
+#else
+#error Little-endian PowerPC #defines are unknown
+#endif
+
+#endif
+
+#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__)
+/* Nonstandard libc-specific macros for determining endianness. */
+#if defined(__GLIBC__)
+#include <endian.h>
+#if BYTE_ORDER == LITTLE_ENDIAN
+#define __FLASHROM_LITTLE_ENDIAN__ 1
+#elif BYTE_ORDER == BIG_ENDIAN
+#define __FLASHROM_BIG_ENDIAN__ 1
+#endif
+#endif
+#endif
+
+#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__)
+#error Unable to determine endianness. Please add support for your arch or libc.
+#endif
+
+#define ___constant_swab8(x) ((uint8_t)(				\
+	(((uint8_t)(x) & (uint8_t)0xffU))))
+
+#define ___constant_swab16(x) ((uint16_t)(				\
+	(((uint16_t)(x) & (uint16_t)0x00ffU) << 8) |			\
+	(((uint16_t)(x) & (uint16_t)0xff00U) >> 8)))
+
+#define ___constant_swab32(x) ((uint32_t)(				\
+	(((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) |		\
+	(((uint32_t)(x) & (uint32_t)0x0000ff00UL) <<  8) |		\
+	(((uint32_t)(x) & (uint32_t)0x00ff0000UL) >>  8) |		\
+	(((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24)))
+
+#define ___constant_swab64(x) ((uint64_t)(				\
+	(((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) |	\
+	(((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) |	\
+	(((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) |	\
+	(((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) <<  8) |	\
+	(((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >>  8) |	\
+	(((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) |	\
+	(((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) |	\
+	(((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56)))
+
+#if defined (__FLASHROM_BIG_ENDIAN__)
+
+#define cpu_to_le(bits)							\
+static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val)	\
+{									\
+	return ___constant_swab##bits(val);				\
+}
+
+cpu_to_le(8)
+cpu_to_le(16)
+cpu_to_le(32)
+cpu_to_le(64)
+
+#define cpu_to_be8
+#define cpu_to_be16
+#define cpu_to_be32
+#define cpu_to_be64
+
+#elif defined (__FLASHROM_LITTLE_ENDIAN__)
+
+#define cpu_to_be(bits)							\
+static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val)	\
+{									\
+	return ___constant_swab##bits(val);				\
+}
+
+cpu_to_be(8)
+cpu_to_be(16)
+cpu_to_be(32)
+cpu_to_be(64)
+
+#define cpu_to_le8
+#define cpu_to_le16
+#define cpu_to_le32
+#define cpu_to_le64
+
+#else
+
+#error Could not determine endianness.
+
+#endif
+
+#define be_to_cpu8 cpu_to_be8
+#define be_to_cpu16 cpu_to_be16
+#define be_to_cpu32 cpu_to_be32
+#define be_to_cpu64 cpu_to_be64
+#define le_to_cpu8 cpu_to_le8
+#define le_to_cpu16 cpu_to_le16
+#define le_to_cpu32 cpu_to_le32
+#define le_to_cpu64 cpu_to_le64
+
+#if defined (__i386__) || defined (__x86_64__)
+
 /* for iopl and outb under Solaris */
 #if defined (__sun) && (defined(__i386) || defined(__amd64))
 #include <strings.h>
@@ -162,4 +286,18 @@
 int freebsd_wrmsr(int addr, msr_t msr);
 #endif

+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+/* PCI port I/O is not yet implemented on PowerPC. */
+
+#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
+
+/* PCI port I/O is not yet implemented on MIPS. */
+
+#else
+
+#error Unknown architecture, please check if it supports PCI port IO.
+
+#endif
+
 #endif /* !__HWACCESS_H__ */
Index: flashrom-arch_abstraction/it87spi.c
===================================================================
--- flashrom-arch_abstraction/it87spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/it87spi.c	(Arbeitskopie)
@@ -23,6 +23,8 @@
  * Contains the ITE IT87* SPI specific routines
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include <stdlib.h>
 #include "flash.h"
@@ -351,3 +353,5 @@

return 0;
 }
+
+#endif
Index: flashrom-arch_abstraction/physmap.c
===================================================================
--- flashrom-arch_abstraction/physmap.c	(Revision 1008)
+++ flashrom-arch_abstraction/physmap.c	(Arbeitskopie)
@@ -241,6 +241,8 @@
    return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO);
 }

+#if defined(__i386__) || defined(__x86_64__)
+
 #ifdef __linux__
 /*
  * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr,
@@ -462,4 +464,6 @@
 #endif
 #endif
 #endif
-
+#else
+/* Does MSR exist on non-x86 architectures? */
+#endif
Index: flashrom-arch_abstraction/spi.c
===================================================================
--- flashrom-arch_abstraction/spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/spi.c	(Arbeitskopie)
@@ -42,6 +42,7 @@
    },

#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    { /* SPI_CONTROLLER_ICH7 */
    	.command = ich_spi_send_command,
    	.multicommand = ich_spi_send_multicommand,
@@ -84,6 +85,7 @@
    	.write_256 = wbsio_spi_write_1,
    },
 #endif
+#endif

#if FT2232_SPI_SUPPORT == 1
    { /* SPI_CONTROLLER_FT2232 */
Index: flashrom-arch_abstraction/nic3com.c
===================================================================
--- flashrom-arch_abstraction/nic3com.c	(Revision 1008)
+++ flashrom-arch_abstraction/nic3com.c	(Arbeitskopie)
@@ -23,6 +23,8 @@
 #include <sys/types.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 #define BIOS_ROM_ADDR		0x04
 #define BIOS_ROM_DATA		0x08
 #define INT_STATUS		0x0e
@@ -112,3 +114,7 @@
    OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
    return INB(io_base_addr + BIOS_ROM_DATA);
 }
+
+#else
+#error Unsupported architecture for nic3com. You need a way to emulate port IO access.
+#endif
Index: flashrom-arch_abstraction/Makefile
===================================================================
--- flashrom-arch_abstraction/Makefile	(Revision 1008)
+++ flashrom-arch_abstraction/Makefile	(Arbeitskopie)
@@ -124,7 +124,9 @@

ifeq ($(CONFIG_INTERNAL), yes)
 FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1'
-PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o
+PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o
+# FIXME: The PROGRAMMER_OBJS below should only be included on x86.
+PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o
 NEED_PCI := yes
 endif

@@ -260,7 +262,7 @@
    rm -f .dependencies .features .libdeps

dep:
-	@$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies
+	@$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies

strip: $(PROGRAM)
    $(STRIP) $(STRIP_ARGS) $(PROGRAM)
Index: flashrom-arch_abstraction/wbsio_spi.c
===================================================================
--- flashrom-arch_abstraction/wbsio_spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/wbsio_spi.c	(Arbeitskopie)
@@ -18,6 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include "flash.h"
 #include "chipdrivers.h"
@@ -199,3 +201,5 @@

return spi_chip_write_1(flash, buf);
 }
+
+#endif
Index: flashrom-arch_abstraction/chipset_enable.c
===================================================================
--- flashrom-arch_abstraction/chipset_enable.c	(Revision 1008)
+++ flashrom-arch_abstraction/chipset_enable.c	(Arbeitskopie)
@@ -34,6 +34,8 @@
 #include <fcntl.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 extern int ichspi_lock;

static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
@@ -1285,8 +1287,11 @@
    return 0;
 }

+#endif
+
 /* Please keep this list alphabetically sorted by vendor/device. */
 const struct penable chipset_enables[] = {
+#if defined(__i386__) || defined(__x86_64__)
    {0x10B9, 0x1533, OK, "ALi", "M1533",		enable_flash_ali_m1533},
    {0x1022, 0x7440, OK, "AMD", "AMD-768",		enable_flash_amd8111},
    {0x1022, 0x7468, OK, "AMD", "AMD8111",		enable_flash_amd8111},
@@ -1425,7 +1430,7 @@
    {0x1106, 0x0596, OK, "VIA", "VT82C596",		enable_flash_amd8111},
    {0x1106, 0x0586, OK, "VIA", "VT82C586A/B",	enable_flash_amd8111},
    {0x1106, 0x0686, NT, "VIA", "VT82C686A/B",	enable_flash_amd8111},
-
+#endif
    {},
 };

Index: flashrom-arch_abstraction/sb600spi.c
===================================================================
--- flashrom-arch_abstraction/sb600spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/sb600spi.c	(Arbeitskopie)
@@ -21,6 +21,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include "flash.h"
 #include "chipdrivers.h"
@@ -166,3 +168,5 @@

return 0;
 }
+
+#endif
Index: flashrom-arch_abstraction/flashrom.c
===================================================================
--- flashrom-arch_abstraction/flashrom.c	(Revision 1008)
+++ flashrom-arch_abstraction/flashrom.c	(Arbeitskopie)
@@ -276,6 +276,7 @@
 #endif

#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    {
    	.name			= "it87spi",
    	.init			= it87spi_init,
@@ -293,6 +294,7 @@
    	.delay			= internal_delay,
    },
 #endif
+#endif

#if FT2232_SPI_SUPPORT == 1
    {
@@ -1208,17 +1210,22 @@
 #endif
 #endif
 #ifdef __clang__
-	msg_ginfo(" LLVM %i/clang %i", __llvm__, __clang__);
+	msg_ginfo(" LLVM %i/clang %i, ", __llvm__, __clang__);
 #elif defined(__GNUC__)
    msg_ginfo(" GCC");
 #ifdef __VERSION__
-	msg_ginfo(" %s", __VERSION__);
+	msg_ginfo(" %s,", __VERSION__);
 #else
-	msg_ginfo(" unknown version");
+	msg_ginfo(" unknown version,");
 #endif
 #else
-	msg_ginfo(" unknown compiler");
+	msg_ginfo(" unknown compiler,");
 #endif
+#if defined (__FLASHROM_LITTLE_ENDIAN__)
+	msg_ginfo(" little endian");
+#else
+	msg_ginfo(" big endian");
+#endif
    msg_ginfo("\n");
 }

Index: flashrom-arch_abstraction/internal.c
===================================================================
--- flashrom-arch_abstraction/internal.c	(Revision 1008)
+++ flashrom-arch_abstraction/internal.c	(Arbeitskopie)
@@ -99,10 +99,12 @@
 #endif

#if INTERNAL_SUPPORT == 1
-struct superio superio = {};
 int force_boardenable = 0;
 int force_boardmismatch = 0;

+#if defined(__i386__) || defined(__x86_64__)
+struct superio superio = {};
+
 void probe_superio(void)
 {
    superio = probe_superio_ite();
@@ -112,8 +114,9 @@
    	superio = probe_superio_winbond();
 #endif
 }
+#endif

-int is_laptop;
+int is_laptop = 0;

int internal_init(void)
 {
@@ -166,10 +169,13 @@
     * mainboard specific flash enable sequence.
     */
    coreboot_init();
+
+#if defined(__i386__) || defined(__x86_64__)
    dmi_init();

/* Probe for the Super I/O chip and fill global struct superio. */
    probe_superio();
+#endif

/* Warn if a laptop is detected. */
    if (is_laptop) {
@@ -203,8 +209,10 @@
    		 "will most likely fail.\n");
    }

+#if defined(__i386__) || defined(__x86_64__)
    /* Probe for IT87* LPC->SPI translation unconditionally. */
    it87xx_probe_spi_flash(NULL);
+#endif

board_flash_enable(lb_vendor, lb_part);

Index: flashrom-arch_abstraction/ichspi.c
===================================================================
--- flashrom-arch_abstraction/ichspi.c	(Revision 1008)
+++ flashrom-arch_abstraction/ichspi.c	(Arbeitskopie)
@@ -33,6 +33,8 @@
  *
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include "flash.h"
 #include "chipdrivers.h"
@@ -832,3 +834,5 @@
    }
    return ret;
 }
+
+#endif
Index: flashrom-arch_abstraction/print_wiki.c
===================================================================
--- flashrom-arch_abstraction/print_wiki.c	(Revision 1008)
+++ flashrom-arch_abstraction/print_wiki.c	(Arbeitskopie)
@@ -104,6 +104,7 @@
 /* Please keep these lists alphabetically ordered by vendor/board. */
 const struct board_info_url boards_url[] = {
    /* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"AX8",			"http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=Y..." },
    { "Abit",		"Fatal1ty F-I90HD",	"http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NAM..." },
    { "Advantech",		"PCM-5820", 		"http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" },
@@ -279,8 +280,10 @@
    { "VIA",		"EPIA-N/NL",		"http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&a..." }, /* EPIA-N link for now */
    { "VIA",		"EPIA SP",		"http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&a..." },
    { "VIA",		"PC3500G",		"http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp" },
+#endif

/* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"IS-10",		"http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NAM..." },
    { "ASRock",		"K7VT4A+",		"http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=" },
    { "ASUS",		"MEW-AM",		"ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/" },
@@ -298,18 +301,23 @@
    { "Sun",		"Fire x4150",		"http://www.sun.com/servers/x64/x4150/" },
    { "Sun",		"Fire x4200",		"http://www.sun.com/servers/entry/x4200/" },
    { "Sun",		"Fire x4600",		"http://www.sun.com/servers/x64/x4600/" },
+#endif

/* Verified working laptops. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire 1520",		"http://support.acer.com/us/en/acerpanam/notebook/0000/Acer/Aspire1520/Aspire..." },
    { "Lenovo",		"3000 V100 TF05Cxx",	"http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Leno..." },
+#endif

/* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One",		NULL },
    { "ASUS",		"Eee PC 701 4G",	"http://www.asus.com/product.aspx?P_ID=h6SPd3tEzLEsrEiS" },
    { "Dell",		"Latitude CPi A366XT",	"http://www.coreboot.org/Dell_Latitude_CPi_A366XT" },
    { "HP/Compaq",		"nx9010",		"http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc..." },
    { "IBM/Lenovo",		"Thinkpad T40p",	"http://www.thinkwiki.org/wiki/Category:T40p" },
    { "IBM/Lenovo",		"240",			"http://www.stanford.edu/~bresnan//tp240.html" },
+#endif

{ NULL,			NULL,			0 },
 };
@@ -317,6 +325,7 @@
 /* Please keep these lists alphabetically ordered by vendor/board. */
 const struct board_info_notes boards_notes[] = {
    /* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "ASI",		"MB-5BLMP",		"Used in the IGEL WinNET III thin client." },
    { "ASRock",		"K8S8X",		"The Super I/O isn't found on this board. See http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html." },
    { "ASUS",		"A8V-E SE",		"See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." },
@@ -324,23 +333,30 @@
    { "BCOM",		"WinNET100",		"Used in the IGEL-316 thin client." },
    { "GIGABYTE",		"GA-7ZM",		"Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option." },
    { "ASUS",		"M2N-E",		"If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html" },
+#endif

/* Verified working boards that DO need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One",		"See http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html." },
+#endif

/* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "MSI",		"MS-6178",		"Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot." },
    { "MSI",		"MS-7260 (K9N Neo)",	"Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot." },
+#endif

/* Verified working laptops. */
    /* None which need comments, yet... */

/* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One",		"http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html" },
    { "ASUS",		"Eee PC 701 4G",	"It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)." },
    { "Dell",		"Latitude CPi A366XT",	"The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop." },
    { "HP/Compaq",		"nx9010",		"Hangs upon '''flashrom -V''' (needs hard power-cycle then)." },
    { "IBM/Lenovo",		"Thinkpad T40p",	"Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later." },
+#endif

{ NULL,			NULL,			0 },
 };
Index: flashrom-arch_abstraction/print.c
===================================================================
--- flashrom-arch_abstraction/print.c	(Revision 1008)
+++ flashrom-arch_abstraction/print.c	(Arbeitskopie)
@@ -257,6 +257,7 @@
 /* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info boards_ok[] = {
    /* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"AX8", },
    { "Abit",		"Fatal1ty F-I90HD", },
    { "Advantech",		"PCM-5820", },
@@ -377,13 +378,14 @@
    { "VIA",		"pc2500e", },
    { "VIA",		"PC3500G", },
    { "VIA",		"VB700X", },
-
+#endif
    {},
 };

/* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info boards_bad[] = {
    /* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"IS-10", },
    { "ASRock",		"K7VT4A+", },
    { "ASUS",		"MEW-AM", },
@@ -401,29 +403,31 @@
    { "Sun",		"Fire x4200", },
    { "Sun",		"Fire x4540", },
    { "Sun",		"Fire x4600", },
-
+#endif
    {},
 };

/* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info laptops_ok[] = {
    /* Verified working laptops. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Lenovo",		"3000 V100 TF05Cxx", },
    { "Acer",               "Aspire 1520", },
-
+#endif
    {},
 };

/* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info laptops_bad[] = {
    /* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One", },
    { "ASUS",		"Eee PC 701 4G", },
    { "Dell",		"Latitude CPi A366XT", },
    { "HP/Compaq",		"nx9010", },
    { "IBM/Lenovo",		"Thinkpad T40p", },
    { "IBM/Lenovo",		"240", },
-
+#endif
    {},
 };
 #endif
Index: flashrom-arch_abstraction/board_enable.c
===================================================================
--- flashrom-arch_abstraction/board_enable.c	(Revision 1008)
+++ flashrom-arch_abstraction/board_enable.c	(Arbeitskopie)
@@ -28,6 +28,7 @@
 #include <fcntl.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
 /*
  * Helper functions for many Winbond Super I/Os of the W836xx range.
  */
@@ -1306,6 +1307,8 @@
    return it8712f_gpio_set(32, 1);
 }

+#endif
+
 /**
  * Below is the list of boards which need a special "board enable" code in
  * flashrom before their ROM chip can be accessed/written to.
@@ -1349,6 +1352,7 @@
 struct board_pciid_enable board_pciid_enables[] = {

/* first pci-id set [4],          second pci-id set [4],          dmi identifier coreboot id [2],             vendor name    board name       max_rom_...  OK? flash enable */
+#if defined(__i386__) || defined(__x86_64__)
    {0x10DE, 0x0547, 0x147B, 0x1C2F,  0x10DE, 0x0548, 0x147B, 0x1C2F, NULL,          NULL,         NULL,          "Abit",        "AN-M2",                 0,   NT, nvidia_mcp_gpio2_raise},
    {0x8086, 0x2926, 0x147b, 0x1084,  0x11ab, 0x4364, 0x147b, 0x1084, NULL,          NULL,         NULL,          "Abit",        "IP35",                  0,   OK, intel_ich_gpio16_raise},
    {0x8086, 0x2930, 0x147b, 0x1083,  0x10ec, 0x8167, 0x147b, 0x1083, NULL,          NULL,         NULL,          "Abit",        "IP35 Pro",              0,   OK, intel_ich_gpio16_raise},
@@ -1415,7 +1419,7 @@
    {0x1106, 0x3123, 0x1106, 0x3123,  0x1106, 0x3059, 0x1106, 0x4161, NULL,          NULL,         NULL,          "Termtek",     "TK-3370 (Rev:2.5B)",    0,   OK, w836xx_memw_enable_4e},
    {0x1106, 0x3177, 0x1106, 0xAA01,  0x1106, 0x3123, 0x1106, 0xAA01, NULL,          NULL,         NULL,          "VIA",         "EPIA M/MII/...",        0,   OK, via_vt823x_gpio15_raise},
    {0x1106, 0x0259, 0x1106, 0x3227,  0x1106, 0x3065, 0x1106, 0x3149, NULL,          NULL,         NULL,          "VIA",         "EPIA-N/NL",             0,   OK, via_vt823x_gpio9_raise},
-
+#endif
    {     0,      0,      0,      0,       0,      0,      0,      0, NULL,          NULL,         NULL,          NULL,          NULL,                    0,   NT, NULL}, /* end marker */
 };

[Segher Boessenkool]

> Segher: I'd appreciate if you could take a look and ack it if this looks
> OK from a PowerPC perspective.

Looks okay to me.

Acked-by: Segher Boessenkool

[Uwe Hermann]

On Wed, May 26, 2010 at 12:34:49AM +0200, Carl-Daniel Hailfinger wrote:
> Handle the following architectures in generic flashrom code:
> x86/x86_64 (little endian)
> PowerPC (big endian)
> MIPS (big+little endian)

Build-tested on x86 and x86_64. Runtime-tested on a random
FWH-board/-chip (PREW) on Linux x86_64, still works fine.
> Signed-off-by: Carl-Daniel Hailfinger 
> Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko

Acked-by: Uwe Hermann
> Index: flashrom-arch_abstraction/hwaccess.c
>
> --- flashrom-arch_abstraction/hwaccess.c	(Revision 1008)
> +++ flashrom-arch_abstraction/hwaccess.c	(Arbeitskopie)

[...]
> +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
>
> +static inline void sync_primitive(void)
> +{
> asm("eieio" : : : "memory");

This asm could use a nice long comment about what it does exactly and
why it's needed etc.
> +#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__)
> +#error Unable to determine endianness. Please add support for your arch or libc.
> +#endif
>
> +#define ___constant_swab8(x) ((uint8_t)(				\

^
                                  space here, please
> (((uint8_t)(x) & (uint8_t)0xffU))))
>
> +#define ___constant_swab16(x) ((uint16_t)(				\

^
> (((uint16_t)(x) & (uint16_t)0x00ffU) << 8) |			\
> (((uint16_t)(x) & (uint16_t)0xff00U) >> 8)))
>
> +#define ___constant_swab32(x) ((uint32_t)(				\

^
> (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) |		\
> (((uint32_t)(x) & (uint32_t)0x0000ff00UL) <<  8) |		\
> (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >>  8) |		\
> (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24)))
>
> +#define ___constant_swab64(x) ((uint64_t)(				\

^
Ditto for these other 3 places.
> +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
>
> +/* PCI port I/O is not yet implemented on PowerPC. */
>
> +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
>
> +/* PCI port I/O is not yet implemented on MIPS. */
>
> +#else
>
> +#error Unknown architecture, please check if it supports PCI port IO.

^^
"IO" -> "I/O" for consistency.
> Index: flashrom-arch_abstraction/nic3com.c
>
> --- flashrom-arch_abstraction/nic3com.c	(Revision 1008)
> +++ flashrom-arch_abstraction/nic3com.c	(Arbeitskopie)
> @@ -23,6 +23,8 @@
>  #include <sys/types.h>
>  #include "flash.h"
>
> +#if defined(__i386__) || defined(__x86_64__)
>
> #define BIOS_ROM_ADDR		0x04
>  #define BIOS_ROM_DATA		0x08
>  #define INT_STATUS		0x0e
> @@ -112,3 +114,7 @@
>    OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
>    return INB(io_base_addr + BIOS_ROM_DATA);
>  }
>
> +#else
> +#error Unsupported architecture for nic3com. You need a way to emulate port IO access.

"IO" -> "I/O" for consistency.

Also, wouldn't the nicrealtek code need the same #ifdefs and #error?

Uwe.

[Carl-Daniel Hailfinger]

Thanks everyone for reviewing this!

New patch, addresses Uwe's comments and incorporates Segher's
suggestions for explanatory wording for eieieo on PowerPC.

Handle the following architectures in generic flashrom code:
- x86/x86_64 (little endian)
- PowerPC (big endian)
- MIPS (big+little endian)

No changes to programmer specific code. This means any drivers with MMIO
access will _not_ suddenly start working on big endian systems, but with
this patch everything is in place to fix them.

Compilation should work on all architectures listed above for all
drivers except nic3com and nicrealtek which require PCI Port IO which is
x86-only for now.

To compile without nic3com and nicrealtek, run
make distclean
make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no

Thanks to Misha Manulis for testing early versions of this patch on
PowerPC (big endian) with the satasii programmer.
Thanks to Segher Boessenkool for design review and for helping out with
compiler tricks and pointing out that we need eieio on PowerPC.
Thanks to Vladimir Serbinenko for compile testing on MIPS (little
endian) and PowerPC (big endian) and for runtime testing on MIPS (little
endian).
Thanks to David Daney for compile testing on MIPS (big endian).
Thanks to Uwe Hermann for compile and runtime testing on x86_64.

DO NOT RUN FLASHROM ON NON-X86 AFTER APPLYING THIS PATCH!

Signed-off-by: Carl-Daniel Hailfinger 
Acked-by: Misha Manulis 
Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko 
Acked-by: Uwe Hermann 
Acked-by: Segher Boessenkool

Index: flashrom-arch_abstraction/hwaccess.c
===================================================================
--- flashrom-arch_abstraction/hwaccess.c	(Revision 1008)
+++ flashrom-arch_abstraction/hwaccess.c	(Arbeitskopie)
@@ -26,6 +26,15 @@
 #include <errno.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
+/* sync primitive is not needed because x86 uses uncached accesses
+ * which have a strongly ordered memory model.
+ */
+static inline void sync_primitive(void)
+{
+}
+
 #if defined(__FreeBSD__) || defined(__DragonFly__)
 int io_fd;
 #endif
@@ -54,19 +63,68 @@
 #endif
 }

+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+static inline void sync_primitive(void)
+{
+	/* Prevent reordering and/or merging of reads/writes to hardware.
+	 * Such reordering and/or merging would break device accesses which
+	 * depend on the exact access order.
+	 */
+	asm("eieio" : : : "memory");
+}
+
+/* PCI port I/O is not yet implemented on PowerPC. */
+void get_io_perms(void)
+{
+}
+
+/* PCI port I/O is not yet implemented on PowerPC. */
+void release_io_perms(void)
+{
+}
+
+#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
+
+/* sync primitive is not needed because /dev/mem on MIPS uses uncached accesses
+ * in mode 2 which has a strongly ordered memory model.
+ */
+static inline void sync_primitive(void)
+{
+}
+
+/* PCI port I/O is not yet implemented on MIPS. */
+void get_io_perms(void)
+{
+}
+
+/* PCI port I/O is not yet implemented on MIPS. */
+void release_io_perms(void)
+{
+}
+
+#else
+
+#error Unknown architecture
+
+#endif
+
 void mmio_writeb(uint8_t val, void *addr)
 {
    *(volatile uint8_t *) addr = val;
+	sync_primitive();
 }

void mmio_writew(uint16_t val, void *addr)
 {
    *(volatile uint16_t *) addr = val;
+	sync_primitive();
 }

void mmio_writel(uint32_t val, void *addr)
 {
    *(volatile uint32_t *) addr = val;
+	sync_primitive();
 }

uint8_t mmio_readb(void *addr)
@@ -83,3 +141,33 @@
 {
    return *(volatile uint32_t *) addr;
 }
+
+void mmio_le_writeb(uint8_t val, void *addr)
+{
+	mmio_writeb(cpu_to_le8(val), addr);
+}
+
+void mmio_le_writew(uint16_t val, void *addr)
+{
+	mmio_writew(cpu_to_le16(val), addr);
+}
+
+void mmio_le_writel(uint32_t val, void *addr)
+{
+	mmio_writel(cpu_to_le32(val), addr);
+}
+
+uint8_t mmio_le_readb(void *addr)
+{
+	return le_to_cpu8(mmio_readb(addr));
+}
+
+uint16_t mmio_le_readw(void *addr)
+{
+	return le_to_cpu16(mmio_readw(addr));
+}
+
+uint32_t mmio_le_readl(void *addr)
+{
+	return le_to_cpu32(mmio_readl(addr));
+}
Index: flashrom-arch_abstraction/flash.h
===================================================================
--- flashrom-arch_abstraction/flash.h	(Revision 1008)
+++ flashrom-arch_abstraction/flash.h	(Arbeitskopie)
@@ -63,8 +63,10 @@
    PROGRAMMER_ATAHPT,
 #endif
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    PROGRAMMER_IT87SPI,
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    PROGRAMMER_FT2232SPI,
 #endif
@@ -407,6 +409,12 @@
 uint8_t mmio_readb(void *addr);
 uint16_t mmio_readw(void *addr);
 uint32_t mmio_readl(void *addr);
+void mmio_le_writeb(uint8_t val, void *addr);
+void mmio_le_writew(uint16_t val, void *addr);
+void mmio_le_writel(uint32_t val, void *addr);
+uint8_t mmio_le_readb(void *addr);
+uint16_t mmio_le_readw(void *addr);
+uint32_t mmio_le_readl(void *addr);

/* programmer.c */
 int noop_shutdown(void);
@@ -603,6 +611,7 @@
 enum spi_controller {
    SPI_CONTROLLER_NONE,
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    SPI_CONTROLLER_ICH7,
    SPI_CONTROLLER_ICH9,
    SPI_CONTROLLER_IT87XX,
@@ -610,6 +619,7 @@
    SPI_CONTROLLER_VIA,
    SPI_CONTROLLER_WBSIO,
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    SPI_CONTROLLER_FT2232,
 #endif
Index: flashrom-arch_abstraction/spi25.c
===================================================================
--- flashrom-arch_abstraction/spi25.c	(Revision 1008)
+++ flashrom-arch_abstraction/spi25.c	(Arbeitskopie)
@@ -172,12 +172,14 @@
    /* only some SPI chipsets support 4 bytes commands */
    switch (spi_controller) {
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    case SPI_CONTROLLER_ICH7:
    case SPI_CONTROLLER_ICH9:
    case SPI_CONTROLLER_VIA:
    case SPI_CONTROLLER_SB600:
    case SPI_CONTROLLER_WBSIO:
 #endif
+#endif
 #if FT2232_SPI_SUPPORT == 1
    case SPI_CONTROLLER_FT2232:
 #endif
@@ -996,11 +998,13 @@

switch (spi_controller) {
 #if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    case SPI_CONTROLLER_WBSIO:
    	msg_cerr("%s: impossible with Winbond SPI masters,"
    			" degrading to byte program\n", __func__);
    	return spi_chip_write_1(flash, buf);
 #endif
+#endif
    default:
    	break;
    }
Index: flashrom-arch_abstraction/hwaccess.h
===================================================================
--- flashrom-arch_abstraction/hwaccess.h	(Revision 1008)
+++ flashrom-arch_abstraction/hwaccess.h	(Arbeitskopie)
@@ -24,13 +24,139 @@
 #ifndef __HWACCESS_H__
 #define __HWACCESS_H__ 1

+#if defined (__i386__) || defined (__x86_64__)
 #if defined(__GLIBC__)
 #include <sys/io.h>
 #endif
+#endif
+
 #if NEED_PCI == 1
 #include <pci/pci.h>
 #endif

+#if defined (__i386__) || defined (__x86_64__)
+
+/* All x86 is little-endian. */
+#define __FLASHROM_LITTLE_ENDIAN__ 1
+
+#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
+
+/* MIPS can be either endian. */
+#if defined (__MIPSEL) || defined (__MIPSEL__) || defined (_MIPSEL) || defined (MIPSEL)
+#define __FLASHROM_LITTLE_ENDIAN__ 1
+#elif defined (__MIPSEB) || defined (__MIPSEB__) || defined (_MIPSEB) || defined (MIPSEB)
+#define __FLASHROM_BIG_ENDIAN__ 1
+#endif
+
+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+/* PowerPC can be either endian. */
+#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__)
+#define __FLASHROM_BIG_ENDIAN__ 1
+/* Error checking in case some weird header has #defines for LE as well. */
+#if defined (_LITTLE_ENDIAN) || defined (__LITTLE_ENDIAN__)
+#error Conflicting endianness #define
+#endif
+#else
+#error Little-endian PowerPC #defines are unknown
+#endif
+
+#endif
+
+#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__)
+/* Nonstandard libc-specific macros for determining endianness. */
+#if defined(__GLIBC__)
+#include <endian.h>
+#if BYTE_ORDER == LITTLE_ENDIAN
+#define __FLASHROM_LITTLE_ENDIAN__ 1
+#elif BYTE_ORDER == BIG_ENDIAN
+#define __FLASHROM_BIG_ENDIAN__ 1
+#endif
+#endif
+#endif
+
+#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__)
+#error Unable to determine endianness. Please add support for your arch or libc.
+#endif
+
+#define ___constant_swab8(x) ((uint8_t) (				\
+	(((uint8_t)(x) & (uint8_t)0xffU))))
+
+#define ___constant_swab16(x) ((uint16_t) (				\
+	(((uint16_t)(x) & (uint16_t)0x00ffU) << 8) |			\
+	(((uint16_t)(x) & (uint16_t)0xff00U) >> 8)))
+
+#define ___constant_swab32(x) ((uint32_t) (				\
+	(((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) |		\
+	(((uint32_t)(x) & (uint32_t)0x0000ff00UL) <<  8) |		\
+	(((uint32_t)(x) & (uint32_t)0x00ff0000UL) >>  8) |		\
+	(((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24)))
+
+#define ___constant_swab64(x) ((uint64_t) (				\
+	(((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) |	\
+	(((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) |	\
+	(((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) |	\
+	(((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) <<  8) |	\
+	(((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >>  8) |	\
+	(((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) |	\
+	(((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) |	\
+	(((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56)))
+
+#if defined (__FLASHROM_BIG_ENDIAN__)
+
+#define cpu_to_le(bits)							\
+static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val)	\
+{									\
+	return ___constant_swab##bits(val);				\
+}
+
+cpu_to_le(8)
+cpu_to_le(16)
+cpu_to_le(32)
+cpu_to_le(64)
+
+#define cpu_to_be8
+#define cpu_to_be16
+#define cpu_to_be32
+#define cpu_to_be64
+
+#elif defined (__FLASHROM_LITTLE_ENDIAN__)
+
+#define cpu_to_be(bits)							\
+static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val)	\
+{									\
+	return ___constant_swab##bits(val);				\
+}
+
+cpu_to_be(8)
+cpu_to_be(16)
+cpu_to_be(32)
+cpu_to_be(64)
+
+#define cpu_to_le8
+#define cpu_to_le16
+#define cpu_to_le32
+#define cpu_to_le64
+
+#else
+
+#error Could not determine endianness.
+
+#endif
+
+#define be_to_cpu8 cpu_to_be8
+#define be_to_cpu16 cpu_to_be16
+#define be_to_cpu32 cpu_to_be32
+#define be_to_cpu64 cpu_to_be64
+#define le_to_cpu8 cpu_to_le8
+#define le_to_cpu16 cpu_to_le16
+#define le_to_cpu32 cpu_to_le32
+#define le_to_cpu64 cpu_to_le64
+
+#if defined (__i386__) || defined (__x86_64__)
+
+#define __FLASHROM_HAVE_OUTB__ 1
+
 /* for iopl and outb under Solaris */
 #if defined (__sun) && (defined(__i386) || defined(__amd64))
 #include <strings.h>
@@ -162,4 +288,18 @@
 int freebsd_wrmsr(int addr, msr_t msr);
 #endif

+#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)
+
+/* PCI port I/O is not yet implemented on PowerPC. */
+
+#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips)
+
+/* PCI port I/O is not yet implemented on MIPS. */
+
+#else
+
+#error Unknown architecture, please check if it supports PCI port IO.
+
+#endif
+
 #endif /* !__HWACCESS_H__ */
Index: flashrom-arch_abstraction/it87spi.c
===================================================================
--- flashrom-arch_abstraction/it87spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/it87spi.c	(Arbeitskopie)
@@ -23,6 +23,8 @@
  * Contains the ITE IT87* SPI specific routines
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include <stdlib.h>
 #include "flash.h"
@@ -351,3 +353,5 @@

return 0;
 }
+
+#endif
Index: flashrom-arch_abstraction/physmap.c
===================================================================
--- flashrom-arch_abstraction/physmap.c	(Revision 1008)
+++ flashrom-arch_abstraction/physmap.c	(Arbeitskopie)
@@ -241,6 +241,8 @@
    return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO);
 }

+#if defined(__i386__) || defined(__x86_64__)
+
 #ifdef __linux__
 /*
  * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr,
@@ -462,4 +464,6 @@
 #endif
 #endif
 #endif
-
+#else
+/* Does MSR exist on non-x86 architectures? */
+#endif
Index: flashrom-arch_abstraction/nicrealtek.c
===================================================================
--- flashrom-arch_abstraction/nicrealtek.c	(Revision 1008)
+++ flashrom-arch_abstraction/nicrealtek.c	(Arbeitskopie)
@@ -18,6 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <stdlib.h>
 #include <string.h>
 #include <sys/types.h>
@@ -87,3 +89,7 @@
    return val ;

}
+
+#else
+#error PCI port I/O access is not supported on this architecture yet.
+#endif
Index: flashrom-arch_abstraction/spi.c
===================================================================
--- flashrom-arch_abstraction/spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/spi.c	(Arbeitskopie)
@@ -42,6 +42,7 @@
    },

#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    { /* SPI_CONTROLLER_ICH7 */
    	.command = ich_spi_send_command,
    	.multicommand = ich_spi_send_multicommand,
@@ -84,6 +85,7 @@
    	.write_256 = wbsio_spi_write_1,
    },
 #endif
+#endif

#if FT2232_SPI_SUPPORT == 1
    { /* SPI_CONTROLLER_FT2232 */
Index: flashrom-arch_abstraction/nic3com.c
===================================================================
--- flashrom-arch_abstraction/nic3com.c	(Revision 1008)
+++ flashrom-arch_abstraction/nic3com.c	(Arbeitskopie)
@@ -18,6 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <stdlib.h>
 #include <string.h>
 #include <sys/types.h>
@@ -112,3 +114,7 @@
    OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
    return INB(io_base_addr + BIOS_ROM_DATA);
 }
+
+#else
+#error PCI port I/O access is not supported on this architecture yet.
+#endif
Index: flashrom-arch_abstraction/Makefile
===================================================================
--- flashrom-arch_abstraction/Makefile	(Revision 1008)
+++ flashrom-arch_abstraction/Makefile	(Arbeitskopie)
@@ -124,7 +124,9 @@

ifeq ($(CONFIG_INTERNAL), yes)
 FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1'
-PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o
+PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o
+# FIXME: The PROGRAMMER_OBJS below should only be included on x86.
+PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o
 NEED_PCI := yes
 endif

@@ -260,7 +262,7 @@
    rm -f .dependencies .features .libdeps

dep:
-	@$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies
+	@$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies

strip: $(PROGRAM)
    $(STRIP) $(STRIP_ARGS) $(PROGRAM)
Index: flashrom-arch_abstraction/wbsio_spi.c
===================================================================
--- flashrom-arch_abstraction/wbsio_spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/wbsio_spi.c	(Arbeitskopie)
@@ -18,6 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include "flash.h"
 #include "chipdrivers.h"
@@ -199,3 +201,5 @@

return spi_chip_write_1(flash, buf);
 }
+
+#endif
Index: flashrom-arch_abstraction/chipset_enable.c
===================================================================
--- flashrom-arch_abstraction/chipset_enable.c	(Revision 1008)
+++ flashrom-arch_abstraction/chipset_enable.c	(Arbeitskopie)
@@ -34,6 +34,8 @@
 #include <fcntl.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
+
 extern int ichspi_lock;

static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
@@ -1285,8 +1287,11 @@
    return 0;
 }

+#endif
+
 /* Please keep this list alphabetically sorted by vendor/device. */
 const struct penable chipset_enables[] = {
+#if defined(__i386__) || defined(__x86_64__)
    {0x10B9, 0x1533, OK, "ALi", "M1533",		enable_flash_ali_m1533},
    {0x1022, 0x7440, OK, "AMD", "AMD-768",		enable_flash_amd8111},
    {0x1022, 0x7468, OK, "AMD", "AMD8111",		enable_flash_amd8111},
@@ -1425,7 +1430,7 @@
    {0x1106, 0x0596, OK, "VIA", "VT82C596",		enable_flash_amd8111},
    {0x1106, 0x0586, OK, "VIA", "VT82C586A/B",	enable_flash_amd8111},
    {0x1106, 0x0686, NT, "VIA", "VT82C686A/B",	enable_flash_amd8111},
-
+#endif
    {},
 };

Index: flashrom-arch_abstraction/sb600spi.c
===================================================================
--- flashrom-arch_abstraction/sb600spi.c	(Revision 1008)
+++ flashrom-arch_abstraction/sb600spi.c	(Arbeitskopie)
@@ -21,6 +21,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include "flash.h"
 #include "chipdrivers.h"
@@ -166,3 +168,5 @@

return 0;
 }
+
+#endif
Index: flashrom-arch_abstraction/flashrom.c
===================================================================
--- flashrom-arch_abstraction/flashrom.c	(Revision 1008)
+++ flashrom-arch_abstraction/flashrom.c	(Arbeitskopie)
@@ -276,6 +276,7 @@
 #endif

#if INTERNAL_SUPPORT == 1
+#if defined(__i386__) || defined(__x86_64__)
    {
    	.name			= "it87spi",
    	.init			= it87spi_init,
@@ -293,6 +294,7 @@
    	.delay			= internal_delay,
    },
 #endif
+#endif

#if FT2232_SPI_SUPPORT == 1
    {
@@ -1208,17 +1210,22 @@
 #endif
 #endif
 #ifdef __clang__
-	msg_ginfo(" LLVM %i/clang %i", __llvm__, __clang__);
+	msg_ginfo(" LLVM %i/clang %i, ", __llvm__, __clang__);
 #elif defined(__GNUC__)
    msg_ginfo(" GCC");
 #ifdef __VERSION__
-	msg_ginfo(" %s", __VERSION__);
+	msg_ginfo(" %s,", __VERSION__);
 #else
-	msg_ginfo(" unknown version");
+	msg_ginfo(" unknown version,");
 #endif
 #else
-	msg_ginfo(" unknown compiler");
+	msg_ginfo(" unknown compiler,");
 #endif
+#if defined (__FLASHROM_LITTLE_ENDIAN__)
+	msg_ginfo(" little endian");
+#else
+	msg_ginfo(" big endian");
+#endif
    msg_ginfo("\n");
 }

Index: flashrom-arch_abstraction/internal.c
===================================================================
--- flashrom-arch_abstraction/internal.c	(Revision 1008)
+++ flashrom-arch_abstraction/internal.c	(Arbeitskopie)
@@ -99,10 +99,12 @@
 #endif

#if INTERNAL_SUPPORT == 1
-struct superio superio = {};
 int force_boardenable = 0;
 int force_boardmismatch = 0;

+#if defined(__i386__) || defined(__x86_64__)
+struct superio superio = {};
+
 void probe_superio(void)
 {
    superio = probe_superio_ite();
@@ -112,8 +114,9 @@
    	superio = probe_superio_winbond();
 #endif
 }
+#endif

-int is_laptop;
+int is_laptop = 0;

int internal_init(void)
 {
@@ -166,10 +169,13 @@
     * mainboard specific flash enable sequence.
     */
    coreboot_init();
+
+#if defined(__i386__) || defined(__x86_64__)
    dmi_init();

/* Probe for the Super I/O chip and fill global struct superio. */
    probe_superio();
+#endif

/* Warn if a laptop is detected. */
    if (is_laptop) {
@@ -203,8 +209,10 @@
    		 "will most likely fail.\n");
    }

+#if defined(__i386__) || defined(__x86_64__)
    /* Probe for IT87* LPC->SPI translation unconditionally. */
    it87xx_probe_spi_flash(NULL);
+#endif

board_flash_enable(lb_vendor, lb_part);

Index: flashrom-arch_abstraction/ichspi.c
===================================================================
--- flashrom-arch_abstraction/ichspi.c	(Revision 1008)
+++ flashrom-arch_abstraction/ichspi.c	(Arbeitskopie)
@@ -33,6 +33,8 @@
  *
  */

+#if defined(__i386__) || defined(__x86_64__)
+
 #include <string.h>
 #include "flash.h"
 #include "chipdrivers.h"
@@ -832,3 +834,5 @@
    }
    return ret;
 }
+
+#endif
Index: flashrom-arch_abstraction/print_wiki.c
===================================================================
--- flashrom-arch_abstraction/print_wiki.c	(Revision 1008)
+++ flashrom-arch_abstraction/print_wiki.c	(Arbeitskopie)
@@ -104,6 +104,7 @@
 /* Please keep these lists alphabetically ordered by vendor/board. */
 const struct board_info_url boards_url[] = {
    /* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"AX8",			"http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=Y..." },
    { "Abit",		"Fatal1ty F-I90HD",	"http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NAM..." },
    { "Advantech",		"PCM-5820", 		"http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" },
@@ -279,8 +280,10 @@
    { "VIA",		"EPIA-N/NL",		"http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&a..." }, /* EPIA-N link for now */
    { "VIA",		"EPIA SP",		"http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&a..." },
    { "VIA",		"PC3500G",		"http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp" },
+#endif

/* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"IS-10",		"http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NAM..." },
    { "ASRock",		"K7VT4A+",		"http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=" },
    { "ASUS",		"MEW-AM",		"ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/" },
@@ -298,18 +301,23 @@
    { "Sun",		"Fire x4150",		"http://www.sun.com/servers/x64/x4150/" },
    { "Sun",		"Fire x4200",		"http://www.sun.com/servers/entry/x4200/" },
    { "Sun",		"Fire x4600",		"http://www.sun.com/servers/x64/x4600/" },
+#endif

/* Verified working laptops. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire 1520",		"http://support.acer.com/us/en/acerpanam/notebook/0000/Acer/Aspire1520/Aspire..." },
    { "Lenovo",		"3000 V100 TF05Cxx",	"http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Leno..." },
+#endif

/* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One",		NULL },
    { "ASUS",		"Eee PC 701 4G",	"http://www.asus.com/product.aspx?P_ID=h6SPd3tEzLEsrEiS" },
    { "Dell",		"Latitude CPi A366XT",	"http://www.coreboot.org/Dell_Latitude_CPi_A366XT" },
    { "HP/Compaq",		"nx9010",		"http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc..." },
    { "IBM/Lenovo",		"Thinkpad T40p",	"http://www.thinkwiki.org/wiki/Category:T40p" },
    { "IBM/Lenovo",		"240",			"http://www.stanford.edu/~bresnan//tp240.html" },
+#endif

{ NULL,			NULL,			0 },
 };
@@ -317,6 +325,7 @@
 /* Please keep these lists alphabetically ordered by vendor/board. */
 const struct board_info_notes boards_notes[] = {
    /* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "ASI",		"MB-5BLMP",		"Used in the IGEL WinNET III thin client." },
    { "ASRock",		"K8S8X",		"The Super I/O isn't found on this board. See http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html." },
    { "ASUS",		"A8V-E SE",		"See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." },
@@ -324,23 +333,30 @@
    { "BCOM",		"WinNET100",		"Used in the IGEL-316 thin client." },
    { "GIGABYTE",		"GA-7ZM",		"Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option." },
    { "ASUS",		"M2N-E",		"If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html" },
+#endif

/* Verified working boards that DO need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One",		"See http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html." },
+#endif

/* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "MSI",		"MS-6178",		"Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot." },
    { "MSI",		"MS-7260 (K9N Neo)",	"Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot." },
+#endif

/* Verified working laptops. */
    /* None which need comments, yet... */

/* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One",		"http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html" },
    { "ASUS",		"Eee PC 701 4G",	"It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)." },
    { "Dell",		"Latitude CPi A366XT",	"The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop." },
    { "HP/Compaq",		"nx9010",		"Hangs upon '''flashrom -V''' (needs hard power-cycle then)." },
    { "IBM/Lenovo",		"Thinkpad T40p",	"Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later." },
+#endif

{ NULL,			NULL,			0 },
 };
Index: flashrom-arch_abstraction/print.c
===================================================================
--- flashrom-arch_abstraction/print.c	(Revision 1008)
+++ flashrom-arch_abstraction/print.c	(Arbeitskopie)
@@ -257,6 +257,7 @@
 /* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info boards_ok[] = {
    /* Verified working boards that don't need write-enables. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"AX8", },
    { "Abit",		"Fatal1ty F-I90HD", },
    { "Advantech",		"PCM-5820", },
@@ -377,13 +378,14 @@
    { "VIA",		"pc2500e", },
    { "VIA",		"PC3500G", },
    { "VIA",		"VB700X", },
-
+#endif
    {},
 };

/* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info boards_bad[] = {
    /* Verified non-working boards (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Abit",		"IS-10", },
    { "ASRock",		"K7VT4A+", },
    { "ASUS",		"MEW-AM", },
@@ -401,29 +403,31 @@
    { "Sun",		"Fire x4200", },
    { "Sun",		"Fire x4540", },
    { "Sun",		"Fire x4600", },
-
+#endif
    {},
 };

/* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info laptops_ok[] = {
    /* Verified working laptops. */
+#if defined(__i386__) || defined(__x86_64__)
    { "Lenovo",		"3000 V100 TF05Cxx", },
    { "Acer",               "Aspire 1520", },
-
+#endif
    {},
 };

/* Please keep this list alphabetically ordered by vendor/board. */
 const struct board_info laptops_bad[] = {
    /* Verified non-working laptops (for now). */
+#if defined(__i386__) || defined(__x86_64__)
    { "Acer",		"Aspire One", },
    { "ASUS",		"Eee PC 701 4G", },
    { "Dell",		"Latitude CPi A366XT", },
    { "HP/Compaq",		"nx9010", },
    { "IBM/Lenovo",		"Thinkpad T40p", },
    { "IBM/Lenovo",		"240", },
-
+#endif
    {},
 };
 #endif
Index: flashrom-arch_abstraction/board_enable.c
===================================================================
--- flashrom-arch_abstraction/board_enable.c	(Revision 1008)
+++ flashrom-arch_abstraction/board_enable.c	(Arbeitskopie)
@@ -28,6 +28,7 @@
 #include <fcntl.h>
 #include "flash.h"

+#if defined(__i386__) || defined(__x86_64__)
 /*
  * Helper functions for many Winbond Super I/Os of the W836xx range.
  */
@@ -1306,6 +1307,8 @@
    return it8712f_gpio_set(32, 1);
 }

+#endif
+
 /**
  * Below is the list of boards which need a special "board enable" code in
  * flashrom before their ROM chip can be accessed/written to.
@@ -1349,6 +1352,7 @@
 struct board_pciid_enable board_pciid_enables[] = {

/* first pci-id set [4],          second pci-id set [4],          dmi identifier coreboot id [2],             vendor name    board name       max_rom_...  OK? flash enable */
+#if defined(__i386__) || defined(__x86_64__)
    {0x10DE, 0x0547, 0x147B, 0x1C2F,  0x10DE, 0x0548, 0x147B, 0x1C2F, NULL,          NULL,         NULL,          "Abit",        "AN-M2",                 0,   NT, nvidia_mcp_gpio2_raise},
    {0x8086, 0x2926, 0x147b, 0x1084,  0x11ab, 0x4364, 0x147b, 0x1084, NULL,          NULL,         NULL,          "Abit",        "IP35",                  0,   OK, intel_ich_gpio16_raise},
    {0x8086, 0x2930, 0x147b, 0x1083,  0x10ec, 0x8167, 0x147b, 0x1083, NULL,          NULL,         NULL,          "Abit",        "IP35 Pro",              0,   OK, intel_ich_gpio16_raise},
@@ -1415,7 +1419,7 @@
    {0x1106, 0x3123, 0x1106, 0x3123,  0x1106, 0x3059, 0x1106, 0x4161, NULL,          NULL,         NULL,          "Termtek",     "TK-3370 (Rev:2.5B)",    0,   OK, w836xx_memw_enable_4e},
    {0x1106, 0x3177, 0x1106, 0xAA01,  0x1106, 0x3123, 0x1106, 0xAA01, NULL,          NULL,         NULL,          "VIA",         "EPIA M/MII/...",        0,   OK, via_vt823x_gpio15_raise},
    {0x1106, 0x0259, 0x1106, 0x3227,  0x1106, 0x3065, 0x1106, 0x3149, NULL,          NULL,         NULL,          "VIA",         "EPIA-N/NL",             0,   OK, via_vt823x_gpio9_raise},
-
+#endif
    {     0,      0,      0,      0,       0,      0,      0,      0, NULL,          NULL,         NULL,          NULL,          NULL,                    0,   NT, NULL}, /* end marker */
 };

[Carl-Daniel Hailfinger]

On 26.05.2010 02:49, Carl-Daniel Hailfinger wrote:
> Handle the following architectures in generic flashrom code:
> x86/x86_64 (little endian)
> PowerPC (big endian)
> MIPS (big+little endian)
>
> No changes to programmer specific code. This means any drivers with MMIO
> access will _not_ suddenly start working on big endian systems, but with
> this patch everything is in place to fix them.
>
> DO NOT RUN FLASHROM ON NON-X86 AFTER APPLYING THIS PATCH!
>
> Signed-off-by: Carl-Daniel Hailfinger 
> Acked-by: Misha Manulis 
> Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko 
> Acked-by: Uwe Hermann 
> Acked-by: Segher Boessenkool

And committed in r1013.

Regards,
Carl-Daniel

[PATCH] Convert PCI-based programmers to LE MMIO accessors

[Carl-Daniel Hailfinger]

Misha, could you please test this patch with the satasii programmer on
your CurtisWright Raptor and ack it if it works? A verbose log from a
successful write would be appreciated.
The patch applies on top of an otherwise unpatched tree with latest
flashrom from svn.

Convert all PCI-based external programmers to use special little-endian
accessors for all MMIO regions of PCI devices.
This patch does _not_ touch the internal programmer (which is PCI-based
as well).

Huge thanks go to Misha Manulis who worked with me to create a first
version of this patch for the satasii programmer based on modification
of generic code.

To test on x86, compile flashrom normally.
To test on non-x86, please run

make distclean
make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no

Signed-off-by: Carl-Daniel Hailfinger

Index: flashrom-pci_endian/flash.h
===================================================================
--- flashrom-pci_endian/flash.h	(Revision 1013)
+++ flashrom-pci_endian/flash.h	(Arbeitskopie)
@@ -403,6 +403,8 @@
 uint32_t internal_chip_readl(const chipaddr addr);
 void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
 #endif
+
+/* hwaccess.c */
 void mmio_writeb(uint8_t val, void *addr);
 void mmio_writew(uint16_t val, void *addr);
 void mmio_writel(uint32_t val, void *addr);
@@ -415,6 +417,12 @@
 uint8_t mmio_le_readb(void *addr);
 uint16_t mmio_le_readw(void *addr);
 uint32_t mmio_le_readl(void *addr);
+#define pci_mmio_writeb mmio_le_writeb
+#define pci_mmio_writew mmio_le_writew
+#define pci_mmio_writel mmio_le_writel
+#define pci_mmio_readb mmio_le_readb
+#define pci_mmio_readw mmio_le_readw
+#define pci_mmio_readl mmio_le_readl

/* programmer.c */
 int noop_shutdown(void);
Index: flashrom-pci_endian/drkaiser.c
===================================================================
--- flashrom-pci_endian/drkaiser.c	(Revision 1013)
+++ flashrom-pci_endian/drkaiser.c	(Arbeitskopie)
@@ -70,10 +70,10 @@

void drkaiser_chip_writeb(uint8_t val, chipaddr addr)
 {
-	mmio_writeb(val, drkaiser_bar + addr);
+	pci_mmio_writeb(val, drkaiser_bar + addr);
 }

uint8_t drkaiser_chip_readb(const chipaddr addr)
 {
-	return mmio_readb(drkaiser_bar + addr);
+	return pci_mmio_readb(drkaiser_bar + addr);
 }
Index: flashrom-pci_endian/gfxnvidia.c
===================================================================
--- flashrom-pci_endian/gfxnvidia.c	(Revision 1013)
+++ flashrom-pci_endian/gfxnvidia.c	(Arbeitskopie)
@@ -95,10 +95,10 @@

void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr)
 {
-	mmio_writeb(val, nvidia_bar + addr);
+	pci_mmio_writeb(val, nvidia_bar + addr);
 }

uint8_t gfxnvidia_chip_readb(const chipaddr addr)
 {
-	return mmio_readb(nvidia_bar + addr);
+	return pci_mmio_readb(nvidia_bar + addr);
 }
Index: flashrom-pci_endian/satasii.c
===================================================================
--- flashrom-pci_endian/satasii.c	(Revision 1013)
+++ flashrom-pci_endian/satasii.c	(Arbeitskopie)
@@ -62,7 +62,7 @@
    sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset;

/* Check if ROM cycle are OK. */
-	if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26))))
+	if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26))))
    	msg_pinfo("Warning: Flash seems unconnected.\n");

buses_supported = CHIP_BUSTYPE_PARALLEL;
@@ -82,32 +82,32 @@
 {
    uint32_t ctrl_reg, data_reg;

-	while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;
+	while ((ctrl_reg = pci_mmio_readl(sii_bar)) & (1 << 25)) ;

/* Mask out unused/reserved bits, set writes and start transaction. */
    ctrl_reg &= 0xfcf80000;
    ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff);

-	data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val;
-	mmio_writel(data_reg, (sii_bar + 4));
-	mmio_writel(ctrl_reg, sii_bar);
+	data_reg = (pci_mmio_readl((sii_bar + 4)) & ~0xff) | val;
+	pci_mmio_writel(data_reg, (sii_bar + 4));
+	pci_mmio_writel(ctrl_reg, sii_bar);

-	while (mmio_readl(sii_bar) & (1 << 25)) ;
+	while (pci_mmio_readl(sii_bar) & (1 << 25)) ;
 }

uint8_t satasii_chip_readb(const chipaddr addr)
 {
    uint32_t ctrl_reg;

-	while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ;
+	while ((ctrl_reg = pci_mmio_readl(sii_bar)) & (1 << 25)) ;

/* Mask out unused/reserved bits, set reads and start transaction. */
    ctrl_reg &= 0xfcf80000;
    ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff);

-	mmio_writel(ctrl_reg, sii_bar);
+	pci_mmio_writel(ctrl_reg, sii_bar);

-	while (mmio_readl(sii_bar) & (1 << 25)) ;
+	while (pci_mmio_readl(sii_bar) & (1 << 25)) ;

-	return (mmio_readl(sii_bar + 4)) & 0xff;
+	return (pci_mmio_readl(sii_bar + 4)) & 0xff;
 }